WO2023216360A1 - 三维存储器及其形成方法 - Google Patents

三维存储器及其形成方法 Download PDF

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Publication number
WO2023216360A1
WO2023216360A1 PCT/CN2022/098851 CN2022098851W WO2023216360A1 WO 2023216360 A1 WO2023216360 A1 WO 2023216360A1 CN 2022098851 W CN2022098851 W CN 2022098851W WO 2023216360 A1 WO2023216360 A1 WO 2023216360A1
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region
layer
opening
dimensional memory
substrate
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PCT/CN2022/098851
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English (en)
French (fr)
Inventor
邵光速
肖德元
邱云松
白卫平
蒋懿
苏星松
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长鑫存储技术有限公司
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Priority to US17/891,125 priority Critical patent/US20230371231A1/en
Publication of WO2023216360A1 publication Critical patent/WO2023216360A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a three-dimensional memory and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • the three-dimensional memory and its formation method provided by some embodiments of the present disclosure are used to simplify the manufacturing process of the three-dimensional memory and improve the yield of the three-dimensional memory.
  • the present disclosure provides a method for forming a three-dimensional memory, including the steps of: forming a substrate, and a stacked layer located on the substrate, the stacked layer including The first semiconductor layer and the second semiconductor layer are alternately stacked in the plane direction, the thickness of the second semiconductor layer is D1, the first semiconductor layer includes a plurality of channel regions, and each channel region is distributed along the first direction. In the first area and the second area on opposite sides of the channel area, the first direction is a direction parallel to the top surface of the substrate; a plurality of the trenches are respectively exposed in the stacked layer.
  • a plurality of first openings in the track area, and the gap width between two adjacent first openings along the second direction is D2, D1>D2, and the second direction is parallel to the substrate
  • the top surface and the direction intersecting the first direction; using an atomic layer deposition process to deposit a conductive layer along the first opening, the conductive layer includes covering the channel region and filling along the second direction The gap between adjacent first openings.
  • the specific steps of forming a substrate and stacked layers located on the substrate include: forming a substrate; alternately depositing the first semiconductor layer and the second semiconductor layer on the surface of the substrate , forming the stacked layer; etching the stacked layer to form a plurality of isolation trenches arranged in parallel along the second direction and penetrating the stacked layer in a direction perpendicular to the top surface of the substrate, The isolation trench separates each first semiconductor layer into a plurality of active regions arranged in parallel along the second direction, and each active region includes the channel region, the first region and the second region; filling the first insulating material in the isolation trench to form an isolation layer.
  • the method before forming a plurality of first openings in the stacked layer to respectively expose a plurality of the channel regions, the method further includes the following steps: forming a plurality of first openings in the second semiconductor layer to expose the first regions. a second opening and a third opening exposing the second region; forming a filling layer filling the second opening and the third opening.
  • the specific steps of forming the second opening exposing the first region and the third opening exposing the second region in the second semiconductor layer include: etching the isolation layer to form uniform First etching holes and second etching holes penetrating the isolation layer in a direction perpendicular to the top surface of the substrate; etching the first etching hole and the second etching hole along the first etching hole and the second etching hole.
  • a second opening exposing the first region and a third opening exposing the second region are formed in a partial region of the second semiconductor layer.
  • the step before forming the filling layer filling the second opening and the third opening, the step further includes: rounding the corners of the second opening and the third opening. chemical treatment.
  • the specific steps of forming a filling layer filling the second opening and the third opening include: filling a second insulating material into the second opening and the third opening, forming the filling layer .
  • the step before depositing the conductive layer along the first opening using an atomic layer deposition process, the step further includes: oxidizing the surface of the channel region along the first opening to form a gate oxide layer.
  • the specific steps of using an atomic layer deposition process to deposit a conductive layer along the first opening include: using an atomic layer deposition process to deposit a conductive material along the first opening to form the conductive layer, the conductive layer It includes a first part covering the gate oxide layer and a second part connected to the first part and covering the sidewall of the filling layer, and any two adjacent ones along the second direction are Part of the connection.
  • the method further includes the following steps: removing the filling layer and the second portion of the conductive layer, A source region is formed in the region, a drain region is formed in the second region, and a plurality of the first portions connected along the second direction form a word line.
  • the step before removing the filling layer and the second part of the conductive layer, the step further includes filling a third insulating material into the first opening on the top of the stacked layer to form Covering layer.
  • the specific steps of removing the filling layer and the second part of the conductive layer include: removing the filling layer to expose the first region and the second region; removing the the second part.
  • the first region and the second region of the first semiconductor layer each include doping elements; the filling layer is removed to expose the first region and the second region. Specific steps include: removing the filling layer, the exposed first region forming a source region, and the exposed second region forming a drain region.
  • the method further includes the following steps: reducing the thickness of the first region and the second region; forming a source region on the surface of the first region, and forming The drain region is on the surface of the second region.
  • the specific steps of reducing the thickness of the first region and the second region include: oxidizing the surface of the first region and the surface of the second region to form an oxide layer; removing the oxide layer.
  • the present disclosure also provides a three-dimensional memory, including:
  • a stacked structure located on the substrate, the stacked structure including a plurality of first semiconductor layers arranged in parallel in a direction perpendicular to the top surface of the substrate, the first semiconductor layer including a plurality of Active regions are arranged parallel and spaced apart along the second direction, each of the active regions includes a channel region extending along the first direction, and both the first direction and the second direction are parallel to the liner.
  • the direction of the top surface of the bottom, and the first direction intersects the second direction;
  • Word lines a plurality of the word lines are arranged in parallel and at intervals in a direction perpendicular to the top surface of the substrate, and each of the word lines continuously covers all the trenches in one of the first semiconductor layers. track area, and each of the word lines extends along the second direction;
  • the distance between the active areas in the second direction is smaller than the distance in the vertical direction.
  • the first semiconductor layer also includes a peripheral area located outside the active area; the stacked structure further includes: a second semiconductor layer located on two adjacent layers of the first semiconductor layer. between the peripheral regions of the layer; an insulating dielectric layer located between the active regions of the two adjacent first semiconductor layers.
  • an isolation layer is further included, located between two adjacent active regions in each of the first semiconductor layers and extending in a direction parallel to the first direction.
  • the insulating dielectric layer further includes an air gap between adjacent channel regions.
  • the method further includes: a source region located in the active region of the first semiconductor layer and extending along the first direction; a drain region located in all areas of the first semiconductor layer. Within the active region and extending along the first direction, the source region and the drain region are distributed on opposite sides of the channel region along the first direction.
  • the method further includes: a source region located on the surface of the first semiconductor layer, and in a direction perpendicular to the top surface of the substrate, the projection of the source region is located on the active In the region; the drain region is located on the surface of the first semiconductor layer, in a direction perpendicular to the top surface of the substrate, the projection of the drain region is located in the active region, and the The projection of the source region and the projection of the drain region are distributed on opposite sides of the channel region along the first direction.
  • Some embodiments of the present disclosure provide a three-dimensional memory and a method for forming the same, by alternately stacking first semiconductor layers and second semiconductor layers to form stacked layers, and then etching the stacked layers to form and expose each of the first semiconductor layers.
  • a plurality of first openings in the channel regions, and the thickness of the second semiconductor layer is smaller than the gap width between the plurality of first openings in the horizontal direction, so that when the atomic layer deposition process is used along the first opening,
  • the horizontal word line structure also helps to reduce the internal resistance of the three-dimensional memory and improve the electrical performance of the three-dimensional memory.
  • Figure 1 is a flow chart of a method for forming a three-dimensional memory in a specific embodiment of the present disclosure
  • 2A-2Q are main process schematic diagrams in the process of forming a three-dimensional memory according to specific embodiments of the present disclosure
  • Figure 3 is a schematic structural diagram of a three-dimensional memory in a specific embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another three-dimensional memory in a specific embodiment of the present disclosure.
  • FIG. 1 is a flow chart of the method for forming a three-dimensional memory in the specific embodiment of the present disclosure.
  • Figures 2A-2Q are the process of forming the three-dimensional memory in the specific embodiment of the present disclosure.
  • the three-dimensional memory described in this specific embodiment may be, but is not limited to, DRAM.
  • 2A to 2Q show a schematic top view of the main processes in the formation process of the three-dimensional memory, and the schematic top view in the a-a' direction, b-b' direction, c-c' direction and d-d'
  • the formation method of the three-dimensional memory includes the following steps:
  • Step S11 forming a substrate 20 and a stacked layer 21 located on the substrate 20 .
  • the stacked layer 21 includes a first semiconductor layer 211 and a first semiconductor layer 211 alternately stacked in a direction perpendicular to the top surface of the substrate 20 .
  • the thickness of the second semiconductor layer 212 is D1.
  • the first semiconductor layer 211 includes a plurality of channel regions and is distributed in each of the channel regions along the first direction a-a'. In the first area and the second area on opposite sides, the first direction a-a' is a direction parallel to the top surface of the substrate 20, as shown in FIG. 2A.
  • the substrate 20 may be, but is not limited to, a silicon substrate.
  • the substrate 20 is a silicon substrate as an example for description.
  • the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate 20 is used to support device structures above it.
  • An epitaxial growth process may be used to alternately deposit the first semiconductor layer 211 and the second semiconductor layer 211 in a direction perpendicular to the top surface of the substrate 20 (ie, the surface of the substrate 20 used to form the stacked layer 21 ).
  • the semiconductor layer 212 forms the stacked layer 21 with a superlattice stack structure.
  • the number of alternately stacked first semiconductor layers 211 and second semiconductor layers 212 in the stacked layer 21 can be selected by those skilled in the art according to actual needs. The greater the number of stacked layers 21 , the greater the storage area capacity of the three-dimensional memory.
  • the etching selectivity ratio between the first semiconductor layer 211 and the second semiconductor layer 212 should be greater than 3 to facilitate subsequent exposure of the first region, the second region and the trench through selective etching. Road area.
  • the material of the first semiconductor layer 211 may be Si
  • the material of the second semiconductor layer 212 may be SiGe.
  • specific steps of forming the substrate 20 and the stacked layer 21 located on the substrate 20 include:
  • the stacked layer 21 is etched to form a plurality of isolation trenches 22 arranged in parallel along the second direction d-d' and penetrating the stacked layer 21 in a direction perpendicular to the top surface of the substrate 20 , as shown in FIG. 2B , the isolation trench 22 separates each of the first semiconductor layers 211 into a plurality of active regions arranged in parallel along the second direction d-d′.
  • Each of the active regions A region includes the channel region, the first region, and the second region;
  • the first insulating material is filled into the isolation trench 21 to form an isolation layer 23, as shown in FIG. 2C.
  • a dry etching process may be used to etch the stacked layer 21 in a direction perpendicular to the top surface of the substrate 20 to form a plurality of holes penetrating the stacked layer 21
  • the isolation groove 22 separates each of the first semiconductor layers 211 into a plurality of active areas arranged in parallel in the second direction d-d', and each of the active areas includes an active area along the first direction a- The channel region, the first region and the second region arranged in a'.
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process can be used to deposit a first insulating material such as an oxide (such as silicon dioxide) in the isolation trench 21 to form all the isolation trenches 21 filled.
  • a first insulating material such as an oxide (such as silicon dioxide)
  • the isolation layer 23 is used to electrically isolate the adjacent active areas.
  • Step S12 forming a plurality of first openings 31 in the stacked layer 21 that respectively expose a plurality of the channel regions 30 , and two adjacent first openings 31 are adjacent along the second direction dd′.
  • the gap width between 31 is D2, D1>D2, and the second direction d-d' is parallel to the top surface of the substrate 20 and intersects with the first direction a-a', such as As shown in Figure 2H.
  • a filling layer 29 filling the second opening 25 and the third opening 26 is formed, as shown in FIG. 2G.
  • the specific steps of forming the second opening 25 exposing the first region 27 and the third opening 26 exposing the second region 28 in the second semiconductor layer 212 include:
  • the third opening 26 of the second area 28 is shown in Figure 2E.
  • the isolation layer 23 extends along the third direction bb', and the third direction bb' is parallel to the first direction a-a' and parallel to the second direction d- d' intersect.
  • the intersection described in this specific embodiment may be a vertical intersection or an oblique intersection. In one embodiment, in order to simplify the manufacturing process, the intersection is a vertical intersection.
  • a dry etching process can be used to etch the isolation layer 23 downward in a direction perpendicular to the top surface of the substrate 20 , and form in the isolation layer 23 along the vertical direction.
  • the first etching hole 241 and the second etching hole 242 penetrate the isolation layer 23 in the direction of the top surface of the substrate 20 , as shown in FIG.
  • a wet etching process can be used to etch a partial area of the second semiconductor layer 212 along the first etching hole 241 and the second etching hole 242, and each second semiconductor layer A second opening 25 exposing the first region 27 and a third opening 26 exposing the second region 28 are formed in 212, as shown in FIG. 2E.
  • the exposed first region 27 is used to form a source region of the transistor, and the exposed second region 28 is used to form a drain region of the transistor.
  • filling the second opening 25 and the third opening is formed. Before filling the opening 26, the following steps are also included:
  • the corners of the second opening 25 and the third opening 26 are rounded, as shown in FIG. 2F .
  • the specific steps of forming the filling layer 29 filling the second opening 25 and the third opening 26 include:
  • the second insulating material is filled into the second opening 25 and the third opening 26 to form the filling layer 29 .
  • the second insulating material may be deposited on the second opening 25 and the third opening 26 using an atomic layer deposition process.
  • the third opening 26 forms the filling layer 29 filled with the second opening 25 and the third opening 26 .
  • the second insulating material may be, but is not limited to, a nitride (eg silicon nitride) material.
  • the second opening 25 and the third opening 26 are filled with the filling layer 29.
  • the second opening 25 and the third opening 26 can be filled.
  • the first region and the second region are protected to prevent the process of exposing the channel region 30 from causing damage to the first region and the second region; on the other hand, the filling layer 29 can also cause damage to the first region and the second region.
  • the stacked layer 21 is used to support the stacked layer 21 to prevent the stacked layer 21 from tipping or collapsing during the process of exposing the channel region 30 .
  • a portion of the second semiconductor layer 212 and a portion of the isolation layer 23 in the stacked layer 21 are etched to form a plurality of third channel regions 30 respectively exposed.
  • An opening 31, and the gap width between two adjacent first openings 31 along the second direction d-d' is D2, D1>D2, the second direction d-d' is parallel to The top surface of the substrate 20 and the direction intersecting the first direction a-a' are as shown in FIG. 2H.
  • This specific embodiment controls the gap width between the two adjacent first openings 31 along the second direction d-d' to be D2, D1>D2, so that subsequent deposition in the first opening 31
  • the conductive layer is connected, the conductive layers in the plurality of first openings 31 arranged parallel and spaced along the second direction d-d' are first connected to form a line, and then are connected along a line perpendicular to the substrate.
  • the conductive layers in the plurality of first openings 31 arranged in parallel and spaced directions on the top surface of 20 are then connected into lines, so that a horizontal word line structure can be finally formed.
  • Step S13 Use an atomic layer deposition process to deposit a conductive layer 33 along the first opening 31.
  • the conductive layer 33 covers the channel region 30 and fills the adjacent channels along the second direction d-d'.
  • the gap between the first openings 31 is as shown in Figure 2K.
  • the following steps are further included:
  • the surface of the channel region 30 is oxidized along the first opening 31 to form a gate oxide layer 32, as shown in FIG. 2J.
  • the corners of the first opening 31 are rounded, as shown in FIG. 2I, to increase the area of subsequent deposition in the The contact area between the material in the first opening 31 and the inner wall of the first opening 31 reduces defects at the corners of the first opening.
  • a thermal oxidation method may be used to oxidize the surface of the channel region 30 in-situ to form the gate oxide layer 32, as shown in FIG. 2J.
  • the specific steps of depositing the conductive layer 32 along the first opening 31 using an atomic layer deposition process include:
  • the conductive layer 32 includes a first part covering the gate oxide layer 32, and a first part connected to the first part.
  • the second part covering the side wall of the filling layer 29 is connected to any two adjacent first parts along the second direction d-d', as shown in Figure 2K.
  • the following steps are further included:
  • the filling layer 29 and the second part of the conductive layer 32 are removed, a source region is formed in the first region 27 and a drain region is formed in the second region 28, along the second direction.
  • a plurality of the first parts connected by d-d' form a word line, as shown in Figure 2N.
  • the following steps are further included:
  • the third insulating material is filled into the first opening 31 on the top of the stacked layer 21 to form a covering layer 34, as shown in FIG. 2L.
  • specific steps of removing the filling layer 29 and the second portion of the conductive layer 32 include:
  • the second portion is removed as shown in Figure 2N.
  • the atomic layer deposition process is used to deposit conductive materials such as tungsten along the first opening 31, due to the gap between the two adjacent first openings 31 along the second direction d-d', The width is smaller than the thickness of the second semiconductor layer 212. Therefore, when the conductive layer 33 is deposited in the first opening 31, a plurality of the conductive layers 33 are arranged parallel and spaced apart along the second direction d-d'.
  • the conductive layer 33 in the first opening 31 is first connected to form a line, and then the conductive layers in a plurality of the first openings 31 are arranged parallel and spaced apart in a direction perpendicular to the top surface of the substrate 20 Layer 33 is then wired.
  • the conductive layer 33 includes a first part covering the gate oxide layer 32 and a second part connected to the first part and covering the sidewall of the filling layer 29 .
  • a third insulating material such as silicon dioxide
  • the covering layer 34 remaining on the top surface of the stacked layer 21 is removed through a chemical mechanical polishing process to form a structure as shown in FIG. 2L.
  • the covering layer 34 is used to isolate the conductive layer 33 from the external environment to protect the conductive layer 33 .
  • the filling layer 29 is removed through a selective etching process to expose the first region 27 and the second region 28, as shown in FIG. 2M, to facilitate the subsequent formation of transistors and the
  • the second portion of the conductive layer 33 is etched.
  • the second part is completely removed by etching in a direction perpendicular to the top surface of the substrate 20 , leaving only the first part.
  • the conductive layers 33 covering the surface of the two adjacent layers of the channel region 30 are not connected, and in the second direction d-d'
  • a plurality of the first portions covering the surface of each first semiconductor layer 211 are connected to form a word line 35, that is, a horizontal word line structure is formed, as shown in FIG. 2N.
  • the horizontal word line structure of this specific embodiment not only has a simple formation process, but also can avoid the yield and process challenges caused by the size shrinkage of the three-dimensional memory, and helps to reduce the contact resistance inside the three-dimensional memory.
  • the first part of the part may also be removed simultaneously, so that after etching, the gate
  • the oxide layer 32 protrudes from the remaining first portion along the first direction a-a', that is, in a direction perpendicular to the top surface of the substrate 20 , the projection of the remaining first portion is completely located with it. Contact the interior of the projection of the gate oxide layer 32 .
  • both the first region 27 and the second region 28 of the first semiconductor layer 211 include doping elements; the filling layer 29 is removed to expose the first region 27 and the second region 28 .
  • the specific steps of the second area 28 include:
  • the filling layer 27 is removed, the exposed first region 27 forms a source region, and the exposed second region 28 forms a drain region.
  • the first region 27 and the second region 28 in the first semiconductor layer 211 can be doped first, that is, before forming the The source region and the drain region are formed when layers 21 are stacked. After the filling layer 27 is removed, the source region and the drain region are directly exposed. Then, an insulating material such as oxide (eg, silicon dioxide) is deposited on the second opening 25 and the third opening 26 to form an insulating dielectric layer 36, as shown in FIG. 2O.
  • oxide eg, silicon dioxide
  • a source region is formed on the surface of the first region 27
  • a drain region is formed on the surface of the second region 28 .
  • specific steps of reducing the thickness of the first region 27 and the second region 28 include:
  • the first region 27 and the second region 28 in the first semiconductor layer 211 may not be doped first, and then the conductive After the second portion of layer 33, an in-situ oxidation process may be used to oxidize the surface of the first region 27 and the surface of the second region 28 to form an oxide layer. Afterwards, a selective etching process is used to remove the oxide layer, thereby reducing the thickness of the first region 27 and the second region 28 in a direction perpendicular to the substrate 20 to increase electrons in the transistor. migration rate.
  • silicon and other materials are epitaxially grown on the surface of the remaining first region 27 and the remaining second region 28 to form an epitaxial layer, and the source region 38 and the drain region are formed by doping the epitaxial layer. 39, as shown in Figure 2P.
  • an insulating material such as oxide (eg, silicon dioxide) is deposited on the second opening 25 and the third opening 26 to form an insulating dielectric layer 36, as shown in FIG. 2Q.
  • FIG. 3 is a schematic structural diagram of a three-dimensional memory in the specific embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another three-dimensional memory in the specific embodiment of the present disclosure.
  • the three-dimensional memory provided in this specific embodiment can be formed by using the memory forming method as shown in FIG. 1 and FIG. 2A-FIG. 2Q.
  • the three-dimensional memory described in this specific embodiment may be, but is not limited to, DRAM.
  • the three-dimensional memory includes:
  • a stacked structure is located on the substrate 20 .
  • the stacked structure includes a plurality of first semiconductor layers 211 arranged in parallel in a direction perpendicular to the top surface of the substrate 20 .
  • the first semiconductor layers 211 includes a plurality of active regions arranged parallel and spaced apart along the second direction d-d', each of the active regions includes a channel region 30 extending along the first direction, the first direction a-a' and the second direction d-d' are directions parallel to the top surface of the substrate 20, and the first direction a-a' intersects the second direction d-d';
  • Word lines 35 A plurality of word lines 35 are arranged in parallel and at intervals in a direction perpendicular to the top surface of the substrate 20. Each of the word lines 35 continuously covers one of the first semiconductor layers 211. All of the channel regions 30 , and each of the word lines 35 extends along the second direction d-d';
  • the spacing distance of the active areas in the second direction d-d' is smaller than the spacing distance in the vertical direction.
  • the separation distance between two adjacent channel regions 30 along the second direction d-d′ is smaller than the distance between two adjacent channel regions 30 along the direction perpendicular to the top surface of the substrate 20 .
  • the distance between the two channel regions 30 is smaller than the distance between the two channel regions 30 .
  • the first semiconductor layer 211 also includes a peripheral region located outside the active region; the stacked structure further includes:
  • the second semiconductor layer 212 is located between the peripheral regions of the two adjacent first semiconductor layers 211;
  • the insulating dielectric layer 36 is located between the active regions of the two adjacent first semiconductor layers 211 .
  • the three-dimensional memory further includes: an isolation layer located between two adjacent active regions in each of the first semiconductor layers 211 and along a direction parallel to the first direction a- extends in the direction of a'.
  • the insulating dielectric layer 36 further includes an air gap 361 between adjacent channel regions 30 .
  • the three-dimensional memory further includes:
  • a source region is located in the active region of the first semiconductor layer 211 and extends along the first direction a-a’;
  • the drain region is located in the active region of the first semiconductor layer 211 and extends along the first direction a-a'.
  • the source region and the drain region extend along the first direction.
  • a-a' are distributed on both sides of the channel region 30 .
  • the three-dimensional memory further includes:
  • the source region 38 is located on the surface of the first semiconductor layer 211, and in a direction perpendicular to the top surface of the substrate 20, the projection of the source region 38 is located in the active region;
  • the drain region 39 is located on the surface of the first semiconductor layer 211. In a direction perpendicular to the top surface of the substrate 20, the projection of the drain region 39 is located in the active region, and the The projection of the source region 38 and the projection of the drain region 39 are distributed on opposite sides of the channel region 30 along the first direction a-a'.
  • the three-dimensional memory and its formation method provided by this specific embodiment form a stacked layer by alternately stacking first semiconductor layers and second semiconductor layers, and then etching the stacked layer to expose multiple layers in each of the first semiconductor layers.
  • a plurality of first openings in the channel region, and the thickness of the second semiconductor layer is greater than the gap width between the plurality of first openings in the horizontal direction, so that when the atomic layer deposition process is used along the first
  • the conductive layer is deposited in the opening, the conductive layers in the plurality of first openings in the horizontal direction are connected into a line, thereby forming a horizontal word line structure, thus simplifying the manufacturing process of the three-dimensional memory and improving the manufacturing yield of the three-dimensional memory.
  • the horizontal word line structure also helps to reduce the internal resistance of the three-dimensional memory and improve the electrical performance of the three-dimensional memory.

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Abstract

本公开提供的三维存储器的形成方法包括如下步骤：形成衬底、以及堆叠层，堆叠层包括交替堆叠的第一半导体层和第二半导体层，第二半导体层的厚度为D1，第一半导体层中包括多个沟道区域、以及沿第一方向分布于每一沟道区域的相对两侧的第一区域和第二区域，第一方向为平行于衬底的顶面的方向；形成分别暴露多个沟道区域的多个第一开口，且在沿第二方向上相邻的两个第一开口之间的间隙宽度为D2，D1>D2，第二方向为平行于衬底的顶面、且与第一方向相交的方向；沿第一开口沉积导电层，导电层包括包覆沟道区域且沿第二方向填充相邻第一开口之间的间隙。本公开形成了水平字线结构，改善了三维存储器的电学性能。

Description

三维存储器及其形成方法
相关申请引用说明
本申请要求于2022年05月10日递交的中国专利申请号202210502920.8、申请名为“三维存储器及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种三维存储器及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着DRAM等存储器结构的不断微缩，给三维存储器的制造工艺、以及制造量良率都带来了较大的挑战。例如，随着DRAM等存储器结构的尺寸微缩，竖直字线结构会导致存储器内部的电阻过高，影响存储器的电学性能。
因此，如何简化三维存储器的制造工艺，以提高三维存储器的良率，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的三维存储器及其形成方法，用于简化三维存储器的制造工艺、提高三维存储器的良率。
根据一些实施例，本公开提供了一种三维存储器的形成方法，包括如下步骤：形成衬底、以及位于所述衬底上的堆叠层，所述堆叠层包括沿垂直于所述衬底的顶面的方向交替堆叠的第一半导体层和第二半导体层，所述第二半导体层的厚度为D1，所述第一半导体层中包括多个沟道区域、以及沿第一方向分布于每一所述沟道区域的相对两侧的第一区域和第二区域，所述第一方向为平行于所述衬底的顶面的方向；于所述堆叠层中形成分别暴露多个所述沟道区域的多个第一开口，且在沿第二方向上相邻的两个所述第一开口之间的间隙宽度为D2，D1>D2，所述第二方向为平行于所述衬底的顶面、且与所述第一方向相交的方向；采用原子层沉积工艺沿所述第一开口沉积导电层，所述导电层包括包覆所述沟道区域且沿所述第二方向填充相邻所述第一开口之间的间隙。
在一些实施例中，形成衬底、以及位于所述衬底上的堆叠层的具体步骤包括：形成衬底；交替沉积所述第一半导体层和所述第二半导体层于所述衬底表面，形成所述堆叠层；刻蚀所述堆叠层，形成多个沿所述第二方向平行排布、其均沿垂直于所述衬底的顶面的方向贯穿所述堆叠层的隔离槽，所述隔离槽将每一个所述第一半导体层分隔为沿所述第二方向平行排布的多个有源区，每一所述有源区包括所述沟道区域、所述第一区域和所述第二区域；填充第一绝缘材料于所述隔离槽内，形成隔离层。
在一些实施例中，于所述堆叠层中形成分别暴露多个所述沟道区域的多个第一开口之前，还包括如下步骤：于所述第二半导体层中形成暴露所述第一区域的第二开口和暴露所述第二区域的第三开口；形成填充所述第二开口和所述第三开口的填充层。
在一些实施例中，于所述第二半导体层中形成暴露所述第一区域的第二开口和暴露所述第二区域的第三开口的具体步骤包括：刻蚀所述隔离层，形成均沿垂直于所述衬底的顶面的方向贯穿所述隔离层的第一刻蚀孔和第二刻蚀孔；沿所述第一刻蚀孔和所述第二刻蚀孔刻蚀所述第二半导体层中的部分区域，形成暴露所述第一区域的第二开口和暴露所述第二区域的第三开口。
在一些实施例中，形成填充所述第二开口和所述第三开口的填充层之前，还包括如下步骤：对所述第二开口的拐角处和所述第三开口的拐角处进行圆角化处理。
在一些实施例中，形成填充所述第二开口和所述第三开口的填充层的具体步骤包括：填充第二绝缘材料至所述第二开口和所述第三开口，形成所述填充层。
在一些实施例中，采用原子层沉积工艺沿所述第一开口沉积导电层之前还包括如下步骤：沿所述第一开口氧化所述沟道区域的表面，形成栅极氧化层。
在一些实施例中，采用原子层沉积工艺沿所述第一开口沉积导电层的具体步骤包括：采用原子层沉积工艺沿所述第一开口沉积导电材料，形成所述导电层，所述导电层包括包覆所述栅极氧化层的第一部 分、以及与所述第一部分连接且覆盖所述填充层侧壁的第二部分，在沿所述第二方向上任意相邻的两个所述第一部分连接。
在一些实施例中，采用原子层沉积工艺沿所述第一开口沉积导电层之后，还包括如下步骤：去除所述填充层、以及所述导电层的所述第二部分，于所述第一区域形成源极区、于所述第二区域形成漏极区，沿所述第二方向连接的多个所述第一部分形成一条字线。
在一些实施例中，去除所述填充层、以及所述导电层的所述第二部分之前，还包括如下步骤：填充第三绝缘材料于所述堆叠层顶部的所述第一开口内，形成覆盖层。
在一些实施例中，去除所述填充层、以及所述导电层的所述第二部分的具体步骤包括：去除所述填充层，暴露所述第一区域和所述第二区域；去除所述第二部分。
在一些实施例中，所述第一半导体层的所述第一区域和所述第二区域中均包括掺杂元素；去除所述填充层，暴露所述第一区域和所述第二区域的具体步骤包括：去除所述填充层，暴露的所述第一区域形成源极区、且暴露的所述第二区域形成漏极区。
在一些实施例中，去除所述第二部分之后，还包括如下步骤：减小所述第一区域和所述第二区域的厚度；形成源极区于所述第一区域的表面、并形成漏极区于所述第二区域的表面。
在一些实施例中，减小所述第一区域和所述第二区域的厚度的具体步骤包括：氧化所述第一区域的表面和所述第二区域的表面，形成氧化层；去除所述氧化层。
根据另一些实施例，本公开还提供了一种三维存储器，包括：
衬底；
叠层结构，位于所述衬底上，所述叠层结构包括沿垂直于所述衬底的顶面的方向平行排布的多个第一半导体层，所述第一半导体层中包括多个沿第二方向平行且间隔排布的有源区，每个所述有源区包括沿第一方向延伸的沟道区域，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
字线，多条所述字线沿垂直于所述衬底的顶面的方向平行、且间隔排布，每一条所述字线连续包覆一个所述第一半导体层中的所有所述沟道区域，且每一条所述字线均沿所述第二方向延伸；
所述有源区在第二方向的间隔距离小于其在竖直方向的间隔。
在一些实施例中，所述第一半导体层中还包括位于所述有源区外部的外围区；所述叠层结构还包括：第二半导体层，位于相邻的两层所述第一半导体层的所述外围区之间；绝缘介质层，位于相邻的两层所述第一半导体层的所述有源区之间。
在一些实施例中，还包括：隔离层，位于每个所述第一半导体层中相邻两个所述有源区之间，且沿平行于所述第一方向的方向延伸。
在一些实施例中，所述绝缘介质层中还包括位于相邻所述沟道区域之间的空气隙。
在一些实施例中，还包括：源极区，位于所述第一半导体层的所述有源区内，且沿所述第一方向延伸；漏极区，位于所述第一半导体层的所述有源区内，且沿所述第一方向延伸，所述源极区和所述漏极区沿所述第一方向分布于所述沟道区域的相对两侧。
在一些实施例中，还包括：源极区，位于所述第一半导体层的表面，在沿垂直于所述衬底的顶面的方向上，所述源极区的投影位于所述有源区内；漏极区，位于所述第一半导体层的表面，在沿垂直于所述衬底的顶面的方向上，所述漏极区的投影位于所述有源区内，且所述源极区的投影和所述漏极区的投影沿所述第一方向分布于所述沟道区域的相对两侧。
本公开一些实施例提供的三维存储器及其形成方法，通过交替堆叠第一半导体层和第二半导体层形成堆叠层，然后通过刻蚀所述堆叠层形成暴露每个所述第一半导体层中的多个沟道区域的多个第一开口，且限定第二半导体层的厚度小于水平方向上的多个所述第一开口之间的间隙宽度，从而使得在采用原子层沉积工艺沿所述第一开口沉积导电层时，水平方向上的多个所述第一开口内的导电层连接成一条线，从而形成水平字线结构，从而简化了三维存储器的制造工艺，提高了三维存储器的制造良率。另外，水平字线结构还有助于降低所述三维存储器内部的电阻，改善三维存储器的电学性能。
附图说明
附图1是本公开具体实施方式中三维存储器的形成方法流程图；
附图2A-2Q是本公开具体实施方式在形成三维存储器的过程中主要的工艺示意图；
附图3是本公开具体实施方式中一三维存储器的结构示意图；
附图4是本公开具体实施方式中另一三维存储器的结构示意图。
具体实施方式
下面结合附图对本公开提供的三维存储器及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种三维存储器的形成方法，附图1是本公开具体实施方式中三维存储器的形成方法流程图，附图2A-2Q是本公开具体实施方式在形成三维存储器的过程中主要的工艺示意图。本具体实施方式中所述的三维存储器可以是但不限于DRAM。图2A-图2Q示出了所述三维存储器在形成过程中主要工艺的俯视示意图、以及所述俯视示意图在a-a’方向、b-b’方向、c-c’方向和d-d’方向上的截面示意图，以清楚地表面所述三维存储器的形成工艺。如图1、图2A-图2Q所示，所述三维存储器的形成方法，包括如下步骤：
步骤S11，形成衬底20、以及位于所述衬底20上的堆叠层21，所述堆叠层21包括沿垂直于所述衬底20的顶面的方向交替堆叠的第一半导体层211和第二半导体层212，所述第二半导体层212的厚度为D1，所述第一半导体层211中包括多个沟道区域、以及沿第一方向a-a’分布于每一所述沟道区域的相对两侧的第一区域和第二区域，所述第一方向a-a’为平行于所述衬底20的顶面的方向，如图2A所示。
具体来说，所述衬底20可以是但不限于硅衬底，本具体实施方式以所述衬底20为硅衬底为例进行说明。在其他示例中，所述衬底20可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20用于支撑在其上方的器件结构。可以采用外延生长工艺沿垂直于所述衬底20的顶面(即所述衬底20用于形成所述堆叠层21的表面)的方向交替沉积所述第一半导体层211和所述第二半导体层212，形成具有超晶格堆栈结构的所述堆叠层21。所述堆叠层21中所述第一半导体层211和所述第二半导体层212交替堆叠的层数，本领域技术人员可以根据实际需要进行选择。所述堆叠层21的堆叠层数越多，所述三维存储器的存储区容量越大。所述第一半导体层211与所述第二半导体层212之间的刻蚀选择比应大于3，以便于后续通过选择性刻蚀暴露所述第一区域、所述第二区域和所述沟道区域。在一实施例中，所述第一半导体层211的材料可以为Si，所述第二半导体层212的材料可以为SiGe。
在一些实施例中，形成衬底20、以及位于所述衬底20上的堆叠层21的具体步骤包括：
形成衬底20；
交替沉积所述第一半导体层211和所述第二半导体层212于所述衬底20表面，形成所述堆叠层21，如图2A所示；
刻蚀所述堆叠层21，形成多个沿所述第二方向d-d’平行排布、其均沿垂直于所述衬底20的顶面的方向贯穿所述堆叠层21的隔离槽22，如图2B所示，所述隔离槽22将每一个所述第一半导体层211分隔为沿所述第二方向d-d’平行排布的多个有源区，每一所述有源区包括所述沟道区域、所述第一区域和所述第二区域；
填充第一绝缘材料于所述隔离槽21内，形成隔离层23，如图2C所示。
具体来说，在形成所述堆叠层21之后，可以采用干法刻蚀工艺沿垂直于所述衬底20的顶面的方向刻蚀所述堆叠层21，形成多个贯穿所述堆叠层21的所述隔离槽22。所述隔离槽22将每一个所述第一半导体层211分隔为所述第二方向d-d’平行排布的多个有源区，每一所述有源区包括沿第一方向a-a’排布的所述沟道区域、所述第一区域和所述第二区域。之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氧化物(例如二氧化硅)等第一绝缘材料于所述隔离槽21内，形成填充满所述隔离槽21的所述隔离层23。所述隔离层23用于电性隔离相邻的所述有源区。
步骤S12，于所述堆叠层21中形成分别暴露多个所述沟道区域30的多个第一开口31，且在沿第二方向d-d’上相邻的两个所述第一开口31之间的间隙宽度为D2，D1>D2，所述第二方向d-d’为平行于所述衬底20的顶面、且与所述第一方向a-a’相交的方向，如图2H所示。
在一些实施例中，于所述堆叠层21中形成分别暴露多个所述沟道区域30的多个第一开口31之前，还包括如下步骤：
于所述第二半导体层212中形成暴露所述第一区域27的第二开口25和暴露所述第二区域28的第三开口26，如图2E所示；
形成填充所述第二开口25和所述第三开口26的填充层29，如图2G所示。
在一些实施例中，于所述第二半导体层212中形成暴露所述第一区域27的第二开口25和暴露所述第二区域28的第三开口26的具体步骤包括：
刻蚀所述隔离层23，形成均沿垂直于所述衬底20的顶面的方向贯穿所述隔离层23的第一刻蚀孔241和第二刻蚀孔242，如图2D所示；
沿所述第一刻蚀孔241和所述第二刻蚀孔242刻蚀所述第二半导体层212中的部分区域，形成暴露所述第一区域27的第二开口25和暴露所述第二区域28的第三开口26，如图2E所示。
具体来说，所述隔离层23沿第三方向b-b’延伸，且所述第三方向b-b’与所述第一方向a-a’平行、并与所述第二方向d-d’相交。本具体实施方式中所述的相交可以是垂直相交、也可以是倾斜相交。在一实施例中，为了简化制程工艺，所述相交为垂直相交。在形成所述隔离层23之后，可以采用干法刻蚀工艺沿垂直于所述衬底20的顶面的方向向下刻蚀所述隔离层23，于所述隔离层23中形成均沿垂直于所述衬底20的顶面的方向贯穿所述隔离层23的第一刻蚀孔241和第二刻蚀孔242，如图2D所示。之后，可以采用湿法刻蚀工艺沿所述第一刻蚀孔241和所述第二刻蚀孔242刻蚀所述第二半导体层212中的部分区域，于每一所述第二半导体层212中形成暴露所述第一区域27的第二开口25和暴露所述第二区域28的第三开口26，如图2E所示。暴露的所述第一区域27用于形成晶体管的源极区，暴露的所述第二区域28用于形成所述晶体管的漏极区。
为了增大后续形成的所述填充层29与所述堆叠层21之间的接触面积，减少因角落空隙引起的缺陷，在一些实施例中，形成填充所述第二开口25和所述第三开口26的填充层之前，还包括如下步骤：
对所述第二开口25的拐角处和所述第三开口26的拐角处进行圆角化处理，如图2F所示。
在一些实施例中，形成填充所述第二开口25和所述第三开口26的填充层29的具体步骤包括：
填充第二绝缘材料至所述第二开口25和所述第三开口26，形成所述填充层29。
具体来说，在对所述第二开口25和所述第三开口26的拐角处进行圆角化处理之后，可以采用原子层沉积工艺沉积所述第二绝缘材料于所述第二开口25和所述第三开口26，形成填充满所述第二开口25和所述第三开口26的所述填充层29。所述第二绝缘材料可以是但不限于氮化物(例如氮化硅)材料。本具体实施方式在形成暴露所述沟道区域30的所述第一开口31之前，通过所述填充层29填充所述第二开口25和所述第三开口26，一方面，能够对所述第一区域和所述第二区域进行保护，避免暴露所述沟道区域30的工艺对所述第一区域和所述第二区域造成损伤；另一方面，所述填充层29还能够对所述堆叠层21进行支撑，避免在暴露所述沟道区域30的过程中出现堆叠层21的倾倒或者坍塌。
在形成所述填充层29之后，刻蚀所述堆叠层21中的部分所述第二半导体层212和部分的所述隔离层23，形成分别暴露多个所述沟道区域30的多个第一开口31，且在沿第二方向d-d’上相邻的两个所述第一开口31之间的间隙宽度为D2，D1>D2，所述第二方向d-d’为平行于所述衬底20的顶面、且与所述第一方向a-a’相交的方向，如图2H所示。本具体实施方式通过控制在沿第二方向d-d’上相邻的两个所述第一开口31之间的间隙宽度为D2，D1>D2，使得后续在所述第一开口31内沉积所述导电层时，沿所述第二方向d-d’平行且间隔排布的多个所述第一开口31内的所述导电层先连接成一条线，之后沿垂直于所述衬底20的顶面的方向平行且间隔排布的多个所述第一开口31内的所述导电层再连接成线，以便于最终能够形成水平字线结构。
步骤S13，采用原子层沉积工艺沿所述第一开口31沉积导电层33，所述导电层33包括包覆所述沟道区域30且沿所述第二方向d-d’填充相邻所述第一开口31之间的间隙，如图2K所示。
在一些实施例中，采用原子层沉积工艺沿所述第一开口31沉积导电层33之前还包括如下步骤：
沿所述第一开口31氧化所述沟道区域30的表面，形成栅极氧化层32，如图2J所示。
具体来说，在形成暴露所述沟道区域30的所述第一开口31之后，对所述第一开口31的拐角处进行圆角化处理，如图2I所示，以增大后续沉积于所述第一开口31内的材料与所述第一开口31内壁的接触面积，减少所述第一开口拐角处的缺陷。接着，可以采用热氧化法原位氧化所述沟道区域30的表面，形成所述栅极氧化层32，如图2J所示。
在一些实施例中，采用原子层沉积工艺沿所述第一开口31沉积导电层32的具体步骤包括：
采用原子层沉积工艺沿所述第一开口31沉积导电材料，形成所述导电层32，所述导电层32包括包 覆所述栅极氧化层32的第一部分、以及与所述第一部分连接且覆盖所述填充层29侧壁的第二部分，在沿所述第二方向d-d’上任意相邻的两个所述第一部分连接，如图2K所示。
在一些实施例中，采用原子层沉积工艺沿所述第一开口31沉积导电层32之后，还包括如下步骤：
去除所述填充层29、以及所述导电层32的所述第二部分，于所述第一区域27形成源极区、于所述第二区域28形成漏极区，沿所述第二方向d-d’连接的多个所述第一部分形成一条字线，如图2N所示。
在一些实施例中，去除所述填充层29、以及所述导电层32的所述第二部分之前，还包括如下步骤：
填充第三绝缘材料于所述堆叠层21顶部的所述第一开口31内，形成覆盖层34，如图2L所示。
在一些实施例中，去除所述填充层29、以及所述导电层32的所述第二部分的具体步骤包括：
去除所述填充层29，暴露所述第一区域27和所述第二区域28，如图2M所示；
去除所述第二部分，如图2N所示。
具体来说，在采用原子层沉积工艺沿所述第一开口31沉积钨等导电材料时，由于在沿第二方向d-d’上相邻的两个所述第一开口31之间的间隙宽度小于所述第二半导体层212的厚度，因此，在所述第一开口31内沉积所述导电层33时，沿所述第二方向d-d’平行且间隔排布的多个所述第一开口31内的所述导电层33先连接成一条线，之后沿垂直于所述衬底20的顶面的方向平行且间隔排布的多个所述第一开口31内的所述导电层33再连接成线。所述导电层33包括包覆所述栅极氧化层32的第一部分、以及与所述第一部分连接且覆盖所述填充层29侧壁的第二部分。接着，沉积第三绝缘材料(例如二氧化硅)于所述堆叠层21顶部的所述第一开口31内，形成填充满所述堆叠层21顶部的所述第一开口31的覆盖层34，并通过化学机械研磨工艺去除残留于所述堆叠层21顶面的所述覆盖层34，形成如图2L所示的结构。所述覆盖层34用于隔离所述导电层33与外界环境，以保护所述导电层33。
在形成所述覆盖层34之后，通过选择性刻蚀工艺去除所述填充层29，暴露所述第一区域27和所述第二区域28，如图2M所示，以便于后续形成晶体管以及对所述导电层33的所述第二部分进行刻蚀。之后，沿垂直于所述衬底20的顶面的方向刻蚀完全去除所述第二部分，仅保留所述第一部分。在沿垂直于所述衬底20的顶面的方向上，相邻的两层所述沟道区域30表面覆盖的所述导电层33不连接，且在沿所述第二方向d-d’上，覆盖于每一层所述第一半导体层211表面上的多个所述第一部分连接形成一条字线35，即形成水平字线结构，如图2N所示。本具体实施方式水平字线结构不仅形成工艺简单，且能够避免三维存储器的尺寸微缩带来的良率和工艺挑战，且有助于降低所述三维存储器内部的接触电阻。
为了避免晶体管的源极区和漏极区与所述字线35接触，在刻蚀去除所述第二部分时，也可以同步去除部分的所述第一部分，使得刻蚀之后，所述栅极氧化层32沿所述第一方向a-a’突出于残留的所述第一部分，即在沿垂直于所述衬底20的顶面的方向上，残留的所述第一部分的投影完全位于与其接触的所述栅极氧化层32的投影的内部。
在一些实施例中，所述第一半导体层211的所述第一区域27和所述第二区域28中均包括掺杂元素；去除所述填充层29，暴露所述第一区域27和所述第二区域28的具体步骤包括：
去除所述填充层27，暴露的所述第一区域27形成源极区、且暴露的所述第二区域28形成漏极区。
具体来说，在外延生长所述第一半导体层211时，可以先对所述第一半导体层211中的所述第一区域27和所述第二区域28进行掺杂，即在形成所述堆叠层21时就形成了所述源极区和所述漏极区。在去除所述填充层27之后，直接暴露所述源极区和所述漏极区。然后，沉积氧化物(例如二氧化硅)等绝缘材料于所述第二开口25和所述第三开口26，形成绝缘介质层36，如图2O所示。
在另一实施例中，去除所述第二部分之后，还包括如下步骤：
减小所述第一区域27和所述第二区域28的厚度；
形成源极区于所述第一区域27的表面、并形成漏极区于所述第二区域28的表面。
在一些实施例中，减小所述第一区域27和所述第二区域28的厚度的具体步骤包括：
氧化所述第一区域27的表面和所述第二区域28的表面，形成氧化层；
去除所述氧化层。
具体来说，在外延生长所述第一半导体层211时，可以先不对所述第一半导体层211中的所述第一区域27和所述第二区域28进行掺杂，在去除所述导电层33的所述第二部分之后，可以采用原位氧化工艺氧化所述第一区域27的表面和所述第二区域28的表面，形成氧化层。之后，采用选择性刻蚀工艺去 除所述氧化层，从而使得所述第一区域27和所述第二区域28沿垂直于所述衬底20的方向上的厚度缩小，以增加晶体管内的电子迁移率。之后，于残留的所述第一区域27和残留的所述第二区域28表面外延生长硅等材料，形成外延层，并通过对所述外延层进行掺杂形成源极区38和漏极区39，如图2P所示。然后，沉积氧化物(例如二氧化硅)等绝缘材料于所述第二开口25和所述第三开口26，形成绝缘介质层36，如图2Q所示。
本具体实施方式还提供了一种三维存储器，附图3是本公开具体实施方式中一三维存储器的结构示意图，附图4是本公开具体实施方式中另一三维存储器的结构示意图。本具体实施方式提供的所述三维存储器可以采用如图1、图2A-图2Q所示的存储器的形成方法形成。本具体实施方式中所述的三维存储器可以是但不限于DRAM。如图2A-图2Q、图3和图4所示，所述三维存储器，包括：
衬底20；
叠层结构，位于所述衬底20上，所述叠层结构包括沿垂直于所述衬底20的顶面的方向平行排布的多个第一半导体层211，所述第一半导体层211中包括多个沿第二方向d-d’平行且间隔排布的有源区，每个所述有源区包括沿第一方向延伸的沟道区域30，所述第一方向a-a’和所述第二方向d-d’均为平行于所述衬底20的顶面的方向，且所述第一方向a-a’与所述第二方向d-d’相交；
字线35，多条所述字线35沿垂直于所述衬底20的顶面的方向平行、且间隔排布，每一条所述字线35连续包覆一个所述第一半导体层211中的所有所述沟道区域30，且每一条所述字线35均沿所述第二方向d-d’延伸；
所述有源区在第二方向d-d’的间隔距离小于其在竖直方向的间隔。
具体来说，在沿所述第二方向d-d’相邻的两个所述沟道区域30之间的间隔距离小于在沿垂直于所述衬底20的顶面的方向上相邻的两个所述沟道区域30之间的间隔距离。
在一些实施例中，所述第一半导体层211中还包括位于所述有源区外部的外围区；所述叠层结构还包括：
第二半导体层212，位于相邻的两层所述第一半导体层211的所述外围区之间；
绝缘介质层36，位于相邻的两层所述第一半导体层211的所述有源区之间。
在一些实施例中，所述三维存储器还包括：隔离层，位于每个所述第一半导体层211中相邻两个所述有源区之间，且沿平行于所述第一方向a-a’的方向延伸。
在一些实施例中，所述绝缘介质层36中还包括位于相邻所述沟道区域30之间的空气隙361。
在一些实施例中，所述三维存储器还包括：
源极区，位于所述第一半导体层211的所述有源区内，且沿所述第一方向a-a’延伸；
漏极区，位于所述第一半导体层211的所述有源区内，且沿所述第一方向a-a’延伸，所述源极区和所述漏极区沿所述第一方向a-a’分布于所述沟道区域30对两侧。
在另一些实施例中，所述三维存储器还包括：
源极区38，位于所述第一半导体层211的表面，在沿垂直于所述衬底20的顶面的方向上，所述源极区38的投影位于所述有源区内；
漏极区39，位于所述第一半导体层211的表面，在沿垂直于所述衬底20的顶面的方向上，所述漏极区39的投影位于所述有源区内，且所述源极区38的投影和所述漏极区39的投影沿所述第一方向a-a’分布于所述沟道区域30的相对两侧。
本具体实施方式提供的三维存储器及其形成方法，通过交替堆叠第一半导体层和第二半导体层形成堆叠层，然后通过刻蚀所述堆叠层形成暴露每个所述第一半导体层中的多个沟道区域的多个第一开口，且限定第二半导体层的厚度大于水平方向上的多个所述第一开口之间的间隙宽度，从而使得在采用原子层沉积工艺沿所述第一开口沉积导电层时，水平方向上的多个所述第一开口内的导电层连接成一条线，从而形成水平字线结构，从而简化了三维存储器的制造工艺，提高了三维存储器的制造良率。另外，水平字线结构还有助于降低所述三维存储器内部的电阻，改善三维存储器的电学性能。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种三维存储器的形成方法，包括如下步骤：
    形成衬底、以及位于所述衬底上的堆叠层，所述堆叠层包括沿垂直于所述衬底的顶面的方向交替堆叠的第一半导体层和第二半导体层，所述第二半导体层的厚度为D1，所述第一半导体层中包括多个沟道区域、以及沿第一方向分布于每一所述沟道区域的相对两侧的第一区域和第二区域，所述第一方向为平行于所述衬底的顶面的方向；
    于所述堆叠层中形成分别暴露多个所述沟道区域的多个第一开口，且在沿第二方向上相邻的两个所述第一开口之间的间隙宽度为D2，D1>D2，所述第二方向为平行于所述衬底的顶面、且与所述第一方向相交的方向；
    采用原子层沉积工艺沿所述第一开口沉积导电层，所述导电层包括包覆所述沟道区域且沿所述第二方向填充相邻所述第一开口之间的间隙。
  2. 根据权利要求1所述的三维存储器的形成方法，其中，形成衬底、以及位于所述衬底上的堆叠层的具体步骤包括：
    形成衬底；
    交替沉积所述第一半导体层和所述第二半导体层于所述衬底表面，形成所述堆叠层；
    刻蚀所述堆叠层，形成多个沿所述第二方向平行排布、其均沿垂直于所述衬底的顶面的方向贯穿所述堆叠层的隔离槽，所述隔离槽将每一个所述第一半导体层分隔为沿所述第二方向平行排布的多个有源区，每一所述有源区包括所述沟道区域、所述第一区域和所述第二区域；
    填充第一绝缘材料于所述隔离槽内，形成隔离层。
  3. 根据权利要求2所述的三维存储器的形成方法，其中，于所述堆叠层中形成分别暴露多个所述沟道区域的多个第一开口之前，还包括如下步骤：
    于所述第二半导体层中形成暴露所述第一区域的第二开口和暴露所述第二区域的第三开口；
    形成填充所述第二开口和所述第三开口的填充层。
  4. 根据权利要求3所述的三维存储器的形成方法，其中，于所述第二半导体层中形成暴露所述第一区域的第二开口和暴露所述第二区域的第三开口的具体步骤包括：
    刻蚀所述隔离层，形成均沿垂直于所述衬底的顶面的方向贯穿所述隔离层的第一刻蚀孔和第二刻蚀孔；
    沿所述第一刻蚀孔和所述第二刻蚀孔刻蚀所述第二半导体层中的部分区域，形成暴露所述第一区域的第二开口和暴露所述第二区域的第三开口。
  5. 根据权利要求4所述的三维存储器的形成方法，其中，形成填充所述第二开口和所述第三开口的填充层之前，还包括如下步骤：
    对所述第二开口的拐角处和所述第三开口的拐角处进行圆角化处理。
  6. 根据权利要求4所述的三维存储器的形成方法，其中，形成填充所述第二开口和所述第三开口的填充层的具体步骤包括：
    填充第二绝缘材料至所述第二开口和所述第三开口，形成所述填充层。
  7. 根据权利要求4所述的三维存储器的形成方法，其中，采用原子层沉积工艺沿所述第一开口沉积导电层之前还包括如下步骤：
    沿所述第一开口氧化所述沟道区域的表面，形成栅极氧化层。
  8. 根据权利要求7所述的三维存储器的形成方法，其中，采用原子层沉积工艺沿所述第一开口沉积导电层的具体步骤包括：
    采用原子层沉积工艺沿所述第一开口沉积导电材料，形成所述导电层，所述导电层包括包覆所述栅极氧化层的第一部分、以及与所述第一部分连接且覆盖所述填充层侧壁的第二部分，在沿所述第二方向上任意相邻的两个所述第一部分连接。
  9. 根据权利要求8所述的三维存储器的形成方法，其中，采用原子层沉积工艺沿所述第一开口沉积导电层之后，还包括如下步骤：
    去除所述填充层、以及所述导电层的所述第二部分，于所述第一区域形成源极区、于所述第二区域形成漏极区，沿所述第二方向连接的多个所述第一部分形成一条字线。
  10. 根据权利要求9所述的三维存储器的形成方法，其中，去除所述填充层、以及所述导电层的所述第二部分之前，还包括如下步骤：
    填充第三绝缘材料于所述堆叠层顶部的所述第一开口内，形成覆盖层。
  11. 根据权利要求9所述的三维存储器的形成方法，其中，去除所述填充层、以及所述导电层的所述第二部分的具体步骤包括：
    去除所述填充层，暴露所述第一区域和所述第二区域；
    去除所述第二部分。
  12. 根据权利要求11所述的三维存储器的形成方法，其中，所述第一半导体层的所述第一区域和所述第二区域中均包括掺杂元素；去除所述填充层，暴露所述第一区域和所述第二区域的具体步骤包括：
    去除所述填充层，暴露的所述第一区域形成源极区、且暴露的所述第二区域形成漏极区。
  13. 根据权利要求11所述的三维存储器的形成方法，其中，去除所述第二部分之后，还包括如下步骤：
    减小所述第一区域和所述第二区域的厚度；
    形成源极区于所述第一区域的表面、并形成漏极区于所述第二区域的表面。
  14. 根据权利要求13所述的三维存储器的形成方法，其中，减小所述第一区域和所述第二区域的厚度的具体步骤包括：
    氧化所述第一区域的表面和所述第二区域的表面，形成氧化层；
    去除所述氧化层。
  15. 一种三维存储器，包括：
    衬底；
    叠层结构，位于所述衬底上，所述叠层结构包括沿垂直于所述衬底的顶面的方向平行排布的多个第一半导体层，所述第一半导体层中包括多个沿第二方向平行且间隔排布的有源区，每个所述有源区包括沿第一方向延伸的沟道区域，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    字线，多条所述字线沿垂直于所述衬底的顶面的方向平行、且间隔排布，每一条所述字线连续包覆一个所述第一半导体层中的所有所述沟道区域，且每一条所述字线均沿所述第二方向延伸；
    所述有源区在第二方向的间隔距离小于其在竖直方向的间隔。
  16. 根据权利要求15所述的三维存储器，其中，所述第一半导体层中还包括位于所述有源区外部的外围区；所述叠层结构还包括：
    第二半导体层，位于相邻的两层所述第一半导体层的所述外围区之间；
    绝缘介质层，位于相邻的两层所述第一半导体层的所述有源区之间。
  17. 根据权利要求15所述的三维存储器，其中，还包括：
    隔离层，位于每个所述第一半导体层中相邻两个所述有源区之间，且沿平行于所述第一方向的方向延伸。
  18. 根据权利要求16所述的三维存储器，其中，所述绝缘介质层中还包括位于相邻所述沟道区域之间的空气隙。
  19. 根据权利要求15所述的三维存储器，还包括：
    源极区，位于所述第一半导体层的所述有源区内，且沿所述第一方向延伸；
    漏极区，位于所述第一半导体层的所述有源区内，且沿所述第一方向延伸，所述源极区和所述漏极区沿所述第一方向分布于所述沟道区域的相对两侧。
  20. 根据权利要求15所述的三维存储器，还包括：
    源极区，位于所述第一半导体层的表面，在沿垂直于所述衬底的顶面的方向上，所述源极区的投影位于所述有源区内；
    漏极区，位于所述第一半导体层的表面，在沿垂直于所述衬底的顶面的方向上，所述漏极区的投影位于所述有源区内，且所述源极区的投影和所述漏极区的投影沿所述第一方向分布于所述沟道区域的相对两侧。
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