WO2023216396A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023216396A1
WO2023216396A1 PCT/CN2022/102679 CN2022102679W WO2023216396A1 WO 2023216396 A1 WO2023216396 A1 WO 2023216396A1 CN 2022102679 W CN2022102679 W CN 2022102679W WO 2023216396 A1 WO2023216396 A1 WO 2023216396A1
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layer
word line
sacrificial layer
initial
semiconductor
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PCT/CN2022/102679
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English (en)
French (fr)
Inventor
邵光速
肖德元
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长鑫存储技术有限公司
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Priority to US17/932,394 priority Critical patent/US11637189B1/en
Publication of WO2023216396A1 publication Critical patent/WO2023216396A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of forming the same.
  • the all-around gate transistor structure When used as a transistor in a dynamic memory, a smaller pattern size can be obtained under given process conditions, which is beneficial to increasing the integration density of the dynamic memory.
  • the word line structure surrounding the channel area of the transistor in a full surround gate transistor is usually formed by processes such as ALD.
  • the morphology of the formed word line structure and the spacing distance between the word line structures depend on the process conditions for forming the word line structure. , but the process conditions for forming the word line structure cannot accurately control the morphology of the word line structure and the spacing distance between adjacent word line structures, which may lead to different morphologies of different word line structures, and between adjacent word line structures. Different spacing distances affect the uniformity of the storage characteristics of dynamic memory.
  • the present disclosure provides a semiconductor structure and a method for forming the same, which is at least beneficial to improving the uniformity of the morphology of the word line structure and the uniformity of the spacing distance between adjacent word line structures.
  • a first aspect of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate and a plurality of spaced-apart stacked structures extending in a first direction on the substrate.
  • the stacked structure includes: in a direction perpendicular to the surface of the substrate
  • a plurality of semiconductor layers are spaced apart on the upper surface of the semiconductor layer, and the opposite top and bottom surfaces of the semiconductor layer each have a first sacrificial layer.
  • the surface of the first sacrificial layer away from the semiconductor layer has a second sacrificial layer, and the same etching process has a first sacrificial layer.
  • the layer and the second sacrificial layer have different etching rates, there is an isolation layer between adjacent stacked structures, and the base includes a word line area; the isolation layer in the word line area is removed to expose the sidewalls of the first sacrificial layer in the word line area.
  • the first sacrificial layer has the same thickness, and the second sacrificial layer has the same thickness.
  • the material of the first sacrificial layer includes doped SiGe; the material of the second sacrificial layer includes undoped SiGe.
  • the process steps of forming the stacked structure and the isolation layer include: forming an initial stacked structure on the surface of the substrate.
  • the initial stacked structure includes: a plurality of initial semiconductor layers spaced apart in a direction perpendicular to the substrate surface, and the top surfaces of the initial semiconductor layers are opposite to each other.
  • a selective epitaxial process is used to form an initial first sacrificial layer, an initial second sacrificial layer and an initial semiconductor layer.
  • the source materials forming the initial first sacrificial layer include silicon source gas, germanium source gas and doping source gas; the source materials forming the initial second sacrificial layer include silicon source gas and germanium source gas.
  • the substrate also includes support areas adjacent to opposite ends of the word line area arranged along the first direction.
  • the isolation layer of the word line area Before removing the isolation layer of the word line area, it also includes: a patterned isolation layer to form multiple isolation layers located in the support area. a first groove, the first groove exposes the first sacrificial layer sidewall and the second sacrificial layer sidewall of the support area; removes the first sacrificial layer and the second sacrificial layer located in the support area; forms a support layer in the support area, The support layer fills the area between adjacent semiconductor layers of the support region.
  • the process steps of forming the etching hole include: removing the support layer of a support area adjacent to the word line area to form a first etching hole; etching and removing the second sacrificial layer exposed by the first etching hole to form The second etching hole is connected with the first etching hole to form an etching hole; forming the word line structure also includes: forming a support layer in the first etching hole.
  • the method further includes: oxidizing the semiconductor layer in the word line region to form an oxide layer to smooth the chamfers of the semiconductor layer in the word line region. ;Remove oxide layer.
  • the method further includes: forming a gate dielectric layer, and the gate dielectric layer covers the surface of the semiconductor layer in the word line region.
  • the method further includes: forming a word line isolation layer, and the word line isolation layer is located between adjacent word line structures.
  • a second aspect of the present disclosure provides a semiconductor structure prepared by using any of the above-mentioned methods for forming a semiconductor structure.
  • the semiconductor structure is formed by using the method for forming a semiconductor structure described in the first aspect.
  • the semiconductor structure includes: a substrate. and a plurality of semiconductor layers arranged at intervals and extending along the first direction on the substrate, and the substrate includes a word line region; a word line structure, the word line structure is located on the semiconductor layer of the word line region, and the word line structure is vertically arranged at intervals in the direction of the substrate surface.
  • the substrate further includes support areas adjacent to opposite ends of the word line area arranged along the first direction, the support area has a support layer, and the support layer is located in a region between adjacent semiconductor layers in the support area.
  • the semiconductor structure further includes: a word line isolation layer, the word line isolation layer is located between adjacent word line structures.
  • the word line structures located on the top or bottom surfaces of different semiconductor layers in the word line region have the same thickness, and the spacing distances between adjacent word line structures in the word line region are the same.
  • 1 to 15 are schematic diagrams of each step of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 16 is a cross-sectional view of a word line region of a semiconductor structure including a chamfered and rounded semiconductor layer according to an embodiment of the present disclosure
  • Figure 17 is a cross-sectional view of a word line region of a semiconductor structure including a gate dielectric layer according to an embodiment of the present disclosure
  • FIG. 18 is a cross-sectional view of a word line region of a semiconductor structure including a word line isolation layer according to an embodiment of the present disclosure.
  • Substrate; 110 Initial stacked structure; 111. Initial semiconductor layer; 112. Initial first sacrificial layer; 113. Initial second sacrificial layer; 120. Stacked structure; 121. Semiconductor layer; 122. First sacrificial layer; 123 , second sacrificial layer; 130, isolation layer; 131, first trench; 140, support layer; 150, initial word line layer; 151, word line structure; 152, word line isolation layer; 160, gate dielectric layer; 170 , first groove; 180, second groove; 190, etching hole; 191, first etching hole; 192, second etching hole; 200, first direction;
  • Embodiments of the present disclosure provide a semiconductor structure and a formation method thereof.
  • the semiconductor layer located in the base word line region stack structure is the channel region of the transistor, and a first sacrificial layer is formed on the top and bottom surfaces of the semiconductor layer.
  • a second sacrificial layer is formed on the surface of the first sacrificial layer away from the semiconductor layer, and after removing the isolation layer between the stacked structures of the word line region, remove the first sacrificial layer on the top surface of the semiconductor layer in the word line region and the first sacrificial layer on the bottom surface of the semiconductor layer.
  • the first sacrificial layer defines the morphology of the initial word line layer
  • the second sacrificial layer is used to define the spacing distance between the initial word line layer on the top or bottom surface of the semiconductor layer and the opposite initial word line layer, forming an initial word line layer with better uniformity. word line layer.
  • the uniformity of the initial word line layer is better, the shape uniformity of the word line structure formed by removing part of the initial word line layer is better, and the uniformity of the spacing distance between adjacent word line structures is better, It is beneficial to improve the electrical performance of semiconductor structures.
  • FIGS. 10 to 15 are schematic diagrams of each step of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 16 is a cross-section of a word line region of a semiconductor structure including a chamfered and rounded semiconductor layer provided by an embodiment of the present disclosure.
  • Figure 17 is a cross-sectional view of a word line region of a semiconductor structure including a gate dielectric layer provided by an embodiment of the present disclosure
  • Figure 18 is a cross-sectional view of a word line region of a semiconductor structure including a word line isolation layer provided by an embodiment of the present disclosure. Sectional view. It should be noted that, for the sake of concise lines, the chamfering and rounding of the semiconductor layer and the gate dielectric layer are not shown in FIGS. 10 to 15 .
  • a method of forming a semiconductor structure includes providing a substrate 100 including a word line region I.
  • the substrate 100 is a silicon substrate.
  • the epitaxial process based on the silicon substrate is relatively mature, which is beneficial to reducing the process difficulty of forming subsequent stacked structures.
  • the material of the substrate 100 can also be a material that can directly enter the manufacturing process to produce semiconductor devices.
  • the material of the substrate 100 can be silicon on insulating substrate (SOI), germanium, silicon carbide, arsenic At least one of materials such as gallium or sapphire.
  • the word line region I of the substrate 100 is the region where the transistor word line structure 151 and the word line isolation layer 152 between the word line structures 151 are formed. It should be noted that the semiconductor channel in the word line region I is the channel region of the transistor surrounded by word line structure 151.
  • the transistor may be a full-surround gate transistor. The full-surround gate transistor can obtain the smallest pattern size under given process conditions, which is beneficial to increasing the integration density of the semiconductor structure.
  • a plurality of stacked structures 120 are also provided on the substrate 100 .
  • the stacked structures 120 extend along the first direction 200 and are arranged at intervals on the substrate 100 .
  • the stacked structures 120 include: spaced apart structures in a direction perpendicular to the surface of the substrate 100 .
  • a plurality of semiconductor layers 121, and the opposite top and bottom surfaces of the semiconductor layer 121 each have a first sacrificial layer 122, and the surface of the first sacrificial layer 122 away from the semiconductor layer 121 has a second sacrificial layer 123, and the same etching process has A sacrificial layer 122 and a second sacrificial layer 123 have different etching rates, and an isolation layer 130 is provided between adjacent stack structures 120 .
  • the first direction 200 is any direction parallel to the surface of the substrate 100.
  • the stacked structure 120 extending along the first direction 200 includes: spaced apart structures along the first direction that are arranged perpendicular to the surface of the substrate 100.
  • the 200 extends a plurality of semiconductor layers 121, the semiconductor layer 121 is used to form a semiconductor channel, the top and bottom surfaces of the semiconductor layer 121 are provided with a first sacrificial layer 122, the first sacrificial layer 122 determines the subsequent transistor channel region provided on the semiconductor channel The morphology of the word line structure 151.
  • a second sacrificial layer 123 is provided on the surface of the first sacrificial layer 122 away from the semiconductor layer 121. The second sacrificial layer 123 can determine the spacing distance between the word line structures 151.
  • the topography of the word line structure 151 and the spacing distance between adjacent word line structures 151 can be controlled, and the uniformity of the semiconductor layer 121, the first sacrificial layer 122 and the second sacrificial layer 123 in the stacked structure 120 can be improved. Improving the uniformity of the word line structure 151 is beneficial to improving the electrical performance of the semiconductor structure.
  • the first sacrificial layer 122 and the second sacrificial layer 123 have different etching rates under the same conditions. In the subsequent process of forming the word line structure 151, different etching processes can be used to remove the first sacrificial layer 122 and the second sacrificial layer 123 respectively.
  • the second sacrificial layer 123 is used to form a uniform word line structure 151 .
  • the isolation layer 130 extending along the first direction 200 between the stacked structures 120 is used to assist in forming the subsequent word line structure 151 .
  • the isolation layer 130 may be made of a common isolation material, such as silicon oxide.
  • the first sacrificial layer 122 has the same thickness and the second sacrificial layer 123 has the same thickness.
  • the first sacrificial layer 122 with the same thickness can make the word line structure 151 on the top or bottom surface of the subsequently formed semiconductor layer 121 have the same thickness, which is beneficial to improving the uniformity of the word line structure 151 .
  • the second sacrificial layer 123 with the same thickness can make the spacing distance between adjacent word line structures 151 formed subsequently the same, improve the uniformity of the distribution position of the word line structures 151, and thereby help improve the electrical performance of the semiconductor structure.
  • the process steps of forming the stacked structure 120 and the isolation layer 130 in the above embodiments may include: forming an initial stacked structure 110 on the surface of the substrate 100 , and the initial stacked structure 110 includes: vertically A plurality of initial semiconductor layers 111 are spaced apart in the surface direction of the substrate 100, and the opposite top and bottom surfaces of the initial semiconductor layer 111 each have an initial first sacrificial layer 112, and the surface of the initial first sacrificial layer 112 away from the initial semiconductor layer 111 is There is an initial second sacrificial layer 113; the initial stack structure 110 is patterned to form a plurality of mutually independent stack structures 120; an isolation layer 130 is formed between adjacent stack structures 120.
  • an initial stack structure 110 is formed on the substrate 100 , and the initial stack structure 110 is patterned to form a stack structure 120 .
  • the initial semiconductor layer 111 with a uniform thickness and a uniform thickness can be formed.
  • the initial first sacrificial layer 112 and the initial second sacrificial layer 113 with uniform thickness, the initial semiconductor layer 111 in the initial stack structure 110 are used to form the semiconductor layer 121, and the semiconductor layer 121 is used to form the semiconductor channel of the transistor, ensuring the initial stack structure 110
  • the uniformity of the thickness of the semiconductor layer 121 can ensure the uniformity of the semiconductor channels of the transistors formed on the substrate 100.
  • the thickness of the initial first sacrificial layer 112 in the initial stack structure 110 defines the thickness of the first sacrificial layer 122.
  • the thickness of layer 122 determines the morphology of the subsequently formed word line structure 151.
  • Forming the initial first sacrificial layer 112 with better thickness uniformity is beneficial to forming the word line structure 151 with better morphology uniformity; the initial second sacrificial layer 113
  • the thickness uniformity of the second sacrificial layer 123 determines the thickness uniformity of different second sacrificial layers 123.
  • the second sacrificial layer 123 with better thickness uniformity can make the spacing distance between the word line structures 151 the same, which is beneficial to forming a uniformly arranged word line structure. 151.
  • the word line structure 151 with uniform arrangement and uniform shape is beneficial to improving the electrical performance of the semiconductor structure.
  • the material of the initial semiconductor layer 111 is silicon. On the basis of silicon, epitaxial processes can be used to form materials with various properties, which is conducive to the simple preparation of the first sacrificial layer 122 and the second sacrificial layer 122 based on silicon. Layer 123 reduces the manufacturing difficulty of the initial stacked structure 110 .
  • the initial semiconductor layer 111 can also be other semiconductor channel materials, such as IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide, Indium Tungsten Oxide) or ITO (Indium Oxide) Tin (Indium Tin Oxide) is one of the above materials. When the semiconductor channel is composed of the above materials, it is beneficial to increase the mobility of carriers in the semiconductor channel, thereby helping the semiconductor channel to efficiently transmit electrical signals.
  • the material of the first sacrificial layer 122 includes doped SiGe; the material of the second sacrificial layer 123 includes undoped SiGe. Then the initial first sacrificial layer 112 is a doped SiGe layer, and the initial second sacrificial layer 113 is an undoped SiGe layer.
  • the initial first sacrificial layer 112 and the initial second sacrificial layer 113 are made of the above materials, there are mainly the following aspects: Advantages: On the one hand, doped SiGe and undoped SiGe have different etching rates under the same conditions, so they can be used as the subsequent first sacrificial layer 122 and the second sacrificial layer 123 respectively to assist in forming a uniform The word line structure 151 (refer to Figure 15); on the other hand, the difference between doped SiGe and undoped SiGe lies in whether they are doped.
  • the SiGe layer can be directly formed, and then the partial thickness of the SiGe layer in the direction away from the substrate 100 can be doped to form the initial first sacrificial layer 112 and the initial second sacrificial layer 113 respectively.
  • the method of performing partial doping to form the initial first sacrificial layer 112 and the initial second sacrificial layer 113 is beneficial to reducing the manufacturing difficulty of the initial stacked structure 110 .
  • a selective epitaxial process is used to form the initial first sacrificial layer 112 , the initial second sacrificial layer 113 and the initial semiconductor layer 111 .
  • the initial stack structure 110 is formed through a selective epitaxial process, so that the thermal expansion coefficients of the initial first sacrificial layer 112, the initial second sacrificial layer 113, the initial semiconductor layer 111 and the substrate 100 can be close and the lattice coefficients can match, thereby making the adjacent ones
  • the thermal expansion coefficients between the film layers are close and the lattice coefficients match, which can avoid stress changes caused by temperature changes and stress mismatch caused by lattice mismatch, which in turn helps avoid the interface between different film layers caused by stress mismatch.
  • the misalignment phenomenon and even the cracking of the film layer improve the flatness of each film layer in the initial stacked structure 110 and the flatness of the substrate 100 .
  • selective epitaxy is used to form the initial stack structure 110 to form the stack structure 120 and the isolation layer 130.
  • the specific steps may be: with reference to Figures 2, 3, and 4, the substrate 100 is placed in the epitaxial reaction chamber. , pass the source material of the initial second sacrificial layer 113 into the epitaxial reaction chamber, and form an initial second sacrificial layer 113 of a certain thickness on the surface of the substrate 100; place the substrate 100 with the initial second sacrificial layer 113 formed in the epitaxial reaction chamber.
  • the source material of the initial first sacrificial layer 112 is passed into the epitaxial reaction chamber, and an initial first sacrificial layer 112 with a certain thickness is formed on the surface of the initial second sacrificial layer 113 away from the substrate 100; an initial second sacrificial layer 112 will be formed.
  • Layer 113 and the substrate 100 of the initial first sacrificial layer 112 are placed in an epitaxial reaction chamber.
  • the source material of the initial semiconductor layer 111 is introduced into the epitaxial reaction chamber, and an initial layer of a certain thickness is formed on the surface of the first sacrificial layer 122 away from the substrate 100 .
  • the remaining initial stack structure is sequentially formed on the surface of the formed initial semiconductor layer 111 away from the substrate 100 110 film layers to form an initial stack structure 110.
  • a first mask layer including a first etching window is formed on the surface of the initial stacked structure 110 away from the substrate 100 , and the initial stacked structure 110 exposed by the first etching window is removed to form a plurality of stacked structures 120 and adjacent stacked structures 120 .
  • an isolation layer 130 is formed in the first trench 131 by deposition or other methods.
  • the source material used to form the initial first sacrificial layer 112 may be different from the one used to form the first sacrificial layer 112 .
  • the initial source materials of the second sacrificial layer 113 are different, thereby forming the first sacrificial layer 122 and the second sacrificial layer 123 with different properties.
  • the source material used to form the initial first sacrificial layer 112 is completely different from the source material used to form the initial second sacrificial layer 113, it will result in the chamber forming the initial first sacrificial layer 112 being different from the chamber used to form the initial second sacrificial layer 113.
  • the source material forming the initial first sacrificial layer 112 may be partially, but not completely, the same as the source material forming the initial second sacrificial layer 113 Similarly, different source materials can be doping materials.
  • the preparation process with a high degree of similarity of the source materials makes the chamber for forming the initial first sacrificial layer 112 and the chamber for forming the initial second sacrificial layer 113 compatible with each other to avoid adding additional components. Preparation equipment will help reduce the cost of preparing semiconductor structures.
  • the source material forming the initial first sacrificial layer 112 includes silicon source gas, germanium source gas and doping source gas; the source material forming the initial second sacrificial layer 113 includes silicon source gas and germanium source gas.
  • the initial first sacrificial layer 112 formed using silicon source gas, germanium source gas and doping source gas is a doped SiGe layer, and the initial second sacrificial layer 113 formed using silicon source gas and germanium source gas is undoped SiGe.
  • the etching rates of the doped SiGe layer and the undoped SiGe layer are different under the same conditions, and the silicon source gas and the germanium source gas are used to form the chamber of the initial first sacrificial layer 112, and the silicon source gas is used.
  • the chambers in which the germanium source gas is used to form the initial second sacrificial layer 113 can be compatible with each other, which avoids adding additional preparation equipment and helps reduce preparation costs.
  • the substrate 100 further includes support regions II adjacent to opposite ends of the word line region I arranged along the first direction 200 , and the isolation layer of the word line region I is removed.
  • 130 also includes: patterning the isolation layer 130 to form a plurality of first grooves 170 located in the support region II, the first grooves 170 exposing the first sacrificial layer 122 sidewalls and the second sacrificial layer 123 side of the support region II wall; remove the first sacrificial layer 122 and the second sacrificial layer 123 located in the support region II; form a support layer 140 in the support region II, and the support layer 140 fills the area between adjacent semiconductor layers 121 in the support region II.
  • the support region II is a region where the support layer 140 is provided.
  • the support layer 140 located between adjacent semiconductor layers 121 in the support region II supports the semiconductor layer 121 located in the support region II, and thereby provides the support layer 140 on the substrate 100 .
  • the semiconductor layer 121 provides support, which is beneficial to improving the stability of the semiconductor structure.
  • the step of forming the support layer 140 may be to form a second mask layer on the substrate 100 including the isolation layer 130 and the stacked structure 120 .
  • the second mask layer includes a third mask layer exposing the isolation layer 130 in the support region II. Two etching windows are used to remove the isolation layer 130 of the support region II through the second etching window. Referring to FIG.
  • first grooves 170 are formed, and the bottom of each first groove 170 exposes the substrate 100; due to the first sacrificial layer 122 and the second sacrificial layer 123 are made of different materials from the semiconductor layer 121.
  • an etching process with a high etching selectivity for the first sacrificial layer 122 and the second sacrificial layer 123 is used to remove the first groove.
  • the first sacrificial layer 122 and the second sacrificial layer 123 located in the support region II are exposed on the sidewalls of the trench 170, the semiconductor layer 121 in the support region II is retained, and the second mask is removed to form the semiconductor structure shown in FIG. 6. Referring to FIG.
  • a support layer 140 is formed in the area between adjacent semiconductor layers 121 in the support region II.
  • a deposition process is used to form the support layer 140 .
  • the support layer 140 is made of silicon nitride, and silicon nitride has a relatively high hardness. High, it can provide good support for semiconductor structures.
  • the method of forming the semiconductor structure further includes removing the isolation layer 130 of the word line region I to expose the first sacrificial layer 122 sidewalls and the second sacrificial layer 123 of the word line region I.
  • the specific steps of removing the isolation layer 130 in the word line region I may be: forming a third mask layer on the surface of the stack structure 120 away from the substrate 100 and the surface of the support layer 140 away from the substrate 100 outside the isolation layer 130 in the word line region I.
  • the third mask layer includes a third etching window that exposes the isolation layer 130 of the word line region I, and the isolation layer 130 exposed by the third etching window is etched away to form a second groove 180 .
  • the bottom of the second groove 180 exposes the substrate 100
  • the sidewalls of the second groove 180 expose the sidewalls of the first sacrificial layer 122 and the second sacrificial layer 123 of the word line region I stack structure 120 .
  • the second sacrificial layer 122 is removed.
  • the groove 180 exposes the first sacrificial layer 122 in the word line region I, and the third mask is removed to form the semiconductor structure shown in FIG. 9 .
  • the method further includes: oxidizing the semiconductor layer 121 in the word line region I.
  • An oxide layer (not shown in the figure) is formed by processing to smooth the chamfer of the semiconductor layer 121 located in the word line region I; the oxide layer is removed.
  • the semiconductor layer 121 has a rectangular columnar structure. Referring to FIG.
  • the rounded chamfering of the semiconductor layer 121 can make the corners formed by the adjacent surfaces of the semiconductor layer 121 in the word line region I form rounded corners, which is beneficial to This avoids tip discharge or current leakage in the semiconductor layer 121 serving as a semiconductor channel, and improves the electrical performance of the semiconductor structure.
  • the semiconductor layer 121 may also have a cylindrical structure, an elliptical columnar structure, a cubic columnar structure or other irregular structures. It can be understood that when the semiconductor layer 121 has a cubic columnar structure, the corners formed by the adjacent side walls of the cubic columnar structure can be rounded corners, which can also avoid the problem of tip discharge.
  • the method further includes: forming a gate dielectric layer 160 , and the gate dielectric layer 160 covers the surface of the semiconductor layer 121 in the word line region I. That is to say, the gate dielectric layer 160 is arranged around the semiconductor layer 121 of the word line region I.
  • the material of the gate dielectric layer 160 can be one of silicon oxide, silicon nitride, silicon oxynitride or other high dielectric constant dielectric materials. kind.
  • the method of forming a semiconductor structure further includes forming an initial word line layer 150 in the word line region I, the initial word line layer 150 filling the area between the second sacrificial layer 123 and the semiconductor layer 121 , and further The area between adjacent semiconductor layers 121 is filled.
  • the material of the initial word line layer 150 may be one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten or aluminum.
  • the specific steps of forming the initial word line layer 150 may be to form an initial word on the surface of the semiconductor layer 121 of the word line region I through an ALD deposition process, that is, the gate dielectric layer 160 of the semiconductor layer 121 of the word line region I on the surface away from the semiconductor layer 121.
  • the line layer 150 and the initial word line layer 150 fill the area between the second sacrificial layer 123 and the gate dielectric layer 160 of the semiconductor layer 121 , and fill the area between the gate dielectric layer 160 of the adjacent semiconductor layer 121 .
  • the initial word line layer 150 and the uniform initial word line layer 150 are beneficial to forming a uniform word line structure.
  • the method of forming the semiconductor structure further includes: removing the second sacrificial layer 123 in the word line region I to form an etching hole 190 , and removing the second sacrificial layer 123 in the word line region I.
  • the etching holes 190 formed by the two sacrificial layers 123 provide a basis for removing part of the initial word line layer 150.
  • the sizes of the etching holes 190 in the word line area I are exactly the same.
  • the spacing distance between adjacent word line structures 151 is also exactly the same, which is beneficial to improving the uniformity of the word line structure 151.
  • the process steps of forming the etching hole 190 may include: removing the support layer 140 of a support region II adjacent to the word line region I to form a first etching hole 191 ;
  • the second sacrificial layer 123 exposed by the first etching hole 191 is etched away to form a second etching hole 192.
  • the second etching hole 192 communicates with the first etching hole 191 to form the etching hole 190. Since it is difficult to directly remove the second sacrificial layer 123 covered by the initial word line layer 150, this embodiment proposes a method of removing the support layer 140 on either side of the word line area I.
  • the support layer 140 can expose the second sacrificial layer 123 in the word line region I, leaving the support layer 140 on the other side to provide support for the semiconductor structure, which not only reduces the difficulty of removing the second sacrificial layer 123 but also ensures the stability of the semiconductor structure.
  • the specific steps of forming the first etching hole 191 may be: after forming the initial word line layer 150, forming a fourth mask layer (not shown in the figure).
  • the fourth mask layer includes exposing each word line region I
  • the fourth etching window of the support area II on either side is etched to remove the support layer 140 of the support area II exposed by the fourth etching window to form the first etching hole 191 shown in Figure 11.
  • the first etching hole 191 The second sacrificial layer 123 of the word line region I is exposed.
  • the specific steps of forming the second etching hole 192 may include: selecting an etching condition with a higher etching rate for the second sacrificial layer 123 through the first etching hole 191 to remove the second sacrificial layer 123 of the word line region I to form
  • the second etching hole 192 is located in the word line area I as shown in FIG. 12 .
  • the second etching hole 192 is connected with the first etching hole 191 to form an etching hole 190 .
  • the first etching hole 191 also exposes the first sacrificial layer 122 and the second sacrificial layer 123 outside the support area II and the word line area I, that is, the first sacrificial layer in the area on the side of the support area II away from the word line area I 122 and the second sacrificial layer 123.
  • the first sacrificial layer 122 and the second sacrificial layer 123 in the area outside the support area II and the word line area I need to be removed when forming subsequent semiconductor structures, so the second sacrificial layer 122 in the word line area I is removed.
  • the first sacrificial layer 122 and the second sacrificial layer 123 in the area other than the support area II and the word line area I exposed by the first etching hole 191 can also be removed to form the semiconductor structure shown in FIG. 12.
  • the method of forming the semiconductor structure further includes: etching and removing the portion of the initial word line layer 150 exposed by the etching holes 190 to form spaced rows along the direction perpendicular to the surface of the substrate 100 .
  • the initial word line layer 150 between the inner walls of the second etching hole 192 perpendicular to the surface of the substrate 100 is removed.
  • a portion of the thickness of the initial word line layer 150 is removed in the surface direction to form a plurality of word line structures 151 spaced apart in a direction perpendicular to the surface of the substrate 100 .
  • the word line structure 151 may extend along a second direction parallel to the surface of the substrate 100 and perpendicular to the first direction 200.
  • a row of semiconductor layers 121 spaced along the second direction in the word line region I share a word line. Line structure151.
  • forming the word line structure 151 further includes forming a support layer 140 in the first etching hole 191 .
  • the first etching hole 191 formed in the previous embodiment is to expose the second sacrificial layer 123 and remove the second sacrificial layer 123.
  • the first etching hole 191 can be refilled with a supporting material to form a support.
  • Layer 140 improves the stability of the semiconductor structure.
  • the method further includes removing the remaining first sacrificial layer 122 and the second sacrificial layer 123 to obtain the semiconductor structure shown in FIG. 15 .
  • the method further includes: forming a word line isolation layer 152 , the word line isolation layer 152 being located between adjacent word line structures 151 .
  • the word line isolation layer 152 not only provides support for the word line structure 151, making the semiconductor structure more stable, but also forms good isolation between adjacent word line structures 151, which is beneficial to reducing parasitics between adjacent word line structures 151. Capacitance, which improves the electrical performance of semiconductor structures.
  • the air gaps between the word line structures 151 are used as the word line isolation layers 152 .
  • Using the air gap between the word line structures 151 as the word line isolation layer 152 not only reduces the difficulty of filling the isolation material, but also helps reduce the parasitic capacitance between adjacent word line structures 151 and improves the heat dissipation of the semiconductor structure. performance.
  • the stacked structures 120 arranged at intervals include a plurality of semiconductor layers 121, an isolation layer 130 is provided between adjacent stacked structures 120, and a third layer is provided on the top and bottom surfaces of the semiconductor layer 121.
  • a second sacrificial layer 123 is provided on the surface of the first sacrificial layer 122 away from the semiconductor layer 121.
  • the semiconductor layer 121 in the stacked structure 120 of the word line region I of the substrate 100 is the channel region of the transistor. The word line is removed.
  • the isolation layer 130 is formed between the stacked structures 120 in the word line region I, the first sacrificial layer 122 on the top surface and the first sacrificial layer 122 on the bottom surface of the semiconductor layer 121 in the word line region I are removed, and the first sacrificial layer 122 on the bottom surface of the semiconductor layer 121 in the word line region I is removed.
  • the initial word line layer 150 is formed by using the first sacrificial layer 122 between the semiconductor layer 121 and the second sacrificial layer 123 and the area between the second sacrificial layer 123 and the adjacent semiconductor layer 121 in the word line region I
  • the topography of the initial word line layer 150 is defined, and the second sacrificial layer 123 is used to define the distribution position of the initial word line structure 151, thereby forming the initial word line layer 150 with a uniform topography.
  • a word line structure 151 with uniform arrangement and uniform shape is formed.
  • the uniform word line structure 151 is conducive to improving the electrical performance of the semiconductor structure.
  • embodiments of the present disclosure also provide a semiconductor structure, which can be formed by the method for forming a semiconductor structure provided in the above embodiments. It should be noted that for parts that are the same as or corresponding to the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments and will not be described in detail below.
  • the semiconductor structure includes: a substrate 100 and a plurality of spaced-apart semiconductor layers 121 extending along the first direction 200 on the substrate 100 , and the substrate 100 includes a word line region I; a word line structure 151 , a word line
  • the structures 151 are located on the semiconductor layer 121 in the word line region I, and the word line structures 151 are spaced apart in a direction perpendicular to the surface of the substrate 100 .
  • the semiconductor layer 121 may be a semiconductor channel of a full surround gate transistor.
  • the semiconductor layer 121 located in the word line region I is a channel region of the full surround gate transistor.
  • the semiconductor layer 121 located outside the word line region I includes a full surround gate transistor.
  • the first direction 200 can be any direction parallel to the surface of the substrate 100, and the word line structure 151 is arranged around the channel region. 4 to 13 , the word line structure 151 is formed by the formation method of sequentially removing the first sacrificial layer 122 and the second sacrificial layer 123 in the previous embodiment. Therefore, the morphology differences of different word line structures 151 are relatively small. Small, the difference in spacing distance between different word line structures 151 and adjacent word line structures 151 is small, that is, the uniformity of the word line structures 151 is better, and the uniform word line structure 151 is conducive to improving the electrical performance of the semiconductor structure.
  • the substrate 100 further includes a support region II adjacent to opposite ends of the word line region I arranged along the first direction 200 .
  • the support region II has a support layer 140 .
  • the support layer 140 A region located between adjacent semiconductor layers 121 in the support region II.
  • the support layer 140 provides support for the semiconductor layer 121 on the substrate 100, which is beneficial to improving the stability of the semiconductor structure.
  • the semiconductor structure includes: a word line isolation layer 152 located between adjacent word line structures 151 .
  • the word line isolation layer 152 provides support for the semiconductor structure, making the semiconductor structure more stable; on the other hand, the word line isolation layer 152 forms good isolation between adjacent word line structures 151, which is beneficial to reducing the risk of adjacent word lines.
  • the parasitic capacitance between the line structures 151 improves the electrical performance of the semiconductor structure.
  • the thickness of the word line structures 151 located on the top or bottom surfaces of different semiconductor layers 121 in the word line region I is the same, and the spacing distance between adjacent word line structures 151 in the word line region I is the same. That is, the shapes of different word line structures 151 are the same, the spacing distances between different word line structures 151 and adjacent word line structures 151 are the same, the uniformity of the word line structures 151 is better, and the uniform word line structures 151 are conducive to improving the performance of the word line structure 151 . Electrical properties of semiconductor structures.
  • a plurality of semiconductor layers 121 are provided on the substrate 100.
  • the word line structure 151 surrounding the multiple semiconductor layers 121 in the word line region I is formed by the formation method of the semiconductor structure provided in the above embodiment. , therefore, the difference in morphology of different word line structures 151 is small, and the difference in spacing distance between different word line structures 151 and adjacent word line structures 151 is small, that is, the uniformity of word line structures 151 is good and uniform.
  • the word line structure 151 is beneficial to improving the electrical performance of the semiconductor structure.
  • the semiconductor layer in the stacked structure on the base word line region is the channel region of the transistor, and a first sacrificial layer is formed on the top and bottom surfaces of the semiconductor layer.
  • a sacrificial layer is formed away from the surface of the semiconductor layer to form a second sacrificial layer, the isolation layer between the stacked structures in the word line area is removed, and different etchings between materials with different properties of the semiconductor layer, the first sacrificial layer and the second sacrificial layer are used.
  • the first sacrificial layer on the top surface of the semiconductor layer in the word line region and the first sacrificial layer on the bottom surface, so that the area between the semiconductor layer and the second sacrificial layer in the word line region, the adjacent semiconductor in the word line region
  • the area between the layers forms the initial word line layer, that is, the first sacrificial layer between the semiconductor layer and the second sacrificial layer is used to define the topography of the initial word line layer, and the second sacrificial layer is used to define the initial shape of the top or bottom surface of the semiconductor layer.
  • the spacing distance between the word line structure and the corresponding initial word line structure forms a uniform initial word line layer. Due to the good uniformity of the initial word line layer, the uniformity of the word line structure formed by removing part of the initial word line layer is also good, which improves the uniformity of the shape of the word line structure and the spacing distance between adjacent word line structures. uniformity.

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Abstract

本公开提供一种半导体结构及其形成方法，涉及半导体技术领域，形成方法包括：提供基底以及在基底上的多个间隔排布的沿第一方向延伸的堆叠结构，堆叠结构包括：在垂直于基底表面方向上间隔设置的多个半导体层，且半导体层相对的顶面和底面均具有第一牺牲层，第一牺牲层远离半导体层的表面均具有第二牺牲层，同一刻蚀工艺对第一牺牲层与第二牺牲层具有不同的刻蚀速率，相邻的堆叠结构之间具有隔离层，基底包括字线区；去除字线区的隔离层以及第一牺牲层；在字线区形成初始字线层；去除位于字线区的第二牺牲层；刻蚀孔露出的部分初始字线层，以形成多个字线结构。

Description

半导体结构及其形成方法
本公开基于申请号为202210494628.6、申请日为2022年05月07日、申请名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其形成方法。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，对动态存储器阵列结构中晶体管的排布方式以及晶体管尺寸产生了更高的要求。
全环绕栅极晶体管结构作为动态存储器中的晶体管时，可在给定工艺条件下可获得较小的图案尺寸，有利于增加动态存储器的集成密度。目前全环绕栅极晶体管中围绕在晶体管沟道区的字线结构通常采用ALD等工艺形成，形成的字线结构的形貌以及字线结构之间的间隔距离取决于形成字线结构的工艺条件，但形成字线结构的工艺条件无法精准的控制字线结构的形貌和相邻字线结构之间的间隔距离，可能导致不同字线结构的形貌不同，以及相邻字线结构之间间隔距离不同，影响动态存储器存储特性的均一性。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构及其形成方法，至少有利于改善字线结构的形貌均匀性以及相邻字线结构之间间隔距离的均匀性。
本公开的第一方面提供了一种半导体结构的形成方法，包括：提供基底以及位于基底上的多个间隔排布的沿第一方向延伸的堆叠结构，堆叠结构包括：在垂直于基底表面方向上间隔设置的多个半导体层，且半导体层相对的顶面和底面均具有第一牺牲层，第一牺牲层远离半导体层的表面均具有第二牺牲层，且同一刻蚀工艺对第一牺牲层与第二牺牲层具有不同的刻蚀速率，相邻的堆叠结构之间具有隔离层，基底包括字线区；去除字线区的隔离层，以露出字线区的第一牺牲层侧壁和第二牺牲层侧壁；去除字线区的第一牺牲层；在字线区形成初始字线层，初始字线层填充第二牺牲层与半导体层之间的区域，且还填充相邻半导体层之间的区域；去除位于字线区的第二牺牲层，以形成刻蚀孔；去除刻蚀孔露出的部分初始字线层，以形成在沿垂直于基底表面方向间隔排布的多个字线结构。
其中，第一牺牲层的厚度相同，第二牺牲层的厚度相同。
其中，第一牺牲层的材料包括掺杂的SiGe；第二牺牲层的材料包括未掺杂的SiGe。
其中，形成堆叠结构以及隔离层的工艺步骤包括：在基底表面形成初始堆叠结构，初始堆叠结构包括：在垂直于基底表面方向上间隔设置的多个初始半导体层，且初始半导体层相对的顶面和底面均具有初始第一牺牲层，初始第一牺牲层远离初始半导体层的表面均具有初始第二牺牲层；图形化初始堆叠结构，形成多个相互分立的堆叠结构；在相邻的堆叠结构之间形成隔离层。
其中，采用选择性外延工艺，形成初始第一牺牲层、初始第二牺牲层以及初始半导体层。
其中，形成初始第一牺牲层的源材料包括硅源气体、锗源气体以及掺杂源气体；形成初始第二牺牲层的源材料包括硅源气体以及锗源气体。
其中，基底还包括分别与字线区沿第一方向排布的相对两端相邻接的支撑区，去除字线区的隔离层之前还包括：图形化隔离层，以形成位于支撑区的多个第一凹槽， 第一凹槽露出支撑区的第一牺牲层侧壁和第二牺牲层侧壁；去除位于支撑区的第一牺牲层以及第二牺牲层；在支撑区形成支撑层，支撑层填充位于支撑区的相邻半导体层之间的区域。
其中，形成刻蚀孔的工艺步骤包括：去除与字线区相邻接的一支撑区的支撑层，形成第一刻蚀孔；刻蚀去除第一刻蚀孔露出的第二牺牲层，形成第二刻蚀孔，第二刻蚀孔与第一刻蚀孔相连通构成刻蚀孔；形成字线结构后还包括：在第一刻蚀孔内形成支撑层。
其中，去除字线区的第一牺牲层后，形成初始字线层前还包括：对字线区的半导体层进行氧化处理形成氧化层，以使位于字线区的半导体层的倒角圆滑化；去除氧化层。
其中，去除氧化层之后，还包括：形成栅介质层，栅介质层覆盖字线区半导体层表面。
其中，在形成字线结构之后，还包括：形成字线隔离层，字线隔离层位于相邻的字线结构之间。
本公开的第二方面提供了一种采用上述任一半导体结构的形成方法制备形成的半导体结构，所述半导体结构为采用第一方面所述的半导体结构的形成方法形成的，半导体结构包括：基底以及位于基底上多个间隔排布的沿第一方向延伸的多个半导体层，且基底包括字线区；字线结构，字线结构位于字线区的半导体层上，且字线结构沿垂直于基底表面方向间隔排布。
其中，基底还包括分别与字线区沿第一方向排布的相对两端相邻接的支撑区，支撑区具有支撑层，支撑层位于支撑区相邻半导体层之间的区域。
其中，所述半导体结构还包括：字线隔离层，字线隔离层位于相邻的字线结构之间。
其中，位于字线区的不同半导体层顶面或底面的字线结构的厚度相同，字线区的相邻的字线结构之间的间隔距离相同。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1至图15为本公开实施例提供的一种半导体结构的形成方法的各步骤示意图；
图16为本公开实施例提供的一种包括倒角圆滑化半导体层的半导体结构字线区的剖面图；
图17为本公开实施例提供的一种包括栅介质层的半导体结构字线区的剖面图；
图18为本公开实施例提供的一种包括字线隔离层的半导体结构字线区的剖面图。
附图标记：
100、基底；110、初始堆叠结构；111、初始半导体层；112、初始第一牺牲层；113、初始第二牺牲层；120、堆叠结构；121、半导体层；122、第一牺牲层；123、第二牺牲层；130、隔离层；131、第一沟槽；140、支撑层；150、初始字线层；151、字线结构；152、字线隔离层；160、栅介质层；170、第一凹槽；180、第二凹槽；190、刻蚀孔；191、第一刻蚀孔；192、第二刻蚀孔；200、第一方向；
I、字线区；II、支撑区。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整 地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，目前形成字线结构的工艺条件无法精准的控制字线结构的形貌和相邻字线结构之间的间隔距离，可能导致不同字线结构的形貌不同，以及相邻字线结构之间间隔距离不同，影响半导体结构的电学性能。
本公开实施例提供了一种半导体结构及其形成方法，形成方法中，位于基底字线区堆叠结构中的半导体层为晶体管的沟道区，在半导体层的顶面和底面形成第一牺牲层，在第一牺牲层远离半导体层的表面形成第二牺牲层，去除字线区的堆叠结构之间的隔离层后，去除字线区的半导体层顶面的第一牺牲层和底面的第一牺牲层，并在字线区的半导体层和第二牺牲层之间的区域、字线区的相邻半导体层之间的区域形成初始字线层，利用半导体层与第二牺牲层之间的第一牺牲层定义初始字线层的形貌，利用第二牺牲层定义半导体层顶面或底面的初始字线层与相对的初始字线层之间的间隔距离，形成均匀性较优的初始字线层。由于初始字线层的均匀性较好，使得通过去除部分初始字线层形成的字线结构的形貌均匀性较好，以及使得相邻字线结构之间的间隔距离的均匀性较好，有利于提高半导体结构的电学性能。
下面将结合附图对本公开各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
图1至图15为本公开实施例提供的一种半导体结构的形成方法的各步骤示意图；图16为本公开实施例提供的一种包括倒角圆滑化半导体层的半导体结构字线区的剖面图；图17为本公开实施例提供的一种包括栅介质层的半导体结构字线区的剖面图；图18为本公开实施例提供的一种包括字线隔离层的半导体结构字线区的剖面图。需要说明的是，为了线条简洁，图10至图15中未示出对半导体层的倒角圆滑化以及栅介质层。
参考图1，半导体结构的形成方法包括：提供基底100，基底100包括字线区I。
在一些实施例中，基底100为硅基底，基于硅基底的外延工艺较成熟，有利于降低形成后续堆叠结构的工艺难度。在另一些实施例中，基底100的材料也可以为可直接进入制造环节的生产半导体器件的材料，例如，基底100的材料可以为绝缘衬底上的硅(SOI)、锗、碳化硅、砷化镓或者蓝宝石等材料中的至少一种。
参考图15、图18，基底100的字线区I为形成晶体管字线结构151以及形成字线结构151之间的字线隔离层152的区域，需要说明的是，字线区I的半导体通道为被字线结构151环绕的晶体管的沟道区。晶体管可以为全环绕栅极晶体管，全环绕栅极晶体管可在给定的工艺条件下可获得最小的图案尺寸，有利于提高半导体结构的集成密度。
参考图4，基底100上还设置有多个堆叠结构120，堆叠结构120沿第一方向200延伸且在基底100上间隔排布，堆叠结构120包括：在垂直于基底100表面方向上间隔设置的多个半导体层121，且半导体层121相对的顶面和底面均具有第一牺牲层122，第一牺牲层122远离半导体层121的表面均具有第二牺牲层123，且同一刻蚀工艺对第一牺牲层122与第二牺牲层123具有不同的刻蚀速率，相邻的堆叠结构120之间具有隔离层130。参考图4、图15，第一方向200为平行于基底100表面的任一方向，沿第一方向200延伸的堆叠结构120包括：沿垂直于基底100表面方向间隔排布的、沿第一方向200延伸的多个半导体层121，半导体层121用于形成半导体通道， 半导体层121的顶面和底面设置有第一牺牲层122，第一牺牲层122决定后续晶体管沟道区半导体通道上设置的字线结构151的形貌，第一牺牲层122远离半导体层121的表面设置有第二牺牲层123，第二牺牲层123可决定字线结构151之间的间隔距离，在堆叠结构120的基础上，形成字线结构151的形貌以及相邻字线结构151之间的间隔距离可控，提高堆叠结构120中半导体层121、第一牺牲层122以及第二牺牲层123的均匀性即可提高字线结构151的均匀性，有利于提高半导体结构的电学性能。另外，第一牺牲层122与第二牺牲层123在同一条件下不同的刻蚀速率，可在后续形成字线结构151的过程中，采用不同的刻蚀工艺分别去除第一牺牲层122和去除第二牺牲层123，以形成均匀的字线结构151。另外，堆叠结构120之间沿第一方向200延伸的隔离层130用于辅助形成后续的字线结构151。其中，隔离层130的材料可以为较为常见的隔离材料，例如氧化硅。
继续参考图3，在一些实施例中，第一牺牲层122的厚度相同，第二牺牲层123的厚度相同。参考图3、图15，厚度相同的第一牺牲层122可使后续形成的半导体层121顶面或底面的字线结构151的厚度相同，有利于提高字线结构151的均匀性。厚度相同的第二牺牲层123可使后续形成的相邻的字线结构151之间的间隔距离相同，提高字线结构151分布位置的均匀性，进而有利于提高半导体结构的电学性能。
参考图2至图4，在一些实施例中，形成上述实施例中的堆叠结构120以及隔离层130的工艺步骤可以包括：在基底100表面形成初始堆叠结构110，初始堆叠结构110包括：在垂直于基底100表面方向上间隔设置的多个初始半导体层111，且初始半导体层111相对的顶面和底面均具有初始第一牺牲层112，初始第一牺牲层112远离初始半导体层111的表面均具有初始第二牺牲层113；图形化初始堆叠结构110，形成多个相互分立的堆叠结构120；在相邻的堆叠结构120之间形成隔离层130。
在本实施例中，参考图2、图15，在基底100上形成初始堆叠结构110，并对初始堆叠结构110进行图形化形成堆叠结构120。为了保证不同堆叠结构120中第一牺牲层122、第二牺牲层123以及半导体层121的形貌相同，即保证形成均匀的字线结构151，可形成厚度均匀的初始半导体层111、厚度均匀的初始第一牺牲层112以及厚度均匀的初始第二牺牲层113，初始堆叠结构110中的初始半导体层111用于形成半导体层121，半导体层121用于形成晶体管的半导体通道，保证初始堆叠结构110中半导体层121的厚度均匀性即可保证基底100上形成的晶体管的半导体通道的均匀性，初始堆叠结构110中初始第一牺牲层112的厚度定义了第一牺牲层122的厚度，第一牺牲层122的厚度决定后续形成的字线结构151的形貌，形成厚度均匀性较好的初始第一牺牲层112有利于形成形貌均匀性较优的字线结构151；初始第二牺牲层113的厚度均匀性决定不同第二牺牲层123的厚度均匀性，厚度均匀性较好的第二牺牲层123可使字线结构151之间的间隔距离相同，有利于形成排布均匀的字线结构151，排布均匀且形貌均匀的字线结构151有利于提高半导体结构的电学性能。
在一些实施例中，初始半导体层111的材料为硅，在硅的基础上可以采用外延工艺形成多种性质的材料，有利于以硅为基础简易地制备得到第一牺牲层122以及第二牺牲层123，降低初始堆叠结构110的制造难度。在另一些实施例中，初始半导体层111也可以为其他半导体通道材料，例如IGZO(铟镓锌氧化物，Indium Gallium Zinc Oxide)、IWO(掺钨氧化铟，Indium Tungsten Oxide)或者ITO(氧化铟锡，Indium Tin Oxide)中的一种，半导体通道由上述材料组成时，有利于提高半导体通道中载流子的迁移率，从而有利于使半导体通道高效地传递电信号。
在一些实施例中，参考图2、图3，第一牺牲层122的材料包括掺杂的SiGe；第二牺牲层123的材料包括未掺杂的SiGe。那么初始第一牺牲层112为掺杂的SiGe层，初始第二牺牲层113为未掺杂的SiGe层，初始第一牺牲层112和初始第二牺牲层113 为上述材料时主要有以下几方面的优点：一方面，掺杂的SiGe与未掺杂的SiGe在同一条件下，具有不同的刻蚀速率，所以可以分别作为后续的第一牺牲层122和第二牺牲层123，以辅助形成均匀的字线结构151(参考图15)；另一方面，掺杂的SiGe与未掺杂的SiGe区别在于是否进行了掺杂，本质均是SiGe，所以形成初始第一牺牲层112和初始第二牺牲层113时，可直接形成SiGe层，再对远离基底100方向的部分厚度的SiGe层进行掺杂，以分别形成初始第一牺牲层112和初始第二牺牲层113，其中通过形成SiGe层，再进行部分掺杂形成初始第一牺牲层112和初始第二牺牲层113的方式，有利于降低初始堆叠结构110的制造难度。
在一些实施例中，参考图2，采用选择性外延工艺，形成初始第一牺牲层112、初始第二牺牲层113以及初始半导体层111。通过选择性外延工艺形成初始堆叠结构110，可使初始第一牺牲层112、初始第二牺牲层113、初始半导体层111以及基底100的热膨胀系数接近且晶格系数相匹配，进而使得相互邻接的膜层之间的热膨胀系数接近且晶格系数相匹配，可避免温度变化导致的应力变化以及晶格失配导致的应力不匹配，进而有利于避免应力不匹配导致的不同膜层之间的界面错位现象甚至膜层破裂现象，提高初始堆叠结构110中各个膜层的平整度以及基底100的平整度。
在本实施例中，采用选择性外延形成初始堆叠结构110，以形成堆叠结构120和隔离层130的具体步骤可以为：参考图2、图3、图4，将基底100放置在外延反应腔室内，向外延反应腔室通入初始第二牺牲层113的源材料，在基底100表面形成一定厚度的初始第二牺牲层113；将形成了初始第二牺牲层113的基底100放置在外延反应腔室中，向外延反应腔室通入初始第一牺牲层112的源材料，在初始第二牺牲层113远离基底100的表面形成一定厚度的初始第一牺牲层112；将形成了初始第二牺牲层113以及初始第一牺牲层112的基底100放置在外延反应腔室中，向外延反应腔室通入初始半导体层111的源材料，在第一牺牲层122远离基底100表面形成一定厚度的初始半导体层111；采用前述形成初始第一牺牲层112、形成初始第二牺牲层113以及形成初始半导体层111的方式，在形成了的初始半导体层111远离基底100的表面依次形成剩余的初始堆叠结构110的膜层，以形成初始堆叠结构110。在初始堆叠结构110远离基底100的表面形成包括第一刻蚀窗口的第一掩膜层，去除第一刻蚀窗口露出的初始堆叠结构110，形成多个堆叠结构120以及相邻堆叠结构120之间的第一沟槽131，第一沟槽131的底部露出基底100，去除第一掩膜层后在第一沟槽131内通过沉积等方式形成隔离层130。
关于上述形成堆叠结构120和隔离层130的方法中，为了使第一牺牲层122与第二牺牲层123在同一条件下的刻蚀速率不同，形成初始第一牺牲层112的源材料可以与形成初始第二牺牲层113的源材料不同，进而形成性质不同的第一牺牲层122与第二牺牲层123。但形成初始第一牺牲层112的源材料若与形成初始第二牺牲层113的源材料完全不同，会导致形成初始第一牺牲层112的腔室与形成初始第二牺牲层113的腔室不能兼容，需要增加工艺腔室甚至增加制备设备，使得制备初始堆叠结构110的成本增加。基于上述原因，且为了保证形成性质不同的第一牺牲层122与第二牺牲层123，形成初始第一牺牲层112的源材料可以与形成初始第二牺牲层113的源材料部分相同但不完全相同，不同的源材料可以为掺杂材料，源材料相似度较高的制备工艺使形成初始第一牺牲层112的腔室与形成初始第二牺牲层113的腔室可相互兼容，避免增加额外的制备设备，有利于降低制备半导体结构的成本。
在一些实施例中，形成初始第一牺牲层112的源材料包括硅源气体、锗源气体以及掺杂源气体；形成初始第二牺牲层113的源材料包括硅源气体以及锗源气体。采用硅源气体、锗源气体以及掺杂源气体形成的初始第一牺牲层112为掺杂的SiGe层，采用硅源气体以及锗源气体形成的初始第二牺牲层113为未掺杂的SiGe层，掺杂的 SiGe层与未掺杂的SiGe层在同一条件下的刻蚀速率不同，且采用形成硅源气体以及锗源气体形成初始第一牺牲层112的腔室，与采用硅源气体以及锗源气体形成初始第二牺牲层113的腔室可相互兼容，避免增加额外的制备设备，有利于降低制备成本。
参考图4至图7，在一些实施例中，基底100还包括分别与字线区I沿第一方向200排布的相对两端相邻接的支撑区II，去除字线区I的隔离层130之前还包括：图形化隔离层130，以形成位于支撑区II的多个第一凹槽170，第一凹槽170露出支撑区II的第一牺牲层122侧壁和第二牺牲层123侧壁；去除位于支撑区II的第一牺牲层122以及第二牺牲层123；在支撑区II形成支撑层140，支撑层140填充位于支撑区II的相邻半导体层121之间的区域。
其中，参考图7，支撑区II为设置支撑层140的区域，位于支撑区II的相邻半导体层121之间的支撑层140支撑起位于支撑区II的半导体层121，进而为基底100上的半导体层121提供支撑，有利于提高半导体结构的稳定性。在本实施例中，形成支撑层140的步骤可以为，在包括隔离层130和堆叠结构120的基底100上形成第二掩膜层，第二掩膜层包括露出支撑区II隔离层130的第二刻蚀窗口，通过第二刻蚀窗口去除支撑区II的隔离层130，参考图5，形成多个第一凹槽170，每一第一凹槽170底部露出基底100；由于第一牺牲层122和第二牺牲层123与半导体层121为不同的材料，通过第一凹槽170，采用对第一牺牲层122和第二牺牲层123高刻蚀选择比的刻蚀工艺，去除第一凹槽170侧壁露出的位于支撑区II的第一牺牲层122和第二牺牲层123，保留支撑区II的半导体层121，并去除第二掩膜，形成图6所示的半导体结构。参考图7，在支撑区II的相邻的半导体层121之间的区域形成支撑层140，在一个例子中，采用沉积工艺形成支撑层140，支撑层140为氮化硅，氮化硅硬度较高，可以为半导体结构提供良好的支撑。
参考图8至图9，形成支撑层140后，半导体结构的形成方法还包括去除字线区I的隔离层130，以露出字线区I的第一牺牲层122侧壁和第二牺牲层123侧壁；去除字线区I的第一牺牲层122；去除字线区I的隔离层130，即可将字线区I堆叠结构120中的第一牺牲层122以及第二牺牲层123露出，进而去除字线区I的第一牺牲层122，以露出字线区I的半导体层121，再对露出的字线区I的半导体层121进行加工。去除字线区I的隔离层130的具体步骤可以为：在字线区I的隔离层130以外的远离基底100的堆叠结构120表面以及支撑层140远离基底100的表面上形成第三掩膜层(图中未示出)，第三掩膜层包括露出字线区I的隔离层130的第三刻蚀窗口，刻蚀去除第三刻蚀窗口露出的隔离层130，形成第二凹槽180。参考图8，第二凹槽180的底部露出基底100，第二凹槽180的侧壁露出字线区I堆叠结构120的第一牺牲层122的侧壁、第二牺牲层123的侧壁以及半导体层121的侧壁，利用第一牺牲层122、第二牺牲层123以及半导体层121不同的刻蚀选择比，采用对第一牺牲层122刻蚀速率较高的刻蚀条件，去除第二凹槽180露出的即字线区I的第一牺牲层122，并去除第三掩膜，形成图9所示的半导体结构。
参考图9、图10和图16，在一些实施例中，去除字线区I的第一牺牲层122后，形成初始字线层150前还包括：对字线区I的半导体层121进行氧化处理形成氧化层(图中未示出)，以使位于字线区I的半导体层121的倒角圆滑化；去除氧化层。本公开实施例中，半导体层121为长方体柱状结构，参考图16，半导体层121的倒角圆滑化可使字线区I的半导体层121相邻面构成的拐角形成圆滑化的拐角，有利于避免作为半导体通道的半导体层121发生尖端放电或者漏电的现象，改善半导体结构的电学性能。需要说明的是，在其他实施例中，半导体层121也可以为圆柱状结构、椭圆柱状结构、正方体柱状结构或者其他不规则结构。可以理解的是，半导体层121为正方体柱状结构时，正方体柱状结构的侧壁相邻面构成的拐角可以为圆滑化的拐角，同 样能够避免尖端放电问题。
参考图9、图17，在一些实施例中，去除氧化层之后，还包括：形成栅介质层160，栅介质层160覆盖字线区I的半导体层121表面。也就是说，栅介质层160环绕字线区I的半导体层121设置，另外，栅介质层160的材料可以为氧化硅、氮化硅、氮氧化硅或其他高介电常数介质材料中的一种。
参考图10，结合图17，半导体结构的形成方法还包括，在字线区I形成初始字线层150，初始字线层150填充第二牺牲层123与半导体层121之间的区域，且还填充相邻半导体层121之间的区域。初始字线层150的材料可以为多晶硅、氮化钛、氮化钽、铜、钨或者铝中的一种。形成初始字线层150的具体步骤可以为，通过ALD沉积工艺在字线区I的半导体层121表面，即字线区I的半导体层121的栅介质层160远离半导体层121的表面形成初始字线层150，初始字线层150填充第二牺牲层123与半导体层121的栅介质层160之间的区域，以及填充相邻半导体层121的栅介质层160之间的区域。第二牺牲层123与半导体层121的栅介质层160之间的区域，以及相邻半导体层121的栅介质层160之间的区域对初始字线层150的形貌形成限制，形成了分布均匀的初始字线层150，均匀的初始字线层150有利于形成均匀的字线结构。
参考图11至图12，形成初始字线层150后，半导体结构的形成方法还包括：去除位于字线区I的第二牺牲层123，以形成刻蚀孔190，去除字线区I的第二牺牲层123形成的刻蚀孔190为去除部分初始字线层150提供了基础，在一些实施例中，字线区I的刻蚀孔190的大小完全相同，参考图15、图18，利用大小相同的刻蚀孔190去除部分初始字线层150后形成的字线结构151中，相邻字线结构151之间的间隔距离也完全相同，有利于提高字线结构151的均匀性。
参考图11至图12，在一些实施例中，形成刻蚀孔190的工艺步骤可以包括：去除与字线区I相邻接的一支撑区II的支撑层140，形成第一刻蚀孔191；刻蚀去除第一刻蚀孔191露出的第二牺牲层123，形成第二刻蚀孔192，第二刻蚀孔192与第一刻蚀孔191相连通构成刻蚀孔190。由于直接去除被初始字线层150覆盖的第二牺牲层123存在一定的难度，因此，本实施例提出去除字线区I任意一侧的支撑层140的方法，去除字线区I任意一侧的支撑层140可露出字线区I的第二牺牲层123，保留另一侧的支撑层140为半导体结构提供支撑，既降低了第二牺牲层123的去除难度还保证了半导体结构的稳定性。其中，形成第一刻蚀孔191的具体步骤可以为，形成初始字线层150后，形成第四掩膜层(图中未示出)，第四掩膜层包括露出每一字线区I任意一侧支撑区II的第四刻蚀窗口，刻蚀去除第四刻蚀窗口露出的支撑区II的支撑层140，形成图11所示的第一刻蚀孔191，第一刻蚀孔191露出字线区I的第二牺牲层123。形成第二刻蚀孔192的具体步骤可以包括：通过第一刻蚀孔191，选择对第二牺牲层123刻蚀速率较高的刻蚀条件去除字线区I的第二牺牲层123，形成位于字线区I如图12所示的第二刻蚀孔192，第二刻蚀孔192与第一刻蚀孔191相连通构成刻蚀孔190。其中，第一刻蚀孔191还露出支撑区II和字线区I以外的第一牺牲层122和第二牺牲层123，即支撑区II远离字线区I一侧区域中的第一牺牲层122和第二牺牲层123，支撑区II和字线区I以外区域中的第一牺牲层122和第二牺牲层123在形成后续半导体结构时需要被去除，所以去除字线区I的第二牺牲层123时，也可去除第一刻蚀孔191露出的支撑区II和字线区I以外区域中的第一牺牲层122和第二牺牲层123，形成图12所示的半导体结构。
参考图12至图13，形成刻蚀孔190后，半导体结构的形成方法还包括：刻蚀去除刻蚀孔190露出的部分初始字线层150，以形成在沿垂直于基底100表面方向间隔排布的多个字线结构151。在本实施例中，通过第一刻蚀孔191和第二刻蚀孔192，去除第二刻蚀孔192垂直于基底100表面的内壁之间的初始字线层150，还沿垂直于 基底100表面的方向上去除部分厚度的初始字线层150，形成沿垂直于基底100表面方向间隔排布的多个字线结构151。在一个例子中，字线结构151可以沿平行于基底100表面且垂直于第一方向200的第二方向延伸，位于字线区I的沿第二方向间隔排布的一行半导体层121共用一条字线结构151。
参考图14，形成字线结构151后还包括：在第一刻蚀孔191内形成支撑层140。前述实施例中形成的第一刻蚀孔191是为了露出第二牺牲层123以及去除第二牺牲层123，形成字线结构151后，可重新在第一刻蚀孔191内填充支撑材料形成支撑层140，提高半导体结构的稳定性。
参考图14至图15，在一些实施例中，重新形成支撑层140后还包括，去除剩余的第一牺牲层122和第二牺牲层123，得到图15所示的半导体结构。
参考图18，在一些实施例中，还包括：形成字线隔离层152，字线隔离层152位于相邻的字线结构151之间。字线隔离层152不仅为字线结构151提供支撑，使半导体的结构更加稳定，还使相邻的字线结构151之间形成良好的隔离，有利于降低相邻字线结构151之间的寄生电容，提高半导体结构的电学性能。在另一些实施例中，形成字线结构151后，将字线结构151之间的空气间隙作为字线隔离层152。采用字线结构151之间的空气间隙作为字线隔离层152不仅有利于降低填充隔离材料的难度，还有利于降低相邻字线结构151之间的寄生电容，以及有利于提高半导体结构的散热性能。
上述实施例提供的半导体结构的形成方法，间隔排布的堆叠结构120中包括多个半导体层121，相邻堆叠结构120之间设置有隔离层130，半导体层121的顶面和底面设置有第一牺牲层122，第一牺牲层122远离半导体层121的表面设置有第二牺牲层123，位于基底100字线区I的堆叠结构120中的半导体层121为晶体管的沟道区，去除字线区I的堆叠结构120之间的隔离层130后，去除字线区I的半导体层121顶面的第一牺牲层122和底面的第一牺牲层122，并在字线区I的半导体层121和第二牺牲层123之间的区域、字线区I的相邻半导体层121之间的区域形成初始字线层150，利用半导体层121与第二牺牲层123之间的第一牺牲层122定义初始字线层150的形貌，利用第二牺牲层123定义初始字线结构151分布位置，形成了形貌均匀的初始字线层150。并通过去除部分初始字线层150，形成了排布均匀且形貌均匀的字线结构151，均匀的字线结构151有利于提高半导体结构的电学性能。
相应的，本公开实施例另一方面还提供一种半导体结构，该半导体结构可以由上述实施例提供的半导体结构的形成方法形成。需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细说明，以下将不做赘述。
参考图15，半导体结构包括：基底100以及位于基底100上多个间隔排布的沿第一方向200延伸的多个半导体层121，且基底100包括字线区I；字线结构151，字线结构151位于字线区I的半导体层121上，且字线结构151沿垂直于基底100表面方向间隔排布。半导体层121可以为全环绕栅极晶体管的半导体通道，位于字线区I的半导体层121为全环绕栅极晶体管的沟道区，位于字线区I以外的半导体层121包括全环绕栅极晶体管的掺杂区，第一方向200可以为平行于基底100表面的任一方向，字线结构151环绕沟道区设置。其中，参照图4至图13，字线结构151为通过前述实施例中依次去除第一牺牲层122和第二牺牲层123的形成方法形成的，因此，不同字线结构151的形貌差异较小，不同字线结构151与相邻的字线结构151之间的间隔距离差异较小，即字线结构151的均匀性较好，均匀的字线结构151有利于提高半导体结构的电学性能。
参考图15，在一些实施例中，基底100还包括分别与字线区I沿第一方向200排布的相对两端相邻接的支撑区II，支撑区II具有支撑层140，支撑层140位于支撑区 II相邻半导体层121之间的区域。支撑层140为基底100上的半导体层121提供支撑，有利于提高半导体结构的稳定性。
参考图18，在一些实施例中，半导体结构包括：字线隔离层152，字线隔离层152位于相邻的字线结构151之间。字线隔离层152一方面为半导体结构提供支撑，使半导体的结构更加稳定；另一方面，字线隔离层152使相邻的字线结构151之间形成良好的隔离，有利于降低相邻字线结构151之间的寄生电容，提高半导体结构的电学性能。
在一些实施例中，位于字线区I的不同半导体层121顶面或底面的字线结构151的厚度相同，字线区I的相邻的字线结构151之间的间隔距离相同。即不同字线结构151的形貌相同，不同字线结构151与相邻的字线结构151之间的间隔距离相同，字线结构151的均匀性较好，均匀的字线结构151有利于提高半导体结构的电学性能。
上述实施例提供的半导体结构中，基底100上设置有多个半导体层121，环绕字线区I的多个半导体层121的字线结构151为通过前述实施例提供的半导体结构的形成方法形成的，因此，不同字线结构151的形貌差异较小，不同字线结构151与相邻的字线结构151之间的间隔距离差异较小，即字线结构151的均匀性较好，均匀的字线结构151有利于提高半导体结构的电学性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其形成方法中，位于基底字线区上堆叠结构 中的半导体层为晶体管的沟道区，在半导体层的顶面和底面形成第一牺牲层，在第一牺牲层远离半导体层的表面形成第二牺牲层，去除字线区的堆叠结构之间的隔离层，利用半导体层、第一牺牲层以及第二牺牲层不同性质的材料之间不同的刻蚀速率，选择性去除字线区半导体层顶面的第一牺牲层和底面的第一牺牲层，以在字线区的半导体层和第二牺牲层之间的区域、字线区的相邻半导体层之间的区域形成初始字线层，即利用半导体层与第二牺牲层之间的第一牺牲层定义初始字线层的形貌，利用第二牺牲层定义半导体层顶面或底面的初始字线结构与相对的初始字线结构之间的间隔距离，形成均匀的初始字线层。由于初始字线层的均匀性较好，使得去除部分初始字线层形成的字线结构的均匀性也较好，改善了字线结构的形貌均匀性以及相邻字线结构之间间隔距离的均匀性。

Claims (15)

  1. 一种半导体结构的形成方法，包括：
    提供基底以及位于所述基底上的多个间隔排布的沿第一方向延伸的堆叠结构，所述堆叠结构包括：在垂直于所述基底表面方向上间隔设置的多个半导体层，且所述半导体层相对的顶面和底面均具有第一牺牲层，所述第一牺牲层远离所述半导体层的表面均具有第二牺牲层，且同一刻蚀工艺对所述第一牺牲层与所述第二牺牲层具有不同的刻蚀速率，相邻的所述堆叠结构之间具有隔离层，所述基底包括字线区；
    去除所述字线区的所述隔离层，以露出所述字线区的所述第一牺牲层侧壁和所述第二牺牲层侧壁；
    去除所述字线区的所述第一牺牲层；
    在所述字线区形成初始字线层，所述初始字线层填充所述第二牺牲层与所述半导体层之间的区域，且还填充相邻所述半导体层之间的区域；
    去除位于所述字线区的所述第二牺牲层，以形成刻蚀孔；
    去除所述刻蚀孔露出的部分所述初始字线层，以形成在沿垂直于所述基底表面方向间隔排布的多个字线结构。
  2. 如权利要求1所述半导体结构的形成方法，其中，所述第一牺牲层的厚度相同，所述第二牺牲层的厚度相同。
  3. 如权利要求1所述半导体结构的形成方法，其中，所述第一牺牲层的材料包括掺杂的SiGe；所述第二牺牲层的材料包括未掺杂的SiGe。
  4. 如权利要求1所述半导体结构的形成方法，其中，形成所述堆叠结构以及所述隔离层的工艺步骤包括：
    在所述基底表面形成初始堆叠结构，所述初始堆叠结构包括：在垂直于所述基底表面方向上间隔设置的多个初始半导体层，且所述初始半导体层相对的顶面和底面均具有初始第一牺牲层，所述初始第一牺牲层远离所述初始半导体层的表面均具有初始第二牺牲层；
    图形化所述初始堆叠结构，形成多个相互分立的所述堆叠结构；
    在相邻的所述堆叠结构之间形成所述隔离层。
  5. 如权利要求4所述半导体结构的形成方法，其中，采用选择性外延工艺，形成所述初始第一牺牲层、所述初始第二牺牲层以及所述初始半导体层。
  6. 如权利要求5所述半导体结构的形成方法，其中，形成所述初始第一牺牲层的源材料包括硅源气体、锗源气体以及掺杂源气体；形成所述初始第二牺牲层的源材料包括所述硅源气体以及所述锗源气体。
  7. 如权利要求1所述半导体结构的形成方法，其中，所述基底还包括分别与所述字线区沿所述第一方向排布的相对两端相邻接的支撑区，去除所述字线区的所述隔离层之前还包括：
    图形化所述隔离层，以形成位于所述支撑区的多个第一凹槽，所述第一凹槽露出所述支撑区的所述第一牺牲层侧壁和所述第二牺牲层侧壁；
    去除位于所述支撑区的所述第一牺牲层以及所述第二牺牲层；
    在所述支撑区形成支撑层，所述支撑层填充位于所述支撑区的相邻所述半导体层之间的区域。
  8. 如权利要求7所述半导体结构的形成方法，其中，形成所述刻蚀孔的工艺步骤包括：
    去除与所述字线区相邻接的一侧的所述支撑区的所述支撑层，形成第一刻蚀孔；
    刻蚀去除所述第一刻蚀孔露出的所述第二牺牲层，形成第二刻蚀孔，所述第二刻蚀孔与所述第一刻蚀孔相连通构成所述刻蚀孔；
    形成所述字线结构后还包括：在所述第一刻蚀孔内形成所述支撑层。
  9. 如权利要求1所述半导体结构的形成方法，其中，去除所述字线区的所述第一牺牲层后，形成所述初始字线层前还包括：对所述字线区的所述半导体层进行氧化处理形成氧化层，以使位于所述字线区的所述半导体层的倒角圆滑化；去除所述氧化层。
  10. 如权利要求9所述半导体结构的形成方法，其中，去除所述氧化层之后，还包括：
    形成栅介质层，所述栅介质层覆盖所述字线区所述半导体层表面。
  11. 如权利要求1所述半导体结构的形成方法，其中，在形成所述字线结构之后，还包括：形成字线隔离层，所述字线隔离层位于相邻的所述字线结构之间。
  12. 一种半导体结构，所述半导体结构为采用权利要求1-11中任一所述的半导体结构的形成方法形成的，包括：
    基底以及位于所述基底上多个间隔排布的沿第一方向延伸的多个半导体层，且所述基底包括字线区；
    字线结构，所述字线结构位于所述字线区的所述半导体层上，且所述字线结构沿垂直于所述基底表面方向间隔排布。
  13. 如权利要求12所述半导体结构，其中，所述基底还包括分别与所述字线区沿所述第一方向排布的相对两端相邻接的支撑区，所述支撑区具有支撑层，所述支撑层位于所述支撑区相邻所述半导体层之间的区域。
  14. 如权利要求12所述半导体结构，还包括：字线隔离层，所述字线隔离层位于相邻的所述字线结构之间。
  15. 如权利要求12所述半导体结构，其中，位于所述字线区的不同所述半导体层顶面或底面的所述字线结构的厚度相同，所述字线区的相邻的所述字线结构之间的间隔距离相同。
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