WO2024027333A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024027333A1
WO2024027333A1 PCT/CN2023/098689 CN2023098689W WO2024027333A1 WO 2024027333 A1 WO2024027333 A1 WO 2024027333A1 CN 2023098689 W CN2023098689 W CN 2023098689W WO 2024027333 A1 WO2024027333 A1 WO 2024027333A1
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layer
semiconductor
support
support layer
word line
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PCT/CN2023/098689
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English (en)
French (fr)
Inventor
林超
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长鑫存储技术有限公司
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Publication of WO2024027333A1 publication Critical patent/WO2024027333A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method of forming the same.
  • an independent word line structure is usually set up in the channel areas of multiple transistors. If the spacing distance between the channel areas of adjacent transistors corresponding to the same word line structure is too large, it may cause interference between the channel areas of adjacent transistors. The word line structure is deformed or even broken. A word line structure with poor continuity will lead to poor reliability of dynamic memory performance and affect the yield rate of dynamic memory.
  • embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a plurality of semiconductor pillars located above the substrate, the semiconductor pillars extending along a first direction, and the plurality of semiconductor pillars being spaced apart along a second direction and a third direction,
  • the semiconductor column has a channel region and doped regions located on opposite sides of the channel region; a first support layer located on the sidewalls of the channel region of the semiconductor column arranged along the second direction; a second support layer, The second support layer is located between adjacent first support layers; a plurality of word line structures, the word line structures extend along the second direction, and at least the channel regions of the plurality of semiconductor pillars arranged along the second direction are in a third direction. Two surfaces facing upward, and also located on two surfaces of the first support layer and the second support layer in the third direction.
  • the first direction and the second direction are both parallel to the substrate surface
  • the third direction is perpendicular to the substrate surface
  • the top surface of the first support layer and the top surface of the second support layer are both in contact with the adjacent semiconductor pillar.
  • the top surfaces are flush
  • the bottom surfaces of the first support layer and the second support layer are flush with the bottom surfaces of adjacent semiconductor pillars.
  • an air gap is included between the first support layer and the second support layer.
  • At least two first support layers and at least two air gaps are included between adjacent semiconductor pillars, the thickness of each first support layer is the same, and the width of each air gap is the same.
  • each first support layer has the same thickness
  • each reinforcement layer has the same thickness.
  • the material of the reinforcing layer is different from the material of the first support and the second support layer.
  • the first support layer and the second support layer are made of the same material.
  • the word line structure includes: a first word line layer located on a top surface of the channel region of the semiconductor pillar, a top surface of the first support layer, and a top surface of the second support layer; Two word line layers, the second word line layer is located on the bottom surface of the channel area of the semiconductor pillar, the bottom surface of the first support layer and the bottom surface of the second support layer; in the third direction, the first word line layer and the second word line layer The thickness is the same.
  • a gate dielectric layer is further included, the gate dielectric layer is located on both surfaces of the channel region of the semiconductor pillar in the third direction, and is located between the word line structure and the channel region of the semiconductor pillar.
  • an isolation layer is further included, and the isolation layer is located between adjacent word line structures.
  • the method further includes: a dielectric layer, the dielectric layer is located between the doped regions of some semiconductor pillars adjacent to the channel region, and surrounds the surface of the doped regions of some of the semiconductor pillars extending in the first direction, and the dielectric layer It is in contact with both ends of the word line structure in the first direction.
  • embodiments of the present disclosure also provide a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of semiconductor pillars located above the substrate, the semiconductor pillars extending along a first direction, and the plurality of semiconductor pillars extending along a second direction;
  • the semiconductor pillars are arranged at intervals in the third direction and have a channel region and doping regions located on opposite sides of the channel region; a first support layer is formed, and the first support layer is located in the channel region of the semiconductor pillars arranged along the second direction.
  • each semiconductor pillar has two surfaces in the third direction, and is also located on both surfaces of the first support layer and the second support layer in the third direction.
  • forming the semiconductor pillar includes: forming a plurality of semiconductor layers spaced apart in the third direction and an epitaxial layer between the semiconductor layers; patterning the semiconductor layer and the epitaxial layer to form a groove extending along the first direction. , the remaining semiconductor layer serves as a semiconductor pillar.
  • forming the first support layer and the second support layer includes: forming a first support film and a second support film in the groove, the first support film being in contact with the semiconductor pillars on the sidewalls of the groove and the epitaxial layer , the second support film and the first support film are arranged at intervals along the second direction and are located between the first support films; a sacrificial layer is formed, and the sacrificial layer is located between the channel regions of some semiconductor pillars adjacent to the doping region, and Surrounding the surface extending along the first direction of the channel areas of part of the semiconductor pillars; removing the sacrificial layer to expose the epitaxial layer between the channel areas of the semiconductor pillars; removing the epitaxial layer between the channel areas of the semiconductor pillars to form etching hole; remove the first support film and the second support film between the side walls of the etching hole, and the remaining first support film serves as the first support layer, The remaining second support film serves as the second support layer.
  • the method before forming the sacrificial layer, the method further includes: forming a reinforcing film; removing the first supporting film and the second supporting film between the side walls of the etching holes, and also removing the reinforcing film between the side walls of the etching holes. .
  • the method further includes: removing the reinforcing film to form an air gap.
  • the method before removing the sacrificial layer, the method further includes: forming a dielectric layer, the dielectric layer being located between the doped regions of some semiconductor pillars adjacent to the sacrificial layer, and surrounding the doped regions of some of the semiconductor pillars extending in the first direction. surface.
  • Figure 1 is a cross-sectional view perpendicular to a first direction of a channel region of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a cross-sectional view perpendicular to the second direction of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a cross-sectional view perpendicular to the first direction of the channel region of another semiconductor structure provided by an embodiment of the present disclosure
  • 4 to 15 are schematic diagrams of each step of a method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • the semiconductor structure includes: a substrate and a semiconductor pillar.
  • the semiconductor pillar is used to form a semiconductor channel of a transistor.
  • the doping regions on both sides of the channel region of the semiconductor pillar are used to form a transistor.
  • the source and drain electrodes further include: word line structures located on the top and bottom surfaces of the channel region of a row of semiconductor pillars arranged along the second direction, the word line structures being used to control the arrangement along the second direction based on the control signal.
  • the area between the word line structure on the top surface of the semiconductor pillar and the word line structure on the bottom surface of the semiconductor pillar includes, in addition to the semiconductor pillars arranged at intervals, a first support layer between adjacent semiconductor pillars and The second support layer, which is in contact with the sidewalls of the channel regions of the semiconductor pillars, is used to provide support for the word line structure and to provide isolation protection for the channel regions of the semiconductor pillars. It is located on the first support layer. The second support layer between them is used to strengthen the support for the word line structure. The first support layer and the second support layer provide support for the word line structure between the top surface and the bottom surface of the channel area, which is beneficial to avoid the word line structure. The structure deforms or even breaks between the channel regions of adjacent semiconductor pillars, which is beneficial to ensuring better continuity of the word line structure.
  • Figure 1 is a cross-sectional view perpendicular to a first direction of a channel region of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a cross-sectional view perpendicular to a second direction of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 A cross-sectional view of a channel region of another semiconductor structure perpendicular to the first direction provided for embodiments of the present disclosure.
  • the semiconductor structure includes: a substrate 100 ; a plurality of semiconductor pillars 110 located above the substrate 100 , the semiconductor pillars 110 extending along the first direction Y, and the plurality of semiconductor pillars 110 extending along the second direction X and the third direction. Arranged at Z intervals, the semiconductor pillar 110 has a channel region II and doping regions located on opposite sides of the channel region II.
  • the material of the substrate 100 is a semiconductor material.
  • the substrate 100 is a silicon substrate.
  • the substrate 100 may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.
  • the semiconductor pillar 110 is used to form a semiconductor channel of the transistor.
  • the material of the semiconductor pillar 110 may be the same as the material of the substrate 100 .
  • the material of the semiconductor pillar 110 may be silicon.
  • the first direction Y and the second direction X may be parallel to the surface of the substrate 100
  • the third direction Z may be perpendicular to the surface of the substrate 100
  • the semiconductor pillars 110 extend in a direction parallel to the surface of the substrate 100 and are arranged at intervals on the substrate 100. This is conducive to realizing multi-layer stacking of transistors in a direction perpendicular to the surface of the substrate 100, and is conducive to utilizing limited space to integrate a larger number of transistors. More transistors increase the integration density of the semiconductor structure and enable smaller volume integration while ensuring better performance.
  • the semiconductor pillar 110 includes a channel region II and doping regions located on both sides of the channel region II.
  • the doping region includes a first doping region I and a second doping region III.
  • the first doping region I and the channel region II and the second doped regions III are sequentially distributed along the extension direction of the semiconductor pillar 110, that is, the first direction Y.
  • the first doped region I and the second doped region III are used to form the source and drain of the transistor, and the semiconductor pillar 110 Channel region II is used to form channel region II of the transistor.
  • the type of doping ions in the first and second doping regions I and III may be different from the type of doping ions in the channel region II.
  • the doping ions in the first doping region I and the second doping region III may be N-type ions
  • the doping ions in the channel region II may be P-type ions
  • the P-type ions may be boron.
  • the N-type ions can be at least one of arsenic ions, phosphorus ions or antimony ions.
  • the doping ions in the first doping region I and the second doping region III may be P-type ions
  • the doping ions in the channel region II may be N-type ions.
  • the doping ion type in the doping region may also be the same as the doping ion type in the channel region II, that is, the semiconductor pillar 110 may be used to form a junctionless field effect transistor.
  • the semiconductor structure further includes: a first support layer 120 located along the second The sidewalls of the channel region II of the semiconductor pillars 110 arranged in the direction X; the second support layer 130 , the second support layer 130 is located between adjacent first support layers 120 .
  • the first support layer 120 in contact with the sidewalls of the channel region II of the semiconductor pillar 110 not only provides support for the word line structure, but also provides isolation protection for the channel region II of the semiconductor pillar 110.
  • the second support layer 130 is conducive to strengthening the supporting force of the word line structure 160, and the first support layer 120 and the second support layer 130 are conducive to preventing the word line structure 160 from being deformed at the position between the channel regions II of the adjacent semiconductor pillars 110 or fracture, which is conducive to ensuring better continuity of the word line structure 160
  • a row of semiconductor pillars 110 arranged along the second direction X shares a word line structure 160 .
  • the word line structure 160 serves as the gate of the transistor, and is used to conduct the channel region II based on the control signal to realize carrier transmission between the source and the drain.
  • the material of the word line structure 160 is a conductive material.
  • the material of the word line structure 160 includes at least one of polysilicon, titanium nitride, tungsten, molybdenum, titanium, cobalt, or ruthenium.
  • the word line structure 160 includes: a first word line layer 161 located on the top surface of the channel region II of the semiconductor pillar 110 , a first support layer 120 and the top surface of the second support layer 130; the second word line layer 162, the second word line layer 162 is located on the bottom surface of the channel region II of the semiconductor pillar 110, the bottom surface of the first support layer 120, and the second support layer 130; in the third direction Z, the thickness of the first word line layer 161 and the second word line layer 162 is the same. That is, the word line structure 160 is a double-layer word line structure composed of two conductive layers.
  • the double-layer word line structure can use less word line material to form a simpler structure while ensuring better driving capabilities for the transistors.
  • the word line structure 160 is beneficial to reducing the preparation cost and processing difficulty of the semiconductor structure.
  • the first word line layer 161 and the second word line layer 162 with the same thickness ensure that the first word line layer 161 and the second word line layer 162 have the same driving ability for the channel region II of the semiconductor pillar 110, so that It is beneficial to improve the electrical performance of semiconductor structures.
  • the first word line layer 161 and the second word line layer 162 are made of the same material, and the first word line layer 161 and the second word line layer 162 are structures formed simultaneously using the same manufacturing process. This is beneficial to The preparation difficulty of the first word line layer 161 and the second word line layer 162 is reduced.
  • the semiconductor structure further includes: a gate dielectric layer 150 , which is located on both surfaces of the channel region II of the semiconductor pillar 110 in the third direction Z, and is located on the character between the line structure 160 and the channel region II of the semiconductor pillar 110 .
  • the gate dielectric layer 150 is used to realize conduction between the source of the driving transistor of the word line structure 160 and the drain of the transistor.
  • the gate dielectric layer 150 may be made of silicon oxide.
  • the thermal oxidation process is a mature process for forming silicon oxide on the semiconductor pillars 110 made of silicon, which helps reduce the difficulty of preparing the gate dielectric layer 150 .
  • the material of the gate dielectric layer 150 may also be silicon nitride or silicon oxynitride.
  • adjacent semiconductor pillars 110 arranged along the second direction X have a space extending toward the first direction Y.
  • the first support layer 120 and the second support are located in the separation area between the sidewalls of the channel region II of the semiconductor pillar 110.
  • a second support layer 130 is included between the first support layer 120, It can be understood that if the distance between the sidewalls of the channel region II of adjacent semiconductor pillars 110 is relatively large, the first support layer 120 may also include a plurality of second support layers spaced apart in the second direction X. Support layer 130.
  • the top surface of the first support layer 120 and the top surface of the second support layer 130 are both flush with the top surface of the adjacent semiconductor pillar 110 .
  • the bottom surfaces of the layers 130 are all flush with the bottom surfaces of the adjacent semiconductor pillars 110 .
  • Line structure 160 breaks.
  • the first support layer 120 and the second support layer 130 are made of the same material. In this way, the first support layer 120 and the second support layer 130 can be prepared simultaneously using the same preparation process, which is beneficial to reducing the difficulty of preparing the first support layer 120 and the second support layer 130 .
  • the material of the first support layer 120 and the second support layer 130 may be silicon oxide.
  • an air gap 180 is included between the first support layer 120 and the second support.
  • the dielectric constant of air is small. Setting the air gap 180 is beneficial to reducing the coupling capacitance between the channel regions II of adjacent semiconductor pillars 110 and is beneficial to improving the electrical performance of the semiconductor structure.
  • the air gap 180 is also beneficial to improving the electrical properties of the semiconductor structure. Heat dissipation capacity.
  • the second direction X at least two first support layers 120 and at least two air gaps 180 are included between adjacent semiconductor pillars 110 , and the thickness of each first support layer 120 is Same, the width of each air gap 180 is the same. In this way, it is ensured that the first support layer 120 and the second support layer 130 between different semiconductor pillars 110 have the same arrangement, and the spacing distance between the sidewalls of the channel region II of the semiconductor pillars 110 is the same, which is beneficial to reducing the The difference in arrangement between the pillars 110 ensures that the semiconductor structure has excellent electrical uniformity.
  • a reinforcement layer 140 is provided between the first support layer 120 and the second support layer 130 .
  • the reinforcement layer 140 can be a dielectric material with strong support. The provision of the reinforcement layer 140 is helpful to further improve the support capacity of the word line structure 160 and ensure that the word line structure 160 in the semiconductor structure has high stability.
  • the thickness of each second support layer 130 is the same. In this way, it is ensured that the first support layer 120, the second support layer 130 and the reinforcement layer 140 between different semiconductor pillars 110 have the same arrangement, and the spacing distance between the sidewalls of the channel region II of the semiconductor pillars 110 is the same. It is beneficial to reduce the arrangement difference between the semiconductor pillars 110 and ensure that the semiconductor structure has excellent electrical uniformity.
  • the material of the reinforcement layer 140 is the same as the material of the first support layer 120 and the second support layer 120 .
  • the materials of the support layer 130 are different. In some embodiments, more common dielectric materials can be used as the first support layer 120 and the second support, and materials with stronger support capabilities can be used as the reinforcement layer 140.
  • the preparation cost and preparation difficulty of the support layer 130 ensure that the word line structure 160 has sufficient supporting force while reducing the processing cost and processing difficulty of the semiconductor structure.
  • the material of the reinforcement layer 140 may be silicon nitride.
  • the semiconductor structure further includes: an isolation layer 170 , the isolation layer 170 is located between adjacent word line structures 160 .
  • the isolation layer 170 isolates the word line structure 160, which not only helps protect the word line structure 160, but also helps prevent the word line structure 160 from being damaged by impurities in subsequent processes.
  • the isolation layer 170 also provides support for other structures subsequently formed on the word line structure 160, which is beneficial to improving the stability of the semiconductor structure.
  • the material of the isolation layer 170 is silicon oxide.
  • the preparation process of silicon oxide is mature, which is beneficial to reducing the processing difficulty of the semiconductor structure.
  • the isolation layer 170 may also be other insulating materials with blocking effects, such as silicon oxynitride.
  • a dielectric layer 107 is also included.
  • the dielectric layer 107 is located between the doped regions of the partial semiconductor pillars 110 adjacent to the channel region II and surrounds the doped regions II of the partial semiconductor pillars 110 .
  • the dielectric layer 107 and the word line structure 160 are in contact at both ends of the first direction Y.
  • the dielectric layer 107 is not only used to provide support for the semiconductor pillars 110 arranged at intervals in the third direction Z, but also to isolate the sidewalls of the word line structure 160 from other structures to avoid subsequent processing of the doped regions of the semiconductor pillars 110 In the process, the channel region II and the word line structure 160 are damaged.
  • the material of the dielectric layer 107 may be silicon nitride.
  • the preparation process of silicon nitride is mature, and silicon nitride has a better blocking effect on impurity ions or water vapor, which is beneficial to forming a better shape of the word line structure 160. Excellent protective effect.
  • the material of the dielectric layer 107 may also be other insulating materials with blocking effects, such as silicon oxynitride.
  • the plurality of semiconductor pillars 110 on the substrate 100 are used to form semiconductor channels of the transistor, and the doped regions on both sides of the channel region II of the semiconductor pillars 110 are used to form the source and drain of the transistor.
  • the word line structure 160 is located on the top and bottom surfaces of the channel region II of a row of semiconductor pillars 110 arranged along the second direction X, and is used to control the channel of a row of semiconductor pillars 110 arranged along the second direction X based on the control signal.
  • Region II in addition to the semiconductor pillars 110 arranged at intervals, between the word line structure 160 on the top surface of the semiconductor pillar 110 and the word line structure 160 on the bottom surface of the semiconductor pillar 110, it also includes a first support layer 120 between adjacent semiconductor pillars 110 and The second support layer 130, the first support layer 120 in contact with the sidewalls of the channel region II of the semiconductor pillar 110 is used to provide support for the word line, and is also used to provide isolation protection for the channel region II of the semiconductor pillar 110, The second support layer 130 is used to strengthen the support force for the word line structure 160.
  • the first support layer 120 and the second support layer 130 are conducive to preventing the word line structure 160 from being damaged between the channel regions II of the adjacent semiconductor pillars 110. The position is bent Or broken, which is helpful to ensure better continuity of the word line structure 160.
  • embodiments of the present disclosure also provide a method for forming a semiconductor structure.
  • the method for forming a semiconductor structure can be used to form the semiconductor structure described in the above embodiments. It should be noted that for parts that are the same as or corresponding to the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments and will not be described in detail below.
  • FIGS. 4 to 15 are schematic diagrams of each step of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that in FIGS. 4 to 15 , FIGS. 7 , 8 and 12 are cross-sectional views perpendicular to the second direction X; FIGS. 9 to 11 are cross-sectional views perpendicular to the second direction X in the channel region II of the semiconductor pillar 110 A cross-sectional view in one direction Y; Figures 13 to 14 are cross-sectional views including the semiconductor pillar 110 perpendicular to the third direction Z (for ease of understanding, Figures 13 to 14 show the channel region II of the semiconductor pillar 110 Wordline structure 160).
  • a method of forming a semiconductor structure includes providing a substrate.
  • the substrate 100 may be a silicon substrate.
  • the epitaxial process based on the silicon substrate is relatively mature, which is beneficial to reducing the process difficulty of forming semiconductor pillars.
  • a plurality of semiconductor pillars 110 are formed.
  • the semiconductor pillars 110 extend along the first direction Y.
  • the plurality of semiconductor pillars 110 are arranged at intervals along the second direction X and the third direction Z.
  • the first direction Y and the third direction Z are arranged at intervals.
  • the semiconductor pillar 110 can be used to form a semiconductor channel of the transistor, the channel region II of the semiconductor pillar 110 is used to form the channel region II of the transistor, and the two doped regions of the semiconductor pillar 110 are respectively used to form the source and the source of the transistor. drain.
  • forming the semiconductor pillar 110 includes forming a plurality of semiconductor layers 101 spaced apart in the third direction Z and the epitaxial layer 102 between the semiconductor layers 101 .
  • the thickness of the epitaxial layer 102 in the third direction Z is used to define the spacing distance between adjacent semiconductor pillars 110 arranged at intervals in the third direction Z. Forming the epitaxial layer 102 and the semiconductor layer 101 with uniform thickness is beneficial to the formation of Semiconductor pillars 110 with uniform morphology and uniform spacing.
  • the material of the semiconductor layer 101 is silicon.
  • epitaxial processes can be used to form materials with various properties, which is conducive to the simple preparation of the epitaxial layer 102 based on silicon and reduces the manufacturing cost of the epitaxial layer 102 Difficulty.
  • the semiconductor layer 101 can also be other semiconductor channel materials, such as IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide, Indium Tungsten Oxide) or ITO (Indium Tin Oxide). , Indium Tin Oxide), when the semiconductor channel is composed of the above materials, it is beneficial to increase the mobility of carriers in the semiconductor channel, thereby helping the semiconductor channel to efficiently transmit electrical signals.
  • the material of the epitaxial layer 102 is silicon germanium. Under the same etching conditions, silicon germanium and silicon materials have different etching selectivity ratios. Therefore, if silicon is used as the material of the semiconductor pillar 110, the When the semiconductor pillar 110 is processed, the epitaxial layer 102 can be relatively easily and selectively removed to expose the surface of the semiconductor pillar 110 . Can It is understood that in other embodiments, the material of the epitaxial layer 102 may also be silicon carbide or other materials with different etching rates compared to silicon.
  • a selective epitaxial process may be used to form the epitaxial layer 102 and the semiconductor layer 101 .
  • the thermal expansion coefficients of the epitaxial layer 102, the semiconductor layer 101 and the substrate 100 can be close to each other and the lattice coefficients match, thereby making the thermal expansion coefficients of adjacent film layers close to each other and the lattice coefficients matching.
  • Matching can avoid stress changes caused by temperature changes and stress mismatch caused by lattice mismatch, which in turn helps avoid interface dislocations and even film ruptures between different film layers caused by stress mismatch, which is conducive to improving the quality of semiconductors.
  • the flatness of layer 101 and epitaxial layer 102 and the flatness of substrate 100 are examples of the substrate 100 .
  • forming the semiconductor layer 101 and the epitaxial layer 102 includes patterning the semiconductor layer 101 and the epitaxial layer 102 to form grooves extending along the first direction Y, and the remaining semiconductor layer 101 serves as the semiconductor pillar 110 .
  • a mask layer with an etching window is formed on the top surface of the semiconductor layer 101 away from the substrate 100, and the semiconductor layer 101 and the epitaxial layer 102 exposed by the etching window are removed to form a plurality of layers extending along the first direction Y. grooves and a plurality of semiconductor pillars 110 arranged at intervals.
  • the method further includes: performing a doping process on the semiconductor pillar 110 to form the channel region II, the first doping region I and the second doping region III of the subsequent semiconductor column 110.
  • the first doping region I and the second doped region III is the doped region on both sides of the channel region II.
  • any process method such as ion implantation or thermal diffusion may be used to dope the semiconductor pillar 110 .
  • the semiconductor layer 101 can also be doped to form the channel region II, the first doped region I and the second doped region III of the subsequent semiconductor pillar 110 .
  • a first support layer 120 and a second support layer 130 are formed.
  • the first support layer 120 is located on the sidewall of the channel region II of the semiconductor pillars 110 arranged along the second direction X.
  • the second support layer 130 located between adjacent first support layers 120 .
  • the first support layer 120 in contact with the sidewalls of the channel region II of the semiconductor pillar 110 is used to provide support for subsequent word line structures and to provide isolation protection for the channel region II of the semiconductor pillar 110.
  • the second support layer 130 is used to improve the supporting force of the word line structure, which is helpful to prevent the word line structure from falling off or even breaking between the channel regions II of the adjacent semiconductor pillars 110, and is helpful to ensure that the word line structure has better Continuity.
  • forming the first support layer 120 and the second support layer 130 may include: forming the first support film 103 and the second support film 105 in the groove, the first support film 103 and the groove
  • the semiconductor pillars 110 of the sidewalls are in contact with the epitaxial layer 102 .
  • the second support film 105 and the first support film 103 are arranged at intervals along the second direction X and are located between the first support films 103 .
  • the first support film 103 in contact with the sidewalls of the channel region II of the semiconductor pillar 110 is used to form a subsequent first support layer, and the second support layer between adjacent sidewalls of the channel region II of different semiconductor pillars 110 Film 105 is used to form a subsequent second support layer.
  • an atomic layer deposition process may be used to form the first support film 103 and the second support film 105.
  • a support film is also formed on the top surface of the semiconductor pillar 110 away from the substrate 100.
  • the second support film 105 is formed on the side wall of the first support film 103, or the first support film 103 and the second support film 105 are arranged at intervals.
  • the process of forming the first support film 103 and the second support film 105 further includes forming a reinforcement film 104 .
  • the reinforcement film 104 is located between the first support film 103 and the second support film 105.
  • the reinforcement film 104 between adjacent sidewalls of the channel region II of different semiconductor pillars 110 can be used to form the subsequent first support layer 120 and the second support film 105.
  • the reinforcement layer 140 between the support layers 130 may serve as a sacrificial film to form an air gap.
  • the reinforcement film 104 may be formed using an atomic layer deposition process.
  • the second support film 105 may be formed.
  • the reinforcing film 104 also provides support for the second support film 105.
  • the second support film 105 can be directly formed by filling, which is beneficial to reducing the difficulty of preparing the second support film 105.
  • a sacrificial layer 106 is formed.
  • the sacrificial layer 106 is located between the channel regions II of some semiconductor pillars 110 adjacent to the doping region, and surrounds the surface of the channel region II of some of the semiconductor pillars 110 extending along the first direction Y, The sacrificial layer 106 is used to form a subsequent etching window that exposes the epitaxial layer 102 between the channel regions II of the semiconductor pillars 110 .
  • an etching process may be used to remove part of the first support film 103, the second support film 105 and the reinforcement film 104 in the trench to expose part of the sidewalls of the channel region II adjacent to the doped region and A portion of the epitaxial layer 102 between the channel regions II is removed, and a portion of the epitaxial layer 102 between the semiconductor pillars 110 is removed to form a filling hole, and a sacrificial layer 106 is formed in the filling hole.
  • the sacrificial layer 106 may be a mask layer formed by spin coating.
  • the dielectric layer 107 is located between the doped regions of the partial semiconductor pillars 110 adjacent to the sacrificial layer 106 , and surrounds the doped regions II of the partial semiconductor pillars 110 along the first A surface extending in Y direction.
  • the dielectric layer 107 can be used to form a support structure between adjacent semiconductor pillars 110, which is beneficial to ensuring that the semiconductor pillars 110 still have relatively reliable structural stability after the epitaxial layer 102 is removed.
  • a filling hole extending to a portion of the doping region of the semiconductor pillar 110 may be formed before forming the sacrificial layer 106.
  • the sacrificial material is filled in the filling hole, part of the sacrificial material is removed, and deposition is performed between the sacrificial materials.
  • the process forms the dielectric layer 107, and the sacrificial material on one side of the dielectric layer 107 serves as the sacrificial layer 106.
  • the sacrificial layer 106 is removed to expose the epitaxial layer 102 between the channel regions II of the semiconductor pillars 110 .
  • the epitaxial layer 102 between the channel areas II of the semiconductor pillars 110 is removed to form Etch holes 108.
  • the etching hole 108 is not only used to etch and remove part of the first support film 103 and part of the second support film 105, but also exposes the top and bottom surfaces of the channel region II of the semiconductor pillar 110, so as to facilitate subsequent processing of the semiconductor pillar.
  • the top and bottom surfaces of channel region II of 110 form a word line structure.
  • FIG. 1 Referring to FIGS. 6 to 7 , the sacrificial layer 106 is removed to expose the epitaxial layer 102 between the channel regions II of the semiconductor pillars 110 .
  • the epitaxial layer 102 between the channel areas II of the semiconductor pillars 110 is removed to form Etch holes 108.
  • the etching hole 108 is not only used to etch and remove part
  • openings may be formed in partial areas between the semiconductor pillars 110 arranged along the second direction X to expose the sidewalls of the sacrificial layer 106 in the second direction X, and then the sacrificial layer 106 is removed. .
  • the first support film 103 and the second support film 105 between the side walls of the etching hole 108 are removed, the remaining first support film 103 serves as the first support layer 120, and the remaining second support film 105 serves as the third support layer 120.
  • Second support layer 130 In some embodiments, while removing the first support film 103 and the second support film 105 between the side walls of the etching hole 108 in the second direction X, the reinforcing film between the side walls of the etching hole 108 is also removed. 104.
  • an etching liquid with a high etching selectivity for the first support film 103, the second support film 105 and the reinforcing film 104 can be made to flow into the etching hole 108 to remove part of the first support film 103, the second support film 105 and the reinforcing film 104. Part of the reinforcement film 104 can be removed. In this way, only the first support film 103, the second support film 105 and the reinforcement film 104 exposed on the side walls of the etching hole 108 can be removed, which is beneficial to reducing the preparation of the first support layer 120 and the second support layer 130. Difficulty.
  • the remaining reinforcement film 104 serves as the reinforcement layer 140 to improve the structural stability of the subsequent word line structures 160 located on the top and bottom surfaces of the first support layer 120 and the second support layer 130 .
  • the method of forming a semiconductor structure further includes: forming a gate dielectric layer 150 .
  • a gate dielectric layer 150 may be used to form gates on the top and bottom surfaces of the channel region II of the semiconductor pillar 110 .
  • a gate dielectric layer 150 is also formed on the top and bottom surfaces of the first support layer 120, the second support layer 130 and the reinforcement layer 140.
  • a plurality of word line structures 160 are formed.
  • the word line structures 160 extend along the second direction X, at least on the top surface of the channel region II of the plurality of semiconductor pillars 110 arranged along the second direction X.
  • the bottom surface is also located on the top and bottom surfaces of the first support layer 120 and the second support layer 130 .
  • a conductive layer may be formed on the surface of the gate dielectric layer 150 away from the semiconductor pillar 110 and on the surface of the gate dielectric layer 150 away from the first support layer 120 , the second support layer 130 and the reinforcement layer 140 , located on the semiconductor pillar 110
  • the conductive layer on the top surface of the channel region II, the top surface of the first support layer 120 and the top surface of the second support layer 130 is the first word line layer 161, which is located on the bottom surface of the channel region II and the bottom surface of the first support layer 120 of the semiconductor pillar 110.
  • the conductive layer on the bottom surface of the second support layer 130 is the second word line layer 162.
  • the first word line layer 161 and the second word line layer 162 together form the word line structure 160.
  • the word line structure 160 may be formed using at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
  • forming the word line structure 160 also includes: forming an isolation layer 170 between the word line structures 160 .
  • the isolation layer 170 is located between adjacent word line structures 160 , which not only facilitates It protects the word line structure 160 and helps improve the stability of the semiconductor structure.
  • the method further includes: removing the reinforcement layer 140 to form an air gap 180 .
  • an isolation layer 170 is also formed between sidewalls of the channel region II of the semiconductor pillars 110 adjacent to portions of the doped regions arranged along the second direction X.
  • the process before removing the reinforcement layer 140 , the process includes: removing the isolation in contact with the first support layer 120 , the second support layer 130 and the sidewalls of the reinforcement layer 140 in the first direction Y.
  • the opening formed by removing the sacrificial layer 106 can also be used to remove the reinforcing film 104 between the first support film 103 and the second support film 105 to form The subsequent air gap 180 between the first support layer 120 and the second support layer 130 .
  • removing the reinforcement layer 140 further includes forming a dielectric layer 107 that provides support for the semiconductor pillar 110 .
  • removing the dielectric layer 107 includes removing only the first support layer 120 , the second support layer 130 and the dielectric layer 107 in the sidewall extension direction of the reinforcement film 104 in the first direction Y, leaving the top surface of the semiconductor pillar 110 and dielectric layer 107 between the bottom surfaces.
  • the method of forming a semiconductor structure further includes: removing the dielectric layer 107 and other insulating materials between a doped region of the semiconductor pillar 110 to form a capacitor structure. Therefore, the semiconductor structure can also be removed after removing the dielectric layer 107 and other insulating materials. After removing the dielectric layer 107 and other insulating materials between a doped region of the pillar 110, the sidewall of the reinforcement layer 140 on one side in the first direction Y is exposed, and the reinforcement layer 140 is removed. In this way, there is no need to add additional process steps to remove the reinforcement layer 140 , which helps reduce the difficulty of removing the reinforcement layer 140 .
  • the first support layer 120 and the second support layer 130 are formed between the channel regions II of the semiconductor pillars 110 arranged in the second direction X, and between the semiconductor pillars 110
  • the top and bottom of the channel region II, the top and bottom of the first support layer 120 and the top and bottom of the second support layer 130 form a word line structure 160.
  • the first support layer 120 and the second support layer 130 are used as word lines.
  • the structure 160 provides support to prevent the word line structure 160 from deforming and breaking, which is beneficial to forming a word line structure 160 with better continuity and higher structural stability.

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Abstract

公开了一种半导体结构及其形成方法，半导体结构包括：基底以及多个半导体柱，半导体柱具有沟道区以及位于沟道区相对两侧的掺杂区，半导体结构还包括：第一支撑层、第二支撑层以及多个字线结构，第一支撑层位于沿第二方向排布的半导体柱的沟道区侧壁，第二支撑层位于相邻的第一支撑层之间，字线结构至少位于沿第二方向排布的多个半导体柱的沟道区在第三方向上的两个表面，且还位于第一支撑层以及第二支撑层在第三方向上的两个表面。

Description

半导体结构及其形成方法
交叉引用
本公开要求于2022年08月04日递交的名称为“半导体结构及其形成方法”、申请号为202210934508.3的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，对动态存储器阵列结构中晶体管的排布方式以及晶体管尺寸产生了更高的要求。
目前一个独立的字线结构通常要设置在多个晶体管的沟道区上，若同一字线结构对应的相邻晶体管沟道区的间隔距离过大，可能导致相邻晶体管沟道区之间的字线结构发生形变，甚至断裂，连续性较差的字线结构会导致动态存储器性能的可靠性较差，影响动态存储器的良率。
发明内容
本公开实施例一方面提供一种半导体结构，包括：基底；位于基底上方的多个半导体柱，半导体柱沿第一方向延伸，多个半导体柱在沿第二方向以及第三方向间隔排布，半导体柱具有沟道区以及位于沟道区相对两侧的掺杂区；第一支撑层，第一支撑层位于沿第二方向排布的半导体柱的沟道区侧壁；第二支撑层，第二支撑层位于相邻的第一支撑层之间；多个字线结构，字线结构沿第二方向延伸，至少位于沿第二方向排布的多个半导体柱的沟道区在第三方向上的两个表面，且还位于第一支撑层以及第二支撑层在第三方向上的两个表面。
在一些实施例中，第一方向以及第二方向均平行于基底表面，第三方向垂直于基底表面，第一支撑层的顶面和第二支撑层的顶面均与相邻的半导体柱的顶面平齐，第一支撑层和第二支撑层的底面均与相邻的半导体柱的底面平齐。
在一些实施例中，第一支撑层与第二支撑层之间包含空气间隙。
在一些实施例中，在第二方向上，相邻半导体柱之间包含至少两个第一支撑层和至少两个空气间隙，每一第一支撑层的厚度相同，每一空气间隙的宽度相同。
在一些实施例中，第一支撑层与第二支撑层之间具有加强层。
在一些实施例中，在第二方向上，相邻半导体柱之间包含至少两个第一支撑层和至少两个加强层，每一第一支撑层的厚度相同，每一加强层的厚度相同。
在一些实施例中，加强层的材料与第一支撑的材料以及第二支撑层的材料不相同。
在一些实施例中，第一支撑层和第二支撑层的材料相同。
在一些实施例中，字线结构包括：第一字线层，第一字线层位于半导体柱的沟道区的顶面、第一支撑层的顶面以及第二支撑层的顶面；第二字线层，第二字线层位于半导体柱的沟道区的底面、第一支撑层的底面以及第二支撑层的底面；在第三方向上，第一字线层与第二字线层的厚度相同。
在一些实施例中，还包括：栅介质层，栅介质层位于半导体柱的沟道区在第三方向上的两个表面，且位于字线结构与半导体柱的沟道区之间。
在一些实施例中，还包括：隔离层，隔离层位于相邻字线结构之间。
在一些实施例中，还包括：介质层，介质层位于邻近沟道区的部分半导体柱的掺杂区之间，且环绕部分半导体柱的掺杂区沿第一方向延伸的表面，且介质层与字线结构在第一方向的两端相接触。
本公开实施例另一方面还提供一种半导体结构的形成方法，包括：提供基底；形成位于基底上方的多个半导体柱，半导体柱沿第一方向延伸，多个半导体柱在沿第二方向以及第三方向间隔排布，半导体柱具有沟道区以及位于沟道区相对两侧的掺杂区；形成第一支撑层，第一支撑层位于沿第二方向排布的半导体柱的沟道区侧壁；形成第二支撑层，第二支撑层位于相邻的第一支撑层之间；形成多个字线结构，字线结构沿第二方向延伸，至少位于沿第二方向排布的多个半导体柱的沟道区在第三方向上的两个表面，且还位于第一支撑层以及第二支撑层在第三方向上的两个表面。
在一些实施例中，形成半导体柱包括：形成在第三方向上间隔排布的多个半导体层以及半导体层之间的外延层；图形化半导体层以及外延层，形成沿第一方向延伸的凹槽，剩余半导体层作为半导体柱。
在一些实施例中，形成第一支撑层和第二支撑层包括：在凹槽内形成第一支撑膜和第二支撑膜，第一支撑膜与凹槽侧壁的半导体柱以及外延层相接触，第二支撑膜与第一支撑膜沿第二方向间隔排布，且位于第一支撑膜之间；形成牺牲层，牺牲层位于邻近掺杂区的部分半导体柱的沟道区之间，且环绕部分半导体柱的沟道区沿第一方向延伸的表面；去除牺牲层，以露出半导体柱的沟道区之间的外延层；去除半导体柱的沟道区之间的外延层，形成刻蚀孔；去除刻蚀孔侧壁之间的第一支撑膜和第二支撑膜，剩余第一支撑膜作为第一支撑层， 剩余第二支撑膜作为第二支撑层。
在一些实施例中，形成牺牲层前还包括：形成加强膜；去除刻蚀孔侧壁之间的第一支撑膜和第二支撑膜的同时，还去除刻蚀孔侧壁之间的加强膜。
在一些实施例中，还包括：去除加强膜，形成空气间隙。
在一些实施例中，去除牺牲层之前还包括：形成介质层，介质层位于邻近牺牲层的部分半导体柱的掺杂区的之间，且环绕部分半导体柱的掺杂区沿第一方向延伸的表面。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种半导体结构的沟道区垂直于第一方向的剖面图；
图2为本公开实施例提供的一种半导体结构垂直于第二方向的剖面图；
图3为本公开实施例提供的另一种半导体结构的沟道区垂直于第一方向的剖面图；
图4至图15为本公开实施例提供的一种半导体结构的形成方法的各步骤示意图。
具体实施方式
由背景技术可知，字线结构对应的相邻晶体管沟道区的间隔距离过大，可能导致字线结构出现连续性较差的问题。
本公开实施例提供了一种半导体结构及其形成方法，半导体结构包括：基底以及半导体柱，半导体柱用于形成晶体管的半导体通道，半导体柱的沟道区两侧的掺杂区用于形成晶体管的源极和漏极，还包括：位于沿第二方向排布的一行半导体柱的沟道区的顶面和底面的字线结构，字线结构用于基于控制信号控制沿第二方向排布的一行半导体柱的沟道区，半导体柱顶面的字线结构与半导体柱底面的字线结构之间的区域除了间隔设置的半导体柱，还包括相邻半导体柱之间的第一支撑层以及第二支撑层，与半导体柱的沟道区的侧壁相接触的第一支撑层用于为字线结构提供支撑的同时，以及为半导体柱的沟道区提供隔离保护，位于第一支撑层之间的第二支撑层用于加强对字线结构的支撑力，第一支撑层和第二支撑层为沟道区顶面与底面之间的字线结构提供了支撑，有利于避免字线结构在相邻的半导体柱的沟道区之间的位置发生形变甚至断裂，有利于保证字线结构具有较佳的连续性。
下面将结合附图对本公开各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
图1为本公开实施例提供的一种半导体结构的沟道区垂直于第一方向的剖面图；图2为本公开实施例提供的一种半导体结构垂直于第二方向的剖面图；图3为本公开实施例提供的另一种半导体结构的沟道区垂直于第一方向的剖面图。
参考图1和图2，半导体结构包括：基底100；位于基底100上方的多个半导体柱110，半导体柱110沿第一方向Y延伸，多个半导体柱110在沿第二方向X以及第三方向Z间隔排布，半导体柱110具有沟道区II以及位于沟道区II相对两侧的掺杂区。
基底100的材料为半导体材料，在一些实施例中，基底100为硅基底。在另一些实施例中，基底100也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。
半导体柱110用于形成晶体管的半导体通道，在一些实施例中，半导体柱110的材料可以与基底100的材料相同。在一个例子中，半导体柱110的材料可以为硅。
在一些实施例中，第一方向Y以及第二方向X可以平行于基底100表面，第三方向Z可以垂直于基底100表面。半导体柱110在平行于基底100表面的方向延伸，并在基底100上间隔排布，如此有利于实现晶体管在垂直于基底100表面的方向上的多层堆叠，有利于利用有限的空间集成数量更多的晶体管，提高半导体结构的集成密度，以及在保证具有较优的性能的同时，实现更小体积的集成。
半导体柱110包括沟道区II以及位于沟道区II两侧的掺杂区，掺杂区包括第一掺杂区I和第二掺杂区III，第一掺杂区I、沟道区II以及第二掺杂区III沿半导体柱110的延伸方向即第一方向Y依次分布，第一掺杂区I和第二掺杂区III用于形成晶体管的源极和漏极，半导体柱110的沟道区II用于形成晶体管的沟道区II。在一些实施例中，第一掺杂区I和第二掺杂区III中的掺杂离子类型可以与沟道区II中的掺杂离子的类型不同。在一个例子中，第一掺杂区I和第二掺杂区III中的掺杂离子可以为N型离子，沟道区II中的掺杂离子可以为P型离子，P型离子可以是硼离子、铟离子或者镓离子中的至少一种，N型离子可以是砷离子、磷离子或者锑离子中的至少一种。在另一个例子中，第一掺杂区I和第二掺杂区III中的掺杂离子可以为P型离子，沟道区II中的掺杂离子可以为N型离子。在另一些实施例中，掺杂区中的掺杂离子类型也可以与沟道区II中的掺杂离子类型相同，即半导体柱110可以用于形成无结场效应晶体管。
参考图1和图2，半导体结构还包括：第一支撑层120，第一支撑层120位于沿第二 方向X排布的半导体柱110的沟道区II的侧壁；第二支撑层130，第二支撑层130位于相邻的第一支撑层120之间。多个字线结构160，字线结构160沿第二方向X延伸，至少位于沿第二方向X排布的多个半导体柱110的沟道区II在所述第三方向上的两个表面，且还位于第一支撑层120以及第二支撑层130在所述第三方向上的两个表面。其中，与半导体柱110的沟道区II的侧壁相接触的第一支撑层120在为字线结构提供支撑的同时，还为半导体柱110的沟道区II提供了隔离保护，第二支撑层130有利于加强对字线结构160的支撑力，第一支撑层120和第二支撑层130有利于避免字线结构160在相邻的半导体柱110沟道区II之间的位置发生形变或者断裂，有利于保证字线结构160具有较佳的连续性
本公开实施例中，沿第二方向X排布的一行半导体柱110共用一个字线结构160。字线结构160作为晶体管的栅极，用于基于控制信号导通沟道区II，实现源极与漏极之间载流子的传输。字线结构160的材料为导电材料，在一些例子中，字线结构160的材料包括多晶硅、氮化钛、钨、钼、钛、钴或者钌中的至少一者。
在一些实施例中，参考图1和图2，字线结构160包括：第一字线层161，第一字线层161位于半导体柱110的沟道区II的顶面、第一支撑层120的顶面以及第二支撑层130的顶面；第二字线层162，第二字线层162位于半导体柱110的沟道区II的底面、第一支撑层120的底面以及第二支撑层130的底面；在第三方向Z上，第一字线层161与第二字线层162的厚度相同。即字线结构160为两层导电层组成的双层字线结构，双层字线结构可在保证对晶体管具有较优的驱动能力的情况下，利用较少的字线材料形成结构更为简单的字线结构160，有利于降低半导体结构的制备成本以及加工难度。并且，厚度相同的第一字线层161和第二字线层162保证了第一字线层161和第二字线层162对半导体柱110的沟道区II具有同等效果的驱动能力，有利于提高半导体结构的电学性能。
在一些实施中，第一字线层161和第二字线层162的材料相同，且第一字线层161和第二字线层162为采用同一制备工艺同时形成的结构，如此，有利于降低第一字线层161和第二字线层162的制备难度。
在一些实施例中，参考图1和图2，半导体结构还包括：栅介质层150，栅介质层150位于半导体柱110的沟道区II在第三方向Z上的两个表面，且位于字线结构160与半导体柱110的沟道区II之间。栅介质层150用于实现字线结构160驱动晶体管的源极与晶体管的漏极导通。在一些实施例中，栅介质层150的材料可以为氧化硅，采用热氧工艺在材料为硅的半导体柱110上形成氧化硅的工艺成熟，有利于降低栅介质层150的制备难度。在另一些实施例中，栅介质层150的材料也可以为氮化硅或者氮氧化硅。
参考图1，沿第二方向X排布的相邻半导体柱110之间具有向第一方向Y延伸的间 隔区域，第一支撑层120以及第二支撑位于半导体柱110沟道区II侧壁之间的间隔区域中，本公开实施例中，第一支撑层120之间包括一个第二支撑层130，可以理解的是，若相邻半导体柱110的沟道区II的侧壁之间的间隔距离较大，第一支撑层120之间也可以包括多个在第二方向X间隔排布的第二支撑层130。
在一些实施例中，参考图1，第一支撑层120的顶面和第二支撑层130的顶面均与相邻的半导体柱110的顶面平齐，第一支撑层120和第二支撑层130的底面均与相邻的半导体柱110的底面平齐。如此，有利于保证字线结构160在半导体柱110、第一支撑层120以及第二支撑层130组成的较为平整的平面上延伸，有利于避免字线结构160发生弯折，进而有利于避免字线结构160断裂。
在一些实施例中，第一支撑层120和第二支撑层130的材料相同。如此，可采用同种制备工艺同时制备得到第一支撑层120和第二支撑层130，有利于降低第一支撑层120和第二支撑层130的制备难度。在一个例子中，第一支撑层120和第二支撑层130的材料可以为氧化硅。
参考图3，在一些实施例中，第一支撑层120与第二支撑之间包含空气间隙180。空气的介电常数较小，设置空气间隙180有利于降低相邻半导体柱110的沟道区II之间的耦合电容，有利于提高半导体结构的电学性能，空气间隙180还有利于提高半导体结构的散热能力。
参考图3，在一些实施例中，在第二方向X上，相邻半导体柱110之间包含至少两个第一支撑层120和至少两个空气间隙180，每一第一支撑层120的厚度相同，每一空气间隙180的宽度相同。如此，保证了不同半导体柱110之间的第一支撑层120、第二支撑层130具有相同的排布方式，且半导体柱110沟道区II侧壁之间的间隔距离相同，有利于降低半导体柱110之间的排布差异，保证半导体结构具有较优的电学均匀性。
参考图1，在一些实施例中，第一支撑层120与第二支撑层130之间具有加强层140。加强层140可以为支撑性较强的介质材料，设置加强层140有利于进一步提高对字线结构160的支撑能力，保证半导体结构中的字线结构160具有较高的稳定性。
参考图1，在一些实施例中，在第二方向X上，相邻半导体柱110之间包含至少两个第一支撑层120和至少两个加强层140，每一第二支撑层130的厚度相同，每一加强层140的厚度相同。如此，保证了不同半导体柱110之间的第一支撑层120、第二支撑层130以及加强层140具有相同的排布方式，且半导体柱110沟道区II侧壁之间的间隔距离相同，有利于降低半导体柱110之间的排布差异，保证半导体结构具有较优的电学均匀性。
参考图1，在一些实施例中，加强层140的材料与第一支撑层120的材料以及第二支 撑层130的材料不相同。在一些实施例中，可以采用较为常见的介质材料作为第一支撑层120和第二支撑，采用支撑能力较强的材料作为加强层140，通过平衡加强层140与第一支撑层120或第二支撑层130的制备成本以及制备难度，保证字线结构160具有足够的支撑力的同时，降低半导体结构的加工成本以及加工难度。在一个例子中，加强层140的材料可以为氮化硅。
参考图1或图3，在一些实施例中，半导体结构还包括：隔离层170，隔离层170位于相邻字线结构160之间。隔离层170将字线结构160隔离开，不仅有利于对字线结构160进行保护，还有利于防止字线结构160被后续工艺过程中的杂质破坏。隔离层170也为后续在字线结构160上形成的其它结构提供了支撑，有利于提高半导体结构的稳定性。
在一些实施例中，隔离层170的材料为氧化硅，氧化硅的制备工艺成熟，有利于降低半导体结构的加工难度。在另一些实施例中，隔离层170也可以为其它具有阻挡效果的绝缘材料，例如氮氧化硅。
参考图2，在一些实施例中，还包括：介质层107，介质层107位于邻近沟道区II的部分半导体柱110的掺杂区之间，且环绕部分半导体柱110的掺杂区II沿第一方向Y延伸的表面，介质层107与字线结构160在第一方向Y的两端相接触。介质层107不仅用于为在第三方向Z间隔排布的半导体柱110提供支撑，还将字线结构160的侧壁与其它结构隔离开，避免后续对半导体柱110的掺杂区的进行加工的过程中，对沟道区II以及字线结构160造成损伤。
在一些实施例中，介质层107的材料可以为氮化硅，氮化硅的制备工艺成熟，且氮化硅对杂质离子或水汽具有较佳的阻挡效果，有利于对字线结构160形成较优的保护效果。在另一些实施例中，介质层107的材料也可以为其它具有阻挡效果的绝缘材料，例如氮氧化硅。
上述实施例提供的半导体结构中，基底100上的多个半导体柱110用于形成晶体管的半导体通道，半导体柱110的沟道区II两侧的掺杂区用于形成晶体管的源极和漏极，字线结构160位于沿第二方向X排布的一行半导体柱110的沟道区II的顶面和底面，用于基于控制信号控制沿第二方向X排布的一行半导体柱110的沟道区II，半导体柱110顶面的字线结构160与半导体柱110底面的字线结构160之间除了具有间隔设置的半导体柱110，还包括相邻半导体柱110之间的第一支撑层120以及第二支撑层130，与半导体柱110的沟道区II的侧壁相接触的第一支撑层120用于为字线提供支撑，还用于为半导体柱110的沟道区II提供隔离保护，第二支撑层130用于以加强对字线结构160的支撑力，第一支撑层120和第二支撑层130有利于避免字线结构160在相邻的半导体柱110沟道区II之间的位置发生弯折 或者断裂，有利于保证字线结构160具有较佳的连续性。
相应的，本公开实施例另一方面还提供一种半导体结构的形成方法，半导体结构的形成方法可用于形成上述实施例所述的半导体结构。需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细说明，以下将不做赘述。
图4至图15为本公开实施例提供的一种半导体结构的形成方法的各步骤示意图。需要说明的是，图4至图15中，图7、图8以及图12为垂直于第二方向X的剖面图；图9至图11为半导体柱110的沟道区II处的垂直于第一方向Y的剖面图；图13至图14为垂直于第三方向Z的包括半导体柱110的剖面图(为了便于理解，图13至图14示出了半导体柱110的沟道区II上的字线结构160)。
参考图4，半导体结构的形成方法包括：提供基底。在一些实施例中，基底100可以为硅基底，基于硅基底的外延工艺较成熟，有利于降低形成半导体柱的工艺难度。
参考图4至图5，形成多个半导体柱110，半导体柱110沿第一方向Y延伸，多个半导体柱110在沿第二方向X以及第三方向Z间隔排布，第一方向Y以及第二方向X均平行于基底100表面，第三方向Z垂直于基底100表面，半导体柱110具有沟道区II以及位于沟道区II相对两侧的掺杂区。其中，半导体柱110可以用于形成晶体管的半导体通道，半导体柱110的沟道区II用于形成晶体管的沟道区II，半导体柱110的两个掺杂区分别用于形成晶体管的源极和漏极。
参考图4至图5，在一些实施例中，形成半导体柱110包括：形成在第三方向Z上间隔排布的多个半导体层101以及半导体层101之间的外延层102。其中，外延层102在第三方向Z的厚度用于定义在第三方向Z间隔排布的相邻半导体柱110之间的间隔距离，通过形成厚度均匀的外延层102以及半导体层101有利于形成形貌均匀且间隔距离均匀的半导体柱110。
在一些实施例中，半导体层101的材料为硅，在硅的基础上可以采用外延工艺形成多种性质的材料，有利于以硅为基础简易地制备得到外延层102，降低外延层102的制造难度。在另一些实施例中，半导体层101也可以为其它半导体通道材料，例如IGZO(铟镓锌氧化物，Indium Gallium Zinc Oxide)、IWO(掺钨氧化铟，Indium Tungsten Oxide)或者ITO(氧化铟锡，Indium Tin Oxide)中的一种，半导体通道由上述材料组成时，有利于提高半导体通道中载流子的迁移率，从而有利于使半导体通道高效地传递电信号。
在一些实施例中，外延层102的材料为锗化硅，在同一刻蚀条件下，锗化硅与硅材料具有不同的刻蚀选择比，如此，若采用硅作为半导体柱110的材料，对半导体柱110进行加工时，则可实现较为简易的对外延层102的选择性去除，以露出半导体柱110的表面。可 以理解的是，在另一些实施例中，外延层102的材料也可以为碳化硅或其它与硅相比具有不同刻蚀速率的材料。
在一些实施例中，可以采用选择性外延工艺形成外延层102以及半导体层101。通过选择性外延工艺形成外延层102，可使外延层102、半导体层101与基底100的热膨胀系数接近且晶格系数相匹配，进而使得相互邻接的膜层之间的热膨胀系数接近且晶格系数相匹配，可避免温度变化导致的应力变化以及晶格失配导致的应力不匹配，进而有利于避免应力不匹配导致的不同膜层之间的界面错位现象甚至膜层破裂现象，有利于提高半导体层101以及外延层102的平整度以及基底100的平整度。
参考图4和图5，形成半导体层101以及外延层102后包括：图形化半导体层101以及外延层102，形成沿第一方向Y延伸的凹槽，剩余半导体层101作为半导体柱110。在一些实施例中，在远离基底100的半导体层101的顶面形成具有刻蚀窗口的掩膜层，去除刻蚀窗口露出的半导体层101以及外延层102，形成多个沿第一方向Y延伸的凹槽以及多个间隔排布的半导体柱110。
在一些实施例中，还包括：对半导体柱110进行掺杂工艺，以形成后续半导体柱110的沟道区II、第一掺杂区I和第二掺杂区III，第一掺杂区I和第二掺杂区III即为沟道区II两侧的掺杂区。在一些实施例中，可以采用离子注入或者热扩散中的任一种工艺方法对半导体柱110进行掺杂。在另一些实施例中，也可以在形成半导体层101后，对半导体层101进行掺杂，以形成后续半导体柱110的沟道区II、第一掺杂区I和第二掺杂区III。
参考图5至图10，形成第一支撑层120和第二支撑层130，第一支撑层120位于沿第二方向X排布的半导体柱110的沟道区II侧壁，第二支撑层130位于相邻的第一支撑层120之间。其中，与半导体柱110的沟道区II的侧壁相接触的第一支撑层120用于为后续的字线结构提供支撑，以及用于为半导体柱110的沟道区II提供隔离保护，第二支撑层130用于提高对字线结构的支撑力，有利于避免字线结构在相邻的半导体柱110沟道区II之间的位置脱落甚至断裂，有利于保证字线结构具有较佳的连续性。
参考图5，在一些实施例中，形成第一支撑层120和第二支撑层130可以包括：在凹槽内形成第一支撑膜103和第二支撑膜105，第一支撑膜103与凹槽侧壁的半导体柱110以及外延层102相接触，第二支撑膜105与第一支撑膜103沿第二方向X间隔排布，且位于第一支撑膜103之间。与半导体柱110的沟道区II的侧壁相接触的第一支撑膜103用于形成后续的第一支撑层，不同半导体柱110的沟道区II的相邻侧壁之间的第二支撑膜105用于形成后续的第二支撑层。在一些实施例中，可以采用原子层沉积工艺形成第一支撑膜103以及第二支撑膜105，除了在凹槽内形成支撑膜，在远离基底100的半导体柱110的顶面也形成有 第一支撑膜103和第二支撑膜105。可选的，第二支撑膜105形成于第一支撑膜103的侧壁，或者，第一支撑膜103和第二支撑膜105间隔排布。
在一些实施例中，形成第一支撑膜103以及第二支撑膜105的过程中，还包括：形成加强膜104。加强膜104位于第一支撑膜103与第二支撑膜105之间，不同半导体柱110的沟道区II的相邻侧壁之间的加强膜104可用于形成后续第一支撑层120与第二支撑层130之间的加强层140，或者用于作为形成空气间隙的牺牲膜。在一些实施例中，可以在形成第一支撑膜103后，采用原子层沉积工艺形成加强膜104，形成加强膜104后，再形成第二支撑膜105。如此，相较于形成第一支撑膜103以及第二支撑膜105后，再形成加强膜104的工艺，不仅避免了在第一支撑膜103以及第二支撑膜105间隔的空隙中填充加强膜104，降低了加强膜104的制备难度，加强膜104还为第二支撑膜105提供了支撑，可通过填充的方式直接形成第二支撑膜105，有利于降低第二支撑膜105的制备难度。
参考图6，形成牺牲层106，牺牲层106位于邻近掺杂区的部分半导体柱110的沟道区II之间，且环绕部分半导体柱110的沟道区II沿第一方向Y延伸的表面，牺牲层106用于形成后续的露出半导体柱110的沟道区II之间的外延层102的刻蚀窗口。在一些实施例中，可以采用刻蚀工艺，去除沟槽内的部分第一支撑膜103、第二支撑膜105以及加强膜104，以露出邻近掺杂区的部分沟道区II的侧壁以及部分沟道区II之间的外延层102，去除部分半导体柱110之间的外延层102，形成填充孔，在填充孔形成牺牲层106。在一些实施例中，牺牲层106可以为采用旋涂的方式形成的掩膜层。
在一些实施例中，参考图6，还包括：形成介质层，介质层107位于邻近牺牲层106的部分半导体柱110的掺杂区之间，且环绕部分半导体柱110的掺杂区II沿第一方向Y延伸的表面。介质层107可以用于形成相邻半导体柱110之间的支撑结构，有利于保证去除外延层102后的半导体柱110仍具有较为可靠的结构稳定性。在一些实施例中，在形成牺牲层106之前，可以形成延伸至部分半导体柱110的掺杂区的填充孔，在填充孔内填充牺牲材料后，去除部分牺牲材料，在牺牲材料之间采用沉积工艺形成介质层107，介质层107一侧的牺牲材料作为牺牲层106。
参考图6至图7，去除牺牲层106，以露出半导体柱110的沟道区II之间的外延层102，参考图8，去除半导体柱110的沟道区II之间的外延层102，形成刻蚀孔108。刻蚀孔108不仅用于刻蚀去除部分第一支撑膜103和部分第二支撑膜105，刻蚀孔108还露出半导体柱110的沟道区II的顶面和底面，以便于后续在半导体柱110的沟道区II的顶面和底面形成字线结构。在一些实施例中，参考图6，可以在沿第二方向X排布的半导体柱110之间的部分区域形成开口，以露出牺牲层106在第二方向X的侧壁，进而去除牺牲层106。
参考图9和图10，去除刻蚀孔108侧壁之间的第一支撑膜103和第二支撑膜105，剩余第一支撑膜103作为第一支撑层120，剩余第二支撑膜105作为第二支撑层130。在一些实施例中，去除刻蚀孔108在第二方向X上的侧壁之间的第一支撑膜103和第二支撑膜105的同时，还去除刻蚀孔108侧壁之间的加强膜104。其中，可以使对第一支撑膜103、第二支撑膜105以及加强膜104刻蚀选择比较高的刻蚀液流入刻蚀孔108，以去除部分第一支撑膜103、第二支撑膜105以及部分加强膜104，如此，可以仅去除刻蚀孔108侧壁露出的第一支撑膜103、第二支撑膜105和加强膜104，有利于降低第一支撑层120以及第二支撑层130的制备难度。
参考图10，在一些实施例中，剩余的加强膜104作为加强层140，以提高后续位于第一支撑层120和第二支撑层130顶面以及底面的字线结构160的结构稳定性。
参考图11，半导体结构的形成方法还包括：形成栅介质层150，在一些实施例中，可以采用原子层沉积工艺或热氧工艺在半导体柱110的沟道区II的顶面和底面形成栅介质层150，在一些实施例中，第一支撑层120、第二支撑层130以及加强层140的顶面和底面也形成有栅介质层150。
参考图11和图12，形成多个字线结构160，字线结构160沿第二方向X延伸，至少位于沿第二方向X排布的多个半导体柱110的沟道区II的顶面和底面，且还位于第一支撑层120以及第二支撑层130的顶面和底面。在一些实施例中，可以在栅介质层150远离半导体柱110的表面以及栅介质层150远离第一支撑层120、第二支撑层130以及加强层140的表面形成导电层，位于半导体柱110的沟道区II顶面、第一支撑层120顶面以及第二支撑层130顶面的导电层为第一字线层161，位于半导体柱110的沟道区II底面、第一支撑层120底面以及第二支撑层130底面的导电层为第二字线层162，第一字线层161和第二字线层162共同构成字线结构160。
在一些实施例中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺中的至少一种方式形成字线结构160。
在一些实施例中，参考图1和图2，形成字线结构160后还包括：形成字线结构160之间的隔离层170，隔离层170位于相邻字线结构160之间，不仅有利于对字线结构160进行保护，以及有利于提高半导体结构的稳定性。
在一些实施例中，参考图3、图13至图15，还包括：去除加强层140，形成空气间隙180。参考图13，在一些实施例中，在邻近掺杂区的部分沿第二方向X排布的半导体柱110的沟道区II的侧壁之间的也形成有隔离层170。参考图14，去除加强层140之前包括：去除与第一支撑层120、第二支撑层130以及加强层140在第一方向Y的侧壁相接触的隔离 层170以及介质层107，以露出加强层140在第一方向Y的侧壁，在利用对加强层140刻蚀选择比较高的刻蚀工艺，选择性去除第一支撑层120和第二支撑层130之间的加强层140。
在一些实施例中，参考图6，也可以在去除牺牲层106之前，利用去除牺牲层106形成的开口，去除第一支撑膜103与第二支撑膜105之间的加强膜104，即可形成后续的第一支撑层120与第二支撑层130之间的空气间隙180。
在一些实施例中，去除加强层140后还包括，形成对半导体柱110提供支撑的介质层107。
在一些实施例中，去除介质层107包括仅去除第一支撑层120、第二支撑层130以及加强膜104在第一方向Y的侧壁延伸方向的介质层107，保留半导体柱110顶面与底面之间的介质层107。
在一些实施例中，参考图15，半导体结构的形成方法还包括：去除半导体柱110的一掺杂区之间的介质层107以及其它绝缘材料，以形成电容结构，因此，也可在去除半导体柱110的一掺杂区之间的介质层107以及其它绝缘材料后，露出加强层140在第一方向Y的一侧的侧壁，并去除加强层140。如此，无需增加额外的工艺步骤去除加强层140，有利于降低去除加强层140的难度。
上述实施例提供的半导体结构的形成方法中，形成了在第二方向X排布的半导体柱110的沟道区II之间的第一支撑层120以及第二支撑层130，以及在半导体柱110的沟道区II的顶部和底部、第一支撑层120的顶部和底部以及第二支撑层130的顶部和底部形成字线结构160，利用第一支撑层120和第二支撑层130为字线结构160提供支撑，避免了字线结构160形变以及避免了字线结构160断裂，有利于形成连续性更优以及结构稳定性更高的字线结构160。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自变动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (18)

  1. 一种半导体结构，包括：
    基底(100)；
    位于所述基底(100)上方的多个半导体柱(110)，所述半导体柱(110)沿第一方向(Y)延伸，多个所述半导体柱(110)在沿第二方向(X)以及第三方向(Z)间隔排布，所述半导体柱(110)具有沟道区(II)以及位于所述沟道区(II)相对两侧的掺杂区；
    第一支撑层(120)，所述第一支撑层(120)位于沿所述第二方向(X)排布的所述半导体柱(110)的所述沟道区(II)侧壁；
    第二支撑层(130)，所述第二支撑层(130)位于相邻的所述第一支撑层(120)之间；
    多个字线结构(160)，所述字线结构(160)沿所述第二方向(X)延伸，至少位于沿所述第二方向(X)排布的多个所述半导体柱(110)的所述沟道区(II)在所述第三方向(Z)上的两个表面，且还位于所述第一支撑层(120)以及所述第二支撑层(130)在所述第三方向(Z)上的两个表面。
  2. 根据权利要求1所述的半导体结构，其中，所述第一方向(Y)以及所述第二方向(X)均平行于所述基底(100)表面，所述第三方向(Z)垂直于所述基底(100)表面，所述第一支撑层(120)的顶面和所述第二支撑层(130)的顶面均与相邻的所述半导体柱(110)的顶面平齐，所述第一支撑层(120)和所述第二支撑层(130)的底面均与相邻的所述半导体柱(110)的底面平齐。
  3. 根据权利要求1所述的半导体结构，其中，所述第一支撑层(120)与所述第二支撑层(130)之间包含空气间隙(180)。
  4. 根据权利要求3所述的半导体结构，其中，在所述第二方向(X)上，相邻所述半导体柱(110)之间包含至少两个所述第一支撑层(120)和至少两个所述空气间隙(180)，每一所述第一支撑层(120)的厚度相同，每一所述空气间隙(180)的宽度相同。
  5. 根据权利要求1所述的半导体结构，其中，所述第一支撑层(120)与所述第二支撑层(130)之间具有加强层(140)。
  6. 根据权利要求5所述的半导体结构，其中，在所述第二方向(X)上，相邻所述半导体柱(110)之间包含至少两个所述第一支撑层(120)和至少两个所述加强层(140)，每一所述第一支撑层(120)的厚度相同，每一所述加强层(140)的厚度相同。
  7. 根据权利要求5所述的半导体结构，其中，所述加强层(140)的材料与所述第一支撑的 材料以及所述第二支撑层(130)的材料不相同。
  8. 根据权利要求1所述的半导体结构，其中，所述第一支撑层(120)和所述第二支撑层(130)的材料相同。
  9. 根据权利要求2所述的半导体结构，其中，所述字线结构(160)包括：
    第一字线层(161)，所述第一字线层(161)位于所述半导体柱(110)的所述沟道区(II)的顶面、所述第一支撑层(120)的顶面以及所述第二支撑层(130)的顶面；
    第二字线层(162)，所述第二字线层(162)位于所述半导体柱(110)的所述沟道区(II)的底面、所述第一支撑层(120)的底面以及所述第二支撑层(130)的底面；
    在所述第三方向(Z)上，所述第一字线层(161)与所述第二字线层(162)的厚度相同。
  10. 根据权利要求1所述的半导体结构，其中，还包括：栅介质层(150)，所述栅介质层(150)位于所述半导体柱(110)的所述沟道区(II)在所述第三方向(Z)上的两个表面，且位于所述字线结构(160)与所述半导体柱(110)的所述沟道区(II)之间。
  11. 根据权利要求1所述的半导体结构，其中，还包括：隔离层(170)，所述隔离层(170)位于相邻所述字线结构(160)之间。
  12. 根据权利要求1所述的半导体结构，其中，还包括：介质层(107)，所述介质层(107)位于邻近所述沟道区(II)的部分所述半导体柱(110)的所述掺杂区之间，且环绕部分所述半导体柱(110)的所述掺杂区沿所述第一方向(Y)延伸的表面，所述介质层(107)与所述字线结构(160)在所述第一方向(Y)的两端相接触。
  13. 一种半导体结构的形成方法，包括：
    提供基底(100)；
    形成位于所述基底(100)上方的多个半导体柱(110)，所述半导体柱(110)沿第一方向(Y)延伸，多个所述半导体柱(110)在沿第二方向(X)以及第三方向(Z)间隔排布，所述半导体柱(110)具有沟道区(II)以及位于所述沟道区(II)相对两侧的掺杂区；
    形成第一支撑层(120)，所述第一支撑层(120)位于沿所述第二方向(X)排布的所述半导体柱(110)的所述沟道区(II)侧壁；
    形成第二支撑层(130)，所述第二支撑层(130)位于相邻的所述第一支撑层(120)之间；
    形成多个字线结构(160)，所述字线结构(160)沿所述第二方向(X)延伸，至少位于沿所述第二方向(X)排布的多个所述半导体柱(110)的所述沟道区(II)在所述第三方向(Z)上的两个表面，且还位于所述第一支撑层(120)以及所述第二支撑层(130)在所述第三方向(Z)上的两个表面。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，形成所述半导体柱(110)包括：
    形成在所述第三方向(Z)上间隔排布的多个半导体层(101)以及所述半导体层(101)之间的外延层(102)；
    图形化所述半导体层(101)以及所述外延层(102)，形成沿所述第一方向(Y)延伸的凹槽，剩余所述半导体层(101)作为所述半导体柱(110)。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，形成所述第一支撑层(120)和所述第二支撑层(130)包括：
    在所述凹槽内形成第一支撑膜(103)和第二支撑膜(105)，所述第一支撑膜(103)与所述凹槽侧壁的所述半导体柱(110)以及所述外延层(102)相接触，所述第二支撑膜(105)与所述第一支撑膜(103)沿所述第二方向(X)间隔排布，且位于所述第一支撑膜(103)之间；
    形成牺牲层(106)，所述牺牲层(106)位于邻近所述掺杂区的部分所述半导体柱(110)的所述沟道区(II)之间，且环绕部分所述半导体柱(110)的所述沟道区(II)沿所述第一方向(Y)延伸的表面；
    去除所述牺牲层(106)，以露出所述半导体柱(110)的所述沟道区(II)之间的所述外延层(102)；
    去除所述半导体柱(110)的所述沟道区(II)之间的所述外延层(102)，形成刻蚀孔(108)；
    去除所述刻蚀孔(108)侧壁之间的所述第一支撑膜(103)和所述第二支撑膜(105)，剩余所述第一支撑膜(103)作为所述第一支撑层(120)，剩余所述第二支撑膜(105)作为所述第二支撑层(130)。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，形成所述牺牲层(106)前还包括：
    形成加强膜(104)；
    去除所述刻蚀孔(108)侧壁之间的所述第一支撑膜(103)和所述第二支撑膜(105)的同时，还去除所述刻蚀孔(108)侧壁之间的所述加强膜(104)。
  17. 根据权利要求16所述的半导体结构的形成方法，其中，还包括：去除所述加强膜(104)，形成空气间隙(180)。
  18. 根据权利要求15所述的半导体结构的形成方法，其中，去除所述牺牲层(106)之前还包括：
    形成介质层(107)，所述介质层(107)位于邻近所述牺牲层(106)的部分所述半导体柱(110)的所述掺杂区的之间，且环绕部分所述半导体柱(110)的所述掺杂区沿所述第一方向(Y)延伸的表面。
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