WO2023060796A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

Info

Publication number
WO2023060796A1
WO2023060796A1 PCT/CN2022/071263 CN2022071263W WO2023060796A1 WO 2023060796 A1 WO2023060796 A1 WO 2023060796A1 CN 2022071263 W CN2022071263 W CN 2022071263W WO 2023060796 A1 WO2023060796 A1 WO 2023060796A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
semiconductor structure
bit line
line contact
structure according
Prior art date
Application number
PCT/CN2022/071263
Other languages
English (en)
French (fr)
Inventor
严勋
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22782646.8A priority Critical patent/EP4207264A4/en
Priority to US17/805,738 priority patent/US20230114038A1/en
Publication of WO2023060796A1 publication Critical patent/WO2023060796A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
  • Dynamic random access memory (Dynamic random access memory, referred to as DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices.
  • DRAM generally includes a plurality of repeated storage cells, each of which includes a transistor and a capacitor, wherein the gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line through the bit line contact structure, and the drain is electrically connected to the bit line.
  • the capacitor contact is electrically connected with the capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.
  • bit line contact structure when the bit line contact structure is formed, voids are easily formed in the bit line contact structure, and the void will cause electrical connection between the capacitive contact structure and the bit line, thereby reducing the yield of the semiconductor structure.
  • a first aspect of an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which includes the following steps:
  • the substrate has a plurality of bit line contact regions arranged at intervals;
  • first conductive layer in each of the bit line contact regions, the first conductive layer enclosing a contact hole in each of the bit line contact regions;
  • a second conductive layer is formed in each of the contact holes, the second conductive layer and the first conductive layer constitute a conductive layer, wherein the concentration of doping impurities in the second conductive layer is greater than that of the first conductive layer The concentration of dopant impurities in the conductive layer.
  • the concentration of doped impurities in the second conductive layer is 1.5 to 3 times the concentration of doped impurities in the first conductive layer.
  • the step of forming the first conductive layer in the bit line contact region includes:
  • first initial conductive layer in each of the bit line contact areas, the first initial conductive layer enclosing an intermediate hole in each of the bit line contact areas;
  • the remaining first initial conductive layer constitutes the first conductive layer, and the first conductive layer is in the bit line contact region surround the contact hole.
  • the contact hole has a longitudinal section shape of a trapezoid with a larger top and a smaller bottom.
  • the contact hole takes a section perpendicular to the substrate as a longitudinal section, the contact hole has a V-shaped longitudinal section.
  • the included angle between the sidewall of the contact hole and the direction perpendicular to the substrate is 10°-20°.
  • the thickness of the first conductive layer is between 0nm and 6nm.
  • the thickness of the first conductive layer on the bottom wall of the bit line contact region is between 5nm and 8nm.
  • the thickness of the first initial conductive layer is between 5nm and 18nm.
  • the thickness of the first initial conductive layer on the bottom wall of the bit line contact region is between 10nm and 18nm.
  • both the first conductive layer and the second conductive layer are made of polysilicon, and doped with phosphorus ions.
  • the preparation method before the step of forming the first conductive layer in the bit line contact region, the preparation method further includes:
  • a protective layer is formed on sidewalls of the bit line contact region.
  • the thickness of the protective layer is 3-6 nm, and the material of the protective layer includes polysilicon.
  • the etching gas includes chlorine gas, and the etching temperature is between 250°C and 320°C.
  • a second aspect of the embodiments of the present disclosure provides a semiconductor structure, which is manufactured by the semiconductor structure manufacturing method in the above embodiments.
  • FIG. 1 is a structural schematic diagram 1 of a semiconductor structure provided in the related art
  • FIG. 2 is a structural schematic diagram II of a semiconductor structure provided in the related art
  • FIG. 3 is a process flow diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of forming a bit line contact region in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of forming a protective layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a first initial conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7 is a structural schematic diagram 1 of forming a contact hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 8 is a second structural schematic diagram of forming a contact hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 9 is a structural schematic diagram of forming a second conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • Fig. 10 is a second structural schematic diagram of forming a second conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • bit line structure and the isolation sidewall covering the bit line structure are usually formed first.
  • the bit line structure includes a bit line contact structure and a bit line arranged in layers. Afterwards, a capacitive contact structure is formed between adjacent isolation spacers, wherein the capacitive contact structure is used to connect the capacitor and the active area of the substrate to realize data storage.
  • the bit line contact region is first formed in the substrate 10, and then the conductive layer 20 is formed in the bit line contact region.
  • the conductive layer 20 is etched to form a bit line contact structure, the voids will be exposed, resulting in disconnection in some areas of the bit line contact structure, and then forming an isolation side.
  • the insulating material used to form the isolation side wall will fill the gap, causing the isolation side wall to break in the gap and cannot completely cover the bit line.
  • the capacitive contact structure is subsequently formed, the capacitive contact structure It is easy to be electrically connected to the bit line structure, reducing the yield of the semiconductor structure.
  • the first conductive layer and the second conductive layer are respectively formed by two deposition processes, and the concentration of doping impurities in the first conductive layer is lower than that of the doping impurities in the second conductive layer. Concentration, because the lower the concentration of doping impurity is, the higher the filling ability is, so when forming the first conductive layer, gaps can be avoided.
  • the first conductive layer forms a contact hole in the bit line contact region, and the contact hole has A smaller aspect ratio, so that when forming the second conductive layer, it can also avoid the formation of gaps in the second conductive layer, thereby avoiding the formation of gaps in the conductive layer, so that in the subsequent formation of bit line structures and isolation spacers, there will be no Damage to the isolation sidewall will not cause electrical connection between the capacitor contact structure and the bit line, thereby improving the yield rate of the semiconductor structure.
  • FIG. 3 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIGS. 4 to 10 are schematic diagrams of various stages of the method for preparing a semiconductor structure. The method for preparing a semiconductor structure will be described in detail below in conjunction with FIGS. 4 to 10 introduction.
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • the method for preparing a semiconductor structure includes the following steps:
  • Step S100 providing a substrate, in which there are a plurality of bit line contact regions arranged at intervals.
  • the substrate 10 is used as a supporting component of the DRAM for supporting other components disposed thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be silicon, germanium, One or more of silicon-germanium compounds and silicon-carbon compounds.
  • the substrate 10 has a plurality of active regions 11 and an isolation structure 12 for separating each active region 11, wherein the plurality of active regions 11 can be arranged at intervals, and the active regions 11 are used for setting semiconductor devices, such as transistors and capacitors .
  • the preparation process of the isolation structure 12 is usually to pattern the substrate 10 to form an isolation trench in the substrate 10, and then deposit silicon oxide in the isolation trench by using a deposition process to form the isolation structure 12.
  • the isolation structure 12 is used to realize each Insulation between the active regions 11 is provided.
  • bit line contact regions 13 there are a plurality of bit line contact regions 13 in the substrate 10, and the plurality of bit line contact regions 13 can be arranged on the substrate 10 at intervals.
  • a patterned mask layer 30 can be formed on the substrate 10 , and then using the mask layer 30 as a mask, using etching gas or etching solution to remove part of the thickness of the substrate 10 to form the bit line contact region 13 in the substrate 10 .
  • a photoresist layer with a certain thickness can be formed on the mask layer 30 through the process of coating, and then a mask can be formed on the photoresist layer through the processes of exposure, etching and development. Then, the mask layer 30 not covered by the mask pattern is removed by using an etching solution or an etching gas to form a pattern in the mask layer 30 .
  • the mask layer 30 can be a single film layer, or a composite film layer.
  • the mask layer 30 can include a silicon nitride layer, a polysilicon layer, and a silicon oxide layer stacked in sequence, wherein the silicon nitride layer is set On the substrate 10, in this embodiment, by making the mask layer 30 a composite film layer, the pattern can be transferred to the silicon oxide layer in the pattern transfer process, and then transferred to the polysilicon layer, the silicon nitride layer and the substrate 10 in sequence. In this way, the accuracy of the pattern transfer process can be improved, and the accuracy of the pattern of the bit line contact region 13 can be ensured.
  • the protective layer 40 can be formed in the bit line contact region 13 , or the conductive layer 20 can be directly formed.
  • the following embodiments form the protective layer 40 in the bit line contact region 13 As an example to illustrate.
  • a protection layer 40 is formed on the sidewall of the bit line contact region 13, and the protection layer 40 is used to protect the isolation structure 12 exposed in the bit line contact region 13 to prevent subsequent The isolation structure 12 is damaged when the bit line contact region 13 is cleaned.
  • the material of the protection layer 40 includes polysilicon.
  • the protective layer 40 has a thickness of 3-6 nm. As shown in FIG. 5 , along the X direction in the figure, the protective layer 40 has a certain thickness D1, and the thickness D1 is between 3-6 nm.
  • the thickness of the protection layer 40 is less than 3nm, the thickness of the protection layer 40 will be too small, so that the isolation structure 12 will still be damaged when the bit line contact region 13 is subsequently cleaned. If the thickness of the protection layer 40 is greater than 6nm, then The area surrounded by the protection layer 40 will be too small, and the aspect ratio of the area will be increased, so that there will still be gaps in the subsequently formed bit line contact structure.
  • the present embodiment limits the thickness of the protective layer 40. While protecting the isolation structure 12, it can also prevent gaps in the subsequent formation of the bit line contact structure, thereby avoiding the occurrence of the capacitive contact structure and the bit line structure. electrical connection, improving the yield of the semiconductor structure.
  • Step S200 forming a first conductive layer in each bit line contact area, the first conductive layer enclosing a contact hole in each bit line contact area.
  • the first conductive layer 21 is formed by a deposition process
  • the deposition process may include at least one of a physical vapor deposition process, a chemical vapor deposition process and an atomic layer deposition process.
  • Step S300 forming a second conductive layer in each contact hole, the second conductive layer and the first conductive layer constitute a conductive layer, wherein the concentration of doped impurities in the second conductive layer is greater than that of the doped impurities in the first conductive layer Concentration, its structure is shown in Figure 9 and Figure 10.
  • the second conductive layer 22 may also be formed by a deposition process, for example, the deposition process may include at least one of a physical vapor deposition process, a chemical vapor deposition process and an atomic layer deposition process.
  • the materials in the first conductive layer 21 and the second conductive layer 22 are both polysilicon, and the doped impurities are all phosphorus ions, wherein the concentration of the doped impurities in the second conductive layer 22 is equal to that of the first conductive layer 22.
  • the layer 21 is doped with 1.5 to 3 times the concentration of impurities.
  • the concentration of dopant impurities in the first conductive layer 21 is 1E20-10E20, that is, the concentration of dopant impurities in the first conductive layer 21 is 1*10 20 -10*10 20
  • the concentration of dopant impurities in the second conductive layer 22 is The concentration of doping impurities in the second conductive layer 22 is 15E20 ⁇ 30E20, that is, the concentration of doping impurities in the second conductive layer 22 is 15*10 20 ⁇ 30*10 20 .
  • the conductive layer 20 is formed by two deposition processes in this embodiment, that is, the first deposition process is used to form the first conductive layer 21.
  • the second deposition process is used to form the second conductive layer 22, and the concentration of doping impurities in the first conductive layer 21 is smaller than the concentration of doping impurities in the second conductive layer 22, because the lower the concentration of doping impurities, the filling The higher the capability, the formation of gaps can be avoided when forming the first conductive layer 21.
  • the first conductive layer 21 forms a contact hole 25 in the bit line contact region 13, and the contact hole 25 has a smaller aspect ratio, so that
  • the second conductive layer 22 it is also possible to avoid the formation of gaps in the second conductive layer 22, thereby avoiding the formation of gaps in the conductive layer 20, so that when the bit line structure and the isolation spacer are subsequently formed, the isolation spacer will not be damaged.
  • the electrical connection between the capacitive contact structure and the bit line will not be caused, and the yield rate of the semiconductor structure is improved.
  • the concentration of doping impurities in the second conductive layer 22 is relatively high, which can improve the conductivity of the second conductive layer 22 , thereby improving the conductivity of the conductive layer 20 and improving the performance of the semiconductor structure.
  • the process of forming the first conductive layer 21 in each bit line contact region 13 may be implemented in the following manner.
  • a first initial conductive layer 23 is formed in each bit line contact region 13 by a deposition process, and the first initial conductive layer 23 extends out of the bit line contact region 13 and covers the mask layer 30 , wherein the first initial conductive layer 23 encloses a middle hole 24 in each bit line contact region 13 .
  • the deposition process may include at least one of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.
  • the thickness of the first initial conductive layer 23 is between 5nm and 18nm.
  • the thickness of the first initial conductive layer 23 is as shown in D2 in Figure 6. If so, the thickness of the first initial conductive layer 23 is less than 5nm, which is not conducive to Subsequent formation of the first conductive layer 21, if the first initial conductive layer 23 is greater than 18nm, the thickness of the first initial conductive layer 23 is too large, it is difficult to form the middle hole 24, and the difficulty of subsequent formation and removal of the first initial conductive layer 23 is increased. Therefore, in this embodiment, the thickness of the first initial conductive layer 23 is limited to 5-18 nm, which can facilitate the formation of the first conductive layer 21 and reduce the difficulty of preparation of the first conductive layer 21 .
  • the first direction may be the X direction in FIG. 6 .
  • the thickness of the first initial conductive layer 23 on the bottom wall of the bit line contact region 13 is between 10 and 18 nm, and the thickness of the first initial conductive layer 23 on the bottom wall of the bit line contact region 13 is as shown in FIG. 6 Indicated in D3.
  • the thickness of the first initial conductive layer 23 on the bottom wall of the bit line contact region 13 is less than 10 nm, the thickness of the subsequently formed first conductive layer 21 along the direction perpendicular to the substrate 10 will be too small, resulting in contact holes.
  • the depth of 25 is still very large, which will cause voids to be formed in the subsequently formed second conductive layer 22 .
  • the thickness of the first initial conductive layer 23 on the bottom wall of the bit line contact region 13 is greater than 18 nm, the depth of the subsequently formed contact hole 25 will be reduced, resulting in a lower conductivity of the subsequently formed second conductive layer 22 , thereby reducing the conductivity of the conductive layer 20 .
  • the thickness of the first initial conductive layer 23 located on the bottom wall of the bit line contact region 13 is limited to 10-18 nm, which can prevent the formation of voids in the second conductive layer 22 and improve the conductivity.
  • the ability of layer 20 to conduct electricity enhances the performance of the semiconductor structure.
  • an etching gas is introduced into the middle hole 24, and the etching gas can etch part of the first initial conductive layer 23, and the remaining first initial conductive layer
  • the layer 23 constitutes the first conductive layer 21, and the first conductive layer 21 encloses a contact hole 25 in the bit line contact area.
  • the etching gas includes chlorine gas
  • the etching temperature is between 250°C and 320°C. If the etching temperature is lower than 250°C, the etching rate will decrease, the etching time will be increased, and the production cost will be increased. If so, the etching temperature will be lower than 250°C. If the temperature is higher than 320°C, it is easy to over-etch the first initial conductive layer 23, reduce the thickness of the first conductive layer 21, and cause the contact hole 25 to still have a high aspect ratio. As a limitation, both the production cost and the aspect ratio of the contact hole 25 must be reduced to prevent the formation of voids in the bit line contact structure.
  • the shape of the contact hole 25 can be selected in many ways.
  • the vertical section of the contact hole 25 is a trapezoid with a vertical section perpendicular to the substrate 10, and the trapezoid is large at the top and small at the bottom.
  • the structure is as shown in FIG. 7; for another example, the vertical section of the contact hole 25 is V-shaped with the cross section perpendicular to the direction of the substrate 10, and its structure is shown in FIG. 8.
  • This embodiment adopts Defining the shape of the contact hole 25 can facilitate subsequent deposition of the second conductive layer 22 and prevent the formation of voids in the second conductive layer 22 .
  • the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 is 10°-20°, and the angle between the sidewall of the contact hole 25 and the direction perpendicular to the Y direction The included angle is ⁇ in Fig. 7 and Fig. 8 .
  • the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 is less than 10°, the top opening of the contact hole 25 will be too small, which will increase the difficulty of subsequent deposition of the second conductive layer 22. Still Voids will be formed in the second conductive layer 22 .
  • the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 is greater than 20°, the depth of the contact hole 25 will be too small, and the thickness of the subsequently formed second conductive layer 22 will be too small, reducing the The conductivity of the second conductive layer 22 further reduces the conductivity of the conductive layer 20 and reduces the performance of the semiconductor structure.
  • this embodiment limits the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 , which can prevent the formation of voids in the second conductive layer 22 and increase the conductivity of the conductive layer 20 .
  • the thickness of the first conductive layer 21 is between 0 nm and 6 nm.
  • the thickness of the first conductive layer 21 is D4, and the thickness of the first conductive layer 21 is D4 is between 0 and 6 nm, wherein the thickness of the first conductive layer 21 can be equal, that is, along the direction perpendicular to the substrate 10, the thickness of the first conductive layer 21 can be equal everywhere; along the direction perpendicular to the substrate 10 , the thickness of the first conductive layer 21 can be gradual, for example, as shown in FIG.
  • a conductive layer 21 may have a thickness of 3-6 nm.
  • the thickness of the first conductive layer 21 by limiting the thickness of the first conductive layer 21 , it can not only prevent the formation of voids in the first conductive layer 21 , but also ensure the conductivity of the conductive layer 20 and improve the performance of the semiconductor structure.
  • the thickness of the first conductive layer 21 on the bottom wall of the bit line contact region 13 is between 5nm and 8nm.
  • the thickness D5 of the first conductive layer 21 is between 5nm and 8nm. If the thickness D5 of the first conductive layer 21 is less than 5nm, the contact hole 25 will still have an aspect ratio, resulting in the formation of When the second conductive layer 22 is formed, voids are easily formed in the second conductive layer 22 , thereby causing the subsequently formed capacitive contact structure to be electrically connected to the bit line structure, reducing the yield of the semiconductor structure.
  • the thickness D5 of the first conductive layer 21 is greater than 8nm, the depth of the contact hole 25 will be too small, and the thickness of the second conductive layer 22 will be too small, which will reduce the conductivity of the second conductive layer 22.
  • the conductivity of the conductive layer 20 will be reduced, and the performance of the semiconductor structure will be reduced.
  • the thickness of the first conductive layer 21 is limited along the direction perpendicular to the substrate 10, which can prevent the subsequently formed capacitive contact structure from being electrically connected to the bit line structure, and improve the yield of the semiconductor structure. , can also ensure the conductivity of the conductive layer 20, improving the performance of the semiconductor structure.
  • the bit line contact structure in the semiconductor structure in this embodiment includes the first conductive layer stacked 21 and the second conductive layer 22, and the first conductive layer 21 and the second conductive layer 22 have a dense structure without gaps, so that when the bit line and the spacer spacer are subsequently formed, the spacer spacer will not be damaged, and the spacer spacer will not be damaged. This will cause electrical connection between the capacitive contact structure and the bit line structure, thereby improving the yield rate of the semiconductor structure.
  • the concentration of doping impurities in the second conductive layer 22 is relatively high, so as to ensure that there will be no voids in the second conductive layer 22, and at the same time, it can also improve the conductivity of the second conductive layer 22, thereby improving the contact structure of the bit line.
  • the ability to conduct electricity improves the performance of semiconductor structures.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开提供一种半导体结构及其制备方法，涉及半导体技术领域，该半导体结构的制备方法包括：提供具有位线接触区的基底；在位线接触区形成第一导电层和第二导电层。本公开通过两次沉积工艺分别形成第一导电层和第二导电层，且第一导电层中掺杂杂质的浓度小于第二导电层中掺杂杂质的浓度，由于掺杂杂质的浓度越低填充能力越高，这样在形成第一导电层时可以避免形成缝隙，并且第一导电层在位线接触区内围成接触孔具有较小的深宽比，在形成第二导电层时，可以避免在第二导电层形成缝隙，这样在后续形成位线以及隔离侧墙时，不会损坏隔离侧墙，进而不会造成电容接触结构与位线发生电连接，提高了半导体结构的良率。

Description

半导体结构及其制备方法
本公开要求于2021年10月13日提交中国专利局、申请号为202111192543.4、申请名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法。
背景技术
动态随机存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
动态随机存储器通常包括多个重复的储存单元，每个存储单元包括一个晶体管和一个电容器，其中，晶体管的栅极与字线电连接、源极通过位线接触结构与位线电连接、漏极通过电容接触与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
但是在形成位线接触结构时，位线接触结构内易形成空隙，该空隙会致使电容接触结构与位线之间发生电连接，进而降低半导体结构的良率。
发明内容
本公开实施例的第一方面提供一种半导体结构的制备方法，其包括如下步骤：
提供基底，所述基底内具有多个间隔设置的位线接触区；
在每个所述位线接触区内形成第一导电层，所述第一导电层在每个所述位线接触区内围成一个接触孔；
在每个所述接触孔内形成第二导电层，所述第二导电层和所述第一导 电层构成导电层，其中，所述第二导电层中掺杂杂质的浓度大于所述第一导电层中掺杂杂质的浓度。
在一些实施例中，所述第二导电层中掺杂杂质的浓度为所述第一导电层中掺杂杂质的浓度的1.5～3倍。
在一些实施例中，在所述位线接触区内形成第一导电层的步骤中包括：
在每个所述位线接触区形成第一初始导电层，所述第一初始导电层在每个所述位线接触区内围成一个中间孔；
向所述中间孔内通入刻蚀气体，去除部分所述第一初始导电层，被保留下来的第一初始导电层构成第一导电层，且第一导电层在所述位线接触区内围成接触孔。
在一些实施例中，以垂直于所述基底的方向的截面为纵截面，所述接触孔的纵截面形状为上大下小的梯形。
在一些实施例中，以垂直于所述基底的方向的截面为纵截面，所述接触孔的纵截面形状为V型。
在一些实施例中，所述接触孔的侧壁与垂直于所述基底的方向之间的夹角位于10°～20°。
在一些实施例中，沿第一方向，所述第一导电层的厚度位于0～6nm之间。
在一些实施例中，位于所述位线接触区的底壁上的第一导电层的厚度位于5～8nm之间。
在一些实施例中，沿第一方向，所述第一初始导电层的厚度位于5～18nm之间。
在一些实施例中，位于所述位线接触区的底壁上的第一初始导电层的厚度位于10～18nm之间。
在一些实施例中，所述第一导电层和所述第二导电层的材质均包括多晶硅，且掺杂杂质均为磷离子。
在一些实施例中，在所述位线接触区内形成第一导电层的步骤之前，所述制备方法还包括：
在所述位线接触区的侧壁上形成防护层。
在一些实施例中，所述防护层的厚度位于3～6nm，且所述防护层的材质包括多晶硅。
在一些实施例中，所述刻蚀气体包括氯气，且刻蚀温度位于250℃～320℃。
本公开实施例的第二方面提供一种半导体结构，所述半导体结构通过如上述实施例中的半导体结构的制备方法制得。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施例提供的半导体结构及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中提供的半导体结构的结构示意图一；
图2为相关技术中提供的半导体结构的结构示意图二；
图3为本公开实施例提供的半导体结构的制备方法的工艺流程图；
图4为本公开实施例提供的半导体结构的制备方法中形成位线接触区的结构示意图；
图5为本公开实施例提供的半导体结构的制备方法中形成防护层的结构示意图；
图6为本公开实施例提供的半导体结构的制备方法中形成第一初始导电层的结构示意图；
图7为本公开实施例提供的半导体结构的制备方法中形成接触孔的结构示意图一；
图8为本公开实施例提供的半导体结构的制备方法中形成接触孔的结构示意图二；
图9为本公开实施例提供的半导体结构的制备方法中形成第二导电层的结构示意图一
图10为本公开实施例提供的半导体结构的制备方法中形成第二导电 层的结构示意图二。
附图标记：
10：基底；                11：有源区；
12：隔离结构；            13：位线接触区；
20：导电层；              21：第一导电层；
22：第二导电层；          23：第一初始导电层；
24：中间孔；              25：接触孔；
30：掩膜层；              40：防护层。
具体实施方式
半导体结构的制备过程中，通常是先形成位线结构以及包覆位线结构的隔离侧墙，该位线结构包括层叠设置的位线接触结构和位线，待形成位线结构和隔离侧墙之后，会在相邻的隔离侧墙之间形成电容接触结构，其中，电容接触结构用于连接电容器与基底的有源区，以实现对数据的存储。
如图1和图2所示，在形成位线接触结构时，通过先在基底10内形成位线接触区，然后在位线接触区内形成导电层20，但是，由于位线接触区具有较大的深宽比，导电层20内会形成空隙，在蚀刻导电层20形成位线接触结构时，空隙会被暴露出来，致使位线接触结构的部分区域会发生断开，进而在形成隔离侧墙时，用于形成隔离侧墙的绝缘材质会填充到空隙中，致使隔离侧墙在空隙处发生断裂，不能完全包覆住位线，相应地，在后续形成电容接触结构时，电容接触结构容易与位线结构发生电连接，降低半导体结构的良率。
针对上述的技术问题，在本公开实施例中，通过两次沉积工艺分别形成第一导电层和第二导电层，且第一导电层中掺杂杂质的浓度小于第二导电层中掺杂杂质的浓度，由于掺杂杂质的浓度越低填充能力越高，这样在形成第一导电层时可以避免形成缝隙，其次，第一导电层在位线接触区内围成接触孔，该接触孔具有较小的深宽比，这样在形成第二导电层时，也可以避免在第二导电层形成缝隙，进而避免导电层内形成缝隙，这样在后续形成位线结构以及隔离侧墙时，不会损坏隔离侧墙，进而不会造成电容接触结构与位线发生电连接，提高了半导体结构的良率。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
图3为本公开实施例提供的半导体结构的制备方法的流程图，图4～图10为半导体结构的制备方法的各个阶段的示意图，下面结合图4～图10对半导体结构的制备方法进行详细的介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图3所示，本公开实施例提供的半导体结构的制备方法，包括如下的步骤：
步骤S100：提供基底，基底内具有多个间隔设置的位线接触区。
示例性地，如图4所示，基底10作为动态随机存储器的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
基底10具有多个有源区11以及用于分隔各个有源区11的隔离结构12，其中，多个有源区11可以间隔设置，有源区11用于设置半导体器件，比如，晶体管和电容器。
隔离结构12的制备过程通常为图形化基底10，以在基底10内形成隔离沟槽，然后，利用沉积工艺在隔离沟槽内沉积氧化硅，以形成隔离结构12，隔离结构12用于实现各个有源区11之间的绝缘设置。
基底10内具有多个位线接触区13，多个位线接触区13可以间隔设置在基底10，在形成多个位线接触区13时，可以在基底10上形成具有图案的掩膜层30，然后以掩膜层30作为掩膜版，利用刻蚀气体或者刻蚀液去除部分厚度的基底10，以在基底10内形成位线接触区13。
在形成图案的掩膜层30时，可以通过涂覆的工艺，在掩膜层30上形成一定厚度的光刻胶层，然后通过曝光、刻蚀以及显影的工艺在光刻胶层 上形成掩膜图案，然后，利用刻蚀液或者刻蚀气体，去除未被掩膜图案遮挡的掩膜层30，以在掩膜层30内形成图案。
其中，掩膜层30可以为单一膜层，也可以为复合膜层，比如，掩膜层30可以包括依次层叠设置的氮化硅层、多晶硅层以及氧化硅层，其中，氮化硅层设置在基底10上，本实施例通过使掩膜层30为复合膜层，可以在图形转移过程中，先将图形转移到氧化硅层上，然后依次转移到多晶硅层、氮化硅层以及基底10上，这样可以提高图形转移过程的准确性，确保位线接触区13的图形的准确性。
需要说明的是，在形成位线接触区13之后，可以在位线接触区13内形成防护层40，也可以直接形成导电层20，以下的实施例以在位线接触区13形成防护层40为例进行阐述。
示例性地，如图5所示，在位线接触区13的侧壁上形成防护层40，该防护层40用于对暴露在位线接触区13内的隔离结构12进行保护，防止在后续清洗位线接触区13时对隔离结构12造成损伤。其中，防护层40的材质包括多晶硅。
在本实施例中，防护层40的厚度位于3～6nm，如图5所示，沿图中的X方向，防护层40具有一定的厚度D1，该厚度D1位于3～6nm之间。
若防护层40的厚度小于3nm，则会造成防护层40的厚度过小，致使在后续清洗位线接触区13时，仍然会对隔离结构12造成损伤，若防护层40的厚度大于6nm，则会造成防护层40所围成区域的面积过小，增加该区域的深宽比，致使后续形成的位线接触结构中仍然会存在空隙。
因此，本实施例对防护层40的厚度进行了限定，在实现对隔离结构12进行保护的同时，也能够防止后续形成位线接触结构中具有空隙，进而，避免电容接触结构与位线结构发生电连接，提高了半导体结构的良率。
步骤S200：在每个位线接触区内形成第一导电层，第一导电层在每个位线接触区内围成一个接触孔。
其中，第一导电层21通过沉积工艺形成的，比如，沉积工艺可以包括物理气相沉积工艺、化学气相沉积工艺和原子层沉积工艺中的至少一种。
步骤S300：在每个接触孔内形成第二导电层，第二导电层和第一导电层构成导电层，其中，第二导电层中掺杂杂质的浓度大于第一导电层中掺杂杂质的浓度，其结构图9和图10所示。
第二导电层22也可以通过沉积工艺形成，比如，沉积工艺可以包括物理气相沉积工艺、化学气相沉积工艺和原子层沉积工艺中的至少一种。
在本实施例中，第一导电层21和第二导电层22中的材质均为多晶硅，且掺杂杂质均为磷离子，其中，第二导电层22中掺杂杂质的浓度为第一导电层21中掺杂杂质的浓度的1.5～3倍。
示例性地，第一导电层21中掺杂杂质的浓度为1E20～10E20，即，第一导电层21中掺杂杂质的浓度为1*10 20～10*10 20，第二导电层22中的掺杂杂质的浓度为15E20～30E20，即，第二导电层22中掺杂杂质的浓度为15*10 20～30*10 20。
与相关技术中，导电层20是通过一次沉积工艺形成的技术方案相比，本实施例中导电层20是通过两次沉积工艺形成的，即，第一次沉积工艺用于形成第一导电层21，第二次沉积工艺用于形成第二导电层22，且第一导电层21中掺杂杂质的浓度小于第二导电层22中掺杂杂质的浓度，由于掺杂杂质的浓度越低填充能力越高，这样在形成第一导电层21时可以避免形成缝隙，其次，第一导电层21在位线接触区13内形成接触孔25，该接触孔25具有较小的深宽比，这样在形成第二导电层22时，也可以避免在第二导电层22形成缝隙，进而避免导电层20内形成缝隙，这样在后续形成位线结构以及隔离侧墙时，不会损坏隔离侧墙，进而不会造成电容接触结构与位线发生电连接，提高了半导体结构的良率。
此外，第二导电层22的掺杂杂质的浓度较高，可以提高第二导电层22的导电能力，进而提高导电层20的导电能力，提高了半导体结构的性能。
在一些实施例中，在每个位线接触区13内形成第一导电层21的工艺可以通过如下的方式实施。
示例性地，如图6所示，利用沉积工艺在每个位线接触区13内形成第一初始导电层23，第一初始导电层23延伸至位线接触区13外，并覆盖在掩膜层30上，其中，第一初始导电层23在每个位线接触区13内围成一个中间孔24。
在本实施例中，沉积工艺可以包括物理气相沉积工艺、化学气相沉积工艺和原子层沉积工艺中的至少一种。
沿第一方向，第一初始导电层23的厚度位于5～18nm之间，第一初 始导电层23的厚度如图6中的D2，若是，第一初始导电层23的厚度小于5nm，不利于后续形成第一导电层21，若是第一初始导电层23大于18nm，使得第一初始导电层23的厚度过大，难以形成中间孔24，增加了后续形成去除第一初始导电层23的难度，因此，本实施例将第一初始导电层23的厚度限定在5～18nm之间，这样既可以便于第一导电层21的形成，也可以降低第一导电层21的制备难度。
第一方向可以为图6中的X方向。
其次，位于位线接触区13的底壁上的第一初始导电层23的厚度位于10～18nm之间，位于位线接触区13的底壁上的第一初始导电层23的厚度为图6中标示的D3。
若是，位于位线接触区13的底壁上的第一初始导电层23的厚度小于10nm，会致使后续形成的第一导电层21沿垂直于基底10的方向的厚度过小，进而造成接触孔25的深度仍然很大，这样会造成后续形成的第二导电层22内形成空隙。
若是，位于位线接触区13的底壁上的第一初始导电层23的厚度大于18nm，则会降低后续形成的接触孔25的深度，致使后续形成的第二导电层22的导电能力较低，进而降低了导电层20的导电能力。
因此，本实施例将位于位线接触区13的底壁上的第一初始导电层23的厚度限定在10～18nm之间，这样既可以防止第二导电层22内形成空隙，也能提高导电层20的导电能力，提高了半导体结构的性能。
如图7所示，待形成第一初始导电层23之后，向中间孔24内通入刻蚀气体，该刻蚀气体能够刻蚀部分第一初始导电层23，被保留下来的第一初始导电层23构成第一导电层21，且第一导电层21在位线接触区内围成接触孔25。
其中，刻蚀气体包括氯气，刻蚀温度位于250℃～320℃，若是，刻蚀温度低于250℃，则会造成刻蚀速率降低，增加刻蚀时间，进而增加生产成本，若是，刻蚀温度高于320℃，容易对第一初始导电层23造成过刻蚀，降低第一导电层21的厚度，进而致使接触孔25仍然具有高深宽比，因此，本实施例对刻蚀温度进行了限定，既要降低生产成本，也要降低接触孔25的深宽比，防止位线接触结构中形成空隙。
在本实施例中，接触孔25的形状可以有多种选择，比如，以垂直于基底 10的方向的截面为纵截面，接触孔25的纵截面形状为梯形，且该梯形为上大下小的结构，其结构如图7所示；又比如，以垂直于基底10的方向的截面为纵截面，接触孔25的纵截面形状为V型，其结构如图8所示，本实施例通过对接触孔25的形状进行限定，可以方便后续第二导电层22的沉积，防止第二导电层22中形成空隙。
在一些实施例中，如图7和图8所示，接触孔25的侧壁与垂直于基底10的方向之间的夹角位于10°～20°，接触孔25的侧壁与Y方向的夹角为图7和图8中α。
若是，接触孔25的侧壁与垂直于基底10的方向之间的夹角小于10°，则会使接触孔25的顶部开口过小，则会增加后续沉积第二导电层22的难度，仍然会致使第二导电层22中形成空隙。
若是，接触孔25的侧壁与垂直于基底10的方向之间的夹角大于20°，则会造成接触孔25的深度过小，造成后续形成的第二导电层22的厚度过小，降低第二导电层22的导电能力，进而降低导电层20的导电能力和降低半导体结构的性能。
因此，本实施例对接触孔25的侧壁与垂直于基底10的方向之间的夹角进行了限定，既可以防止第二导电层22中形成空隙，也可以增加导电层20的导电能力。
在一些实施例中，沿第一方向，第一导电层21的厚度位于0～6nm之间，沿图7中的X方向，第一导电层21的厚度为D4，第一导电层21的厚度D4位于0～6nm之间，其中，第一导电层21的厚度可以为等值，即，沿垂直于基底10的方向，第一导电层21的厚度可以处处相等；沿垂直于基底10的方向，第一导电层21的厚度可以呈渐变式的，例如，如图7所示，位于接触孔25的顶部的第一导电层21的厚度可以为0～3nm，位于接触孔25的底部的第一导电层21的厚度可以为3～6nm。
本实施例通过对第一导电层21的厚度进行限定，既可以防止第一导电层21内形成空隙，也可以保证导电层20的导电能力，提高半导体结构的性能。
在一些实施例中，继续参考图7，位于位线接触区13的底壁上的第一导电层21的厚度位于5～8nm之间。
沿垂直于基底10的方向，第一导电层21的厚度D5位于5～8nm之间， 若是，第一导电层21的厚度D5小于5nm，仍然会造成接触孔25具有深宽比，造成在形成第二导电层22时，第二导电层22内易形成空隙，进而致使在后续形成的电容接触结构与位线结构发生电连接，降低半导体结构的良率。
若是，第一导电层21的厚度D5大于8nm，则会造成接触孔25的深度过小，则会造成形成第二导电层22的厚度过小，降低了第二导电层22的导电能力，进而会降低导电层20的导电能力，和降低了半导体结构的性能。
因此，本实施例对沿垂直于基底10的方向上，第一导电层21的厚度进行限定，这样既可以防止后续形成的电容接触结构与位线结构发生电连接，提高了半导体结构的良率，也可以保证导电层20的导电能力，提高了半导体结构的性能。
本公开实施例的第二方面提供的半导体结构，通过上述实施例中的半导体结构的制备方法制得的，因此，本实施例中半导体结构中的位线接触结构包括层叠设置的第一导电层21和第二导电层22，且第一导电层21和第二导电层22为致密结构，并不存在空隙，这样在后续形成位线以及隔离侧墙时，不会损坏隔离侧墙，进而不会造成电容接触结构与位线结构发生电连接，提高了半导体结构的良率。
此外，第二导电层22的掺杂杂质的浓度较高，这样保证第二导电层22内不会出现空隙的同时，也能提高第二导电层22的导电能力，进而提高位线接触结构的导电能力，提高半导体结构的性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方 式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括如下步骤：
    提供基底，所述基底内具有多个间隔设置的位线接触区；
    在每个所述位线接触区内形成第一导电层，所述第一导电层在每个所述位线接触区内围成一个接触孔；
    在每个所述接触孔内形成第二导电层，所述第二导电层和所述第一导电层构成导电层，其中，所述第二导电层中掺杂杂质的浓度大于所述第一导电层中掺杂杂质的浓度。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述第二导电层中掺杂杂质的浓度为所述第一导电层中掺杂杂质的浓度的1.5～3倍。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，在所述位线接触区内形成第一导电层的步骤中包括：
    在每个所述位线接触区形成第一初始导电层，所述第一初始导电层在每个所述位线接触区内围成一个中间孔；
    向所述中间孔内通入刻蚀气体，去除部分所述第一初始导电层，被保留下来的第一初始导电层构成第一导电层，且第一导电层在所述位线接触区内围成接触孔。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，以垂直于所述基底的方向的截面为纵截面，所述接触孔的纵截面形状为上大下小的梯形。
  5. 根据权利要求3所述的半导体结构的制备方法，其中，以垂直于所述基底的方向的截面为纵截面，所述接触孔的纵截面形状为V型。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，所述接触孔的侧壁与垂直于所述基底的方向之间的夹角位于10°～20°。
  7. 根据权利要求1～5任一项所述的半导体结构的制备方法，其中，沿第一方向，所述第一导电层的厚度位于0～6nm之间。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，位于所述位线接触区的底壁上的第一导电层的厚度位于5～8nm之间。
  9. 根据权利要求3～5任一项所述的半导体结构的制备方法，其中，沿第一方向，所述第一初始导电层的厚度位于5～18nm之间。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，位于所述位线接触区的底壁上的第一初始导电层的厚度位于10～18nm之间。
  11. 根据权利要求1～5任一项所述的半导体结构的制备方法，其中，所述第一导电层和所述第二导电层的材质均包括多晶硅，且掺杂杂质均为磷离子。
  12. 根据权利要求1～5任一项所述的半导体结构的制备方法，其中，在所述位线接触区内形成第一导电层的步骤之前，所述制备方法还包括：
    在所述位线接触区的侧壁上形成防护层。
  13. 根据权利要求12所述的半导体结构的制备方法，其中，所述防护层的厚度位于3～6nm，且所述防护层的材质包括多晶硅。
  14. 根据权利要求3所述的半导体结构的制备方法，其中，所述刻蚀气体包括氯气，且刻蚀温度位于250℃～320℃。
  15. 一种半导体结构，所述半导体结构通过如权利要求1～14任一项所述半导体结构的制备方法制得。
PCT/CN2022/071263 2021-10-13 2022-01-11 半导体结构及其制备方法 WO2023060796A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22782646.8A EP4207264A4 (en) 2021-10-13 2022-01-11 SEMICONDUCTOR STRUCTURE AND PRODUCTION PROCESS THEREOF
US17/805,738 US20230114038A1 (en) 2021-10-13 2022-06-07 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111192543.4A CN115988869A (zh) 2021-10-13 2021-10-13 半导体结构及其制备方法
CN202111192543.4 2021-10-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/805,738 Continuation US20230114038A1 (en) 2021-10-13 2022-06-07 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2023060796A1 true WO2023060796A1 (zh) 2023-04-20

Family

ID=84767122

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/071263 WO2023060796A1 (zh) 2021-10-13 2022-01-11 半导体结构及其制备方法

Country Status (2)

Country Link
CN (1) CN115988869A (zh)
WO (1) WO2023060796A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176936A (ja) * 1997-11-18 1999-07-02 Samsung Electron Co Ltd 微細な線幅と高縦横比を有する領域に絶縁膜を埋込む方法
CN103855002A (zh) * 2012-11-28 2014-06-11 上海华虹宏力半导体制造有限公司 一种超级结深沟槽填充工艺方法
CN108962894A (zh) * 2018-06-22 2018-12-07 长鑫存储技术有限公司 一种填充沟槽形成触点的方法
CN113314469A (zh) * 2021-05-27 2021-08-27 长鑫存储技术有限公司 位线接触结构及其形成方法、半导体结构和半导体器件
CN113658918A (zh) * 2021-08-17 2021-11-16 福建省晋华集成电路有限公司 半导体器件的制备方法及半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176936A (ja) * 1997-11-18 1999-07-02 Samsung Electron Co Ltd 微細な線幅と高縦横比を有する領域に絶縁膜を埋込む方法
CN103855002A (zh) * 2012-11-28 2014-06-11 上海华虹宏力半导体制造有限公司 一种超级结深沟槽填充工艺方法
CN108962894A (zh) * 2018-06-22 2018-12-07 长鑫存储技术有限公司 一种填充沟槽形成触点的方法
CN113314469A (zh) * 2021-05-27 2021-08-27 长鑫存储技术有限公司 位线接触结构及其形成方法、半导体结构和半导体器件
CN113658918A (zh) * 2021-08-17 2021-11-16 福建省晋华集成电路有限公司 半导体器件的制备方法及半导体器件

Also Published As

Publication number Publication date
CN115988869A (zh) 2023-04-18

Similar Documents

Publication Publication Date Title
US5164337A (en) Method of fabricating a semiconductor device having a capacitor in a stacked memory cell
JP2531473B2 (ja) 半導体メモリ装置およびその製造方法
JPH08330586A (ja) バーチカルトランジスタ及びその製造方法
US20050272251A1 (en) Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin
TWI455250B (zh) 動態隨機存取記憶體低寄生電容接觸層及閘極結構及其製程
JPS6156446A (ja) 半導体装置およびその製造方法
US20120161215A1 (en) Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same
WO2024037135A1 (zh) 半导体结构及制备方法
WO2023279719A1 (zh) 半导体结构的制备方法及半导体结构
JP2682509B2 (ja) 半導体装置の製造方法
WO2022148067A1 (zh) 半导体结构及其制作方法
KR101414076B1 (ko) 반도체 소자 및 이의 제조 방법
WO2023060796A1 (zh) 半导体结构及其制备方法
TW201301447A (zh) 半導體元件的單元接觸和位元線的製作方法
EP4207264A1 (en) Semiconductor structure and manufacturing method therefor
CN108281423B (zh) 制作半导体元件的方法
WO2023206641A1 (zh) 半导体结构的制作方法及其结构
JPH01265556A (ja) 半導体記憶装置及びその製造方法
US20220285361A1 (en) Semiconductor structure and manufacturing method thereof
US20240015946A1 (en) Integrated circuit device and method of manufacturing the same
WO2023130698A1 (zh) 半导体结构及其制备方法
US20240064969A1 (en) Semiconductor structure and method for fabricating same
WO2023272875A1 (zh) 半导体结构及其制作方法
WO2022142293A1 (zh) 半导体结构及半导体结构的制作方法
TW202329398A (zh) 半導體結構及其製作方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2022782646

Country of ref document: EP

Effective date: 20221011