WO2023272875A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023272875A1
WO2023272875A1 PCT/CN2021/110726 CN2021110726W WO2023272875A1 WO 2023272875 A1 WO2023272875 A1 WO 2023272875A1 CN 2021110726 W CN2021110726 W CN 2021110726W WO 2023272875 A1 WO2023272875 A1 WO 2023272875A1
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Prior art keywords
substrate
fin
semiconductor structure
bottom wall
trench
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PCT/CN2021/110726
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English (en)
French (fr)
Inventor
宛伟
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长鑫存储技术有限公司
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Publication of WO2023272875A1 publication Critical patent/WO2023272875A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and method of making the same.
  • Dynamic Random Access Memory (English: Dynamic Random Access Memory, referred to as: DRAM) is a semiconductor memory widely used in mobile phones, computers, automobiles and other electronic products. With the development of science and technology, the feature size of integrated circuit devices is continuously reduced, and the size of key positions of DRAM is also getting smaller and smaller, which puts forward higher requirements for the electrical performance of DRAM.
  • the disclosure provides a semiconductor structure and a manufacturing method thereof.
  • a first aspect of the present disclosure provides a semiconductor structure comprising:
  • the fin located on the bottom wall of the channel groove, the fin protrudes toward the inner side of the channel groove, and there is a gap between the fin and the side wall of the channel groove;
  • the side wall of the channel groove includes a connecting surface and a stepped surface, and the stepped surface includes at least one stepped unit.
  • a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure comprising:
  • a fin is formed on the bottom wall of the accommodating groove, and the fin protrudes toward the inner side of the accommodating groove.
  • FIG. 1 is a schematic diagram of a semiconductor structure shown according to an exemplary comparative example
  • FIG. 2 is a schematic diagram of a semiconductor structure shown according to an exemplary comparative example
  • Fig. 3 is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment
  • Fig. 4 is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment
  • Fig. 5 is a schematic diagram of a semiconductor structure according to an exemplary embodiment
  • Fig. 6 is a schematic diagram of a semiconductor structure according to an exemplary embodiment
  • Fig. 7 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 8 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 9 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 10 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 11 is a schematic diagram of an initial structure involved in a manufacturing method of a semiconductor structure according to an exemplary embodiment
  • Fig. 12 is a schematic diagram of forming an initial channel involved in a method of manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 13 is a schematic diagram of forming a first oxide layer involved in a method of manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 14 is a schematic diagram of a substrate exposed by etching a first oxide layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 15 is a schematic diagram of a channel trench during the formation process involved in a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 16 is a schematic diagram of forming a second oxide layer involved in a method of manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 17 is a schematic diagram of etching a second oxide layer to form accommodating grooves involved in a manufacturing method of a semiconductor structure according to an exemplary embodiment
  • Fig. 18 is a schematic diagram of forming an initial fin involved in a method of manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 19 is a schematic diagram of removing initial fins and forming fins involved in a manufacturing method of a semiconductor structure according to an exemplary embodiment
  • Fig. 20 is a schematic diagram of removing the first oxide layer and the second oxide layer to form trenches involved in a manufacturing method of a semiconductor structure according to an exemplary embodiment
  • Fig. 21 is a schematic diagram of forming a third oxide layer involved in a method of manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 22 is a schematic diagram of forming a barrier layer involved in a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 23 is a schematic diagram of gate formation involved in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • barrier layer 500, second oxide layer
  • the current buried gate structure includes a substrate 10 ′, a trench 20 ′ located in the substrate 10 ′, and a buried gate disposed in the trench 20 ′.
  • Pole 100' As shown in FIG. 1, the channel groove 20' includes a bottom wall 21' and side walls 22' on both sides, and the length of the channel groove 20' is equal to the length of the bottom wall 21' and the length of the side walls 22' on both sides. sum.
  • the threshold voltage of the transistor will decrease. This is because when the length of the channel groove 20' After the reduction to a certain extent, the proportion of the depletion region of the source and drain in the entire trench 20' increases, and the surface of the substrate 10' below the buried gate 100' forms an inversion layer. The amount of charge required decreases, which in turn leads to a decrease in the threshold voltage and a short channel effect.
  • the present disclosure provides a semiconductor structure in which fins are provided in the channel groove and a step surface is added on the side wall of the channel groove to increase the length of the channel groove and solve the short channel effect of the semiconductor structure , improving the stability and electrical performance of semiconductor devices.
  • An exemplary embodiment of the present disclosure provides a semiconductor structure. As shown in FIG. The fin portion 30 of the bottom wall 21 protrudes toward the inner side of the trench 20 , and there is a gap 31 between the fin portion 30 and the sidewall 22 of the trench 20 .
  • the surface area of the channel groove 20 is increased by arranging the raised fin portion 30 in the channel groove 20, which can solve the short channel effect, thereby solving the problem of the reduction of the threshold voltage of the transistor caused by the short channel effect. And other problems, improve the stability and electrical performance of semiconductor devices.
  • the sidewall 22 of the trench 20 of the semiconductor structure in this embodiment includes a connection surface 222 and a stepped surface 221
  • the stepped surface 221 includes at least one stepped unit 220 , which further increases the surface area of the trench 20 .
  • the semiconductor structure of this embodiment improves the structure of the trench and increases the length of the trench to meet the needs of the miniaturization development of integrated circuit devices. On the premise of reducing the size of the trench, it can still ensure the stability of the trench. Length, to avoid problems such as short channel effect and the decrease of threshold voltage caused by it, and still ensure the stability and electrical performance of semiconductor devices.
  • An exemplary embodiment of the present disclosure provides a semiconductor structure. As shown in FIG.
  • the fin portion 30 of the bottom wall 21 protrudes toward the inner side of the trench 20 , and there is a gap between the fin portion 30 and the sidewall 22 of the trench 20 .
  • the sidewall 22 of the trench 20 includes a connecting surface 222 and a stepped surface 221 , and the stepped surface 221 includes at least one stepped unit 220 .
  • the fin portion 30 includes one or more fin units 300.
  • a gap is formed between adjacent fin units 300, and the fin adjacent to the side wall 22 of the channel groove 20
  • a gap is formed between the cell 300 and the sidewall 22 of the trench 20 .
  • two fin units 300 are set in one trench 20, a gap is formed between the two fin units 300, and each fin unit 300 is formed between the sidewall 22 of the adjacent trench 20.
  • the gap effectively increases the length of the trench 20 .
  • the fin portion 30 may include one fin unit 300 , three fin units 300 or five fin units 300 , and so on.
  • the shape of the fin unit 300 in the longitudinal section is square.
  • the fin unit 300 may be a cylinder, a cuboid, a cube or any other three-dimensional structure with a square longitudinal section.
  • the size of the fin unit 300 is set according to the size of the trench 20, for example, the height of the fin unit 300 is 10-30 nm, and the width of the fin unit 300 is 5-10 nm.
  • the internal space of the trench is fully utilized to arrange a plurality of fin units, further increasing the length of the trench, and avoiding the problem of short channel effect.
  • the number of fin units can be set according to the size of the channel groove, so as to prevent the number of fin units from increasing and the distance between adjacent fin units from being too close.
  • An exemplary embodiment of the present disclosure provides a semiconductor structure. As shown in FIG.
  • the fin portion 30 protrudes toward the inner side of the channel groove 20 , and there is a gap between the fin portion 30 and the sidewall 22 of the channel groove 20 .
  • the fin portion 30 may include one or more fin units 300 , and when the fin portion 30 includes multiple fin units 300 , there is a gap between two adjacent fin units 300 .
  • the sidewall 22 of the trench 20 includes a connecting surface 222 and a stepped surface 221
  • the stepped surface 221 includes at least one stepped unit 220 .
  • the connecting surface 222 is connected to the stepped surface 221
  • the connecting surface 222 is connected to the top surface of the substrate 10
  • the stepped surface 221 is connected to the bottom wall 21 of the trench 20 .
  • a plurality of grooves with different widths and different depths are formed along a direction perpendicular to the substrate 10 .
  • the size of the step unit 220 is set according to the size of the trench 20 , for example, the length of the connection surface 222 may be 20-60 nm, and the width of the first surface 2201 of the step unit 220 is 2-8 nm.
  • the length of the second surface 2202 of the bottommost step unit 220 is greater than the height of the fin 30 .
  • the projection of the bottom wall 21 of the trench 20 on the substrate 10 is located within the projection of the notch of the trench 20 on the substrate. That is, based on the direction shown in FIG. 3 , the width of the grooves located in the upper layer is larger than the width of the grooves located in the lower layer.
  • a plurality of step units 220 are connected in sequence to form a plurality of step surfaces on the sidewall of the trench 20 , thereby increasing the length of the trench 20 .
  • the semiconductor structure includes: a substrate 10 and a trench 20 located in the substrate 10 , and The fin portion 30 protrudes toward the inner side of the channel groove 20 , and there is a gap between the fin portion 30 and the sidewall 22 of the channel groove 20 .
  • the fin portion 30 includes one or more fin units 300 ; the fin portion 30 includes a plurality of fin units 300 , and there is a gap between two adjacent fin units 300 .
  • the side wall 22 of the trench 20 includes a connecting surface 222 and a stepped surface 221 , and the stepped surface 221 includes at least one stepped unit 220 .
  • the connecting surface 222 is connected to the stepped surface 221
  • the connecting surface 222 is connected to the top surface 11 of the substrate 10
  • the stepped surface 221 is connected to the bottom wall of the trench.
  • the step surface 221 includes a plurality of end-to-end connected step units 220
  • the step unit 220 includes a connected first surface 2201 and a second surface 2202, the first surface 2201 is parallel to the substrate 10, and the second surface 2202 Vertical to the substrate 10;
  • the second surface 2202 of the step unit 220 is connected to the bottom wall 21, or connected to the first surface 2201 of the adjacent step unit 220;
  • the first surface 2201 of the step unit 220 is connected to the connecting surface 222 connected, or connected to the second surface 2202 of the adjacent step unit 220 .
  • the projection of the first surface 2201 of the step unit 220 on the substrate 10 is outside the projection of the bottom wall of the trench 20 on the substrate 10 .
  • the sum of the area of the projection of one or more first surfaces 2201 on the substrate 11 and the projection of the bottom wall 21 on the substrate 11 is equal to the projected area of the notch of the trench 20 on the substrate 10 .
  • the number of step units 200 is set according to the size of the channel groove 20 , two step units 220 , three step units 220 , four step units 220 , five step units 220 etc. can be set in the channel groove 20 .
  • two stepped units 220 are formed on the sidewall 22 of the trench 20.
  • the two stepped units 220 of the trench 20 are defined as two Grooves of varying widths and depths.
  • the internal space of the trenches is fully utilized to arrange a plurality of step units, further increasing the length of the trenches, and avoiding the problem of the short channel effect.
  • An exemplary embodiment of the present disclosure provides a semiconductor structure. As shown in FIG.
  • the fin portion 30 of the bottom wall 21 protrudes toward the inner side of the trench 20 , and there is a gap between the fin portion 30 and the sidewall 22 of the trench 20 .
  • the sidewall 22 of the trench 20 includes a connecting surface 222 and a stepped surface 221 , and the stepped surface 221 includes at least one stepped unit 220 .
  • the semiconductor structure in this embodiment further includes: a third oxide layer 40 covering the bottom wall 21 and side wall 22 of the trench 20 and the outer surface of the fin 30 , covering the third oxide layer 40 The barrier layer 50 of the bottom wall and part of the sidewall, and the gate 60 covering the bottom wall and sidewall of the barrier layer 50 .
  • the length of the trench 20 is increased, and the contact area between the gate 60 and the substrate 10 is increased, which can avoid the problem of the short channel effect.
  • a semiconductor structure according to an embodiment of the present disclosure may be used for a transistor, and a semiconductor structure according to an embodiment of the present disclosure may be included in a memory cell and a memory cell array.
  • a memory array may be included in a memory device.
  • the memory device may be used in DRAM (Dynamic Random Access Memory). However, it can also be applied to SRAM (Static Random Access Memory), flash memory, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PRAM (Phase Change Random Access Memory), and the like.
  • FIG. 7 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 11 - FIG. 23 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure, and the manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 11-23 .
  • the manufacturing method of the semiconductor structure in this embodiment includes:
  • the substrate 10 may be a semiconductor substrate including a silicon-containing substance.
  • the semiconductor substrate may include a silicon substrate, a silicon germanium substrate or an SOI (silicon on insulator, silicon on insulator) substrate.
  • S120 Form an accommodating groove in the substrate.
  • the accommodating groove 200 is an intermediate structure formed during the intermediate process of forming the channel groove 20 , the accommodating groove 200 is surrounded by the first oxide layer 400 , the second oxide layer 500 and the substrate 10 , the second The dioxide layer 500 and the first oxide layer 400 surround the sidewalls of the accommodating groove 200 in sequence.
  • the size of the second oxide layer 500 is different from that of the first oxide layer 400 .
  • the fin 30 is formed at the bottom of the accommodating groove 200 , the bottom wall of the fin 30 is connected to the substrate 10 , and the fin 30 protrudes into the accommodating groove 200 by a predetermined length.
  • the predetermined length can be set according to the requirement in the real-time process.
  • the material of the fin portion 30 includes a substance containing silicon, for example, the material of the fin portion 30 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or silicon germanide. In this embodiment, the material of the fin portion 30 is the same as that of the substrate 10 .
  • fins are formed in the channel groove, which increases the length of the channel groove, and solves the problem of the short channel effect of the semiconductor structure, thereby avoiding the threshold voltage of the transistor caused by the short channel effect of the semiconductor structure Reduce and other problems, further improve the stability and electrical performance of semiconductor devices.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 8 , which shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • the manufacturing method of the semiconductor structure in this embodiment includes:
  • S220 Form an accommodating groove in the substrate.
  • step S210 and step S230 in this embodiment are implemented in the same manner as step S110 and step S130 in the foregoing embodiment, and details are not repeated here.
  • forming the etch stop layer 80 on the substrate 10 includes, as shown in FIG. 12, referring to FIG. Form initial channel groove 210; As shown in Figure 14, referring to Figure 13, form first oxide layer 400, first oxide layer 400 covers the bottom wall and sidewall of initial channel groove 210 at least; The first oxide layer 400 of the bottom wall exposes the substrate 10; the exposed substrate 10 is etched, as shown in FIG. The second oxide layer 500 and the second oxide layer 500 cover at least the bottom wall and the sidewall of the process trench 220 ; the second oxide layer 500 covering the bottom wall of the process trench 220 is removed to form the accommodating trench 200 .
  • a photoresist mask 90 is formed on the etch stop layer 80, and a pattern 901 of a predetermined shape is defined on the photoresist mask 90.
  • the barrier layer 80 and the substrate 10 are etched to form an initial trench 210 .
  • the pattern 901 defined on the photoresist mask 90 can be directly defined by illumination, and the pattern 901 can also be defined first by illumination and then realized by pitch double. The method for defining the pattern 901 is based on the width of the trench Decide.
  • the photoresist mask 90 includes a photoresist material, for example, the photoresist mask 90 includes photoresist/SION/Carbon/SOC/SiO2/DARK, and the thickness of the photoresist mask 90 is 20-250nm.
  • an atomic layer deposition process can be used to deposit a first oxide layer 400.
  • the first oxide layer 400 covers the sidewalls and bottom of the initial trench 210 and the top surface of the substrate 10, Dry or wet etching removes the first oxide layer 400 on the top surface of the substrate 10 , and removes the first oxide layer 400 on the bottom wall of the initial trench 210 to expose the substrate 10 .
  • the second oxide layer 500 can be deposited by an atomic layer deposition process (Atomic Layer Deposition, ALD), and the second oxide layer 500 covers the sidewall, the bottom and the substrate 10 of the process trench 220
  • ALD atomic layer deposition
  • the top surface of the substrate 10 is removed by dry or wet etching to remove the second oxide layer 500 on the top surface of the substrate 10, and the second oxide layer 500 on the bottom wall of the channel groove 220 is removed to expose the substrate 10, as shown in Figure 17 As shown, an accommodating groove 200 is formed.
  • the accommodating groove 200 of the semiconductor structure is formed in the process channel groove 220, and along the direction perpendicular to the substrate 10, the process channel groove 220 is such that the size of the upper layer groove is larger than the size of the lower layer groove structure, increase the length of the channel groove, and avoid the short channel effect of the semiconductor structure.
  • FIG. 9 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • the manufacturing method of the semiconductor structure in this embodiment includes:
  • S310 provides a substrate.
  • S330 Form a fin on the bottom wall of the accommodating groove, and the fin protrudes toward the inner side of the accommodating groove.
  • step S310 and step S320 in this embodiment are implemented in the same manner as step S210 and step S220 in the foregoing embodiment, and details are not repeated here.
  • forming a fin 30 on the bottom wall of the accommodating tank includes: forming an initial fin 3 on the bottom wall of the accommodating tank 200 , and the initial fin 3 at least covers the accommodating tank 200 ; as shown in FIG. 19 , etch the initial fin portion 3 to form the fin portion 30 .
  • forming the initial fin portion 3 on the bottom wall of the accommodating groove 200 includes: depositing a polysilicon layer, the polysilicon layer covering the accommodating groove 200 and the top wall of the substrate 10 , etching back by dry or wet etching The initial fin 3 reaches a predetermined height, and the fin 30 is obtained.
  • the fin portion 30 may include one or more fin units 300 ; the accommodating slots 200 correspond to the fin units one by one. That is to say, in step S420 of this embodiment, a plurality of accommodating grooves 220 are formed in the process channel groove 220, and a fin unit 300 is correspondingly formed in each accommodating groove 220, as shown in FIG. 4 , a plurality of The fin units 300 collectively form the fin 30 present in the final trench 20 .
  • a plurality of fin units are arranged in the final trench of the semiconductor structure to make full use of the internal space of the trench and effectively increase the length of the trench.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 10 , which shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • the manufacturing method of the semiconductor structure in this embodiment includes:
  • S430 Form a fin on the bottom wall of the accommodating groove, and the fin protrudes toward the inner side of the accommodating groove.
  • S470 forming a gate, and the gate covers the bottom wall and the sidewall of the barrier layer.
  • step S410 to step S430 in this embodiment are implemented in the same manner as step S310 to step S330 in the above embodiment, and details are not repeated here.
  • the first oxide layer 400 and the second oxide layer 500 are removed to form trenches 20 .
  • a third oxide layer 40 is deposited in the trench 20, and the third oxide layer 40 covers the bottom wall 21 and the sidewall 22 of the trench 20 and the outer surface of the fin 30; as shown in FIG. 22, a barrier layer 50 is deposited, and the barrier layer 50 covers the bottom wall and part of the side walls of the third oxide layer 40. As shown in FIG. 23, a gate 60 is deposited, and the gate 60 covers the bottom wall and side walls of the barrier layer 50. .
  • the semiconductor structure produced in this embodiment can be used in transistors, and can avoid problems such as the decrease of threshold voltage caused by the short channel effect.
  • fins are arranged in the channel groove and a step surface is added on the side wall of the channel groove, which increases the length of the channel groove and solves the short channel of the semiconductor structure. effect, improving the stability and electrical performance of semiconductor devices.

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Abstract

本公开提供一种半导体结构及其制作方法，半导体结构包括：衬底；沟道槽，位于所述衬底内；鳍部，位于所述沟道槽的底壁，所述鳍部向所述沟道槽的内侧凸出，所述鳍部与所述沟道槽的侧壁之间具有间隙；所述沟道槽的侧壁包括连接面和台阶面，所述台阶面包括至少一个台阶单元。

Description

半导体结构及其制作方法
本公开基于申请号为202110753754.4，申请日为2021年07月02日，申请名称为“一种半导体结构及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法。
背景技术
动态随机存储器(英文：Dynamic Random Access Memory，简称：DRAM)是一种广泛应用于手机、电脑、汽车等电子产品中的半导体存储器。随着科技的发展，集成电路器件特征尺寸不断缩小，DRAM的关键位置的尺寸也越来越小，对DRAM的电性能提出了更高要求。
目前，DRAM的有源区的栅极大多为埋入式栅极，埋入式栅极的尺寸小，栅极尺寸越小越容易出现短沟道效应。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构及其制作方法。
本公开的第一方面提供一种半导体结构，所述半导体结构包括：
衬底；
沟道槽，位于所述衬底内；
鳍部，位于所述沟道槽的底壁，所述鳍部向所述沟道槽的内侧凸出，所述鳍部与所述沟道槽的侧壁之间具有间隙；
所述沟道槽的侧壁包括连接面和台阶面，所述台阶面包括至少一个台阶单元。
本公开的第二方面提供一种提供了一种半导体结构的制作方法，所述半导体结构的制作方法包括：
提供衬底；
在所述衬底内形成容置槽；
在所述容置槽的底壁形成鳍部，所述鳍部向所述容置槽的内侧凸出。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性对比例示出的一种半导体结构的示意图；
图2是根据一示例性对比例示出的一种半导体结构的示意图；
图3是根据一示例性实施例示出的一种半导体结构的示意图；
图4是根据一示例性实施例示出的一种半导体结构的示意图；
图5是根据一示例性实施例示出的一种半导体结构的示意图；
图6是根据一示例性实施例示出的一种半导体结构的示意图；
图7是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图8是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图9是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图10是根据一示例性实施例示出的一种半导体结构的制作方法的流程图；
图11是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的初始结构的示意图；
图12是根据一示例性实施例示出的一种半导体结构的制作方法涉及 到的形成初始沟道槽的示意图；
图13是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成第一氧化层示意图；
图14是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的刻蚀第一氧化物层显露出初始沟道槽的衬底的示意图；
图15是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成过程沟道槽的示意图；
图16是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成第二氧化层的示意图；
图17是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的刻蚀第二氧化层形成容置槽的示意图；
图18是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成初始鳍部的示意图；
图19是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的去除初始鳍部形成鳍部的示意图；
图20是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的去除第一氧化层和第二氧化层形成沟道槽的示意图；
图21是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成第三氧化层的示意图；
图22是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成阻挡层的示意图；
图23是根据一示例性实施例示出的一种半导体结构的制作方法涉及到的形成栅极的示意图。
附图标记：
10、衬底；
20、沟道槽；200、容置槽；210、初始沟道槽；220、过程沟道槽；21、沟道槽的底壁；22、沟道槽的侧壁；221、台阶面；220、台阶单元；2201、第一面；2202、第二面；222、连接面；
30、鳍部；31、间隙；300、鳍单元；
40、第三氧化层；
50、阻挡层；500、第二氧化层；
60、栅极；
400、第一氧化层；
80、刻蚀阻挡层；
90、光刻胶掩膜；901、图形；
10’、衬底；20’、沟道槽；100’、埋入式栅极；21’、底壁；22’、侧壁。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
如图2所示，参照图1，目前埋入式栅极结构包括衬底10’和位于衬底10’内的沟道槽20’，以及设置在沟道槽20’中的埋入式栅极100’。图1所示，沟道槽20’包括底壁21’以及两侧的侧壁22’，沟道槽20’的长度即为底壁21’的长度与两侧的侧壁22’的长度的总和。
随着集成电路器件微缩化发展，埋入式栅极100’以及用于设置埋入式栅极100’的沟道槽20’越小，沟道槽20’的长度越小。当金属氧化物半导体场效应管的沟道槽20’的长度降低到十几纳米，甚至几纳米的量级时，晶体管会出现阈值电压减小的问题，这是因为当沟道槽20’长度减小到一定程度后，源极和漏极的耗尽区在整个沟道槽20’中所占的比重增大，埋入式栅极100’下方的衬底10’表面形成反型层所需的电荷量减小，进而导致阈值电压减小，出现短沟道效应。
鉴于此，本公开的提供了一种半导体结构，在沟道槽中设置鳍部并且在沟道槽的侧壁增设台阶面，增加了沟道槽的长度，解决了半导体结构的短沟道效应，提高了半导体器件的稳定性以及电学性能。
本公开示例性的实施例中提供一种半导体结构，如图3所示，本实施例中的半导体结构包括衬底10和位于衬底10内的沟道槽20，以及位于沟道槽20的底壁21的鳍部30，鳍部30向沟道槽20的内侧凸出，鳍部30与沟道槽20的侧壁22之间具有间隙31。
本实施例的半导体结构，通过在沟道槽20中设置凸起的鳍部30，增加了沟道槽20的表面积，可以解决短沟道效应，从而解决由于短沟道效应引起晶体管阈值电压降低等问题，提高了半导体器件的稳定性以及电学性能。
另外，本实施例中的半导体结构的沟道槽20的侧壁22包括连接面222和台阶面221，台阶面221包括至少一个台阶单元220，进一步增加了沟道槽20的表面积。
本实施例的半导体结构通过改进了沟道槽的结构，增加沟道槽的长度，满足集成电路器件微缩化发展的需求，在沟道槽尺寸缩小的前提下，但仍能保证沟道槽的长度，避免出现沟短沟道效应及其引起的阈值电压降低等问题，仍能保证半导体器件的稳定性以及电学性能。
本公开示例性的实施例中提供一种半导体结构，如图4所示，本实施例中的半导体结构包括衬底10和位于衬底10内的沟道槽20，以及位于沟道槽20的底壁21的鳍部30，鳍部30向沟道槽20的内侧凸出，鳍部30与沟道槽20的侧壁22之间具有间隙。沟道槽20的侧壁22包括连接面222和台阶面221，台阶面221包括至少一个台阶单元220。
鳍部30包括一个或多个鳍单元300，在沟道槽20中凸出设置一个以上鳍单元300时，相邻的鳍单元300之间形成间隙，临近沟道槽20的侧壁22的鳍单元300和沟道槽20的侧壁22之间形成间隙。本实施例中，一个沟道槽20中设置两个鳍单元300，两个鳍单元300之间形成间隙，且每一个鳍单元300分别和与其相邻的沟道槽20的侧壁22间形成间隙，有效增加了沟道槽20的长度。在其他可能的实施例中，鳍部30可以包括一个鳍单元300、三个鳍单元300或五个鳍单元300等。
本实施例中，如图4所示，以垂直于衬底10的平面为纵截面，鳍单元300在纵截面上的形状呈方形。例如，鳍单元300可以为圆柱形、长方体、立方体或其它任意纵截面为方形的立体结构。
本实施例中，鳍单元300尺寸根据沟道槽20的尺寸设置，例如，鳍单元 300的的高度为10-30nm，鳍单元300的宽度为5-10nm。
本实施例充分利用沟道槽的内部空间设置多个鳍单元，进一步增加沟道槽的长度，避免短沟道效应问题。其中，鳍单元的数量可以根据沟道槽的尺寸设置，避免鳍单元数量增多而相邻鳍单元之间距离太近。
本公开示例性的实施例中提供一种半导体结构，如图3所示，半导体结构包括衬底10和位于衬底10内的沟道槽20，以及位于沟道槽20的底壁21的鳍部30，鳍部30向沟道槽20的内侧凸出，鳍部30与沟道槽20的侧壁22之间具有间隙。其中，鳍部30可以包括一个或多个鳍单元300，当鳍部30包括多个鳍单元300时，相邻的两个鳍单元300之间具有间隙。
本实施例中，沟道槽20的侧壁22包括连接面222和台阶面221，台阶面221包括至少一个台阶单元220。连接面222与台阶面221相连，连接面222与衬底10的顶面相连，台阶面221与沟道槽20的底壁21相连。根据台阶面221所包含的台阶单元220的数量不同时，沿垂直于衬底10的方向，形成了多个宽度不同、深度不同的沟槽。
本实施例中，台阶单元220的尺寸根据沟道槽20的尺寸设置，例如，连接面222的长度可以为20-60nm，台阶单元220的第一面2201的宽度为2-8nm。本实施例中，沟道槽20包括多个台阶单元220时，沿垂直于衬底10的方向，最下方的台阶单元220的第二面2202的长度大于鳍部30的高度。
本实施例中，沟道槽20的底壁21在衬底10上的投影位于沟道槽20的槽口在衬底上的投影内。也即，以图3中示出的方向为准，位于上层的沟槽的宽度大于位于下层的沟槽的宽度。同时，多个台阶单元220依次相连，在沟道槽20的侧壁形成多个台阶面，增加了沟道槽20的长度。
本公开示例性的实施例中提供一种半导体结构，如图5所示，半导体结构包括：衬底10和位于衬底10内的沟道槽20，以及位于沟道槽20的底壁21的鳍部30，鳍部30向沟道槽20的内侧凸出，鳍部30与沟道槽20的侧壁22之间具有间隙。鳍部30包括一个或多个鳍单元300；鳍部30包括多个鳍单元300，相邻的两个鳍单元300之间具有间隙。其中，沟道槽20的侧壁22包括连接面222和台阶面221，台阶面221包括至少一个台阶单元220。本实施例中，连接面222与台阶面221相连，连接面222与衬底10的顶面11相连，台阶面221与沟道槽的底壁相连。
如图5所示，台阶面221包括多个首尾相连的台阶单元220，台阶单元220包括相连接的第一面2201和第二面2202，第一面2201平行于衬底10，第二面2202垂直于衬底10；台阶单元220的第二面2202与底壁21相连，或者，与和其相邻的台阶单元220的第一面2201相连；台阶单元220的第一面2201与连接面222相连，或者，与和其相邻的台阶单元220的第二面2202相连。
本实施例中，台阶单元220的第一面2201在衬底10上的投影位于沟道槽20的底壁在衬底10上的投影的外部。一个或多个第一面2201在衬底11上的投影与底壁21在衬底11上的投影的面积之和，与沟道槽20的槽口在衬底10上的投影面积相等。
其中，台阶单元200的数量根据沟道槽20的尺寸设置，沟道槽20中可以设置两个台阶单元220、三个台阶单元220、四个台阶单元220、五个台阶单元220等。如图5所示，本实施例的半导体结构在沟道槽20的侧壁22形成两个台阶单元220，沿垂直于衬底10的方向，沟道槽20两个台阶单元220限定成两个宽度不同、深度不同的沟槽。
本实施例充分利用沟道槽的内部空间设置多个台阶单元，进一步增加沟道槽的长度，避免短沟道效应问题。
本公开示例性的实施例中提供一种半导体结构，如图6所示，本实施例中的半导体结构包括衬底10和位于衬底10内的沟道槽20，以及位于沟道槽20的底壁21的鳍部30，鳍部30向沟道槽20的内侧凸出，鳍部30与沟道槽20的侧壁22之间具有间隙。沟道槽20的侧壁22包括连接面222和台阶面221，台阶面221包括至少一个台阶单元220。
如图6所示，本实施例中的半导体结构还包括：覆盖沟道槽20的底壁21和侧壁22，以及鳍部30的外表面的第三氧化层40，覆盖第三氧化层40的底壁和部分侧壁的阻挡层50，以及覆盖阻挡层50的底壁和侧壁的栅极60。
本实施例的半导体结构增加了沟道槽20长度，增加了栅极60与衬底10的接触面积，能够避免短沟道效应的问题。
根据本公开的实施例的半导体结构可用于晶体管，根据本公开的实施例的半导体结构可以被包括在存储器单元和存储器单元阵列中。存储器阵列可以被包括在存储器件中。存储器件可以用在DRAM(动态随机存储器)中。 然而，也可以应用于SRAM(静态随机存储器)、快闪存储器、FeRAM(铁电随机存储器)、MRAM(磁性随机存储器)、PRAM(相变随机存储器)等。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图7所示，图7示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图11-图23为半导体结构的制作方法的各个阶段的示意图，下面结合图11-图23对半导体结构的制作方法进行介绍。
如图7所示，本实施例中的半导体结构的制作方法包括：
S110：提供衬底。
衬底10的结构如图11所示，衬底10可以为包括含硅物质的半导体衬底。其中，半导体衬底可以包括硅衬底、硅锗衬底或SOI(silicon on insulator，绝缘体上硅)衬底。
S120：在衬底内形成容置槽。
如图17所示，容置槽200是在形成沟道槽20的中间过程中形成的中间结构，容置槽200由第一氧化层400、第二氧化层500和衬底10围成，第二氧化层500、第一氧化层400依次围绕容置槽200的侧壁。沿衬底10的厚度方向，第二氧化层500和第一氧化层400的尺寸不同。
S130：在容置槽的底壁形成鳍部，鳍部向容置槽的内侧凸出。
如图19，鳍部30形成于容置槽200的底部，鳍部30的底壁和衬底10连接，鳍部30向容置槽200内部凸出预定长度。其中，预定长度可以根据实时过程中的需求设置。
其中，鳍部30的材质包括含硅物质，比如，鳍部30的材质可以为氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅锗化物。在本实施例中，鳍部30的材质和衬底10的材质相同。
本实施例的半导体结构的制作方法，在沟道槽中形成鳍部，增加了沟道槽的长度，能够半导体结构短沟道效应的问题，从而避免半导体结构出现短沟道效应引起晶体管阈值电压降低等问题，进一步提高了半导体器件的稳定性以及电学性能。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图8所示，图8示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流 程图。
如图8所示，本实施例中的半导体结构的制作方法包括：
S210：提供衬底。
S220：在衬底内形成容置槽。
S230：在容置槽的底壁形成鳍部，鳍部30向容置槽200的内侧凸出。
在本实施例中，本实施例的步骤S210和步骤S230和上述实施例的步骤S110和步骤S130的实现方式相同，在此，不再赘述。
其中，在衬底10上形成刻蚀阻挡层80包括，如图12所示，参照图11，依据定义的图形901，对刻蚀阻挡层80和衬底10进行刻蚀，在衬底10内形成初始沟道槽210；如图14所示，参照图13，形成第一氧化层400，第一氧化层400至少覆盖初始沟道槽210的底壁和侧壁；去除覆盖初始沟道槽210的底壁的第一氧化层400，暴露衬底10；对暴露的衬底10进行刻蚀，如图15所示，形成过程沟道槽220；如图17所示，参照图16，形成第二氧化层500，第二氧化层500至少覆盖过程沟道槽220的底壁和侧壁；去除覆盖过程沟道槽220的底壁的第二氧化层500，形成容置槽200。
其中，图11、12所示，在刻蚀阻挡层80上形成光刻胶掩膜90，光刻胶掩膜90上定义有预定形状的图形901，根据光刻胶掩膜90定义的图案901刻蚀阻挡层80和衬底10，形成初始沟道槽210。其中，光刻胶掩膜90上定义的图形901可以通过光照直接定义，也可以光照先定义图形901再通过间距倍增(pitch double)的方法实现，图形901定义的方法根据根据沟道槽的宽度决定。
光刻胶掩膜90包括光阻材料，例如，光刻胶掩膜90包括光阻/SION/Carbon/SOC/SiO2/DARK，光刻胶掩膜90的厚度为20-250nm。
参照图13、14，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积第一氧化层400，第一氧化层400覆盖初始沟道槽210的侧壁、底部以及衬底10的顶面，干法或湿法刻蚀去除衬底10的顶面的第一氧化层400、去除初始沟道槽210的底壁的第一氧化层400至暴露出衬底10。
如图16所示，参照图15，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积第二氧化层500，第二氧化层500覆盖过程沟道槽220的侧壁、底部以及衬底10的顶面，干法或湿法刻蚀去除衬底10的顶面的第 二氧化层500、去除过程沟道槽220的底壁的第二氧化层500至暴露出衬底10，如图17所示，形成容置槽200。
本实施例的制作方法，半导体结构的容置槽200形成于过程沟道槽220中，沿垂直于衬底10的方向，过程沟道槽220为上层沟槽的尺寸大于下层沟槽的尺寸的结构，增加沟道槽的长度，避免半导体结构出现短沟道效应。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图9所示，图9示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图9所示，本实施例中的半导体结构的制作方法包括：
S310提供衬底。
S320在衬底10内形成容置槽。
S330在容置槽的底壁形成鳍部，鳍部向容置槽的内侧凸出。
在本实施例中，本实施例的步骤S310和步骤S320和上述实施例的步骤S210和步骤S220的实现方式相同，在此，不再赘述。
如图18所示，在容置槽的底壁形成鳍部30，包括：在容置槽200的底壁形成初始鳍部3，初始鳍部3至少覆盖容置槽200；如图19所示，刻蚀初始鳍部3，形成鳍部30。
如图18所示，在容置槽200的底壁形成初始鳍部3，包括：沉积多晶硅层，多晶硅层覆盖容置槽200和衬底10的顶壁，干法或湿法刻蚀回刻初始鳍部3至预定高度，得到鳍部30。
其中，鳍部30可包括一个或多个鳍单元300；容置槽200与鳍单元一一对应。也即，在本实施例的步骤S420中，在过程沟道槽220中形成多个容置槽220，在每个容置槽220中对应形成一个鳍单元300，如图4所示，多个鳍单元300共同形成鳍部30存在于最终的沟道槽20中。
本实施例中，半导体结构最终的沟道槽中设置多个鳍单元，充分利用沟道槽内部空间，有效增加了沟道槽的长度。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图10所示，图10示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图10所示，本实施例中的半导体结构的制作方法包括：
S410：提供衬底；
S420：在衬底内形成容置槽；
S430：在容置槽的底壁形成鳍部，鳍部向容置槽的内侧凸出。
S440：去除第一氧化层和第二氧化层，形成沟道槽。
S450：形成第三氧化层，第三氧化层覆盖沟道槽的底壁和侧壁，以及鳍部的外表面；
S460：形成阻挡层，阻挡层覆盖第三氧化层的底壁和部分侧壁；
S470：形成栅极，栅极覆盖阻挡层的底壁和侧壁。
在本实施例中，本实施例的步骤S410-步骤S430和上述实施例的步骤S310-步骤S330的实现方式相同，在此，不再赘述。
如图20所示，去除第一氧化层400和第二氧化层500，形成沟道槽20。
如图21所示，参照图20，在沟道槽20内沉积第三氧化层40，第三氧化层40覆盖沟道槽20的底壁21和侧壁22以及鳍部30的外表面；如图22所示，沉积阻挡层50，阻挡层50覆盖第三氧化层40的底壁和部分侧壁如图23所示，沉积栅极60，栅极60覆盖阻挡层50的底壁和侧壁。
本实施例制作的半导体结构可用于晶体管，能够避免短沟道效应其引起的阈值电压降低等问题。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化 描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制作方法，在沟道槽中设置鳍部并且在沟道槽的侧壁增设台阶面，增加了沟道槽的长度，解决了半导体结构的短沟道效应，提高了半导体器件的稳定性以及电学性能。

Claims (15)

  1. 一种半导体结构，包括：
    衬底；
    沟道槽，位于所述衬底内；
    鳍部，位于所述沟道槽的底壁，所述鳍部向所述沟道槽的内侧凸出，所述鳍部与所述沟道槽的侧壁之间具有间隙；
    所述沟道槽的侧壁包括连接面和台阶面，所述台阶面包括至少一个台阶单元。
  2. 根据权利要求1所述的半导体结构，其中，所述鳍部包括一个或多个鳍单元；
    所述鳍部包括多个所述鳍单元，相邻的两个所述鳍单元之间具有间隙。
  3. 根据权利要求2所述的半导体结构，其中，垂直于所述衬底的平面为纵截面，所述鳍单元在所述纵截面上的形状呈方形。
  4. 根据权利要求1至3任一项所述的半导体结构，其中，
    所述连接面与所述台阶面相连，所述连接面与所述衬底的顶面相连，所述台阶面与所述沟道槽的底壁相连。
  5. 根据权利要求4所述的半导体结构，其中，所述沟道槽的底壁在所述衬底上的投影位于所述沟道槽的槽口在所述衬底上的投影内。
  6. 根据权利要求4所述的半导体结构，其中，所述台阶面包括多个台阶单元，多个所述台阶单元首尾相连；
    所述台阶单元包括相连接的第一面和第二面，所述第一面平行于所述衬底，所述第二面垂直于所述衬底；
    所述台阶单元的第二面与所述底壁相连，或者，与和其相邻的所述台阶单元的第一面相连；
    所述台阶面的第一面与所述连接面相连，或者，与和其相邻的所述台阶单元的第二面相连。
  7. 根据权利要求6所述的半导体结构，其中，所述第一面在所述衬 底上的投影位于所述沟道槽的底壁在所述衬底上的投影的外部。
  8. 根据权利要求6所述的半导体结构，其中，一个或多个所述第一面在所述衬底上的投影与所述底壁在所述衬底上的投影的面积之和，与所述沟道槽的槽口在所述衬底上的投影面积相等。
  9. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：
    第三氧化层，覆盖所述沟道槽的底壁和侧壁，以及所述鳍部的外表面；
    阻挡层，覆盖所述第三氧化层的底壁和部分侧壁；
    栅极，覆盖所述阻挡层的底壁和侧壁。
  10. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供衬底；
    在所述衬底内形成容置槽；
    在所述容置槽的底壁形成鳍部，所述鳍部向所述容置槽的内侧凸出。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述在所述衬底内形成容置槽，包括：
    在所述衬底上形成刻蚀阻挡层；
    依据定义的图形，对所述刻蚀阻挡层和所述衬底进行刻蚀，在所述衬底内形成初始沟道槽；
    形成第一氧化层，所述第一氧化层至少覆盖所述初始沟道槽的底壁和侧壁；
    去除覆盖所述初始沟道槽的底壁的所述第一氧化层，暴露所述衬底；
    对暴露的所述衬底进行刻蚀，形成过程沟道槽；
    形成第二氧化层，所述第二氧化层至少覆盖所述过程沟道槽的底壁和侧壁；去除覆盖所述过程沟道槽的底壁的所述第二氧化层，形成所述容置槽。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述在所述容置槽的底壁形成鳍部，包括：
    在所述容置槽的底壁形成初始鳍部，所述初始鳍部至少覆盖所述容置槽；
    刻蚀所述初始鳍部，形成所述鳍部。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，所述鳍部包括一个或多个鳍单元；
    所述容置槽与所述鳍单元一一对应。
  14. 根据权利要求13所述的半导体结构的制作方法，所述半导体结构的制作方法还包括：
    去除所述第一氧化层和所述第二氧化层，形成沟道槽。
  15. 根据权利要求14所述的半导体结构的制作方法，所述半导体结构的制作方法还包括：
    形成第三氧化层，所述第三氧化层覆盖所述沟道槽的底壁和侧壁，以及所述鳍部的外表面；
    形成阻挡层，所述阻挡层覆盖所述第三氧化层的底壁和部分侧壁；
    形成栅极，所述栅极覆盖所述阻挡层的底壁和侧壁。
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