CN108281423B - 制作半导体元件的方法 - Google Patents

制作半导体元件的方法 Download PDF

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CN108281423B
CN108281423B CN201611261914.9A CN201611261914A CN108281423B CN 108281423 B CN108281423 B CN 108281423B CN 201611261914 A CN201611261914 A CN 201611261914A CN 108281423 B CN108281423 B CN 108281423B
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CN108281423A (zh
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蔡建成
黄丰铭
王嫈乔
何建廷
冯立伟
蔡综颖
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种制作半导体元件的方法，包括：首先提供一基底，该基底上具有一存储区以及一周边区，然后形成一第一埋入式栅极以及一第二埋入式栅极于存储区的基底内，形成一第一硅层于周边区的基底上，形成一堆叠层于第一硅层上，形成一外延层于第一埋入式栅极与第二埋入式栅极间的基底上以及形成一第二硅层于存储区的外延层上以及周边区的堆叠层上。

Description

制作半导体元件的方法
技术领域
本发明涉及一种制作半导体元件的方法，特别是涉及一种制作动态随机存取存储器元件的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存取存储器(Dynamic RandomAccess Memory,DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明较佳实施例揭露一种制作半导体元件的方法。首先提供一基底，该基底上具有一存储区以及一周边区，然后形成一第一埋入式栅极以及一第二埋入式栅极于存储区的基底内，形成一第一硅层于周边区的基底上，形成一堆叠层于第一硅层上，形成一外延层于第一埋入式栅极与第二埋入式栅极间的基底上以及形成一第二硅层于存储区的外延层上以及周边区的堆叠层上。
附图说明
图1至图8为本发明较佳实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 存储区(存储器区)
16 周边区 18 埋入式栅极
20 埋入式栅极 22 埋入式栅极
24 埋入式栅极 26 埋入式栅极
28 埋入式栅极 30 浅沟隔离
32 阻障层 34 导电层
36 硬掩模 38 薄氧化层
40 第一硅层 42 堆叠层
44 有机介电层 46 含硅硬掩模及抗反射层
48 图案化掩模 50 凹槽
52 外延层 54 第二硅层
56 第三硅层 58 图案化掩模
具体实施方式
请参照图1至图8，图1至图8为本发明较佳实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(silicon-on-insulator,SOI)基板。基底12上较佳定义有至少一存储区14以及一周边区16，其中存储区14可用来制备具有凹入式栅极的随机动态处理存储器(dynamic random access memory,DRAM)元件，周边区16则可用来制备例如金属氧化物半导体晶体管等主动元件。
在本实施例中，存储区14的基底12中可设置多个埋入式栅极18、20、22、24、26、28，存储区14与周边区16之间可设至少一浅沟隔离(shallow trench isolation,STI)30用来隔开记设于存储区14与周边区16的元件。在本实施例中，各埋入式栅极18、20、22、24、26、28较佳包含一阻障层32、一导电层34以及一硬掩模36设于阻障层32与导电层34上并切齐基底12表面，其中阻障层32较佳包含氮化钛，导电层34则较佳包含钨，以及硬掩模36较佳包含氮化硅，但不局限于此。
然后可选择性形成一薄氧化层38于埋入式栅极18、20、22、24、26、28之间的基底12表面以及周边区16的基底12表面，并形成一第一硅层40于周边区16的基底12上，其中第一硅层40可包含非晶硅或多晶硅等材料且较佳包含非晶硅，但不局限于此。在本实施例中，形成第一硅层40的方式可先全面性覆盖一硅层(图未示)于存储区14与周边区16，然后再进行光刻暨蚀刻制作工艺去除设于存储区14的硅层，以于周边区16形成图案化的第一硅层40。
接着如图2所示，先形成一堆叠层42于存储区14的基底12上以及周边区16的第一硅层40上，然后依序形成一有机介电层(organic dielectric layer,ODL)44、一含硅硬掩模及抗反射层(silicon-containing hard mask bottom anti-reflective coating,SHB)46以及一图案化掩模48于堆叠层42上。在本实施例中，堆叠层42较佳包含一氧化物-氮化物(oxide-nitride,ON)堆叠层或一氧化物-氮化物-氧化物(oxide-nitride-oxide，ONO)堆叠层，图案化掩模48则较佳包含一图案化光致抗蚀剂，但不局限于此。
随后如图3所示，利用图案化掩模48为掩模以蚀刻方式去除存储区14的部分含硅硬掩模及抗反射层46、部分有机介电层44、部分堆叠层42以及埋入式栅极20、22间的基底12与埋入式栅极26、28间的基底12以形成凹槽50。之后再完全去除图案化掩模48、含硅硬掩模及抗反射层46以及有机介电层44。
如图4所示，然后利用一选择性外延成长制作工艺形成外延层52于埋入式栅极20、22与埋入式栅极26、28间的基底12上，其中所成长的外延层52较佳填满凹槽50并凸出于基底12表面。在本实施例中，所成长的外延层52可包含硅、锗或锗化硅等材料，但不局限于此。
接着如图5所示，形成一第二硅层54于存储区14的外延层52上与周边区16的堆叠层42上。在本实施例中，第一硅层40与第二硅层54较佳为不同材料，但依据本发明一实施例，第一硅层40与第二硅层54又可依据制作工艺需求选用相同材料，且两者均可包含多晶硅或非晶硅。
值得注意的是，由于本发明较佳于形成第二硅层54之前便先于部分埋入式栅极，例如埋入式栅极20、22与埋入式栅极26、28之间的基底12表面形成外延层52，并藉由外延层52的设置产生一种垫高的效果，使之后覆盖其上且由存储区14延伸至周边区16的第二硅层54在整体上更为平坦。
随后如图6所示，进行一蚀刻制作工艺去除存储区14与周边区16的第二硅层54以及存储区14的部分外延层52并暴露出下面的堆叠层42，其中剩余的外延层52上表面在经过蚀刻后较佳切齐存储区14的堆叠层42上表面。在本实施例中，用来去除第二硅层54与外延层52的蚀刻制作工艺较佳包含一干蚀刻制作工艺，且所使用的蚀刻气体可包含例如溴化氢。
接着如图7所示，形成一第三硅层56于存储区14与周边区16的堆叠层42上。在本实施例中，第三硅层56可与第二硅层54以及第一硅层40为相同或不同材料，例如第三硅层56也可由多晶硅或非晶硅所组成。
之后如图8所示，先形成一图案化掩模58，例如一图案化光致抗蚀剂于存储区14的第三硅层56上，然后进行一蚀刻制作工艺去除周边区16的部分第三硅层56，藉此暴露出周边区16的堆叠层42。至此即完成随机动态处理存储器中在形成位线之前的前置制作工艺。在本实施例中，由上述图6至图8提供一种分段式的蚀刻方式，其主要包括于先以第一道蚀刻完全去除设于存储区14与周边区16的第二硅层54，形成另一第三硅层56于存储区14与周边区16，之后再以另一道蚀刻去除设于周边区16的第三硅层56。藉由上述分段蚀刻来去除存储区14与周边区16的硅层，本发明最终可使两个区域最终的硅层得到更佳的平坦性。
需注意的是，本实施例虽于图6至图8的制作工艺前先形成外延层52于凹槽50内，但依据本发明一实施例，又可选择于进行第6图的制作工艺前省略形成外延层52的步骤，例如可于图3形成凹槽50后便直接形成第二硅层54于存储区14与周边区16，然后再接续图6至图8的制作工艺，此实施例也属本发明所涵盖的范围。
之后可依据制作工艺需求进行后续位线与接触插塞、周边区16的栅极制作，例如可分别于埋入式栅极两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线，以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (8)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上具有存储区以及周边区；
形成一第一埋入式栅极以及一第二埋入式栅极于该存储区的该基底内；
形成一第一硅层于该周边区的该基底上；
形成一堆叠层于该第一硅层上；
形成一外延层于该第一埋入式栅极与该第二埋入式栅极间的该基底上；
形成一第二硅层于该存储区的该外延层上以及该周边区的该堆叠层上；
进行一蚀刻制作工艺去除该存储区与该周边区的该第二硅层并暴露出该堆叠层；
形成一第三硅层于该存储区及该周边区的该堆叠层上；以及
去除该周边区的部分该第三硅层。
2.如权利要求1所述的方法，另包含：
形成该堆叠层于该存储区的该基底上以及该周边区的该第一硅层上；
去除该存储区的部分该堆叠层以及该第一埋入式栅极与该第二埋入式栅极间的该基底以形成一凹槽；
形成该外延层于该凹槽内；以及
形成该第二硅层于该外延层上。
3.如权利要求1所述的方法，另包含于进行该蚀刻制作工艺时同时去除该存储区的部分该外延层。
4.如权利要求1所述的方法，其中该第二硅层与该第三硅层包含相同材料。
5.如权利要求1项所述的方法，其中该第一硅层与该第二硅层包含不同材料。
6.如权利要求1所述的方法，其中该第一硅层包含非晶硅。
7.如权利要求1所述的方法，其中该堆叠层包含一氧化物-氮化物-氧化物堆叠层。
8.如权利要求1所述的方法，其中该第二硅层包含多晶硅。
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