CN110246841B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN110246841B
CN110246841B CN201810189345.4A CN201810189345A CN110246841B CN 110246841 B CN110246841 B CN 110246841B CN 201810189345 A CN201810189345 A CN 201810189345A CN 110246841 B CN110246841 B CN 110246841B
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CN110246841A (zh
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徐伟伦
施泓林
黄哲弘
徐秉诚
王序扬
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

本发明公开一种半导体元件及其制作方法，该制作半导体元件的方法包括，其主要先形成一半导体层于基底上，然后去除部分半导体层以及部分基底以形成一凹槽，接着形成一衬垫层于凹槽内，去除部分衬垫层以形成一间隙壁于凹槽两侧，再形成一位线结构于凹槽内。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作动态随机存取存储器(Dynamic Random Access Memory,DRAM)元件的位线结构的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存取存储器(DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明一实施例公开一种制作半导体元件的方法，其主要先形成一半导体层于基底上，然后去除部分半导体层以及部分基底以形成一凹槽，接着形成一衬垫层于凹槽内，去除部分衬垫层以形成一间隙壁于凹槽两侧，再形成一位线结构于凹槽内。
本发明另一实施例公开一种半导体元件，其主要包含一位线结构设于一基底上以及一间隙壁环绕位线结构，其中间隙壁上表面切齐或低于基底上表面。此外半导体元件又包含一浅沟隔离设于基底内，其中间隙壁被浅沟隔离所环绕，且间隙壁上表面切齐或低于浅沟隔离上表面。另外位线结构又细部包含一导电层设于基底内、一金属层于导电层上以及一掩模层于金属层上，其中导电层下表面低于基底上表面，且间隙壁设于导电层以及浅沟隔离之间。
附图说明
图1为本发明一实施例的动态随机存取存储器元件的上视图；
图2至图6为图1中沿着切线A-A’方向制作动态随机存取存储器元件的位线结构的方法示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线结构
14 字符线 16 基底
18 主动区 20 存储单元区
22 栅极 24 浅沟绝缘
26 位线结构 28 位线结构
30 绝缘层 32 半导体层
34 凹槽 36 氧化硅层
38 氮化硅层 40 氧化硅层
42 衬垫层 44 间隙壁
46 间隙壁 48 间隙壁
50 导电层 52 金属层
54 掩模层 56 钛层
58 氮化钛层 60 硅化钨层
62 钨层 64 位线结构
66 位线接触
具体实施方式
请参照图1至图6，图1至图6为本发明一实施例制作一动态随机存取存储器元件的方法示意图，其中图1为本发明制作一动态随机存取存储器元件的上视图，图2至图6则显示图1中沿着切线AA’方向制作动态随机存取存储器元件的位线的方法示意图。本实施例是提供一存储器元件，例如是具备凹入式栅极的动态随机存取存储器元件10，其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示)，以作为DRAM阵列中的最小组成单元并接收来自于位线或位线结构12、26、28及字符线14的电压信号。
如图1所示，动态随机存取存储器元件10包含一基底16，例如一由硅所构成的半导体基底，然后于基底16内形成有至少一浅沟绝缘24，以于基底16上定义出多个主动区(active area,AA)18。此外，基底16上还定义有一存储单元区20以及一周边区(图未示)。其中，动态随机存取存储器元件10的多个字符线(word line,WL)14与多个位线(bit line,BL)结构12、26、28较佳形成于存储单元区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是，为简化说明，本发明的图1仅绘示出位于存储单元区20的元件上视图并省略了位于周边区的元件。
在本实施例中，各主动区18例如是相互平行地朝向一第一方向延伸，而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说，各栅极22是沿着不同于第一方向的一第二方向，例如Y方向延伸，且第二方向与第一方向相交并小于90度。
另一方面，位线结构12、26、28是相互平行地形成在基底16上沿着一第三方向，例如X方向延伸，并同样横跨各主动区18及浅沟绝缘24。其中，第三方向同样是不同于第一方向，并且较佳是与第二方向垂直。也就是说，第一方向、第二方向及第三方向彼此都不同，且第一方向与第二方向及第三方向都不垂直。此外，字符线14两侧的主动区18内较佳于后续制作工艺中形成接触插塞，例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对形成浅沟隔离24以及字符线14(或又称埋入式字符线)后的制作进行说明。首先如图2所示，先形成一浅沟隔离24于基底16内由此定义出主动区18并于部分浅沟隔离24以及基底16内形成字符线(图未示)，再依序形成一绝缘层30以及一半导体层32于浅沟隔离24以及基底16上。然后进行一光刻及蚀刻制作工艺去除部分半导体层32、部分绝缘层30以及部分基底16以形成一凹槽34于基底16内，其中深入基底16内的部分凹槽34被浅沟隔离24所环绕。在本实施例中，绝缘层30较佳包含一多层结构，例如可细部包含一氧化硅层36、一氮化硅层38以及另一氧化硅层40，而设于绝缘层30上的半导体层32则较佳包含非晶硅，但不局限于此。
如图3所示，接着形成一衬垫层42于凹槽34内但不填满凹槽34，其中衬垫层42较佳覆盖于半导体层32上表面、半导体层32侧壁、绝缘层30侧壁以及凹槽34内的基底16表面。在本实施例中，衬垫层42较佳包含氮化硅，但不局限于此，依据本发明其他实施例衬垫层42又可由例如氧化硅、氮氧化硅或氮碳化硅等介电材料所构成。
随后如图4所示，进行一蚀刻制作工艺去除部分衬垫层42以形成一间隙壁44于凹槽34两侧。在本实施例中，蚀刻制作工艺较佳利用含氟气体来去除部分衬垫层42以形成间隙壁44，其中间隙壁44在实际制作工艺或由俯视的角度下设于凹槽34周围的侧壁并环绕整个凹槽34，但若由图4的剖视图来看则较佳设于凹槽34两侧的浅沟隔离24以及/或基底16侧壁，例如间隙壁44更细部包含间隙壁46设于凹槽34左侧的浅沟隔离24及绝缘层30侧壁以及间隙壁48设于凹槽34右侧的浅沟隔离24及绝缘层30侧壁。在本阶段所形成的间隙壁44上表面较佳切齐或略低于半导体层32下表面，其中各间隙壁46、48的高度在本阶段较佳介于45纳米至55纳米或更佳约50纳米，各间隙壁46、48的宽度则较佳介于25纳米至35纳米或更佳约30纳米。
如图5所示，然后于形成间隙壁44之后先形成一导电层50于凹槽34内填满凹槽34并覆盖半导体层32表面，接着进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)方式去除部分导电层50使剩余的导电层50上表面切齐半导体层32上表面。随后依序形成至少一金属层52于导电层50上以及一掩模层54于金属层52上。在本实施例中，导电层50较佳由具有掺质的外延材料例如磷化硅所构成，但又可包括多晶硅、非晶硅或其他含硅或不含硅的非金属导电材料。金属层52较佳包含一金属堆叠结构，例如可细部包含一钛层56、一氮化钛层58、一硅化钨层60以及一钨层62，而掩模层54则较佳包含一氮化硅层，但又可包括氧化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。
接着如图6所示，进行一光刻及蚀刻制作工艺图案化掩模层54、金属层52以及导电层50以形成一位线结构64于基底16上，其中依据前述制作工艺所形成位于位线结构64以及浅沟隔离24之间的间隙壁44可用来避免漏电流的产生。在本实施例中，位线结构64的制作可先形成一图案化掩模(图未示)于掩模层54上，接着进行一道或一道以上蚀刻制作工艺利用例如溴化氢(HBr)等蚀刻气体依序去除部分掩模层54、部分金属层52以及部分导电层50，其中被图案化的掩模层54、金属层52以及导电层50较佳构成一位线结构64，而接触基底16的导电层50下半部则较佳作为一位线接触66。
需注意的是，设于导电层50以及浅沟隔离24之间的间隙壁44可能在前述图案化过程中被部分去除，因此形成位线结构64之后剩余的间隙壁44高度可能略低于图4的间隙壁44高度。在本实施例中，此阶段所剩余的间隙壁44上表面较佳切齐基底16上表面，但不排除位于绝缘层30上表面以及下表面之间甚至略低于基底16上表面，这些变化型均属本发明所涵盖的范围。之后可依据制作工艺需求于位线结构64两侧形成存储节点接触电连接源极/漏极区域以及后续所制作的电容。由于存储结点接触以及电容的制作均为本领域所熟知技术，在此不另加赘述。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种制作半导体元件的方法，其特征在于，包含：
形成一绝缘层与一半导体层于一基底上，该绝缘层位于该半导体层与该基底之间；
形成一浅沟隔离于该基底内，其中在形成该半导体层之前形成该绝缘层于该浅沟隔离以及该基底上；
去除部分该半导体层、部分该绝缘层以及部分该基底以形成一凹槽；
形成一衬垫层于该凹槽内；
去除部分该衬垫层以形成一间隙壁于该凹槽两侧；以及
形成一位线结构于该凹槽内,
其中该间隙壁上表面低于该半导体层上表面，且该间隙壁上表面与该绝缘层的上表面切齐。
2.如权利要求1所述的方法，另包含：
在形成该间隙壁之后形成一导电层于该凹槽内；
形成一金属层于该导电层上；
形成一掩模层于该金属层上；以及
图案化该掩模层、该金属层以及该导电层以形成该位线结构。
3.如权利要求2所述的方法，另包含：
形成该导电层于该凹槽内；以及
去除部分该导电层使该导电层上表面切齐该半导体层上表面。
4.如权利要求1所述的方法，另包含：
形成该半导体层于该浅沟隔离以及该基底上；以及
形成该凹槽于该基底内，其中该浅沟隔离环绕该凹槽。
5.如权利要求1所述的方法，其中该半导体层包含一非晶硅层。
6.如权利要求1所述的方法，其中该间隙壁包含氮化硅。
7.如权利要求1所述的方法，其中该间隙壁包含氧化硅。
8.一种半导体元件，其特征在于，包含：
位线结构，设于一基底上，其中该位线结构包含设于该基底内的导电层、在该导电层上的金属层、以及在该金属层上的掩模层，其中该导电层下表面低于该基底上表面；
间隙壁，环绕该位线结构；
绝缘层，位于该基底上；
半导体层，位于该绝缘层上；以及
浅沟隔离，设于该基底内，
其中该间隙壁上表面低于该半导体层上表面，且该间隙壁上表面与该绝缘层的上表面切齐。
9.如权利要求8所述的半导体元件，其中该间隙壁被该浅沟隔离所环绕。
10.如权利要求8所述的半导体元件，其中该间隙壁设于该导电层以及该浅沟隔离之间。
11.如权利要求8所述的半导体元件，其中该间隙壁包含氮化硅。
12.如权利要求8所述的半导体元件，其中该间隙壁包含氧化硅。
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