CN108269758B - 半导体元件的制作方法 - Google Patents

半导体元件的制作方法 Download PDF

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Publication number
CN108269758B
CN108269758B CN201611242446.0A CN201611242446A CN108269758B CN 108269758 B CN108269758 B CN 108269758B CN 201611242446 A CN201611242446 A CN 201611242446A CN 108269758 B CN108269758 B CN 108269758B
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bit line
region
layer
wall
semiconductor element
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CN108269758A (zh
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何建廷
邹世芳
吴俊元
冯立伟
林裕杰
王嫈乔
蔡综颖
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to CN201611242446.0A priority Critical patent/CN108269758B/zh
Priority to US15/854,827 priority patent/US10236294B2/en
Publication of CN108269758A publication Critical patent/CN108269758A/zh
Priority to US16/216,954 priority patent/US10763260B2/en
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Abstract

本发明公开一种半导体元件的制作方法，其步骤包含：提供一基底，其上具有一存储区域以及一逻辑区域、在该存储区域以及该逻辑区域中分别形成位线以及逻辑栅极，其中位线之间界定有存储节点区域、在该位线的侧壁上形成一第一低介电系数材料层；在位线之间的存储节点区域中形成掺杂硅层，其中该掺杂硅层的顶面低于位线的顶面、在存储节点区域的侧壁上形成一第二低介电系数材料层、以及在该存储区域的存储节点区域中填入金属插塞。

Description

半导体元件的制作方法
技术领域
本发明大体上涉及一种半导体元件的制作方法，特别是涉及一种使用低介电系数(low-K)材料的半导体元件的制作方法。
背景技术
半导体元件因为具有小尺寸、多功能、以及低制作成本的优点，其被广泛使用在电子工业中。其中，半导体元件可分成用来存储逻辑数据的存储元件、用来处理运算该些逻辑数据的逻辑元件、以及同时具有存储功能与逻辑运算功能的混合元件等。
半导体元件一般会含有垂直堆叠的图形以及与之电连接的接触插塞。在高度整合的情况下，半导体元件中图形之间以及/或图形与接触插塞之间的空间会减少。如此，其间的寄生电容也会增加，可能会导致半导体元件的运作速度下降并且效能劣化。为此，如何减少寄生电容是现今半导体业界亟需研究的课题。
发明内容
本发明的一目的在于提出一种半导体元件的制作方法，其特点为沿着位线的两侧以及存储节点的周围设置低介电系数(low-K)材料层，可有效降低元件中的寄生电容，且其制作工艺步骤可与周边区域逻辑单元的制作工艺整合，不用额外耗费多余的制作成本与时间，为其另一优点。
为了达到上述目的，本发明的一实施例中提出了一种半导体元件的制作方法，其步骤包含提供一基底，其上具有一存储区域以及一逻辑区域、在该存储区域以及该逻辑区域中分别形成位线以及逻辑栅极，其中位线之间界定有存储节点区域、在该位线的侧壁上形成一第一低介电系数材料层；在位线之间的存储节点区域中形成掺杂硅层，其中该掺杂硅层的顶面低于位线的顶面、在存储节点区域的侧壁上形成一第二低介电系数材料层、以及在该存储区域的存储节点区域中填入金属插塞。
无疑地，本发明的这类目的与其他目的在阅者读过下文以多种附图与绘图来描述的较佳实施例细节说明后将变得更为显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，以使阅者对本发明实施例有进一步的了解。该些附图描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些附图中：
图1-图11为根据本发明实施例一半导体元件制作工艺的截面示意图；以及
图12为根据本发明实施例一半导体元件的平面示意图。
须注意本说明书中的所有附图皆为图例性质，为了清楚与方便附图说明之故，附图中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
10 存储区域
20 逻辑区域
100 半导体基板
102 主动区域
104 场氧化区域
106 开口
110 位线
112 位线接触插塞
114 位线电极
116 硬掩模层
118 金属硅化物层
120 第一间隔层
122 第二间隔层
124 第三间隔层
126 第一低介电系数材料层
126a 第一低介电系数材料层
127 存储节点区域
128 接触蚀刻停止层
128a 接触蚀刻停止层
130 层间介电层
132 掺杂硅层(下存储节点结构)
134 第二低介电系数材料层
134a 第二低介电系数材料层
136 接触插塞(上存储节点结构)
210 逻辑栅极
212 栅介电层
214 栅电极
216 上盖层
218 间隔壁
220 源/漏极
224 接触插塞
310 字符线
具体实施方式
在下文的细节描述中，元件符号会标示在随附的附图中成为其中的一部分，并且以可实行该实施例的特例描述方式来表示。这类实施例会说明足够的细节以使该领域的一般技术人士得以具以实施。阅者须了解到本发明中也可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
阅者将能了解到，尽管文中使用了"第一"、"第二"等词来描述本发明的多种部件，这类部件并不会被这类用词所限定。故此，在本发明概念的范畴内，第一部件、第一组件、或第一部位等词也可能被称为第二部件、第二组件、或第二部位等词。
文中用来说明本发明实施例的用词并未意欲要限制本发明概念的范畴。发明公开中使用单个型态来进行部件的说明，然其并未排除掉其他多数型态的部件形式。换言之，除非上下文有具体指明，否则发明概念中单一型态的部件也可能是一或多个形态。阅者将更能了解，当文中使用"包括"、包含等词时，其为具体说明所指称的特征、实体、步骤、运作、元件与/或部件的存在，但其并未排除其他特征、实体、步骤、运作、元件、部件与/或其组合的存在。
现在下文中将依序参照图1至图11来说明本发明半导体元件的制作方法的流程。首先请参照图1，根据本发明半导体元件的制作方法，首先准备一半导体基板100作为部件设置的基础。半导体基板100可包含硅基板、硅锗(SiGe)基板、或是硅覆绝缘(silicon-on-insulator,SOI)基板等，其上分为一存储区域10，用以设置由多个存储单元排列而成的存储阵列，以及一逻辑区域20，其一般位于存储区域10的周边，用以设置其他逻辑功能性电路，如感应放大器、地址缓冲器、及地址解码器等。下文实施例中所提到的制作工艺步骤有些仅在存储区域10与逻辑区域20的其中一区域中进行，有些则是两区域都会进行。
半导体基板100包含了主动区域102与场氧化区域104(或为浅沟槽绝缘结构)，场氧化区域104可为场绝缘材料，如氧化硅，填入预先形成的场氧化物沟槽中而形成，其围绕在主动区域102四周而界定出主动区域102。半导体基板100的存储区域10与逻辑区域20上分别预先形成有位线110与逻辑栅极210，其中位线110由下而上可依序包含一位线接触插塞112，如一受掺杂的多晶硅层或非晶硅层，其伸入半导体基板100中并与其下方的主动区域直接电连接、一位线电极114，如钛/氮化钛/钨(Ti/TiN/W)等复层金属结构、以及一硬掩模层116，如氮化硅层。位线接触插塞112与位线电极114之间还可形成有一金属硅化物层118，如位线电极最下层金属与硅受热反应形成的金属硅化物，来连结位线电极114与位线接触插塞112。制作工艺中可能会因为原先所吃出的位线接触开口宽度大于位线110宽度之故而使得位线栅极110两侧与基底之间形成有开口106。
复参照图1，半导体基板100的逻辑区域20上的逻辑栅极210包含一栅介电层212，如氧化硅层、栅电极层214，如多晶硅层、以及一上盖层216，如氮化硅层。在本发明实施例中，逻辑区域20上的逻辑栅极210与存储区域10上的位线栅极110不在同一道蚀刻制作工艺中形成。然而在其他实施例中，逻辑区域20上的逻辑栅极210与存储区域10上的位线栅极110可能使用同一道蚀刻制作工艺同时形成。
请参照图2，在形成位线110与逻辑栅极210后，接着在存储区域10与逻辑区域20上共形地形成一第一间隔层120与一第二间隔层122，其会覆盖住整个位线110与逻辑栅极210。其中第一间隔层120可为氮化硅层或氮碳化硅层(SiCN)再加上一氧化层，其可作为位线的阻障层。第二间隔层120可为另一氮化硅层，其相对于第一间隔层120而言因为其间具有一氧化层而具有蚀刻选择性。第一间隔层120与第二间隔层122会填满位线110两侧的开口106。或者，在某些实施例中开口106不会被填满而形成气隙。
请参照图3，在形成第一间隔层120与第二间隔层122后，接着再于逻辑区域20形成一第三间隔材料，其后并对逻辑区域10施以一各向异性蚀刻制作工艺形成位于逻辑栅极210两侧的间隔壁218，其由第一间隔层120、第二间隔层122以及第三间隔层124所构成。需注意在此步骤中存储区域10并不会有第三间隔层124残留，其可以通过光致抗蚀剂以及氧化硅蚀刻剂(buffered oxide etch,BOE)来选择性移除存储区域10上的第三间隔层124的作法达成。再者，存储区域10上未受到第三间隔层124覆盖的第二间隔层122之后还会再通过具有蚀刻选择性的其他蚀刻剂来加以移除，仅有部分位于开口区内的第二间隔层122残留，并裸露出第一间隔层120。
请参照图4，在移除第二间隔层122后，接着在存储区域10上共形地形成一第一低介电系数材料层126，其完整覆盖位线110。低介电系数材料的例子包含但不限定为氢硅酸盐聚合物(hydrogen silsesquioxane,HSQ)、甲基硅酸盐聚合物(methyl silsesquioxane,MSQ)、聚苯寡聚物(polyphenylene oligomer)、甲基掺杂石英(methyl doped silica)、有机硅玻璃(organosilicate glass)或多孔性硅化物材料等。需注意在此实施例中逻辑区域20上并不会形成第一低介电系数材料层126。另一方面，逻辑区域20上会进行一离子布值制程在先前所形成的间隔壁218与外侧的场氧化区域104之间形成源/漏极220。
请参照图5，在形成第一低介电系数材料层126后，接着进行一各向异性蚀刻制作工艺移除位于存储区域10表面的第一低介电系数材料层126以及第一间隔层120，仅留下位线110侧壁上的第一低介电系数材料层126a，并使得存储区域10的主动区域102裸露。在本实施例中，位线110之间会界定出存储节点(storage node)区域127，该区域是预留来设置存储元件的存储节点结构。在本发明实施例中，在位线110侧壁上设置第一低介电系数材料层126a将可降低因为位线与周围存储节点等元件距离过近而衍生的寄生电容，有助于改善元件效能。
请参照图6，接着在存储区域10与逻辑区域20上共形地形成一接触蚀刻停止层(contact etch stop layer,CESL)128，如一氮化硅层，其材质相较于后续制作工艺中将要形成的层间介电层(ILD)材料而言具有良好的蚀刻选择性。
请参照图7，在形成接触蚀刻停止层128后，接着在存储区域10与逻辑区域20上毯覆形成一层间介电层(ILD)130，并施以一化学机械研磨制作工艺将其磨至与位线110与逻辑栅极210齐平。层间介电层130会填满位线栅极110之间的存储节点区域127
请参照图8，在层间介电层130形成后，再位于存储区域10中的层间介电层130会通过氧化硅蚀刻剂加以移除，并再进行一各向异性蚀刻制作工艺移除位于存储区域10表面的接触蚀刻停止层128，仅留下位线110侧壁上的接触蚀刻停止层128a，使得存储区域10中的主动区域102裸露。如此存储节点区域127会再次预留出来以供存储节点部件的形成。
请参照图9，接下来在存储区域10中位线110之间的存储节点区域127中形成掺杂硅层132，如一磷掺杂硅层，作为下存储节点结构。其中掺杂硅层132的顶面会低于周围位线栅极110的顶面，使得该存储节点区域127并未被掺杂硅层132所填满。掺杂硅层132可以下列方式形成：首先在存储区域10上覆盖一掺杂硅材料，其填满位线110之间的存储节点区域127，之后再施行一回蚀制作工艺移除存储节点区域127以外的掺杂硅材料直至其顶面低于周围位线110的顶面达一预定高度为止。如此即完成了下存储节点结构。上方剩余的存储节点区域127则可供以形成上存储节点结构。须注意在此实施例中逻辑区域20并不会有掺杂硅层132形成。
请参照图10，在存储节点区域127中形成掺杂硅层132后，接着在存储区域10上共形地形成一第二低介电系数材料层134。第二低介电系数材料层134会覆盖在位线栅极110以及剩余的存储节点区域127表面。第二低介电系数材料134可与第一低介电系数材料相同，其包含但不限定为氢硅酸盐聚合物(hydrogen silsesquioxane,HSQ)、甲基硅酸盐聚合物(methyl silsesquioxane,MSQ)、聚苯寡聚物(polyphenylene oligomer)、甲基掺杂石英(methyl doped silica)、有机硅玻璃(organosilicate glass)或多孔性硅化物材料等。须注意在此实施例中逻辑区域20上不会形成第二低介电系数材料层134。
请参照图11，在形成第二低介电系数材料层134后，接着进行一回蚀制作工艺移除位线110顶面以及存储节点区域127底面的第二低介电系数材料层134，仅留下位线之间侧壁上的第二低介电系数材料层134a，使得存储节点区域127中的掺杂硅层132裸露出来。此外，另再对逻辑区域20进行光刻蚀刻制作工艺以在层间介电层130中吃出接触孔222通往下方的源/漏极220。
复参照图11，之后在存储区域20剩余的存储节点区域127以及逻辑区域10的接触孔222中填入金属，分别形成接触插塞136与224结构，其可能包含钛/氮化钛/钨(Ti/TiN/W)等复层结构，使其分别与下方的掺杂硅层132以及源/漏极220电连接。存储区域20上的接触插塞136是与掺杂硅层132连结作为上存储节点结构。此外，在接触插塞填入前，可先进行一金属硅化物制作工艺以在掺杂硅层132以及源/漏极220的裸露表面形成金属硅化物，以与后续填入的金属插塞有良好的电连接。
请参照图12，其为根据本发明实施例一半导体元件的平面示意图。在本发明实施例中，在制作工艺前段就形成的第一低介电系数材料层126a是沿着位线110的侧壁形成，其可有效降低位线与周围存储节点元件等距离过近而衍生的寄生电容。再者，制作工艺后段所形成的第二低介电系数材料层134a是分布设置在由位线110(横列方向)与字符线310(纵列方向)所界定出的存储节点区域127周围的侧壁上，其可围住整个存储节点区域。如此进一步寄生电容问题将可获得进一步的改善。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种半导体元件的制作方法，包含：
提供一基底，该基底具有存储区域以及逻辑区域；
在该存储区域以及该逻辑区域中分别形成位线以及逻辑栅极，其中该位线之间界定有存储节点区域；
在形成所述位线之后，在该位线的侧壁上形成一第一低介电系数材料层；
在该位线之间的该存储节点区域中形成掺杂硅层，其中该掺杂硅层的顶面低于该位线的顶面；
在该存储节点区域的侧壁上形成一第二低介电系数材料层；
在该存储区域的该存储节点区域中填入接触插塞。
2.如权利要求1所述的半导体元件的制作方法，还包含：
在该位线以及该逻辑栅极上形成一第一间隔层与一第二间隔层；
在形成该第一间隔层与该第二间隔层后，在该逻辑栅极上形成一第三间隔层；以及
移除该位线上的该第二间隔层。
3.如权利要求2所述的半导体元件的制作方法，其中在该逻辑栅极上形成该第三间隔层的步骤包括：
在该存储区域以及该逻辑区域上形成该第三间隔层；以及
进行一蚀刻制作工艺，移除该存储区域上的该第三间隔层。
4.如权利要求2所述的半导体元件的制作方法，还包含对该逻辑栅极上的该第一间隔层、该第二间隔层以及该第三间隔层进行一各向异性蚀刻而在该逻辑栅极两侧形成间隔壁。
5.如权利要求1所述的半导体元件的制作方法，其中在该位线的侧壁上形成该第一低介电系数材料层的步骤包括：
在该存储区域上形成该第一低介电系数材料层；以及
进行一蚀刻制作工艺移除该位线的顶面上以及该基底的表面上的该低介电系数材料层。
6.如权利要求1所述的半导体元件的制作方法，在该位线的侧壁上以及该逻辑栅极上形成一接触蚀刻停止层。
7.如权利要求6所述的半导体元件的制作方法，其中在该位线的侧壁上形成该接触蚀刻停止层的步骤包括：
在该位线以及该逻辑栅极上形成该接触蚀刻停止层；以及
对该存储区域进行一蚀刻制作工艺，移除该位线的顶面上以及该基底的表面上的该接触蚀刻停止层。
8.如权利要求6所述的半导体元件的制作方法，还包含：
在该接触蚀刻停止层上形成一层间介电层；
进行一蚀刻制作工艺移除该存储区域上的该层间介电层并在该逻辑区域的该层间介电层中形成接触孔；以及
在该接触孔中填入该接触插塞。
9.如权利要求1所述的半导体元件的制作方法，其中在该位线之间的该存储节点区域中形成该掺杂硅层的步骤包括：
在该存储区域上形成该掺杂硅层；以及
对该掺杂硅层进行一回蚀制作工艺直至该掺杂硅层的顶面高度低于该位线的顶面高度。
10.如权利要求1所述的半导体元件的制作方法，其中在该存储节点区域的侧壁上形成该第二低介电系数材料层的步骤包括：
在该位线与该掺杂硅层上形成该第二低介电系数材料层；以及
进行一蚀刻制作工艺移除该位线的顶面上以及该掺杂硅层的顶面上的该第二低介电系数材料层，使得仅该存储节点区域的侧壁上残留有该第二低介电系数材料层。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630698B (zh) * 2017-03-24 2019-10-18 联华电子股份有限公司 半导体存储装置及其形成方法
KR20190034023A (ko) * 2017-09-22 2019-04-01 삼성전자주식회사 집적회로 소자
CN110246841B (zh) 2018-03-08 2021-03-23 联华电子股份有限公司 半导体元件及其制作方法
CN113078157B (zh) * 2020-01-06 2023-06-02 华邦电子股份有限公司 存储器结构及其形成方法
CN114267678A (zh) * 2020-09-04 2022-04-01 福建省晋华集成电路有限公司 存储器
CN114188323B (zh) * 2020-09-15 2024-06-07 长鑫存储技术有限公司 半导体器件及其制备方法、存储装置
KR20220067566A (ko) * 2020-11-16 2022-05-25 삼성전자주식회사 반도체 메모리 소자
CN115050700A (zh) * 2022-06-15 2022-09-13 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104005A (zh) * 2009-12-16 2011-06-22 三星电子株式会社 制造垂直沟道晶体管的方法
CN102569248A (zh) * 2010-12-15 2012-07-11 海力士半导体有限公司 具有掩埋栅的半导体器件及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4927321B2 (ja) * 2004-06-22 2012-05-09 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7807582B2 (en) * 2006-03-06 2010-10-05 Micron Technology, Inc. Method of forming contacts for a memory device
KR101924020B1 (ko) * 2012-10-18 2018-12-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102001511B1 (ko) 2012-12-26 2019-07-19 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
KR20140086645A (ko) 2012-12-28 2014-07-08 에스케이하이닉스 주식회사 자기정렬된 에어갭을 구비한 반도체장치 및 그 제조 방법
KR102059863B1 (ko) 2013-08-30 2019-12-30 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9425200B2 (en) 2013-11-07 2016-08-23 SK Hynix Inc. Semiconductor device including air gaps and method for fabricating the same
KR102175040B1 (ko) 2013-12-20 2020-11-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102055333B1 (ko) * 2014-01-29 2020-01-22 에스케이하이닉스 주식회사 듀얼일함수 매립게이트형 트랜지스터 및 그 제조 방법, 그를 구비한 전자장치
KR102185661B1 (ko) * 2014-02-07 2020-12-02 삼성전자주식회사 비트 라인 구조체 및 스토리지 컨택 플러그를 포함하는 반도체 소자
KR102200342B1 (ko) 2014-03-17 2021-01-08 삼성전자주식회사 비트 라인 구조체의 측면들 상에 위치하는 에어 갭들을 포함하는 반도체 소자
KR102156643B1 (ko) * 2014-05-14 2020-09-17 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
KR102238951B1 (ko) 2014-07-25 2021-04-12 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US9337149B2 (en) * 2014-07-29 2016-05-10 Samsung Electronics Co, Ltd. Semiconductor devices and methods of fabricating the same
KR102188063B1 (ko) 2015-01-21 2020-12-07 삼성전자 주식회사 반도체 소자
US9634019B1 (en) * 2015-10-01 2017-04-25 Silicon Storage Technology, Inc. Non-volatile split gate memory cells with integrated high K metal gate, and method of making same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104005A (zh) * 2009-12-16 2011-06-22 三星电子株式会社 制造垂直沟道晶体管的方法
CN102569248A (zh) * 2010-12-15 2012-07-11 海力士半导体有限公司 具有掩埋栅的半导体器件及其制造方法

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