WO2022198885A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022198885A1
WO2022198885A1 PCT/CN2021/112274 CN2021112274W WO2022198885A1 WO 2022198885 A1 WO2022198885 A1 WO 2022198885A1 CN 2021112274 W CN2021112274 W CN 2021112274W WO 2022198885 A1 WO2022198885 A1 WO 2022198885A1
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Prior art keywords
isolation
substrate
along
trench
forming
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PCT/CN2021/112274
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English (en)
French (fr)
Inventor
朱梦娜
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长鑫存储技术有限公司
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Priority to US17/647,893 priority Critical patent/US20220310627A1/en
Publication of WO2022198885A1 publication Critical patent/WO2022198885A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • DRAM Dynamic Random Access Memory
  • each memory cell usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.
  • a plurality of active regions are arranged in an array inside the substrate, and adjacent active regions are isolated from each other by a shallow trench isolation structure.
  • the shallow trench isolation structures and the active regions are alternately arranged.
  • the dimensions of the shallow trench isolation structures inside the substrate are all the same, and the depth of the same word line in the shallow trench isolation structure is greater than the depth in the active region, which results in the word line being located in the shallow trench.
  • Some embodiments of the present application provide a semiconductor structure and a method for forming the same, which are used to solve the problem of large coupling effect between word lines and active regions in the semiconductor structure, so as to improve the electrical performance of the semiconductor structure.
  • the present application provides a method for forming a semiconductor structure, comprising the steps of:
  • a plurality of first trench structures and a plurality of second trench structures are formed in the substrate, and the substrate is divided into a plurality of active regions arranged in an array along the first direction and the second direction, so that The first trench structure is located between the two active regions arranged in parallel along the first direction, and the first trench structure is annular, and a plurality of the second trench structures are arranged along the first direction. They are arranged in parallel in the second direction, and the second trench structures are located between two adjacent rows of the active regions that are arranged in parallel along the second direction.
  • the two trench structures are connected, the first direction and the second direction are both parallel to the surface of the substrate, and the first direction and the second direction intersect;
  • word lines in the substrate extending in a third direction, the word lines passing through at least the first isolation structure and the second isolation structure, the third direction being parallel to the surface of the substrate and It intersects both the first direction and the second direction.
  • the present application also provides a semiconductor structure, comprising:
  • the plurality of the active regions are arranged in an array along a first direction and a second direction inside the substrate, and the first direction and the second direction are both parallel to the substrate a surface, and the first direction intersects the second direction;
  • first isolation structure and a second isolation structure located in the substrate, the first isolation structure is located between the two active regions arranged in parallel along the first direction, and the first isolation structure
  • the structure is annular, a plurality of the second isolation structures are arranged in parallel along the second direction, and the second isolation structures are located in two adjacent rows of the active regions that are arranged in parallel along the second direction between, the first isolation structure communicates with the second isolation structure;
  • word lines extending through at least the first isolation structure and the second isolation structure in a third direction, the third direction being parallel to the substrate surface and being parallel to the first direction and the The second directions all intersect.
  • a semiconductor structure and a method for forming the same are provided, wherein the substrate is divided into arrays arranged in an array along a first direction and a second direction by a first isolation structure and a second isolation structure located in the substrate.
  • the first isolation structure is located between two of the active regions arranged in parallel along the first direction, and the first isolation structure is annular, a plurality of the second The isolation structures are arranged in parallel along the second direction, and the second isolation structures are located between two adjacent rows of the active regions arranged in parallel along the second direction, and the first isolation structures are connected to The second isolation structure is connected, that is, by changing the arrangement of the active region and the isolation structure inside the substrate, the coupling effect between the word line and the adjacent active region is reduced, and the electrical performance of the semiconductor structure is improved.
  • FIG. 1 is a flowchart of a method for forming a semiconductor structure in a specific embodiment of the present application
  • 2A-2V are schematic cross-sectional views of main processes in the process of forming the semiconductor structure in the specific embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming a semiconductor structure in the specific embodiment of the present application
  • FIGS. 2A-2V are the process of forming the semiconductor structure in the specific embodiment of the present application. Schematic diagram of the main process cross-section.
  • the semiconductor structure described in this detailed description can be, but is not limited to, a DRAM.
  • FIG. 2A-FIG. 2V the method for forming a semiconductor structure provided by this specific embodiment includes the following steps:
  • step S11 the substrate 10 is provided, as shown in FIG. 2B.
  • the substrate 10 may be, but is not limited to, a silicon substrate or a polysilicon substrate.
  • the substrate 10 is a silicon substrate as an example for description, and the substrate 10 is used to support device structure on it.
  • the substrate 10 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate 10 may be a single-layer substrate or a multi-layer substrate formed by stacking a plurality of semiconductor layers.
  • Step S12 forming a plurality of first trench structures 24 and a plurality of second trench structures 25 in the substrate 10, and dividing the substrate 10 into an array along the first direction D1 and the second direction D2 A plurality of active regions 26 are distributed, the first trench structure 24 is located between the two active regions 26 arranged in parallel along the first direction D1, and the first trench structure 24 is In a ring shape, a plurality of the second trench structures 25 are arranged in parallel along the second direction D2, and the second trench structures 25 are located in two adjacent rows arranged in parallel along the second direction D2.
  • the first trench structure 24 communicates with the second trench structure 25, the first direction D1 and the second direction D2 are both parallel to the surface of the substrate 10, And the first direction D1 and the second direction D2 intersect, as shown in FIG. 2M- FIG. 2R .
  • the specific steps of forming a plurality of first trench structures 24 and a plurality of second trench structures 25 in the substrate 10 include:
  • a patterned first mask layer 21 is formed, the first mask layer 21 has a plurality of first etching structures and a plurality of second etching structures, and the plurality of the first etching structures are all annular and Arranged in an array along the first direction D1 and the second direction D2, the second etching structure is a strip-shaped structure extending along the first direction D1, and a plurality of the second etching structures Arranged in parallel along the second direction D2, the first etching structure communicates with the second etching structure;
  • the substrate 10 is etched along the first etching structure and the second etching structure, and a plurality of first trench structures 24 and a plurality of second trench structures 25 are formed in the substrate 10 .
  • the specific steps of forming the patterned first mask layer 21 include:
  • a first mask layer 21 is formed on the surface of the substrate 10 , and the first mask layer 21 has a plurality of first mask layers extending along the first direction D1 and arranged in parallel along the second direction D2
  • the etching groove 211 is shown in FIG. 2E and FIG. 2F, and FIG. 2F is a schematic cross-sectional view along the AB direction of FIG. 2E;
  • the second mask layer 22 is patterned to form a plurality of annular second etching grooves 221, and the plurality of annular second etching grooves 221 are along the first direction D1 and the second direction D2 Arranged in an array, as shown in FIG. 2J, FIG. 2K and FIG. 2L, FIG. 2K implements the cross-sectional schematic diagram of FIG. 2J along the AB direction, and FIG. 2L is the cross-sectional schematic diagram of FIG. 2K along the CD direction;
  • FIG. 2N is a schematic cross-sectional view of FIG. 2M along the AB direction
  • FIG. 2O is a cross-sectional schematic view of FIG. 2M along the CD direction.
  • the first mask layer 21 is formed on the surface of the substrate 10 , and a patterned first photoresist layer 20 is formed on the surface of the first mask layer 21 .
  • the resist layer 20 has a plurality of first etching windows 201 penetrating the first photoresist layer 20 in a direction perpendicular to the surface of the substrate 10 , and the plurality of first etching windows 201 are along the second
  • the directions D2 are arranged in parallel, and each of the first etching windows 201 extends along the first direction D1 , as shown in FIGS. 2A and 2B
  • FIG. 2B is a schematic cross-sectional view along the AB direction of FIG. 2A .
  • the first mask layer 21 is etched downward along the first etching window 201 , and a plurality of the first etching grooves 211 are formed in the first mask layer 21 .
  • the first etching grooves 211 are arranged in parallel along the second direction D2, and each of the first etching grooves 211 extends along the first direction D1, as shown in FIG. 2C and FIG. 2D , and FIG. 2D is a diagram of Schematic cross-section of 2C along the AB direction.
  • FIGS. 2E and 2F are obtained, and FIG. 2F is a schematic cross-sectional view of FIG. 2E along the AB direction.
  • the material of the first mask layer 21 may be silicon nitride, silicon oxide or carbon. There should be a high etching selectivity ratio between the first mask layer 21 and the substrate 10, for example, the etching selectivity ratio between the first mask layer 21 and the substrate 10 is greater than 3 .
  • the CD direction is parallel to the first direction D1
  • the AB direction is parallel to the third direction D3.
  • a second mask layer 22 that fills the first etching groove 211 and covers the surface of the first mask layer 21 is formed. There should be a high etching selectivity ratio between the second mask layer 22 and the first mask layer 21 for subsequent selective etching.
  • a patterned second photoresist layer 23 is formed on the surface of the second mask layer 22, and the second photoresist layer 23 has an annular second etching window 231, as shown in FIG. 2G , FIG. 2H and FIG. 2I, FIG. 2H is a schematic cross-sectional view of FIG. 2G along the AB direction, and FIG. 2I is a cross-sectional schematic view of FIG. 2G along the CD direction.
  • the second etching window 231 is located in the first etching groove 211 along the projection of the direction perpendicular to the surface of the substrate 10 .
  • the second mask layer 22 is etched along the second etching window 231 , a second etching groove 221 is formed in the second mask layer 22 , and after the second photoresist layer 23 is removed,
  • FIGS. 2J , 2K and 2L are obtained.
  • FIG. 2K is a schematic cross-sectional view of FIG. 2J along the AB direction
  • FIG. 2L is a cross-sectional schematic view of FIG. 2J along the CD direction.
  • the plurality of second etching grooves 221 are arranged in an array along the first direction D1 and the second direction D2, which means that the plurality of second etching grooves 221 are arranged in the first direction D1 and the second direction D2.
  • the planes formed by the second direction D2 are arranged in a two-dimensional array. For example, a plurality of the second etching grooves 221 are arranged in parallel along the first direction D1 to form a row of the second etching grooves 221; a plurality of the second etching grooves 221 are arranged along the second direction D2 Arranged in parallel to form a row of the second etching grooves 221 .
  • the first mask layer 21 is etched downward along the second etching groove 221 and then the second mask layer 22 is removed to form a plurality of first etchings in the first mask layer 221 structure and a plurality of second etched structures.
  • FIG. 2N is a schematic cross-sectional view of FIG. 2M along the AB direction
  • FIG. 2O is a cross-sectional schematic view of FIG. 2M along the CD direction.
  • a part of the second trench structure 25 communicates with the first trench structure 24 to form a communication trench 251. Due to the influence of the etch loading effect, the The extension depth of the communication trench 251 inside the substrate 10 is greater than the extension depth of other partial regions of the second trench structure 25 inside the substrate 10 .
  • a first isolation structure 27 is formed in the first trench structure 24, and a second isolation structure 28 is formed in the second trench structure 25, as shown in FIG. 2P, FIG. 2Q and FIG. 2R,
  • FIG. 2Q is a schematic cross-sectional view of FIG. 2P along the AB direction
  • FIG. 2R is a cross-sectional schematic view of FIG. 2P along the CD direction.
  • the specific steps of forming the first isolation structure 27 in the first trench structure 24 and forming the second isolation structure 28 in the second trench structure 25 include:
  • Dielectric material is filled in the first trench structure 24 and the second trench structure 25 , and the first isolation structure 27 and the second isolation structure 28 are formed at the same time.
  • the active regions 26 are arranged as shown in FIGS. 2P, 2Q and 2R.
  • the active regions 26 arranged in an array along the first direction D1 and the second direction D2 refer to a plurality of the active regions 26 formed in the first direction D1 and the second direction D2 It is arranged in a two-dimensional array in the plane.
  • the dielectric constant value of the dielectric material may be less than 3 (eg, silicon oxide material) to isolate leakage between adjacent active regions 26 and further alleviate electrical coupling between word lines and adjacent active regions effect.
  • Step S14 forming a word line 29 extending along the third direction D3 in the substrate 10, the word line 29 at least passing through the first isolation structure 27 and the second isolation structure 28, the
  • the third direction D3 is parallel to the surface of the substrate 10 and intersects both the first direction D1 and the second direction D2, as shown in FIG. 2S, FIG. 2T and FIG. 2U,
  • FIG. 2T is the direction AB in FIG. 2S 2U is a schematic cross-sectional view of FIG. 2S along the EF direction.
  • the active region inside the substrate 10 may also be doped, for example, doping elements such as boron to form a channel region, doping elements such as phosphorus to form LDD (lightly doped) Drain region), doped with arsenic and other elements to form a shallow junction.
  • doping elements such as boron to form a channel region
  • doping elements such as phosphorus to form LDD (lightly doped) Drain region
  • arsenic and other elements to form a shallow junction for example, doping elements such as boron to form a channel region, doping elements such as phosphorus to form LDD (lightly doped) Drain region), doped with arsenic and other elements to form a shallow junction.
  • the specific steps of forming the word lines 29 extending along the third direction D3 in the substrate 10 include:
  • the first isolation structure 27 , the second isolation structure 28 and the active region 26 are etched along the third direction D3 to form through the first isolation structure 27 , all the the second isolation structure 28 and the third trench 31 of the active region 26;
  • the third trench 31 is filled to form the word line 29 .
  • a third trench 31 extending along the third direction D3 is formed.
  • a gate dielectric layer 32 covering the inner wall of the third trench 31 and a word line 29 covering the surface of the gate dielectric layer 32 and filling the third trench 31 are formed.
  • the material of the diffusion barrier layer may be, but not limited to, TiN.
  • an insulating dielectric layer 30 covering the word lines 29 is formed.
  • the first isolation structure 27 and the second isolation structure 28 together constitute a shallow trench isolation structure for isolating adjacent active regions, and the annular first isolation structure 27 is added , the charge coupling effect between the word line 29 and the adjacent active region 26 is reduced.
  • the trench width of the first trench structure 24 along the first direction D1 is smaller than the trench width of the second trench structure 25 along the second direction D2.
  • the first trench structure 24 is used for isolating two adjacent active regions 26 arranged along the first direction D1
  • the second trench structure 25 is used for isolating the two adjacent active regions 26 along the second direction D1.
  • Two adjacent rows of the active regions 26 are arranged in the direction D2 (each row of the active regions 26 includes a plurality of the active regions 26 arranged in parallel along the first direction D1 ).
  • Making the trench width of the first trench structure 24 along the first direction D1 smaller than the trench width of the second trench structure 25 along the second direction D2 can effectively prevent the trench along the second direction Signal crosstalk between two adjacent rows of the active regions 26 arranged in D2.
  • the inner diameter Z3 of the annular first trench structure 24 (see FIG. 2T ) is 20 nm ⁇ 80 nm.
  • the second isolation structure 28 includes a first sub-isolation portion 281 and a second sub-isolation portion 282, and the first sub-isolation portion 281 is located in two parallelly arranged sub-isolation portions 281 along the second direction D2. Between the first isolation structures 24, the second sub-isolation portion 282 is located between the two active regions 26 arranged in parallel along the second direction D2;
  • the extension depth Z1 of the first sub-isolation portion 281 inside the substrate 10 is greater than the extension depth Z2 of the second sub-isolation portion 282 inside the substrate 10 , see FIGS. 2P and 2Q .
  • the extension depth of the first sub-isolation portion 281 inside the substrate 10 is 200 nm ⁇ 500 nm.
  • the extension depth of the second sub-isolation portion 282 inside the substrate 10 is 100 nm ⁇ 300 nm.
  • capacitor contacts 35 and bit line contacts 34 may also be formed in the active region. Wherein, two capacitor contacts 35 and one bit line contact 34 are formed in each of the active regions 26 , and the two capacitor contacts 35 are distributed along the same active region 26 along the At opposite ends of the first direction D1 , the bit line contact portion 34 is located between the two capacitor contact portions 35 .
  • a plurality of bit lines 33 arranged in parallel along the third direction D3 are formed over the substrate 10, each of the bit lines 33 extends along the fourth direction D4, and each of the bit lines The contact portion 34 is electrically connected to one of the bit lines 33 to obtain the structure shown in FIG. 2V.
  • the present embodiment also provides a semiconductor structure.
  • the semiconductor structure provided by this specific embodiment can be formed by the method shown in FIG. 1 and FIGS. 2A-2V .
  • the schematic diagrams of the semiconductor structure provided by this specific embodiment can be referred to FIG. 2P-FIG. 2V.
  • the semiconductor structure provided by this specific embodiment includes:
  • a plurality of active regions 26, the plurality of the active regions 26 are arranged in an array inside the substrate 10 along a first direction D1 and a second direction D2, the first direction D1 and the second direction D2 are parallel to the surface of the substrate 10, and the first direction D1 and the second direction D2 intersect;
  • first isolation structure 27 and a second isolation structure 28 located in the substrate 10
  • first isolation structure 27 is located between the two active regions 26 arranged in parallel along the first direction D1
  • the first isolation structure 27 is annular, a plurality of the second isolation structures 28 are arranged in parallel along the second direction D2, and the second isolation structures 28 are arranged in parallel along the second direction D2 Between two adjacent rows of the active regions 26, the first isolation structure 27 communicates with the second isolation structure 28;
  • word lines 29 extending along a third direction D3 parallel to the surface of the substrate 10 and passing through at least the first isolation structure 27 and the second isolation structure 28 It intersects with both the first direction D1 and the second direction D2.
  • the width of the first isolation structure 27 along the first direction D1 is smaller than the width of the second isolation structure 28 along the second direction D2.
  • the inner diameter Z3 of the annular first isolation structure 27 is 20 nm ⁇ 80 nm.
  • the second isolation structure 28 includes a first sub-isolation portion 281 and a second sub-isolation portion 282, and the first sub-isolation portion 281 is located in two parallelly arranged sub-isolation portions 281 along the second direction D2. Between the first isolation structures 24, the second sub-isolation portion 282 is located between the two active regions 26 arranged in parallel along the second direction D2;
  • the extension depth Z1 of the first sub-isolation portion 281 inside the substrate 10 is greater than the extension depth Z2 of the second sub-isolation portion 282 inside the substrate 10 .
  • the extension depth of the first sub-isolation portion 281 inside the substrate 10 is 200 nm ⁇ 500 nm.
  • the extension depth of the second sub-isolation portion 282 inside the substrate 10 is 100 nm ⁇ 300 nm.
  • the materials of the first isolation structure 27 and the second isolation structure 28 are the same.
  • both are silicon oxides.
  • the dielectric constant values of the materials of the first isolation structure 27 and the material of the second isolation structure 28 are both less than 3.
  • a plurality of the word lines 29 are arranged in parallel along a fourth direction D4, and the fourth direction D4 is parallel to the surface of the substrate 10 and perpendicular to the third direction D3;
  • Two adjacent word lines 29 pass through the same active region 26 .
  • the semiconductor structure further includes:
  • the two capacitive contact portions 35 located in the same active region 26, the two capacitive contact portions 35 are distributed at opposite ends of the same active region 26 along the first direction D1;
  • bit line contact portion 34 located in the active region 26, and the bit line contact portion 34 is located between the two capacitor contact portions 35;
  • a plurality of bit lines 33 are arranged in parallel along the third direction D3, each of the bit lines 33 extends along the fourth direction D4, and each of the bit line contact portions 34 is electrically connected to one of the bit lines 33. connect.
  • the substrate is divided into multiple arrays arranged in an array along the first direction and the second direction by the first isolation structure and the second isolation structure located in the substrate.
  • active regions the first isolation structure is located between two of the active regions arranged in parallel along the first direction, the first isolation structure is annular, and a plurality of the second isolation structures
  • the structures are arranged in parallel along the second direction, and the second isolation structures are located between two adjacent rows of the active regions that are arranged in parallel along the second direction, and the first isolation structures are connected to all the active regions.
  • the second isolation structure is connected, that is, by changing the arrangement of the active region and the isolation structure inside the substrate, the coupling effect between the word line and the adjacent active region is reduced, and the electrical performance of the semiconductor structure is improved.

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Abstract

本申请提供的半导体结构的形成方法包括：于衬底内形成第一沟槽结构和第二沟槽结构，第一沟槽结构位于沿第一方向排布的两个有源区之间，第二沟槽结构位于沿第二方向排布的相邻的两个有源区之间，第一沟槽结构与第二沟槽结构连通；形成第一隔离结构和第二隔离结构；形成字线。本申请降低了字线与邻近有源区之间的耦合效应。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2021年3月24日递交的中国专利申请号202110313866.8、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
在当前的DRAM结构中，衬底内部具有呈阵列排布的多个有源区，且相邻的有源区之间通过浅沟槽隔离结构相互隔离。在沿字线的延伸方向上，浅沟槽隔离结构与有源区交替排布。所述衬底内部浅沟槽隔离结构的尺寸均相同，且同一条字线位于所述浅沟槽隔离结构中的深度大于位于所述有源区中的深度，这就导致字线位于浅沟槽隔离结构中的部分和与其相邻的有源区的耦合效应比较明显，从而影响了DRAM的电性能。
因此，如何降低字线与有源区之间的耦合效应，改善半导体结构的电性能，是当前亟待解决的技术问题。
发明内容
本申请一些实施例提供了一种半导体结构及其形成方法，用于解决半导体结构内部字线与有源区之间耦合效应较大的问题，以改善半导体结构的电性能。
根据一些实施例，本申请提供了一种半导体结构的形成方法，包括如下步骤：
提供衬底；
于所述衬底内形成多个第一沟槽结构和多个第二沟槽结构，将所述衬底分隔为沿第一方向和第二方向呈阵列排布的多个有源区，所述第一沟槽结构位于沿所述第一方向平行排布的两个所述有源区之间，且所述第一沟槽结构呈环形，多个所述第二沟槽结构沿所述第二方向平行排布，且所述第二沟槽结构位于沿所述第二方向平行排布的相邻的两行所述有源区之间，所述第一沟槽结构与所述第二沟槽结构连通，所述第一方向和所述第二方向均平行于所述衬底表面，且所述第一方向与所述第二方向相交；
于所述第一沟槽结构内形成第一隔离结构、并于所述第二沟槽结构内形成第二隔离结构；
于所述衬底内形成沿第三方向延伸的字线，所述字线至少穿过所述第一隔离结构和所述第二隔离结构，所述第三方向平行于所述衬底表面且与所述第一方向和所述第二方向均相交。
根据另一些实施例，本申请还提供了一种半导体结构，包括：
衬底；
多个有源区，多个所述有源区在所述衬底内部沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均平行于所述衬底表面，且所述第一方向与所述第二方向相交；
位于所述衬底内的第一隔离结构和第二隔离结构，所述第一隔离结构位于沿所述第一方向平行排布的两个所述有源区之间，且所述第一隔离结构呈环形，多个所述第二隔离结构沿所述第二方向平行排布，且所述第二隔离结构位于沿所述第二方向平行排布的相邻的两行所述有源区之间，所述第一隔离结构与所述第二隔离结构连通；
字线，所述字线沿第三方向延伸且至少穿过所述第一隔离结构和所述第二隔离结构，所述第三方向平行于所述衬底表面且与所述第一方向和所述第二方向均相交。
本申请一些实施例提供的半导体结构及其形成方法，通过位于衬底内的第一隔离结构和第二隔离结构将所述衬底内划分成沿第一方向和第二方向呈阵 列排布的多个有源区，且所述第一隔离结构位于沿所述第一方向平行排布的两个所述有源区之间，且所述第一隔离结构呈环形，多个所述第二隔离结构沿所述第二方向平行排布，且所述第二隔离结构位于沿所述第二方向平行排布的相邻的两行所述有源区之间，所述第一隔离结构与所述第二隔离结构连通，即通过改变所述衬底内部有源区与隔离结构的排布方式，降低了字线与邻近有源区之间的耦合效应，改善了半导体结构的电性能。
附图说明
附图1是本申请具体实施方式中半导体结构的形成方法流程图；
附图2A-2V是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本申请具体实施方式中半导体结构的形成方法流程图，附图2A-2V是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。本具体实施方式中所述的半导体结构可以是但不限于DRAM。如图1、图2A-图2V所示，本具体实施方式提供的半导体结构的形成方法，包括如下步骤：
步骤S11，提供衬底10，如图2B所示。
具体来说，所述衬底10可以是但不限于硅衬底或者多晶硅衬底，本具体实施方式中以所述衬底10为硅衬底为例进行说明，所述衬底10用于支撑在其上的器件结构。在其他示例中，所述衬底10可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底10可以为单层衬底，也可以为由多个半导体层叠置构成的多层衬底。
步骤S12，于所述衬底10内形成多个第一沟槽结构24和多个第二沟槽结构25，将所述衬底10分隔为沿第一方向D1和第二方向D2呈阵列排布的多个有源区26，所述第一沟槽结构24位于沿所述第一方向D1平行排布的两个所述有源区26之间，且所述第一沟槽结构24呈环形，多个所述第二沟槽结构25 沿所述第二方向D2平行排布，且所述第二沟槽结构25位于沿所述第二方向D2平行排布的相邻的两行所述有源区26之间，所述第一沟槽结构24与所述第二沟槽结构25连通，所述第一方向D1和所述第二方向D2均平行于所述衬底10表面，且所述第一方向D1与所述第二方向D2相交，如图2M-图2R所示。
在一些实施例中，于所述衬底10内形成多个第一沟槽结构24和多个第二沟槽结构25的具体步骤包括：
形成图案化的第一掩模层21，所述第一掩模层21中具有多个第一刻蚀结构和多个第二刻蚀结构，多个所述第一刻蚀结构均呈环形且沿所述第一方向D1和所述第二方向D2呈阵列排布，所述第二刻蚀结构呈沿所述第一方向D1延伸的条形结构，且多个所述第二刻蚀结构沿所述第二方向D2平行排布，所述第一刻蚀结构与所述第二刻蚀结构连通；
沿所述第一刻蚀结构和所述第二刻蚀结构刻蚀所述衬底10，于所述衬底10内形成多个第一沟槽结构24和多个第二沟槽结构25。
在一些实施例中，形成图案化的第一掩模层21的具体步骤包括：
形成第一掩模层21于所述衬底10表面，所述第一掩模层21中具有多条沿所述第一方向D1延伸、且沿所述第二方向D2平行排布的第一刻蚀槽211，如图2E和图2F所示，图2F是图2E沿AB方向的截面示意图；
回填所述第一刻蚀槽211，形成覆盖所述第一掩模层21的第二掩模层22；
图案化所述第二掩模层22，形成多个环形的第二刻蚀槽221，且多个环形的所述第二刻蚀槽221沿所述第一方向D1和所述第二方向D2呈阵列排布，如图2J、图2K和图2L所示，图2K实施图2J沿AB方向的截面示意图，图2L是图2K沿CD方向的截面示意图；
沿所述第二刻蚀槽221刻蚀所述第一掩模层21、并去除所述第二掩模层22，形成图案化的所述第一掩模层21，如图2M、图2N和图2O所示，图2N是图2M沿AB方向的截面示意图，图2O是图2M沿CD方向的截面示意图。
具体来说，首先，于所述衬底10表面形成所述第一掩模层21，并于所述第一掩模层21表面形成图案化的第一光阻层20，所述第一光阻层20中具有多 个沿垂直于所述衬底10表面的方向贯穿所述第一光阻层20的第一刻蚀窗口201，多个所述第一刻蚀窗口201沿所述第二方向D2平行排布，且每一所述第一刻蚀窗口201沿所述第一方向D1延伸，如图2A和图2B所示，图2B是图2A沿AB方向的截面示意图。之后，沿所述第一刻蚀窗口201向下刻蚀所述第一掩模层21，于所述第一掩模层21中形成多个所述第一刻蚀槽211，多个所述第一刻蚀槽211沿所述第二方向D2平行排布，且每一个所述第一刻蚀槽211沿所述第一方向D1延伸，如图2C和图2D所示，图2D是图2C沿AB方向的截面示意图。去除所述第一光阻层20之后，得到如图2E和图2F所示的结构，图2F是图2E沿AB方向的截面示意图。所述第一掩模层21的材料可以为氮化硅、氧化硅或者碳。所述第一掩模层21与所述衬底10之间应具有较高的刻蚀选择比，例如所述第一掩模层21与所述衬底10之间的刻蚀选择比大于3。所述CD方向与所述第一方向D1平行，所述AB方向与第三方向D3平行。
接着，形成填充满所述第一刻蚀槽211并覆盖所述第一掩模层21表面的第二掩模层22。所述第二掩模层22与所述第一掩模层21之间应具有较高的刻蚀选择比，以便后续进行选择性刻蚀。然后，形成图案化的第二光阻层23于所述第二掩模层22表面，所述第二光阻层23中具有环形的第二刻蚀窗口231，如图2G、图2H和图2I所示，图2H是图2G沿AB方向的截面示意图，图2I是图2G沿CD方向的截面示意图。所述第二刻蚀窗口231沿垂直于所述衬底10表面方向的投影位于所述第一刻蚀槽211中。沿所述第二刻蚀窗口231刻蚀所述第二掩模层22，在所述第二掩模层22中形成第二刻蚀槽221，在去除所述第二光阻层23之后，得到如图2J、图2K和图2L所示的结构，图2K是图2J沿AB方向的截面示意图，图2L是图2J沿CD方向的截面示意图。
多个所述第二刻蚀槽221沿所述第一方向D1和所述第二方向D2呈阵列排布是指，多个所述第二刻蚀槽221在所述第一方向D1和所述第二方向D2形成的平面内呈二维阵列排布。例如多个所述第二刻蚀槽221沿所述第一方向D1平行排布，形成一行所述第二刻蚀槽221；多个所述第二刻蚀槽221沿所述第二方向D2平行排布，形成一列所述第二刻蚀槽221。
沿所述第二刻蚀槽221向下刻蚀所述第一掩模层21之后去除所述第二掩模层22，以在所述第一掩模层221中形成多个第一刻蚀结构和多个第二刻蚀结构。继续沿所述第一刻蚀结构和所述第二刻蚀结构刻蚀所述衬底10，于所述衬底10内形成多个第一沟槽结构24和多个第二沟槽结构25，如图2M、图2N和图2O所示，图2N是图2M沿AB方向的截面示意图，图2O是图2M沿CD方向的截面示意图。如图2M和图2N所示，所述第二沟槽结构25中的部分区域与所述第一沟槽结构24连通，形成连通沟槽251，由于受刻蚀载入效应的影响，所述连通沟槽251在所述衬底10内部的延伸深度大于所述第二沟槽结构25中其他部分区域在所述衬底10内部的延伸深度。
步骤S13，于所述第一沟槽结构24内形成第一隔离结构27、并于所述第二沟槽结构25内形成第二隔离结构28，如图2P、图2Q和图2R所示，图2Q是图2P沿AB方向的截面示意图，图2R是图2P沿CD方向的截面示意图。
在一些实施例中，于所述第一沟槽结构24内形成第一隔离结构27、并于所述第二沟槽结构25内形成第二隔离结构28的具体步骤包括：
填充介电材料于所述第一沟槽结构24内和所述第二沟槽结构25内，同时形成所述第一隔离结构27和所述第二隔离结构28。
具体来说，在填充所述介电材料，并去除所述第一掩模层21之后，于所述衬底10内形成多个沿所述第一方向D1和所述第二方向D2呈阵列排布的有源区26，如图2P、图2Q和图2R所示。沿所述第一方向D1和所述第二方向D2呈阵列排布的有源区26是指，多个所述有源区26在所述第一方向D1和所述第二方向D2形成的平面内呈二维阵列排布。所述介电材料的介电常数值可以小于3(例如氧化硅材料)，以隔离相邻所述有源区26之间的漏电，并进一步减轻字线与邻近有源区之间的电耦合效应。
步骤S14，于所述衬底10内形成沿所述第三方向D3延伸的字线29，所述字线29至少穿过所述第一隔离结构27和所述第二隔离结构28，所述第三方向D3平行于所述衬底10表面且与所述第一方向D1和所述第二方向D2均相交，如图2S、图2T和图2U所示，图2T是图2S沿AB方向的截面示意图，图2U是图2S沿EF方向的截面示意图。
在形成所述字线29之前，还可以对所述衬底10内部的所述有源区进行掺杂，例如掺杂硼等元素形成沟道区，掺杂磷等元素形成LDD(轻掺杂漏区)，掺杂砷等元素形成浅结(shallow juction)。
在一些实施例中，于所述衬底10内形成沿所述第三方向D3延伸的字线29的具体步骤包括：
沿所述第三方向D3刻蚀所述第一隔离结构27、所述第二隔离结构28和所述有源区26，形成沿所述第三方向D3贯穿所述第一隔离结构27、所述第二隔离结构28和所述有源区26的第三沟槽31；
填充所述第三沟槽31，形成所述字线29。
具体来说，在形成所述第一隔离结构27和所述第二隔离结构28之后，回刻蚀所述第一隔离结构27、所述第二隔离结构28、并同时刻蚀所述有源区26，形成沿所述第三方向D3延伸的第三沟槽31。之后，形成覆盖所述第三沟槽31内壁的栅介质层32、覆盖所述栅介质层32表面并填充满所述第三沟槽31的字线29。本领域技术人员还可以根据实际需要在所述栅介质层32与所述字线29之间形成扩散阻挡层。所述扩散阻挡层的材料可以是但不限于TiN。之后，形成覆盖于所述字线29上的绝缘介电层30。
在本具体实施方式中，所述第一隔离结构27和所述第二隔离结构28共同构成用于隔离相邻有源区的浅沟槽隔离结构，环形的所述第一隔离结构27的加入，减小了所述字线29与邻近的所述有源区26之间的电荷耦合效应。
在一些实施例中，所述第一沟槽结构24沿所述第一方向D1的沟槽宽度小于所述第二沟槽结构25沿所述第二方向D2的沟槽宽度。
所述第一沟槽结构24用于隔离沿所述第一方向D1排布、且相邻的两个所述有源区26，所述第二沟槽结构25用于隔离沿所述第二方向D2排列、且相邻的两行所述有源区26(每行所述有源区26包括沿所述第一方向D1平行排列的多个所述有源区26)。将所述第一沟槽结构24沿所述第一方向D1的沟槽宽度小于所述第二沟槽结构25沿所述第二方向D2的沟槽宽度，可以有效避免沿所述第二方向D2排布、且相邻的两行所述有源区26之间的信号串扰。
在一些实施例中，环形的所述第一沟槽结构24的内圈直径Z3(参见图2T) 为20nm～80nm。
在一些实施例中，所述第二隔离结构28包括第一子隔离部分281和第二子隔离部分282，所述第一子隔离部分281位于沿所述第二方向D2平行排布的两个所述第一隔离结构24之间，所述第二子隔离部分282位于沿所述第二方向D2平行排列的两个所述有源区26之间；
由于在形成所述第一子隔离部分281和所述第二子隔离部分282时，所述第一子隔离部分281的掩膜开口尺寸大于所述第二子隔离部分282的掩膜开口尺寸，因此，所述第一子隔离部分281在所述衬底10内部的延伸深度Z1大于所述第二子隔离部分282在所述衬底10内部的延伸深度Z2，参见图2P和图2Q。
在一些实施例中，所述第一子隔离部分281在所述衬底10内部的延伸深度为200nm～500nm。
在一些实施例中，所述第二子隔离282部分在所述衬底10内部的延伸深度为100nm～300nm。
在形成所述字线29之后，还可以在所述有源区内形成电容接触部35和位线接触部34。其中，每个所述有源区26中形成两个所述电容接触部35和一个所述位线接触部34，两个所述电容接触部35分布于同一所述有源区26沿所述第一方向D1的相对两端，所述位线接触部34位于两个所述电容接触部35之间。接着，再在所述衬底10上方形成多条沿所述第三方向D3平行排布的位线33，每条所述位线33沿所述第四方向D4延伸，每个所述位线接触部34与一条所述位线33电连接，得到如图2V所示的结构。
不仅如此，本具体实施方式还提供了一种半导体结构。本具体实施方式提供的半导体结构可以采用如图1、图2A-图2V所示的方法形成。本具体实施方式提供的半导体结构的示意图可以参见图2P-图2V。如图2P-图2V所示，本具体实施方式提供的半导体结构，包括：
衬底10；
多个有源区26，多个所述有源区26在所述衬底10内部沿第一方向D1和第二方向D2呈阵列排布，所述第一方向D1和所述第二方向D2均平行于所述 衬底10表面，且所述第一方向D1与所述第二方向D2相交；
位于所述衬底10内的第一隔离结构27和第二隔离结构28，所述第一隔离结构27位于沿所述第一方向D1平行排布的两个所述有源区26之间，且所述第一隔离结构27呈环形，多个所述第二隔离结构28沿所述第二方向D2平行排布，且所述第二隔离结构28位于沿所述第二方向D2平行排布的相邻的两行所述有源区26之间，所述第一隔离结构27与所述第二隔离结构28连通；
字线29，所述字线29沿第三方向D3延伸且至少穿过所述第一隔离结构27和所述第二隔离结构28，所述第三方向D3平行于所述衬底10表面且与所述第一方向D1和所述第二方向D2均相交。
在一些实施例中，所述第一隔离结构27沿所述第一方向D1的宽度小于所述第二隔离结构28沿所述第二方向D2的宽度。
在一些实施例中，环形的所述第一隔离结构27的内圈直径Z3为20nm～80nm。
在一些实施例中，所述第二隔离结构28包括第一子隔离部分281和第二子隔离部分282，所述第一子隔离部分281位于沿所述第二方向D2平行排布的两个所述第一隔离结构24之间，所述第二子隔离部分282位于沿所述第二方向D2平行排列的两个所述有源区26之间；
所述第一子隔离部分281在所述衬底10内部的延伸深度Z1大于所述第二子隔离部分282在所述衬底10内部的延伸深度Z2。
在一些实施例中，所述第一子隔离部分281在所述衬底10内部的延伸深度为200nm～500nm。
在一些实施例中，所述第二子隔离282部分在所述衬底10内部的延伸深度为100nm～300nm。
在一些实施例中，所述第一隔离结构27和所述第二隔离结构28的材料相同。例如，均为氧化硅。
在一些实施例中，所述第一隔离结构27和所述第二隔离结构28的材料的介电常数值均小于3。
在一些实施例中，多条所述字线29沿第四方向D4平行排布，所述第四方 向D4平行于所述衬底10表面且与所述第三方向D3垂直；
相邻的两条所述字线29穿过同一所述有源区26。
在一些实施例中，所述半导体结构还包括：
位于同一所述有源区26内的两个电容接触部35，两个所述电容接触部35分布于同一所述有源区26沿所述第一方向D1的相对两端；
位于所述有源区26内的位线接触部34，所述位线接触部34位于两个所述电容接触部35之间；
多条沿所述第三方向D3平行排布的位线33，每条所述位线33沿所述第四方向D4延伸，每个所述位线接触部34与一条所述位线33电连接。
本具体实施方式提供的半导体结构及其形成方法，通过位于衬底内的第一隔离结构和第二隔离结构将所述衬底内划分成沿第一方向和第二方向呈阵列排布的多个有源区，且所述第一隔离结构位于沿所述第一方向平行排布的两个所述有源区之间，且所述第一隔离结构呈环形，多个所述第二隔离结构沿所述第二方向平行排布，且所述第二隔离结构位于沿所述第二方向平行排布的相邻的两行所述有源区之间，所述第一隔离结构与所述第二隔离结构连通，即通过改变所述衬底内部有源区与隔离结构的排布方式，降低了字线与邻近有源区之间的耦合效应，改善了半导体结构的电性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种半导体结构的形成方法，包括如下步骤：
    提供衬底；
    于所述衬底内形成多个第一沟槽结构和多个第二沟槽结构，将所述衬底分隔为沿第一方向和第二方向呈阵列排布的多个有源区，所述第一沟槽结构位于沿所述第一方向平行排布的两个所述有源区之间，且所述第一沟槽结构呈环形，多个所述第二沟槽结构沿所述第二方向平行排布，且所述第二沟槽结构位于沿所述第二方向平行排布的相邻的两行所述有源区之间，所述第一沟槽结构与所述第二沟槽结构连通，所述第一方向和所述第二方向均平行于所述衬底表面，且所述第一方向与所述第二方向相交；
    于所述第一沟槽结构内形成第一隔离结构、并于所述第二沟槽结构内形成第二隔离结构；
    于所述衬底内形成沿第三方向延伸的字线，所述字线至少穿过所述第一隔离结构和所述第二隔离结构，所述第三方向平行于所述衬底表面且与所述第一方向和所述第二方向均相交。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，于所述衬底内形成多个第一沟槽结构和多个第二沟槽结构的具体步骤包括：
    形成图案化的第一掩模层，所述第一掩模层中具有多个第一刻蚀结构和多个第二刻蚀结构，多个所述第一刻蚀结构均呈环形且沿所述第一方向和所述第二方向呈阵列排布，所述第二刻蚀结构呈沿所述第一方向延伸的条形结构，且多个所述第二刻蚀结构沿所述第二方向平行排布，所述第一刻蚀结构与所述第二刻蚀结构连通；
    沿所述第一刻蚀结构和所述第二刻蚀结构刻蚀所述衬底，于所述衬底内形成多个第一沟槽结构和多个第二沟槽结构。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，形成图案化的第一掩模层的具体步骤包括：
    形成第一掩模层于所述衬底表面，所述第一掩模层中具有多条沿所述第一方向延伸、且沿所述第二方向平行排布的第一刻蚀槽；
    回填所述第一刻蚀槽，形成覆盖所述第一掩模层的第二掩模层；
    图案化所述第二掩模层，形成多个环形的第二刻蚀槽，且多个环形的所述第二刻蚀槽沿所述第一方向和所述第二方向呈阵列排布；
    沿所述第二刻蚀槽刻蚀所述第一掩模层、并去除所述第二掩模层，形成图案化的所述第一掩模层。
  4. 根据权利要求1所述的半导体结构的形成方法，其中，所述第一沟槽结构沿所述第一方向的沟槽宽度小于所述第二沟槽结构沿所述第二方向的沟槽宽度。
  5. 根据权利要求1所述的半导体结构的形成方法，其中，环形的所述第一沟槽结构的内圈直径为20nm～80nm。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，所述第二隔离结构包括第一子隔离部分和第二子隔离部分，所述第一子隔离部分位于沿所述第二方向平行排布的两个所述第一隔离结构之间，所述第二子隔离部分位于沿所述第二方向平行排列的两个所述有源区之间；
    所述第一子隔离部分在所述衬底内部的延伸深度大于所述第二子隔离部分在所述衬底内部的延伸深度。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述第一子隔离部分在所述衬底内部的延伸深度为200nm～500nm。
  8. 根据权利要求6所述的半导体结构的形成方法，其中，所述第二子隔离部分在所述衬底内部的延伸深度为100nm～300nm。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，于所述第一沟槽结构内形成第一隔离结构、并于所述第二沟槽结构内形成第二隔离结构的具体步骤包括：
    填充介电材料于所述第一沟槽结构内和所述第二沟槽结构内，同时形成所述第一隔离结构和所述第二隔离结构。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，于所述衬底内形成沿所述第三方向延伸的字线的具体步骤包括：
    沿所述第三方向刻蚀所述第一隔离结构、所述第二隔离结构和所述有源区，形成沿所述第三方向贯穿所述第一隔离结构、所述第二隔离结构和所述有源区的第三沟槽；
    填充所述第三沟槽，形成所述字线。
  11. 一种半导体结构，包括：
    衬底；
    多个有源区，多个所述有源区在所述衬底内部沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均平行于所述衬底表面，且所述第一方向与所述第二方向相交；
    位于所述衬底内的第一隔离结构和第二隔离结构，所述第一隔离结构位于沿所述第一方向平行排布的两个所述有源区之间，且所述第一隔离结构呈环形，多个所述第二隔离结构沿所述第二方向平行排布，且所述第二隔离结构位于沿所述第二方向平行排布的相邻的两行所述有源区之间，所述第一隔离结构与所述第二隔离结构连通；
    字线，所述字线沿第三方向延伸且至少穿过所述第一隔离结构和所述第二隔离结构，所述第三方向平行于所述衬底表面且与所述第一方向和所述第二方向均相交。
  12. 根据权利要求11所述的半导体结构，其中，所述第一隔离结构沿所述第一方向的宽度小于所述第二隔离结构沿所述第二方向的宽度。
  13. 根据权利要求11所述的半导体结构，其中，环形的所述第一隔离结构的内圈直径为20nm～80nm。
  14. 根据权利要求11所述的半导体结构，其中，所述第二隔离结构包括第一子隔离部分和第二子隔离部分，所述第一子隔离部分位于沿所述第二方向平行排布的两个所述第一隔离结构之间，所述第二子隔离部分位于沿所述第二方向平行排列的两个所述有源区之间；
    所述第一子隔离部分在所述衬底内部的延伸深度大于所述第二子隔离部分在所述衬底内部的延伸深度。
  15. 根据权利要求14所述的半导体结构，其中，所述第一子隔离部分在所述衬底内部的延伸深度为200nm～500nm。
  16. 根据权利要求14所述的半导体结构，其中，所述第二子隔离部分在所述衬底内部的延伸深度为100nm～300nm。
  17. 根据权利要求11所述的半导体结构，其中，所述第一隔离结构和所述第二隔离结构的材料相同。
  18. 根据权利要求11所述的半导体结构，其中，所述第一隔离结构和所述第二隔离结构的材料的介电常数值均小于3。
  19. 根据权利要求11所述的半导体结构，其中，多条所述字线沿第四方向平行排布，所述第四方向平行于所述衬底表面且与所述第三方向垂直；
    相邻的两条所述字线穿过同一所述有源区。
  20. 根据权利要求19所述的半导体结构，其中，还包括：
    位于同一所述有源区内的两个电容接触部，两个所述电容接触部分布于同一所述有源区沿所述第一方向的相对两端；
    位于所述有源区内的位线接触部，所述位线接触部位于两个所述电容接触部之间；
    多条沿所述第三方向平行排布的位线，每条所述位线沿所述第四方向延伸，每个所述位线接触部与一条所述位线电连接。
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