WO2023221177A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023221177A1
WO2023221177A1 PCT/CN2022/096424 CN2022096424W WO2023221177A1 WO 2023221177 A1 WO2023221177 A1 WO 2023221177A1 CN 2022096424 W CN2022096424 W CN 2022096424W WO 2023221177 A1 WO2023221177 A1 WO 2023221177A1
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Prior art keywords
word line
layer
semiconductor
forming
word lines
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PCT/CN2022/096424
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English (en)
French (fr)
Inventor
肖德元
蒋懿
邵光速
苏星松
邱云松
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长鑫存储技术有限公司
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Priority to US17/949,580 priority Critical patent/US20230020173A1/en
Publication of WO2023221177A1 publication Critical patent/WO2023221177A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to semiconductor structures and manufacturing methods thereof.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can at least reduce the coupling effect between adjacent word lines.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming a plurality of semiconductor channels arranged in an array along a first direction and a second direction on the substrate; Forming a plurality of bit lines extending along the first direction, the bit lines being located in the substrate, and each bit line being electrically connected to a plurality of the semiconductor channels arranged along the first direction; A plurality of word lines extending along the second direction are formed, and each word line surrounds part of the side surfaces of the plurality of semiconductor channels arranged along the second direction, wherein in the first direction Two adjacent word lines are arranged at intervals in a direction perpendicular to the surface of the substrate; a sidewall conductive layer is formed, and the sidewall conductive layer is located above one of the two adjacent word lines, And the sidewall conductive layer is arranged on the same layer as the other of the two adjacent word lines.
  • the plurality of semiconductor channels include: a plurality of columns of first channel groups, each column of the first channel group including a plurality of first semiconductor channels arranged along the second direction; a plurality of columns of second channel groups.
  • channel group, each column of the second channel group includes a plurality of second semiconductor channels arranged along the second direction, and the plurality of columns of first channel groups and the plurality of columns of second channel groups are in the first Alternately arranged in one direction;
  • the plurality of word lines include: a plurality of first word lines extending along the second direction, each of the first word lines surrounding a column of all the first channel groups.
  • a plurality of second word lines extending along the second direction, each of the second word lines surrounding part of the side surfaces of the semiconductor channels in a column of the second channel group, and The distance between the bottom surface of the second word line and the substrate surface is greater than the distance between the bottom surface of the first word line and the substrate surface; forming the plurality of word lines includes: forming the first word line ; and forming the second word line.
  • forming the first word line includes: forming a first groove that exposes part of a side surface of the first semiconductor channel; forming a first initial word line, the first initial The word line fills the first groove; the first initial word line is etched back, and the remaining first initial word line serves as the first word line.
  • forming the first groove includes: forming a first spacer layer covering sidewalls of the semiconductor channel spaced along the first direction; forming a mask layer, The mask layer covers the second semiconductor channel and the first spacer layer located on the sidewall of the second semiconductor channel; the first spacer layer is patterned using the mask layer as a mask, to form the first groove.
  • forming the second word line and the sidewall conductive layer simultaneously; forming the second word line and the sidewall conductive layer includes: forming a first capping layer, the first capping layer Located on the top surface of the first word line; forming a first isolation layer, the first isolation layer is located between the adjacent semiconductor channels, and the top surface of the first isolation layer is higher than the first word line The top surface of the line; forming a second sidewall layer, the second sidewall layer covering the sidewall of the first capping layer and the sidewall of the second semiconductor channel; forming a second isolation layer, the second sidewall layer The isolation layer is located on the top surface of the first isolation layer, and one side wall of the second isolation layer is in contact with the second side wall layer covering the side wall of the first cover layer, and the other side wall is in contact with the The second spacer layer contacts the sidewall of the second semiconductor channel; etching back the second spacer layer to form a second groove; forming the second word line and the sidewall conductive layer, so The second word line and
  • forming the second word line further includes forming a second cap layer, the second cap layer being located on a top surface of the second word line.
  • the word line that is closer to the substrate surface among the two adjacent word lines in the first direction is defined as a lower word line, and the two adjacent word lines are defined as a lower word line.
  • the word line that is further away from the substrate surface among the word lines is an upper word line, and the bottom surface of the upper word line is located on a side of the top surface of the lower word line away from the substrate surface, forming a During the process, the distance between the top surface of the lower word line and the bottom surface of the upper word line is controlled to be greater than or equal to 3 nm and less than or equal to 10 nm.
  • the semiconductor channel includes a first doped region, a channel region and a second doped region arranged in sequence, the first doped region is electrically connected to the bit line, the first doped region
  • the doping type of the impurity region, the channel region and the second doping region is the same.
  • forming the plurality of semiconductor channels arranged in an array along the first direction and the second direction on the substrate includes: patterning the substrate to form a pattern along the second direction. A plurality of initial semiconductor channels arranged at intervals along the direction; patterning the plurality of initial semiconductor channels to form the plurality of semiconductor channels arranged at intervals along the first direction and the second direction.
  • the material of the semiconductor channel is silicon, and a silicon metallization process is used to form the plurality of bit lines.
  • another aspect of the present disclosure further provides a semiconductor structure, including: a substrate and a plurality of semiconductor channels arranged in an array along a first direction and a second direction on the substrate; along the A plurality of bit lines extending in the first direction, the bit lines are located in the substrate, and each bit line is electrically connected to a plurality of semiconductor channels arranged along the first direction; along the A plurality of word lines extending in a second direction, each word line surrounding part of the side surfaces of a plurality of semiconductor channels arranged along the second direction, wherein adjacent ones along the first direction
  • the two word lines are spaced apart in a direction perpendicular to the surface of the substrate; a sidewall conductive layer is located above one of the two adjacent word lines, and the The sidewall conductive layer is arranged on the same layer as the other two adjacent word lines.
  • the plurality of semiconductor channels include: a plurality of columns of first channel groups, each column of the first channel group including a plurality of first semiconductor channels arranged along the second direction; a plurality of columns of second channel groups.
  • channel group, each column of the second channel group includes a plurality of second semiconductor channels arranged along the second direction, and the plurality of columns of first channel groups and the plurality of columns of second channel groups are in the first Alternately arranged in one direction;
  • the plurality of word lines include: a plurality of first word lines extending along the second direction, each of the first word lines surrounding a column of all the first channel groups.
  • each first word line is flush, and the top surface of each first word line is flush; the bottom surface of each second word line is flush, and each of the second word lines is flush. The top surface of the second word line is flush.
  • the plurality of first word lines are made of the same material; the plurality of second word lines are made of the same material.
  • the first word line and the second word line are made of different materials.
  • the semiconductor structure further includes: a first capping layer located on a top surface of the first word line; a second capping layer located on the second The top surface of the word line; the side wall conductive layer is arranged in the same layer as the second word line and is located on the side of the first cover layer, and the material of the side wall conductive layer is the same as that in the second word line. Conductive materials are the same.
  • the semiconductor structure further includes: a first isolation layer, the first isolation layer is located between adjacent first word lines and second word lines, and the top surface of the first isolation layer is higher than The top surface of the first word line; a second isolation layer, the second isolation layer is located on the top surface of the first isolation layer, and is also located on the side of the second word line and the side of the second capping layer .
  • the word line that is closer to the substrate surface among the two adjacent word lines in the first direction is defined as a lower word line, and the two adjacent word lines are defined as a lower word line.
  • the word line farther away from the substrate surface is an upper word line, and the bottom surface of the upper word line is located on a side of the top surface of the lower word line away from the substrate surface.
  • the distance between the top surface of the lower word line and the bottom surface of the upper word line is greater than or equal to 3 nm and less than or equal to 10 nm.
  • each word line has the same size in a direction perpendicular to the substrate surface.
  • the technical solution provided by the embodiments of the present disclosure at least has the following advantages: by arranging adjacent word lines at intervals in a direction perpendicular to the substrate surface, the spacing between adjacent word lines is increased, thereby reducing the distance between adjacent word lines.
  • the coupling effect between the semiconductor channel layers is formed by arranging the word line to surround the sides of the plurality of semiconductor channel layers arranged in the second direction to form a full surround gate transistor structure, and the sidewall conductive layer is formed to play a shielding role.
  • Figure 1 is a top view of a semiconductor structure provided by an embodiment of the present disclosure
  • 2 to 16 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 17 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. After forming a substrate, a semiconductor channel and a bit line, adjacent word lines can be arranged at intervals in a direction perpendicular to the surface of the substrate. The spacing between word lines increases, and accordingly, the spacing between word lines increases, and the insulation performance between adjacent word lines improves, which can improve the coupling effect between adjacent word lines.
  • the sidewall conductive layer can also be provided. to achieve a shielding effect, thereby improving the reliability of the semiconductor structure.
  • Figure 1 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2 is a semiconductor structure manufacturing method provided by an embodiment of the present disclosure along the AA, BB, CC and DD directions in Figure 1. sectional view.
  • a substrate 100 is provided; a plurality of semiconductor channels 110 arranged in an array along a first direction X and a second direction Y are formed on the substrate 100 ; a plurality of bit lines 120 extending along the first direction X are formed, and the bit lines 120 Located in the substrate 100, each bit line 120 is electrically connected to a plurality of semiconductor channels 110 arranged along the first direction A partial side surface of a plurality of semiconductor channels 110 arranged in the second direction Y, wherein along the first direction X, two adjacent word lines 130 are spaced apart in a direction perpendicular to the surface of the substrate 100 .
  • FIG. 1 is a top view of a semiconductor structure.
  • the adjacent word lines 130 do not show intervals in the direction perpendicular to the surface of the substrate 100 .
  • the two adjacent word lines 130 are vertically separated from each other. arranged at intervals in the direction of the surface of the substrate 100 .
  • the material type of the substrate 100 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or gallium indium arsenide, etc.
  • FIGS. 3 and 4 are cross-sectional views of the manufacturing steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure based on FIG. 2 .
  • a plurality of semiconductor channels 110 arranged in an array along the first direction X and the second direction Y are formed.
  • the substrate 100 is patterned to form a plurality of initial semiconductor channels 111 spaced apart along the second direction.
  • the initial semiconductor channel 111 can be formed by forming a mask on the surface of the substrate 100 and then patterning the substrate 100 through mask etching.
  • forming the initial semiconductor channels 111 further includes filling the grooves between the initial semiconductor channels 111 to form the isolation structure 101.
  • oxide may be used for filling.
  • the isolation structure 101 may be called a shallow trench isolation structure STI (Shallow Trench Isolation).
  • a plurality of initial semiconductor channels 111 are patterned to form a plurality of semiconductor channels 110 arranged at intervals along the first direction and the second direction.
  • the semiconductor channel 110 can be formed through self-aligned double imaging technology SADP (Self-aligned Double Patterning), and the formed semiconductor channel 110 can be made more accurate through the SADP technology.
  • SADP Self-aligned Double Patterning
  • forming the initial semiconductor channel 111 further includes forming a first mask layer 140 on the top surface of the initial semiconductor channel 111, and etching the initial semiconductor channel 111 downward along the first mask layer 140.
  • the first mask layer 140 is an oxide layer, and the first mask layer 140 can be formed by depositing an oxide on the top surface of the semiconductor channel 110 or by oxidizing part of the top surface of the semiconductor channel 110 .
  • the semiconductor channel 110 includes a first doped region 112, a channel region 113 and a second doped region 114 arranged in sequence.
  • the first doped region 112 is electrically connected to the bit line.
  • the semiconductor channel 110 can be ion-doped to form the first doped region 112, the channel region 113, and the second doped region 114, and the doped ion types are the same.
  • a junctionless transistor can be formed by doping the semiconductor channel 110 with the same ion type.
  • the doping ions in the first doped region 112 , the channel region 113 and the second doped region 114 are of the same type.
  • doped The doping ions are all N-type ions.
  • the doping ions in the first doping region 112, the channel region 113 and the second doping region 114 can be the same.
  • "no junction" here refers to no PN junction, that is, there is no PN junction in the transistor composed of the semiconductor channel 110. Since the device is a junctionless transistor, it is helpful to avoid the use of ultra-steep source-drain concentration gradient doping process. The phenomenon of making ultra-steep PN junctions in the nanoscale range can avoid problems such as threshold voltage drift and increase in leakage current caused by doping mutations. It is also conducive to suppressing the short channel effect and can still work within the scale of a few nanometers. , thus helping to further improve the integration density and electrical performance of semiconductor structures.
  • the additional doping here refers to the doping performed in order to make the doping ion type of the first doping region 112 and the second doping region 114 different from the doping ion type of the channel region 113 . miscellaneous.
  • ions may be implanted into the first doped region 112 (that is, the portion of the semiconductor channel 110 corresponding to the first doped region 112 ) using a high-energy method, and at the same time, the first doped region 112
  • the ion concentration is relatively high; the channel region 113 and the second doped region 114 (that is, the portion of the semiconductor channel 110 corresponding to the channel region 113 and the second doped region 114) are implanted using a low-energy method, and at the same time Make the concentration of the channel region 113 and the second doped region 114 lower; and then increase the second doped region 114 by ion implantation (the portion of the semiconductor channel 110 corresponding to the second doped region 114).
  • the concentration of the doped region 114 is such that the concentration of the second doped region 114 is higher.
  • the substrate 100 can also be doped before the semiconductor channel 110 is formed, so that after the semiconductor channel 110 is formed, the semiconductor channel 110 has the first doping region 112, the channel region 113 and the third region arranged in sequence. Two doped regions 114.
  • the length of the channel region 113 is greater than or equal to the sum of the lengths of adjacent word lines, that is, the top surface of the channel region 113 is higher than the top surface of the word lines located above.
  • the top surface is either flush with the top surface of the upper word line, and the bottom surface of the channel region 113 is lower than the bottom surface of the lower word line or flush with the bottom surface of the lower word line.
  • bit lines 120 extending along the first direction X are formed, the bit lines 120 are located in the substrate 100 , and each bit line 120 is electrically connected to a plurality of semiconductor channels 110 arranged along the first direction X.
  • a first spacer layer 150 is also formed on the first mask layer 140 and the sidewall of the semiconductor channel 110. By forming the first spacer layer 150, the subsequent formation of the bit line can be avoided. 120 will have an impact on the semiconductor channel 110.
  • the material of the semiconductor channel is silicon
  • a silicon metallization process is used to form multiple bit lines 120.
  • a method of forming the bit lines 120 may include: forming a metal layer (not shown in the figure), filling the metal layer is located between adjacent semiconductor channels 110, and the metal layers are arranged at intervals along the second direction; the metal layer is subjected to a first rapid thermal annealing process, a cleaning process (to remove unreacted metal layers), and a second rapid thermal annealing process.
  • a metal silicide process is used to form the bit line 120.
  • the contact resistance of the bit line 120 can be reduced through the metal silicide process, and defects between the bit line 120 and the substrate 100 can be reduced through the metal silicide process, thereby improving the semiconductor structure. performance.
  • FIGS. 6 to 15 are structural schematic diagrams of the manufacturing steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure based on FIG. 5 .
  • the plurality of semiconductor channels 110 includes: multiple columns of first channel groups, each column of the first channel group including a plurality of first semiconductor channels arranged along the second direction; multiple columns of second channel groups, each column of the second channel group It includes a plurality of second semiconductor channels arranged along the second direction, and a plurality of first channel groups and a plurality of second channel groups are alternately arranged in the first direction; the plurality of word lines 130 includes: extending along the second direction.
  • a plurality of first word lines 131 each first word line 131 surrounding part of the side surfaces of the semiconductor channels 110 in a row of first channel groups; a plurality of second word lines 132 extending in the second direction, each second The word line 132 surrounds part of the side surfaces of the semiconductor channels 110 in a row of second channel groups, and the distance between the bottom surface of the second word line 132 and the surface of the substrate 100 is greater than the distance between the bottom surface of the first word line 131 and the surface of the substrate 100;
  • Forming the plurality of word lines 130 includes: forming a first word line 131; and forming a second word line 132.
  • first word lines 131 and the second word lines 132 By forming the first word lines 131 and the second word lines 132 arranged at intervals, the coupling effect between adjacent word lines 130 can be reduced.
  • adjacent word lines 130 facing each other in the same plane ie, adjacent first word lines 131 and/or adjacent third word lines 132
  • the spacing between the two word lines 132) can reduce the coupling effect between the two adjacent word lines 130 that are facing each other in the same plane by increasing the spacing between them, thereby avoiding the occurrence of when the two word lines are facing each other in the same plane.
  • Activation of any one of the adjacent word lines 130 results in activation of the other word line 130, thereby increasing the reliability of the semiconductor structure.
  • the step of forming the first word line 131 may include: forming a first groove 180 that exposes part of the side surface of the first semiconductor channel; forming a first initial word line 133 , An initial word line 133 fills the first groove 180; the first initial word line 133 is patterned, and the remaining first initial word line 133 serves as the first word line 131.
  • first filling the first groove 180 to form the first initial word line 133, and then patterning the first word line 131 the height of the top surface of the formed first word line 131 can be better controlled, thereby avoiding The subsequent space left for the sidewall conductive layer is small and affects the performance of the sidewall conductive layer.
  • the steps of forming the first groove 180 include: forming a first spacer layer 150 covering the sidewalls of the semiconductor channel 110 spaced along the first direction; forming a mask layer 170.
  • the mask layer 170 covers the second semiconductor channel and the first spacer layer 150 located on the sidewall of the second semiconductor channel; the first spacer layer 150 is patterned using the mask layer 170 as a mask to form the first groove. 180.
  • forming the first spacer layer 150 further includes forming a first filling layer 160 between the first spacer layers 150 .
  • the material of the first spacer layer 150 may be an oxide, such as silicon oxide.
  • the material of the filling layer 160 may be nitride, such as silicon nitride.
  • the process of forming the first filling layer 160 further includes forming a first initial filling layer, and the first initial filling layer also covers the top surface of the semiconductor channel 110 by chemical mechanical polishing (CMP). A portion of the first initial filling layer is removed to expose the top surface of the semiconductor channel 110 , and the remaining first initial filling layer serves as the first filling layer 160 .
  • CMP chemical mechanical polishing
  • a mask layer 170 is formed.
  • the formation of the mask layer 170 provides a process basis for the subsequent formation of the first groove.
  • the formation of the mask layer 170 can protect the space used for the subsequent formation of the second word line and provide a better foundation for subsequent formation of the second word line.
  • the first word line and the second word line forming intervals provide a process basis.
  • the mask layer can also only cover the first semiconductor channel and the first sidewall layer of the first semiconductor channel sidewall. This application does not limit the position of the mask layer, as long as the mask layer covers the same The top surface of the channel group and the first side wall layer of the side wall of the channel group are sufficient.
  • forming the first groove 180 includes removing the mask layer 170 after forming the first groove 180 .
  • the first groove 180 does not expose the top surface of the bit line 120 , that is, after patterning the first sidewall, the first groove 180 is formed.
  • a portion of the first spacer layer 150 is still retained to avoid the subsequent connection between the first word line and the bit line 120 .
  • forming the first initial word line 133 includes forming a first gate oxide layer 190 before forming the first initial word line 133 .
  • the first gate oxide layer 190 By forming the first gate oxide layer 190 , the first initial word line 133 and the substrate 100 can be avoided. direct contact.
  • the method of forming the first gate oxide layer 190 may be to form the first gate oxide layer 190 by thermally oxidizing a portion of the semiconductor channel 110 , and the oxidation may provide the first initial word line 133 with the formation of the first gate oxide layer 190 .
  • space that is, the formed first gate oxide layer 190 does not occupy the space of the first groove 180 (refer to FIG. 8 ), so that the volume of the first initial word line 133 can be increased, thereby reducing the resistance of the first initial word line 133 , thereby improving the performance of semiconductor structures.
  • the first gate oxide layer 190 can also be formed by deposition.
  • the first initial word line 133 may cover the top surface of the first filling layer 160. Therefore, CMP may be used to make the top surface of the first initial word line 133 The surface of the first initial word line 133 may be flush with the top surface of the first filling layer 160 , and the material of the first initial word line 133 may be titanium nitride or tungsten material.
  • the first word line 131 is formed. Part of the first initial word line 133 can be removed by etching back the first initial word line 133, and the remaining first initial word line 133 (refer to Figure 9) serves as the first word Line 131.
  • the second word line 132 and the sidewall conductive layer 240 are formed simultaneously. Coupling response between adjacent word lines can be reduced by forming the second word line 132 spaced apart from the first word line 131 . Forming the sidewall conductive layer 240 can provide a shielding effect, thereby improving the performance of the semiconductor structure.
  • the step of forming the second word line 132 and the sidewall conductive layer 240 may include: forming a first cap layer 200 located on the top surface of the first word line 131 , the first cap layer 200 It can be used as a protective layer for the first word line 131, and the first word line 131 is covered by the first capping layer 200 to prevent subsequent processes from affecting the first word line 131, thereby improving the reliability of the semiconductor structure.
  • the step of forming the first capping layer 200 may include: forming a first initial capping layer, which also covers the top surface of the first gate oxide layer 190, and removing part of the first initial capping layer by CMP until the first initial capping layer is exposed. On the top surface of the gate oxide layer 190, the remaining first initial capping layer is the first capping layer 200.
  • the material of the first capping layer 200 may be an insulating material such as silicon oxynitride.
  • a first isolation layer 161 is formed.
  • the first isolation layer 161 is located between adjacent semiconductor channels 110 , and the top surface of the first isolation layer 161 is higher than the top surface of the first word line 131 .
  • part of the filling layer 160 can be removed by patterning the filling layer 160, and the remaining filling layer 160 serves as the first isolation layer 161.
  • the formation of the first isolation layer 161 provides a process basis for the subsequent formation of the second word line.
  • a method of patterning the filling layer 160 may be by wet etching.
  • patterning the filling layer 160 may further include removing the first gate oxide layer 190 located on the top surface of the semiconductor channel 110.
  • the method of removing part of the first gate oxide layer 190 may be through wet etching.
  • a second spacer layer 210 is formed.
  • the second spacer layer 210 covers the sidewalls of the first capping layer 200 and the sidewalls of the second semiconductor channel.
  • the method of forming the second spacer layer 210 may be to first form a second initial spacer on the sidewalls of the first capping layer 200 , the sidewalls of the second semiconductor channel and the top surface of the first isolation layer 161 by depositing oxide. layer, and then etch back part of the second initial spacer layer to expose the top surface of the first isolation layer 161 , and the remaining second initial spacer layer serves as the second spacer layer 210 .
  • a second isolation layer 220 is formed.
  • the second isolation layer 220 is located on the top surface of the first isolation layer 161, and one side wall of the second isolation layer 220 is connected with the second side wall layer covering the side wall of the first cover layer 200.
  • 210 (refer to Figure 13), and the other sidewall is in contact with the second spacer layer 210 (refer to Figure 13) of the second semiconductor channel sidewall; the second spacer layer 210 (refer to Figure 13) is etched back to form Second groove 181.
  • the step of forming the second isolation layer 220 may include: forming a second initial isolation layer that also covers the top surface of the semiconductor channel 110, and removing part of the second initial isolation layer by CMP to expose the semiconductor channel 110. top surface.
  • the method of etching back the second spacer layer 210 may be through wet etching. It can be understood that the materials of the first gate oxide layer 190 and the second spacer layer 210 may be the same.
  • the process of etching the second spacer layer 210 also includes etching part of the first gate oxide layer 190. However, the first gate oxide layer 190 is denser than the second spacer layer 210, so the etching speeds of the two are different. That is, the speed of etching the first gate oxide layer 190 is slower than the speed of etching the second spacer layer 210. Therefore, during the process of patterning the second spacer layer 210 (refer to FIG. 13), the second gate oxide layer is removed. The depth of 230 is less than the depth of the removed second spacer layer 210 .
  • the patterned second spacer layer 210 (refer to FIG. 13) provides space for the subsequent formation of the second word line and the sidewall conductive layer, and the second word line and the sidewall conductive layer can be separated by the second isolation layer 220. This prevents the second word line from being electrically connected to the sidewall conductive layer, and the sidewall conductive layer can shield the second word line to reduce the coupling effect between adjacent second word lines.
  • the second word line 132 is formed.
  • the second word line 132 is located in the second groove 181
  • the sidewall conductive layer 240 is formed in the same step.
  • the sidewall conductive layer 240 and the second word line 132 are located in different places. within the second groove 181 (for example, within an adjacent second groove).
  • the material of the sidewall conductive layer 240 and the second word line 132 are the same, for example, they can be titanium nitride.
  • the sidewall conductive layer 240 is located above one of the two adjacent word lines 130 , and the sidewall conductive layer 240 is arranged on the same layer as the other of the two adjacent word lines 130 . In other words, the sidewall conductive layer 240 is at least It is located on the outer periphery of a word line 130 and is opposite to the word line 130 .
  • the step of forming the second word line 132 and the sidewall conductive layer 240 may further include: forming a second initial word line and an initial sidewall conductive layer, and filling the second initial word line and the initial sidewall conductive layer with Different second grooves 181, and the second initial word line and the initial sidewall conductive layer are still located on the semiconductor channel 110, and then part of the second initial word line and the initial sidewall are removed through CMP and etching back.
  • the remaining second initial word line and the initial sidewall conductive layer serve as the second word line 132 and the sidewall conductive layer 240, and the second word line 132 and the sidewall conductive layer 240 are located in the second groove 181, through the first
  • the second word line 132 and the sidewall conductive layer 240 with a required height can be formed by etching after deposition.
  • the sidewall conductive layers 240 are spaced apart in the second direction, and the two sidewall conductive layers 240 are located on both sides of a second word line 132 .
  • forming the second word line 132 further includes: forming a second gate oxide layer 230.
  • the second gate oxide layer 230 may be formed by oxidizing the semiconductor channel 110 exposed by the second groove 181 (refer to FIG. 14), The second gate oxide layer 230 can prevent the second word line 132 from directly contacting the substrate 100 .
  • the second gate oxide layer 230 can also be formed by deposition.
  • part of the second gate oxide layer 230 may also be removed. Therefore, during the process of forming the second word line 132 , the second gate oxide layer 230 is also removed. The top surface of the oxygen layer 230 is filled with part of the filling material of the second word line 132 .
  • the subsequent process of forming the second word line 132 also includes etching back the second word line 132 .
  • the process also includes removing the filling material filled on the top surface of the second gate oxide layer 230 , so a concave hole will be formed on the top surface of the second gate oxide layer 230 .
  • the word line 130 that is closer to the surface of the substrate 100 among the two adjacent word lines 130 in the first direction is defined as the lower word line
  • the word line 130 that is closer to the surface of the substrate 100 among the two adjacent word lines 130 is defined as the lower word line.
  • the word line 130 whose surface is farther away is the upper word line
  • the bottom surface of the upper word line is located on the side of the top surface of the lower word line away from the surface of the substrate 100.
  • the top surface of the lower word line and the bottom surface of the upper word line are controlled. The distance between them is greater than or equal to 3nm and less than or equal to 10nm.
  • the lower word line mentioned here is equal to the first word line 131
  • the upper word line is equal to the second word line 132.
  • FIG. 16 is a cross-sectional view of the manufacturing steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure based on FIG. 15 .
  • the second word line 132 after forming the second word line 132, it further includes: forming a second capping layer 250, the second capping layer 250, the second capping layer 250 is located on the top surface of the second word line 132, and the second capping layer 250 also fills the recessed hole formed on the top surface of the second gate oxide layer during the above-mentioned etching back of the second word line 132 to make the surface of the semiconductor structure smooth, and the second cap layer 250 can also serve as the second word line 132
  • the protective layer can prevent the second word line 132 from reacting with the air by isolating the second word line 132 from the outside world.
  • the second cover layer 250 can also absorb part of the stress to reduce the stress of the second word line 132 . stress effect on the semiconductor structure, thereby improving the stability of the semiconductor structure.
  • the top surface of the semiconductor channel 110 can be exposed through CMP.
  • two film layers or structures are "set on the same layer” means that they are approximately at the same level relative to the substrate, and one is located on one side or both sides of the other. side, and the two are arranged roughly facing each other; for example, the same material can be used and the same process can be performed to simultaneously form two film layers or structures of "same layer arrangement".
  • adjacent word lines 130 are arranged at intervals in a direction perpendicular to the surface of the substrate 100, so that the distance between the adjacent word lines 130 can be reduced.
  • the spacing increases, correspondingly, the spacing between word lines 130 increases, and the insulation performance between adjacent word lines 130 improves, thereby improving the coupling effect between adjacent word lines 130.
  • the sidewall conductive layer 240 it can also It has a shielding effect and thereby improves the reliability of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a semiconductor structure, which can be formed using all or part of the above steps.
  • the semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the previous embodiment can be referred to the corresponding description of the previous embodiment, and will not be described in detail below.
  • an embodiment of the present disclosure provides a semiconductor structure, including: a substrate 100 and a plurality of semiconductor channels 110 formed on the substrate 100 and arranged in an array along a first direction and a second direction;
  • the bit lines 120 are located in the substrate 100, and each bit line 120 is electrically connected to a plurality of semiconductor channels 110 arranged along the first direction;
  • a plurality of word lines 130 extending along the second direction, each word The lines 130 surround part of the side surfaces of the plurality of semiconductor channels 110 arranged along the second direction, wherein two adjacent word lines 130 in the first direction are spaced apart in a direction perpendicular to the surface of the substrate 100; side walls
  • the conductive layer 240 and the sidewall conductive layer 240 are located above one of the two adjacent word lines 130, and the sidewall conductive layer 240 is arranged on the same layer as the other of the two adjacent word lines 130.
  • the spacing between adjacent word lines 130 can be increased, and the insulation performance of the adjacent word lines 130 can be increased by increasing the spacing between adjacent word lines 130.
  • the sidewall conductive layer 240 By providing the sidewall conductive layer 240, the sidewall conductive layer 240 can play a shielding role, thereby reducing the interference intensity, and thereby Improve the performance and reliability of semiconductor structures.
  • the plurality of semiconductor channels 110 includes: a plurality of first channel groups, each column of the first channel group including a plurality of first semiconductor channels arranged along the second direction; a plurality of second channel groups, each column The second channel group includes a plurality of second semiconductor channels arranged along the second direction, and the plurality of first channel groups and the plurality of second channel groups are alternately arranged in the first direction;
  • the plurality of word lines 130 includes: A plurality of first word lines 131 extending in the second direction, each first word line 131 surrounding part of the side surfaces of the semiconductor channels 110 in a row of first channel groups; a plurality of second word lines 132 extending in the second direction, Each second word line 132 surrounds part of the side surfaces of the semiconductor channels 110 in a row of second channel groups, and the distance between the bottom surface of the second word line 132 and the surface of the substrate 100 is greater than the distance between the bottom surface of the first word line 131 and the surface of the substrate 100 distance between.
  • the adjacent word lines 130 are divided into first word lines 131 and second word lines 132.
  • the word line 130 with a relatively higher position can be defined as the second word line 132, and the word line 130 with a lower relative position can be defined as the second word line 132.
  • the word line with a relatively higher position can also be defined as the first word line, and the word line with a lower relative position can be defined as the second word line.
  • the embodiments of the present disclosure do not limit the names of the word lines. , as long as the word lines are arranged at intervals in the direction perpendicular to the substrate.
  • each first word line 131 is flush, and the top surface of each first word line 131 is flush; the bottom surface of each second word line 132 is flush, and the top surface of each second word line 132 is flush.
  • the top surface is flush. That is, for all the first word lines 131 , the projections of the first word lines 131 along the first direction coincide with each other, and the projections of the second word lines 132 along the first direction coincide with each other.
  • each first word line 131 and each second word line 132 By arranging each first word line 131 and each second word line 132 to be flush, the stability of the semiconductor structure can be improved and defects caused by the position between the first word line 131 or the second word line 132 can be avoided. In addition, by arranging each first word line 131 to be flush and each second word line 132 to be flush, the manufacturing process can also be facilitated.
  • flushness can be considered to mean that the top surfaces of the first word lines 131 are completely flush, or it can also be considered that the height difference between the top surfaces of the first word lines 131 is within the allowable error range. When the height difference between the top surfaces of the first word lines 131 is within an allowable error range, the first word lines 131 can also be considered to be flush.
  • the materials of the plurality of first word lines 131 may be the same; the materials of the plurality of second word lines 132 may be the same.
  • the materials of the plurality of first word lines may be different, and the materials of the plurality of second word lines may be different.
  • the materials of the first word line 131 and the second word line 132 may be different. By setting the materials of the first word line 131 and the second word line 132 to be different, it will be easier to locate during subsequent failure analysis. Which step or material causes the problem, and different materials can also be selected according to the relative position of the first word line 131 and the second word line 132. For example, the relative position of the first word line 131 is lower, so the subsequent connection with the capacitor The structure needs to travel a longer path when transmitting electrical signals. Therefore, the material of the first word line 131 can be provided with better conductivity to compensate for the length of the conduction path and improve the performance of the semiconductor structure.
  • the materials of the first word line and the second word line may be the same.
  • the embodiments of the present disclosure do not limit the materials of the first word line and the second word line, as long as they can meet the performance requirements of the semiconductor structure.
  • the word line 130 that is closer to the surface of the substrate 100 among the adjacent word lines 130 in the first direction is an upper word line, and the bottom surface of the upper word line is located on the side of the top surface of the lower word line away from the surface of the substrate 100 .
  • the spacing between word lines can be increased to increase the insulation performance between adjacent word lines, further improving the reliability of the semiconductor structure.
  • the lower word line mentioned here is equal to the first word line 131, and the upper word line is equal to the second word line 132.
  • the distance between the top surface of the lower word line and the bottom surface of the upper word line is greater than or equal to 3 nm and less than or equal to 10 nm in a direction perpendicular to the surface of the substrate 100 .
  • the distance between the bottom surface of the upper word line and the top surface of the lower word line can be greater than or equal to 3 nm, the distance between the upper word line and the lower word line can be increased, thereby improving the insulation between adjacent word lines 130 and avoiding the occurrence of upper word lines.
  • Line conduction leads to the conduction of the lower word line, thereby improving the reliability of the semiconductor structure; by setting the distance between the bottom surface of the upper word line and the top surface of the lower word line to be less than or equal to 10nm, the process difficulty can be reduced.
  • the semiconductor structure may further include: a first cap layer 200 located on top of the first word line 131; a second cap layer 250 located on top of the second word line 132. surface; the sidewall conductive layer 240 is arranged in the same layer as the second word line 132 and is located on the side of the first cover layer 200. The material of the sidewall conductive layer 240 is the same as the conductive material in the second word line 132.
  • the first cap layer 200 can be used as a protective layer for the first word line 131. By providing the first cap layer 200, it can absorb part of the stress when the semiconductor structure is stressed, thereby reducing the stress on the first word line 131, and The first cover layer 200 can also prevent other process steps from affecting the first word line 131 during the formation process; the second cover layer 250 can be used as a protective layer for the second word line 132, and the second cover layer 250 can also be used It is used to fill the semiconductor structure flat, thereby forming a semiconductor structure with better morphology.
  • the semiconductor structure may further include: a first isolation layer 161, the first isolation layer 161 is located between the adjacent first word line 131 and the second word line 132, and the top surface of the first isolation layer 161 Higher than the top surface of the first word line 131; the second isolation layer 220 is located on the top surface of the first isolation layer 161, and is also located on the side of the second word line 132 and the side of the second capping layer 250.
  • the second word line 132 and the sidewall conductive layer 240 can be separated by the first isolation layer 161 and the second isolation layer 220, thereby preventing the second word line 132 from being electrically connected to the sidewall conductive layer 240.
  • the coupling effect between adjacent word lines 130 is not improved.
  • each word line 130 has the same size in a direction perpendicular to the surface of the substrate 100 .
  • the size here refers to the thickness of the word line 130.
  • the difference between adjacent word lines 130 can be reduced, thereby improving the reliability of the semiconductor structure.
  • the semiconductor structure further includes: a first spacer layer 150 covering sidewalls of the semiconductor channel 110 spaced along the first direction; a first gate oxide layer 190 , the first gate oxide layer 190 Located between the first cover layer 200 and the semiconductor channel 110; the second gate oxide layer 230 is located on the sidewall of the semiconductor channel 110.
  • the embodiment of the present disclosure forms a GAA structure by arranging multiple word lines 130 extending along the second direction, and the word lines 130 include a plurality of semiconductor channels 110 arranged along the second direction.
  • the insulation performance between adjacent word lines 130 can also be increased, thereby reducing the coupling effect between adjacent word lines 130; by setting the sidewall conductive layer 240, it can also be used as shielding layer to further improve the performance of the semiconductor structure.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及其制作方法，其中，半导体结构的制作方法包括：提供基底；在基底上形成沿第一方向和第二方向阵列排布的多个半导体通道；形成沿第一方向延伸的多条位线，位线基底内，且每一位线与沿第一方向排布的多个半导体通道电连接；形成沿第二方向延伸的多条字线，每一字线包绕沿第二方向排布的多个半导体通道的部分侧面，其中，在沿第一方向上，相邻的两条字线在垂直于基底表面的方向上间隔排布；形成侧壁导电层，侧壁导电层位于相邻的两条字线之一的上方，且侧壁导电层与相邻的两条字线之另一同层设置。该半导体结构可以降低相邻字线之间的耦合效应。

Description

半导体结构及其制作方法
交叉引用
本公开要求于2022年05月20日递交的名称为“半导体结构及其制作方法”、申请号为202210557400.7的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及半导体结构及其制作方法。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，在对动态存储器阵列结构中晶体管的排布方式以及如何缩小动态存储器阵列结构中单个功能器件的尺寸进行研究的同时，也需要提高小尺寸的功能器件的电学性能。
利用垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构作为动态存储器选择晶体管(access transistor)时，其占据的面积可以达到4F 2(F：在给定工艺条件下可获得的最小特征尺寸)，原则上可以实现更高的密度效率。
然而目前存在相邻字线之间存在较强的耦合效应的问题。
发明内容
本公开实施例提供一种半导体结构及其制作方法，至少可以降低相邻字线之间的耦合效应。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制作方法，包括：提供基底；在所述基底上形成沿第一方向和第二方向阵列排布的多个半导体通道；形成沿所述第一方向延伸的多条位线，所述位线位于所述基底内，且每一所述位线与沿所述第一方向排布的多个所述半导体通道电连接；形成沿所述第二方向延伸的多条字线，每一所述字线包绕沿所述第二方向排布的多个所述半导体通道的部分侧面，其中，在所述第一方向上相邻的两条所述字线在垂直于所述基底表面的方向上间隔排布；形成侧壁导电层，所述侧壁导电层位于相邻的两条所述字线之一的上方，且所述侧壁导电层与相邻的两条所述字线另一同层设置。
在一些实施例中，所述多个半导体通道包括：多列第一通道组，每一列所述第一通道组包括沿所述第二方向排布的多个第一半导体通道；多列第二通道组，每一列所述第二通道组包括沿所述第二方向排布的多个第二半导体通道，且所述多列第一通道组与所述多列第二通道组在所述第一方向上交替排布；所述多条字线包括：沿所述第二方向延伸的多条第一字线，每一所述第一字线包绕一列所述第一通道组中的所述半导体通道的部分侧面；沿所述第二方向延伸的多条第二字线，每一所述第二字线包绕一列所述第二通道组中的所述半导体通道的部分侧面，且所述第二字线底面与所述基底表面之间的距离大于所述第一字线底面与所述基底表面之间的距离；形成所述多条字线包括：形成所述第一字线；以及形成所述第二字线。
在一些实施例中，形成所述第一字线包括：形成第一凹槽，所述第一凹槽暴露所述第一半导体通道的部分侧面；形成第一初始字线，所述第一初始字线填充满所述第一凹槽；回刻蚀所述第一初始字线，剩余所述第一初始字线作为所述第一字线。
在一些实施例中，形成所述第一凹槽包括：形成第一侧墙层，所述第一侧墙层覆盖所述半导体通道沿所述第一方向间隔的侧壁；形成掩膜层，所述掩膜层覆盖所述第二半导体通道及位于所述第二半导体通道侧壁的所述第一侧墙层；以所述掩膜层为掩膜图形化所述第一侧墙层，以形成所述第一凹槽。
在一些实施例中，同步形成所述第二字线和所述侧壁导电层；形成所述第二字线和所述侧壁导电层包括：形成第一盖层，所述第一盖层位于所述第一字线顶面；形成第一隔离层，所述第一隔离层位于相邻的所述半导体通道之间，且所述第一隔离层的顶面高于所述第一字线的顶面；形成第二侧墙层，所述第二侧墙层覆盖所述第一盖层的侧壁及所述第二半导体通道的侧壁；形成第二隔离层，所述第二隔离层位于所述第一隔离层顶面，且所述第二隔离层的一个侧壁与覆盖所述第一盖层侧壁的所述第二侧墙层接触，另一侧壁与所述第二半导体通道侧壁的所述第二侧墙层接触；回刻蚀所述第二侧墙层，以形成第二凹槽；形成所述第二字线和所述侧壁导电层，所述第二字线和所述侧壁导电层位于不同的所述第二凹槽内。
在一些实施例中，形成所述第二字线之后还包括：形成第二盖层，所述第二盖层位于所述第二字线的顶面。
在一些实施例中，定义在所述第一方向上相邻的两条所述字线中与所述基底表面距离较近的所述字线为下字线，定义相邻的两条所述字线中与所述基底表面距离较远的所述字线为上字线，所述上字线底面位于所述下字线顶面远离所述基底表面的一侧，形成所述字线的过程中，控制所述下字线顶面与所述上字线底面之间的距离大于或等于3nm，且小于或等于10nm。
在一些实施例中，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区，所述第一掺杂区与所述位线电连接，所述第一掺杂区、所述沟道区以及所述第二掺杂区的掺杂类型相同。
在一些实施例中，在所述基底上形成沿所述第一方向和所述第二方向阵列排布的所述多个半导体通道，包括：图形化所述基底，以形成沿所述第二方向间隔排布的多个初始半导体通道；图形化所述多个初始半导体通道，以形成沿所述第一方向及所述第二方向都间隔排布的所述多个半导体通道。
在一些实施例中，所述半导体通道的材料为硅，采用硅金属化工艺形成所述多条所述位线。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：基底以及位于所述基底上形成沿第一方向和第二方向阵列排布的多个半导体通道；沿所述第一方向延伸的多条位线，所述位线位于所述基底内，且每一所述位线与沿所述第一方向排布的多个所述半导体通道电连接；沿所述第二方向延伸的多条字线，每一所述字线包绕沿所述第二方向排布的多个所述半导体通道的部分侧面，其中，在沿所述第一方向上，相邻的两条所述字线在垂直于所述基底表面的方向上间隔排布；侧壁导电层，所述侧壁导电层位于相邻的两 条所述字线之一的上方，且所述侧壁导电层与相邻的两条所述字线另一同层设置。
在一些实施例中，所述多个半导体通道包括：多列第一通道组，每一列所述第一通道组包括沿所述第二方向排布的多个第一半导体通道；多列第二通道组，每一列所述第二通道组包括沿所述第二方向排布的多个第二半导体通道，且所述多列第一通道组与所述多列第二通道组在所述第一方向上交替排布；所述多条字线包括：沿所述第二方向延伸的多条第一字线，每一所述第一字线包绕一列所述第一通道组中的所述半导体通道的部分侧面；沿所述第二方向延伸的多条第二字线，每一所述第二字线包绕一列所述第二通道组中的所述半导体通道的部分侧面，且所述第二字线底面与所述基底表面之间的距离大于所述第一字线底面与所述基底表面之间的距离。
在一些实施例中，每一所述第一字线的底面齐平，每一所述第一字线的顶面齐平；每一所述第二字线的底面齐平，每一所述第二字线的顶面齐平。
在一些实施例中，多条所述第一字线的材料相同；多条所述第二字线的材料相同。
在一些实施例中，所述第一字线与所述第二字线的材料不同。
在一些实施例中，所述半导体结构还包括：第一盖层，所述第一盖层位于所述第一字线顶面；第二盖层，所述第二盖层位于所述第二字线顶面；所述侧壁导电层与所述第二字线同层设置，且位于所述第一盖层的侧面，所述侧壁导电层的材料与所述第二字线中的导电材料相同。
在一些实施例中，所述半导体结构还包括：第一隔离层，所述第一隔离层位于相邻的第一字线与第二字线之间，所述第一隔离层顶面高于所述第一字线顶面；第二隔离层，所述第二隔离层位于所述第一隔离层顶面，且还位于所述第二字线的侧面以及所述第二盖层的侧面。
在一些实施例中，定义在所述第一方向上相邻的两条所述字线中与所述基底表面距离较近的所述字线为下字线，定义相邻的两条所述字线中与所述基底表面距离较远的所述字线为上字线，所述上字线底面位于所述下字线顶面远离所述基底表面的一侧。
在一些实施例中，在垂直于所述基底表面的方向上，所述下字线顶面与所述上字线底面之间的距离大于或等于3nm，且小于或等于10nm。
在一些实施例中，在垂直于所述基底表面方向上，每一所述字线的尺寸相同。
本公开实施例提供的技术方案至少具有以下优点：通过将相邻的字线在垂直于基底表面的方向上间隔排布，以增加相邻字线之间的间距，从而降低相邻字线之间的耦合效应，且通过设置字线包绕沿第二方向排布的多个半导体通道层的侧面以形成全环绕栅极晶体管结构，通过形成侧壁导电层可以起到屏蔽作用。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述 中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种半导体结构的俯视图；
图2至图16为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图；
图17为本公开一实施例提供一种半导体结构剖视图。
具体实施方式
本公开实施例通过提供一种半导体结构的制作方法，在形成基底、半导体通道及位线后，通过设置相邻的字线在垂直于基底表面的方向上间隔排布可以使相邻的字线之间的间距增加，相应的，字线之间的间距增加，相邻字线之间的绝缘性能提高，从而可以改善相邻字线之间的耦合效应，通过设置侧壁导电层还可以起到屏蔽的效果，进而提高半导体结构的可靠性。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
参考图1及图2，图1为本公开实施例提供的一种半导体结构的俯视图，图2为本公开实施例提供的一种半导体结构制作方法沿图1中AA、BB、CC及DD方向的剖视图。
参考图1，提供基底100；在基底100上形成沿第一方向X和第二方向Y阵列排布的多个半导体通道110；形成沿第一方向X延伸的多条位线120，位线120位于基底100内，且每一位线120与沿第一方向X排布的多个半导体通道110电连接；形成沿第二方向Y延伸的多条字线130，每一字线130包绕沿第二方向Y排布的多个半导体通道110的部分侧面，其中，在沿第一方向X上，相邻的两条字线130在垂直于基底100表面的方向上间隔排布。
可以理解的是，图1为半导体结构的俯视图，俯视图中，相邻的字线130在垂直于基底100表面的方向上并未示出间隔，然而实际上相邻的两条字线130在垂直于基底100表面的方向上间隔排布。
例如，参考图2，提供基底100，在一些实施例中，基底100的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者砷化镓铟等。
参考图3及图4，图3及图4为本公开实施例提供的一种半导体结构的制作方法在图2基础上的制作步骤的剖视图。
参考图3及图4，形成沿第一方向X和第二方向Y阵列排布的多个半导体通道110。
例如，参考图3，包括：图形化基底100，以形成沿第二方向间隔排布的多个初始半导体通道111。
在一些实施例中，可以通过在基底100的表面形成掩膜，再通过掩膜刻蚀的方式图形化基底100以形成初始半导体通道111。
在一些实施例中，形成初始半导体通道111之后还包括填充初始半导体通道111之间 的凹槽以形成隔离结构101，例如，可以采用氧化物进行填充。隔离结构101可以称为浅沟槽隔离结构STI(Shallow Trench Isolation)。
参考图4，图形化多个初始半导体通道111，以形成沿第一方向及第二方向分别间隔排布的多个半导体通道110。
在一些实施例中，可以通过自对准双重成像技术SADP(Self-aligned Double Patterning)形成半导体通道110，通过SADP技术可以使形成的半导体通道110更加精确。
在一些实施例中，形成初始半导体通道111后还包括在初始半导体通道111的顶面形成第一掩膜层140，沿所述第一掩模层140向下刻蚀所述初始半导体通道111，以形成沿第一方向X及第二方向Y都间隔排布的半导体通道110。例如，第一掩膜层140为氧化层，可以通过在半导体通道110的顶面沉积氧化物或者通过氧化部分半导体通道110的顶面的方式形成第一掩膜层140。
半导体通道110包括依次排列的第一掺杂区112、沟道区113以及第二掺杂区114，第一掺杂区112与位线电连接。例如，可以在形成半导体通道110后，对半导体通道110进行离子掺杂以形成第一掺杂区112、沟道区113以及第二掺杂区114，且掺杂的离子类型相同。通过对半导体通道110掺杂相同的离子类型可以形成无结晶体管，无结晶体管即第一掺杂区112、沟道区113和第二掺杂区114中的掺杂离子的类型相同，例如掺杂离子均为N型离子，进一步地，第一掺杂区112、沟道区113和第二掺杂区114中的掺杂离子可以相同。其中，此处的“无结”指的是无PN结，即半导体通道110构成的晶体管中没有PN结，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。可以理解的是，此处额外的掺杂指的是，为了让第一掺杂区112和第二掺杂区114的掺杂离子类型与沟道区113的掺杂离子类型不同而进行的掺杂。
在一些实施例中，可以先对第一掺杂区112(即半导体通道110的对应形成第一掺杂区112的部分)采用高能量的方式进行离子注入，同时使第一掺杂区112的离子浓度较高；再对沟道区113和第二掺杂区114(即半导体通道110的对应形成沟道区113和第二掺杂区114的部分)采用低能量的方式进行离子注入，同时使沟道区113和第二掺杂区114的浓度较低；再通过对第二掺杂区114(半导体通道110的对应形成第二掺杂区114的部分)进行离子注入的方式增加第二掺杂区114的浓度，以使第二掺杂区114的浓度较高。
需要说明的是，也可以在形成半导体通道110之前，对基底100进行掺杂，从而，在形成半导体通道110之后，半导体通道110具有依次排列的第一掺杂区112、沟道区113以及第二掺杂区114。
在一些实施例中，在垂直于基底100的方向上，沟道区113的长度大于或等于相邻字线的长度之和，即，沟道区113的顶面高于位于上方的字线的顶面或者与位于上方的字线的顶面齐平，沟道区113的底面低于位于下方的字线的底面或者与位于下方的字线的底面齐平。
参考图5，形成沿第一方向X延伸的多条位线120，位线120位于基底100内，且每一位线120与沿第一方向X排布的多个半导体通道110电连接。
在一些实施例中，在形成位线120前还在第一掩膜层140及半导体通道110的侧壁上形成第一侧墙层150，通过形成第一侧墙层150可以避免后续形成位线120的时候对半导体通道110造成影响。
在一些实施例中，半导体通道的材料为硅，采用硅金属化工艺形成多条位线120，例如，形成位线120的方法可以包括：形成金属层(图中未示出)，金属层填充位于相邻半导体通道110之间，且金属层沿第二方向间隔排布；对金属层进行第一次快速热退火处理、清洗处理(去除未反应的金属层)、第二次快速热退火处理，以在基底100内形成金属硅化物，金属硅化物作为位线120。即采用金属硅化工艺的方式形成位线120，通过金属硅化工艺的方式可以降低位线120的接触电阻，且通过金属硅化的方式可以降低位线120与基底100之间的缺陷，从而提高半导体结构的性能。
参考图6至图15，图6至图15为本公开实施例提供的一种半导体结构的制作方法在图5基础上的制作步骤的结构示意图。
例如，多个半导体通道110包括：多列第一通道组，每一列第一通道组包括沿第二方向排布的多个第一半导体通道；多列第二通道组，每一列第二通道组包括沿第二方向排布的多个第二半导体通道，且多列第一通道组与多列第二通道组在第一方向上交替排布；多条字线130包括：沿第二方向延伸的多条第一字线131，每一第一字线131包绕一列第一通道组中的半导体通道110的部分侧面；沿第二方向延伸的多条第二字线132，每一第二字线132包绕一列第二通道组中的半导体通道110的部分侧面，且第二字线132底面与基底100表面之间的距离大于第一字线131底面与基底100表面之间的距离；形成多条字线130包括：形成第一字线131；以及形成第二字线132。
通过形成间隔排布的第一字线131及第二字线132可以降低相邻字线130之间的耦合效应。通过形成间隔排布的第一字线131及第二字线132还可以增加在同一平面内相互正对的相邻字线130(即相邻的第一字线131和/或相邻的第二字线132)之间的间距，通过增加在同一平面内相互正对的相邻字线130之间的间距可以降低二者之间的耦合效应，从而避免出现当在同一平面内相互正对的相邻字线130的其中任一字线130激活导致另一字线130激活的情况，从而增加半导体结构的可靠性。
例如，参考图6至图10，形成第一字线131的步骤可以包括：形成第一凹槽180，第一凹槽180暴露第一半导体通道的部分侧面；形成第一初始字线133，第一初始字线133填充满第一凹槽180；图形化第一初始字线133，剩余第一初始字线133作为第一字线131。通过采用先填充满第一凹槽180形成第一初始字线133，然后在图形化形成第一字线131的方式可以较好的控制形成的第一字线131的顶面高度，从而可以避免后续为侧壁导电层留出的空间较小影响侧壁导电层的性能。
例如，参考图6至图8，形成第一凹槽180的步骤包括：形成第一侧墙层150，第一侧墙层150覆盖半导体通道110沿第一方向间隔的侧壁；形成掩膜层170，掩膜层170覆盖第二半导体通道及位于第二半导体通道侧壁的第一侧墙层150；以掩膜层170为掩膜图形化第一侧墙层150，以形成第一凹槽180。
例如，参考图6，形成第一侧墙层150后还包括在第一侧墙层150之间形成第一填充 层160，第一侧墙层150的材料可以是氧化物，例如氧化硅，第一填充层160的材料可以是氮化物，例如氮化硅。
在一些实施例中，形成第一填充层160的过程还包括形成第一初始填充层，第一初始填充层还覆盖半导体通道110的顶面，通过化学机械研磨(Chemical Mechanical Polishing，CMP)的方式去除掉部分第一初始填充层以暴露半导体通道110的顶面，剩余第一初始填充层作为第一填充层160。
参考图7，形成掩膜层170，通过形成掩膜层170为后续形成第一凹槽提供工艺基础，通过形成掩膜层170可以将后续用于形成第二字线的空间保护起来，为后续形成间隔的第一字线及第二字线提供工艺基础。
在另一些实施例中，掩膜层还可以只覆盖第一半导体通道及第一半导体通道侧壁的第一侧墙层，本申请不对掩膜层的位置进行限制，只需掩膜层覆盖同一通道组的顶面及该通道组侧壁的第一侧墙层即可。
参考图8，形成第一凹槽180，形成第一凹槽180后还包括去除掩膜层170，第一凹槽180并不暴露位线120的顶面，即，在图形化第一侧墙层150的过程中，还保留一部分第一侧墙层150，从而避免出现后续形成的第一字线与位线120连接。
参考图9，形成第一初始字线133，在形成第一初始字线133之前还包括形成第一栅氧层190，通过形成第一栅氧层190可以避免第一初始字线133与基底100直接接触。
在一些实施例中，形成第一栅氧层190的方法可以是通过热氧化部分半导体通道110的方式形成第一栅氧层190，通过氧化的方式可以为形成第一初始字线133提供形成的空间，即，形成的第一栅氧层190不占满第一凹槽180(参考图8)的空间，从而可以增加第一初始字线133的体积，从而降低第一初始字线133的电阻，进而提高半导体结构的性能。当然，也可以通过沉积的方式形成第一栅氧层190。
在一些实施例中，形成第一初始字线133过程中可能出现第一初始字线133覆盖在第一填充层160的顶面，故可以通过CMP的方式以使第一初始字线133的顶面与第一填充层160的顶面齐平，第一初始字线133的材料可以是氮化钛或者钨材料等。
参考图10，形成第一字线131，可以通过回刻蚀第一初始字线133的方式去除掉部分第一初始字线133，剩余第一初始字线133(参考图9)作为第一字线131。
参考图11至图15，同步形成第二字线132及侧壁导电层240。通过形成与第一字线131间隔的第二字线132可以降低相邻字线之间的耦合相应。通过形成侧壁导电层240可以提供屏蔽作用，从而提高半导体结构的性能。
例如，参考图11，形成第二字线132和侧壁导电层240的步骤可以包括：形成第一盖层200，第一盖层200位于第一字线131的顶面，第一盖层200可以作为第一字线131的保护层，通过第一盖层200将第一字线131进行覆盖从而可以避免后续的工艺对第一字线131产生影响，从而可以提高半导体结构的可靠性。
形成第一盖层200的步骤可以包括：形成第一初始盖层，第一初始盖层还覆盖第一栅氧层190的顶面，通过CMP的方式去除部分第一初始盖层直至暴露第一栅氧层190的顶面，剩余第一初始盖层为第一盖层200。
在一些实施例中第一盖层200的材料可以是氮氧化硅等绝缘材料。
参考图12，形成第一隔离层161，第一隔离层161位于相邻的半导体通道110之间，且第一隔离层161的顶面高于第一字线131的顶面。在一些实施例中，可以通过图形化填充层160去除部分填充层160，剩余填充层160作为第一隔离层161，通过形成第一隔离层161为后续形成第二字线提供工艺基础。
图形化填充层160的方法可以是通过湿法刻蚀。
在一些实施例中，图形化填充层160之后还可以包括：去除位于半导体通道110顶面的第一栅氧层190，去除部分第一栅氧层190的方法可以是通过湿法刻蚀。
参考图13，形成第二侧墙层210，第二侧墙层210覆盖第一盖层200的侧壁及第二半导体通道的侧壁。通过形成第二侧墙层210，并在后续通过去除第二侧墙层210的方式可以提供形成第二字线132的空间。
形成第二侧墙层210的方法可以是先通过沉积氧化物的方式在第一盖层200的侧壁、第二半导体通道的侧壁及第一隔离层161的顶面形成第二初始侧墙层，再通过回刻蚀部分第二初始侧墙层以暴露第一隔离层161的顶面，剩余第二初始侧墙层作为第二侧墙层210。
参考图14，形成第二隔离层220，第二隔离层220位于第一隔离层161顶面，且第二隔离层220的一个侧壁与覆盖第一盖层200侧壁的第二侧墙层210(参考图13)接触，另一侧壁与第二半导体通道侧壁的第二侧墙层210(参考图13)接触；回刻蚀第二侧墙层210(参考图13)，以形成第二凹槽181。
形成第二隔离层220的步骤可以包括：形成第二初始隔离层，第二初始隔离层还覆盖半导体通道110的顶面，通过CMP的方式去除掉部分第二初始隔离层以暴露半导体通道110的顶面。
回刻蚀第二侧墙层210(参考图13)的方法可以是通过湿法刻蚀，可以理解的是，第一栅氧层190与第二侧墙层210的材料可以相同，在湿法刻蚀第二侧墙层210的过程中还包括刻蚀部分第一栅氧层190，然而第一栅氧层190的致密度大于第二侧墙层210，故两者的刻蚀速度不同，即，刻蚀第一栅氧层190的速度小于刻蚀第二侧墙层210的速度，故在图形化第二侧墙层210(参考图13)的过程中，去除的第二栅氧层230的深度小于去除的第二侧墙层210的深度。
通过图形化第二侧墙层210(参考图13)为后续形成第二字线及侧壁导电层提供空间，且通过第二隔离层220可以将第二字线及侧壁导电层隔开，从而避免第二字线与侧壁导电层电连接，侧壁导电层可以对第二字线进行屏蔽，以降低相邻第二字线之间的耦合效应。
参考图15，形成第二字线132，第二字线132位于第二凹槽181内，且在同一步骤内形成侧壁导电层240，侧壁导电层240和第二字线132位于不同的第二凹槽181内(例如，位于相邻的第二凹槽内)。侧壁导电层240的材料与第二字线132的材料相同，例如都可以是氮化钛。通过形成与第一字线131间隔的第二字线132在保证半导体结构的正常运作下可以提高相邻字线130之间的间距，从而可以降低第一字线131与第二字线132之间的耦合效应，从而可以提高半导体结构的可靠性，且通过形成侧壁导电层240可以作为屏蔽层，进一步提高半导体结构的性能。
侧壁导电层240位于相邻的两条字线130之一的上方，且侧壁导电层240与相邻的两条字线130之另一同层设置，换句话说，侧壁导电层240至少位于一条字线130的外周，且与字线130正对设置。
在一些实施例中，形成第二字线132和侧壁导电层240的步骤还可以包括：形成第二初始字线及初始侧壁导电层，第二初始字线及初始侧壁导电层填充满不同的第二凹槽181，且第二初始字线及初始侧壁导电层还位于半导体通道110上，再通过CMP的方式及回刻蚀的方式去除掉部分第二初始字线及初始侧壁导电层，剩余第二初始字线及初始侧壁导电层作为第二字线132和侧壁导电层240，且第二字线132和侧壁导电层240位于第二凹槽181内，通过先沉积后刻蚀的方式可以形成所需要高度的第二字线132和侧壁导电层240。
可以理解的是，侧壁导电层240在第二方向上间隔分布，且两个侧壁导电层240位于一条第二字线132的两侧。
在一些实施例中，形成第二字线132之前还包括：形成第二栅氧层230，通过氧化第二凹槽181(参考图14)暴露的半导体通道110可以形成第二栅氧层230，通过第二栅氧层230可以避免第二字线132与基底100直接接触。当然，也可以通过沉积的方式形成第二栅氧层230。
可以理解的是，在图形化第二侧墙层210(参考图13)的过程中可能还会去除部分第二栅氧层230，故在形成第二字线132的过程中还在第二栅氧层230的顶面填充有部分第二字线132的填充材料，后续在形成第二字线132的过程中还包括回刻蚀第二字线132，在回刻蚀第二字线132的过程中还包括去除第二栅氧层230的顶面填充的填充材料，故还会在第二栅氧层230的顶面形成凹孔。
在一些实施例中，定义在第一方向上相邻的两条字线130中与基底100表面距离较近的字线130为下字线，定义相邻的两条字线130中与基底100表面距离较远的字线130为上字线，上字线底面位于下字线顶面远离基底100表面的一侧，形成字线130的过程中，控制下字线顶面与上字线底面之间的距离大于或等于3nm，且小于或等于10nm。
需要说明的是，这里所说的下字线等同于第一字线131，上字线等同于第二字线132，通过设置上字线底面与下字线顶面之间的距离大于或等于3nm可以提高上字线与下字线之间距离，从而提高相邻字线130之间的绝缘性，降低相邻字线130之间的耦合效应，避免出现上字线导通导致下字线导通的情况出现，进而提高半导体结构的可靠性；通过设置上字线底面与下字线顶面之间的距离小于或等于10nm可以降低工艺难度。
参考图16，图16为本公开实施例提供的一种半导体结构的制作方法在图15基础上的制作步骤的剖视图。
在一些实施例中，在形成第二字线132之后还包括：形成第二盖层250，第二盖层250，第二盖层250位于第二字线132的顶面，且第二盖层250还填充上述回刻蚀第二字线132的过程中在第二栅氧层顶面形成凹孔，以使半导体结构的表面平整，且第二盖层250还可以作为第二字线132的保护层，通过将第二字线132与外界隔离可以避免第二字线与空气发生反应，且当半导体结构受到外力影响时，第二盖层250还可以吸收部分应力从而降低第二字线132上受到的应力效果，从而提高半导体结构的稳定性。在此基础上，可以通过CMP的方式 暴露半导体通道110的顶表面。
需要说明的是，在本公开的实施例中，两个膜层或结构“同层设置”是指二者相对于基底而言大致处于同一水平高度，其一位于其另一的一侧或两侧，且二者大致正对设置；例如，可以采用相同的材料并进行相同的工艺以同步形成“同层设置”的两个膜层或结构。
本公开实施例通过在形成基底100、半导体通道110及位线120后，通过设置相邻的字线130在垂直于基底100表面的方向上间隔排布可以使相邻的字线130之间的间距增加，相应的，字线130之间的间距增加，相邻字线130之间的绝缘性能提高，从而可以改善相邻字线130之间的耦合效应，通过设置侧壁导电层240还可以起到屏蔽的效果，进而提高半导体结构的可靠性。
本公开另一实施例还提供一种半导体结构，该半导体结构可采用上述全部或者部分步骤形成。以下将结合附图对本公开另一实施例提供的半导体结构进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图17，本公开实施例通过提供一种半导体结构，包括：基底100以及位于基底100上形成沿第一方向和第二方向阵列排布的多个半导体通道110；沿第一方向延伸的多条位线120，位线120位于基底100内，且每一位线120与沿第一方向排布的多个半导体通道110电连接；沿第二方向延伸的多条字线130，每一字线130包绕沿第二方向排布的多个半导体通道110的部分侧面，其中，在第一方向上相邻的两条字线130在垂直于基底100表面的方向上间隔排布；侧壁导电层240，侧壁导电层240位于相邻的两条字线130之一的上方，且侧壁导电层240与相邻的两条字线130另一同层设置。
通过设置在垂直于基底100表面方向上相互间隔的字线130，可以增加相邻字线130之间的间距，通过增加相邻字线130之间的间距可以增加相邻字线130的绝缘性能从而减小相邻字线130之间的耦合效应，从而可以提高半导体结构的可靠性；通过设置侧壁导电层240，侧壁导电层240可以起到屏蔽的作用，从而减小干扰强度，进而提高半导体结构的性能及可靠性。
在一些实施例中，多个半导体通道110包括：多列第一通道组，每一列第一通道组包括沿第二方向排布的多个第一半导体通道；多列第二通道组，每一列第二通道组包括沿第二方向排布的多个第二半导体通道，且多列第一通道组与多列第二通道组在第一方向上交替排布；多条字线130包括：沿第二方向延伸的多条第一字线131，每一第一字线131包绕一列第一通道组中的半导体通道110的部分侧面；沿第二方向延伸的多条第二字线132，每一第二字线132包绕一列第二通道组中的半导体通道110的部分侧面，且第二字线132底面与基底100表面之间的距离大于第一字线131底面与基底100表面之间的距离。
将相邻字线130分为第一字线131及第二字线132，可以将相对位置较高的字线130定义为第二字线132，将相对位置较低的字线130定义为第一字线131，通过在垂直于基底100的方向上间隔设置字线130，相较于同层设置的字线而言，本公开实施例提供的相邻字线130之间的间距更大，通过设置间距更大的字线130可以增加字线130之间的绝缘性能，从而改善相邻字线130之间耦合效应的问题。
在另一些实施例中，还可以将相对位置较高的字线定义为第一字线，将相对位置较低 的字线定义为第二字线，本公开实施例不对字线的名称进行限制，只需字线在垂直于衬底的方向上间隔排布即可。
在一些实施例中，每一第一字线131的底面齐平，每一第一字线131的顶面齐平；每一第二字线132的底面齐平，每一第二字线132的顶面齐平。即，对于所有的第一字线131而言，第一字线131在沿第一方向上的投影重合，第二字线132在沿第一方向上的投影重合。
通过设置每一第一字线131齐平，每一第二字线132齐平可以提高半导体结构的稳定性，避免出现因第一字线131或第二字线132之间的位置产生的不良影响，且通过设置每一第一字线131齐平，每一第二字线132齐平也可以便于制程。
需要说明的是，这里的齐平可以认为是第一字线131的顶面之间完全齐平，也可以认为是第一字线131的顶面之间的高度差在允许的误差范围内，当第一字线131的顶面之间的高度差在允许的误差范围内时，也可以认为第一字线131之间是齐平的。
在一些实施例中，多条第一字线131的材料可以相同；多条第二字线132的材料可以相同，通过设置材料相同的第一字线131与材料相同的第二字线132可以减少制程中的材料的种类，便于整个制程的管控。
在另一些实施例中，多条第一字线的材料可以不同，多条第二字线的材料可以不同。
在一些实施例中，第一字线131与第二字线132的材料可以不同，通过设置第一字线131与第二字线132的材料不同可以便于后续做失效分析的时候更加容易定位是哪一步或者哪个材料导致的问题，且还可以根据第一字线131和第二字线132的相对位置关系选择不同的材料，例如第一字线131的相对位置较低，故后续在与电容结构进行电信号传递的时候需要行进的路径较长，故可以通过设置第一字线131的材料的导电性更好，从而对传导路径长进行补偿，提高半导体结构的性能。
在另一些实施例中，第一字线与第二字线的材料可以相同，本公开实施例不对第一字线及第二字线的材料进行限制，能满足半导体结构的性能要求即可。
在一些实施例中，定义在第一方向X上相邻的字线130中与基底100表面距离较近的字线130为下字线，定义相邻的字线130中与基底100表面距离较远的字线130为上字线，上字线底面位于下字线顶面远离基底100表面的一侧。通过设置上字线及下字线可以增加字线之间的间距从而增加相邻字线之间的绝缘性能，进一步提高半导体结构的可靠性。
需要说明的是，这里所说的下字线等同于第一字线131，上字线等同于第二字线132。
在一些实施例中在垂直于基底100表面的方向上，下字线顶面与上字线底面之间的距离大于或等于3nm，且小于或等于10nm。通过设置上字线底面与下字线顶面之间的距离大于或等于3nm可以提高上字线与下字线之间距离，从而提高相邻字线130之间的绝缘性，避免出现上字线导通导致下字线导通的情况出现，进而提高半导体结构的可靠性；通过设置上字线底面与下字线顶面之间的距离小于或等于10nm可以降低工艺难度。
在一些实施例中，半导体结构还可以包括：第一盖层200，第一盖层200位于第一字线131顶面；第二盖层250，第二盖层250位于第二字线132顶面；侧壁导电层240与第二字线132同层设置，且位于第一盖层200的侧面，侧壁导电层240的材料与第二字线132中的导电材料相同。
第一盖层200可以作为第一字线131的保护层，通过设置第一盖层200可以在半导体结构受到应力的时候吸收一部分应力作用，从而减少第一字线131上受到的应力作用，且第一盖层200还可以在形成工艺的时候避免其他工艺步骤对第一字线131造成影响；第二盖层250可以作为第二字线132的保护层，且第二盖层250还可以用于将半导体结构填平，从而形成形貌较好的半导体结构。
在一些实施例中，所述半导体结构还可以包括：第一隔离层161，第一隔离层161位于相邻的第一字线131与第二字线132之间，第一隔离层161顶面高于第一字线131顶面；第二隔离层220，第二隔离层220位于第一隔离层161顶面，且还位于第二字线132的侧面以及第二盖层250的侧面。
通过第一隔离层161及第二隔离层220可以将第二字线132及侧壁导电层240隔开，从而避免第二字线132与侧壁导电层240电连接，当第二字线132与侧壁导电层240电连接时改善相邻字线130之间的耦合效应不佳。
在一些实施例中，在垂直于基底100表面方向上，每一字线130的尺寸相同。这里的尺寸指代的是字线130的厚度，换句话说也就是通过设置厚度相同的字线130可以减小相邻字线130之间的差异，从而提高半导体结构的可靠性。
在一些实施例中，半导体结构还包括：第一侧墙层150，第一侧墙层150覆盖半导体通道110沿第一方向间隔的侧壁；第一栅氧层190，第一栅氧层190位于第一盖层200与半导体通道110之间；第二栅氧层230，第二栅氧层230位于半导体通道110的侧壁。
本公开实施例通过将设置沿第二方向延伸的多条字线130，且字线130包饶沿第二方向排布的多个半导体通道110以形成GAA结构，通过将相邻字线130设置为在垂直于基底100表面的方向上间隔排布还可以增加相邻字线130之间的绝缘性能，从而降低相邻字线130之间的耦合效应；通过设置侧壁导电层240还可以作为屏蔽层，进一步提高半导体结构的性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体结构的制作方法，包括：
    提供基底；
    在所述基底上形成沿第一方向和第二方向阵列排布的多个半导体通道；
    形成沿所述第一方向延伸的多条位线，所述位线位于所述基底内，且每一所述位线与沿所述第一方向排布的多个所述半导体通道电连接；
    形成沿所述第二方向延伸的多条字线，每一所述字线包绕沿所述第二方向排布的多个所述半导体通道的部分侧面，其中，在所述第一方向上相邻的两条所述字线在垂直于所述基底表面的方向上间隔排布；
    形成侧壁导电层，所述侧壁导电层位于相邻的两条所述字线之一的上方，且所述侧壁导电层与相邻的两条所述字线之另一同层设置。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述多个半导体通道包括：多列第一通道组，每一列所述第一通道组包括沿所述第二方向排布的多个第一半导体通道；多列第二通道组，每一列所述第二通道组包括沿所述第二方向排布的多个第二半导体通道，且所述多列第一通道组与所述多列第二通道组在所述第一方向上交替排布；所述多条字线包括：沿所述第二方向延伸的多条第一字线，每一所述第一字线包绕一列所述第一通道组中的所述半导体通道的部分侧面；沿所述第二方向延伸的多条第二字线，每一所述第二字线包绕一列所述第二通道组中的所述半导体通道的部分侧面，且所述第二字线底面与所述基底表面之间的距离大于所述第一字线底面与所述基底表面之间的距离；形成所述多条字线包括：形成所述第一字线；以及形成所述第二字线。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述第一字线包括：
    形成第一凹槽，所述第一凹槽暴露所述第一半导体通道的部分侧面；
    形成第一初始字线，所述第一初始字线填充满所述第一凹槽；
    回刻蚀所述第一初始字线，剩余所述第一初始字线作为所述第一字线。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，形成所述第一凹槽包括：
    形成第一侧墙层，所述第一侧墙层覆盖所述半导体通道沿所述第一方向间隔的侧壁；
    形成掩膜层，所述掩膜层覆盖所述第二半导体通道及位于所述第二半导体通道侧壁的所述第一侧墙层；
    以所述掩膜层为掩膜图形化所述第一侧墙层，以形成所述第一凹槽。
  5. 根据权利要求3所述的半导体结构的制作方法，其中，同步形成所述第二字线和所述侧壁导电层；形成所述第二字线和所述侧壁导电层包括：
    形成第一盖层，所述第一盖层位于所述第一字线顶面；
    形成第一隔离层，所述第一隔离层位于相邻的所述半导体通道之间，且所述第一隔离层的顶面高于所述第一字线的顶面；
    形成第二侧墙层，所述第二侧墙层覆盖所述第一盖层的侧壁及所述第二半导体通道的侧壁；
    形成第二隔离层，所述第二隔离层位于所述第一隔离层顶面，且所述第二隔离层的一个 侧壁与覆盖所述第一盖层侧壁的所述第二侧墙层接触，另一侧壁与所述第二半导体通道侧壁的所述第二侧墙层接触；
    回刻蚀所述第二侧墙层，以形成第二凹槽；
    形成所述第二字线和所述侧壁导电层，所述第二字线和所述侧壁导电层位于不同的所述第二凹槽内。
  6. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述第二字线之后还包括：形成第二盖层，所述第二盖层位于所述第二字线的顶面。
  7. 根据权利要求1所述的半导体结构的制作方法，其中，定义在所述第一方向上相邻的两条所述字线中与所述基底表面距离较近的所述字线为下字线，定义相邻的两条所述字线中与所述基底表面距离较远的所述字线为上字线，所述上字线底面位于所述下字线顶面远离所述基底表面的一侧，形成所述字线的过程中，控制所述下字线顶面与所述上字线底面之间的距离大于或等于3nm，且小于或等于10nm。
  8. 根据权利要求1所述的半导体结构的制作方法，其中，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区，所述第一掺杂区与所述位线电连接，所述第一掺杂区、所述沟道区以及所述第二掺杂区的掺杂类型相同。
  9. 根据权利要求1所述的半导体结构的制作方法，其中，在所述基底上形成沿所述第一方向和所述第二方向阵列排布的所述多个半导体通道，包括：图形化所述基底，以形成沿所述第二方向间隔排布的多个初始半导体通道；
    图形化所述多个初始半导体通道，以形成沿所述第一方向及所述第二方向都间隔排布的所述多个半导体通道。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，所述半导体通道的材料为硅，采用硅金属化工艺形成所述多条所述位线。
  11. 一种半导体结构，包括：
    基底以及位于所述基底上形成沿第一方向和第二方向阵列排布的多个半导体通道；
    沿所述第一方向延伸的多条位线，所述位线位于所述基底内，且每一所述位线与沿所述第一方向排布的多个所述半导体通道电连接；
    沿所述第二方向延伸的多条字线，每一所述字线包绕沿所述第二方向排布的多个所述半导体通道的部分侧面，其中，在所述第一方向上相邻的两条所述字线在垂直于所述基底表面的方向上间隔排布；
    侧壁导电层，所述侧壁导电层位于相邻的两条所述字线之一的上方，且所述侧壁导电层与相邻的两条所述字线另一同层设置。
  12. 根据权利要求11所述的半导体结构，其中，所述多个半导体通道包括：
    多列第一通道组，每一列所述第一通道组包括沿所述第二方向排布的多个第一半导体通道；多列第二通道组，每一列所述第二通道组包括沿所述第二方向排布的多个第二半导体通道，且所述多列第一通道组与所述多列第二通道组在所述第一方向上交替排布；
    所述多条字线包括：
    沿所述第二方向延伸的多条第一字线，每一所述第一字线包绕一列所述第一通道组中的 所述半导体通道的部分侧面；
    沿所述第二方向延伸的多条第二字线，每一所述第二字线包绕一列所述第二通道组中的所述半导体通道的部分侧面，且所述第二字线底面与所述基底表面之间的距离大于所述第一字线底面与所述基底表面之间的距离。
  13. 根据权利要求12所述的半导体结构，其中，每一所述第一字线的底面齐平，每一所述第一字线的顶面齐平；每一所述第二字线的底面齐平，每一所述第二字线的顶面齐平。
  14. 根据权利要求12所述的半导体结构，其中，多条所述第一字线的材料相同；多条所述第二字线的材料相同。
  15. 根据权利要求12所述的半导体结构，其中，所述第一字线与所述第二字线的材料不同。
  16. 根据权利要求12所述的半导体结构，其中，还包括：第一盖层，所述第一盖层位于所述第一字线顶面；第二盖层，所述第二盖层位于所述第二字线顶面；所述侧壁导电层与所述第二字线同层设置，且位于所述第一盖层的侧面，所述侧壁导电层的材料与所述第二字线中的导电材料相同。
  17. 根据权利要求16所述的半导体结构，其中，所述半导体结构还包括：第一隔离层，所述第一隔离层位于相邻的所述第一字线与所述第二字线之间，所述第一隔离层顶面高于所述第一字线顶面；第二隔离层，所述第二隔离层位于所述第一隔离层顶面，且还位于所述第二字线的侧面以及所述第二盖层的侧面。
  18. 根据权利要求11所述的半导体结构，其中，定义在所述第一方向上相邻的两条所述字线中与所述基底表面距离较近的所述字线为下字线，定义相邻的两条所述字线中与所述基底表面距离较远的所述字线为上字线，所述上字线底面位于所述下字线顶面远离所述基底表面的一侧。
  19. 根据权利要求18所述的半导体结构，其中，在垂直于所述基底表面的方向上，所述下字线顶面与所述上字线底面之间的距离大于或等于3nm，且小于或等于10nm。
  20. 根据权利要求11所述的半导体结构，其中，在垂直于所述基底表面方向上，每一所述字线的尺寸相同。
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