WO2023221301A1 - 一种半导体结构的制作方法及其结构 - Google Patents

一种半导体结构的制作方法及其结构 Download PDF

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Publication number
WO2023221301A1
WO2023221301A1 PCT/CN2022/110262 CN2022110262W WO2023221301A1 WO 2023221301 A1 WO2023221301 A1 WO 2023221301A1 CN 2022110262 W CN2022110262 W CN 2022110262W WO 2023221301 A1 WO2023221301 A1 WO 2023221301A1
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Prior art keywords
layer
isolation
word line
protective layer
top surface
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PCT/CN2022/110262
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English (en)
French (fr)
Inventor
肖德元
邵光速
邱云松
蒋懿
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长鑫存储技术有限公司
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Priority to US17/934,672 priority Critical patent/US20230380146A1/en
Publication of WO2023221301A1 publication Critical patent/WO2023221301A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a method of manufacturing a semiconductor structure and its structure.
  • the present disclosure provides a method for manufacturing a semiconductor structure and its structure.
  • a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including first grooves spaced apart along a first direction in the substrate and located in the first grooves. Filling layer; patterning the substrate to form second grooves, the second grooves are spaced apart along the second direction, and the second grooves are located on the top surface of the first grooves, and the second grooves are A groove and the second groove form a channel columnar structure; a protective layer is formed on the surface of the substrate, and the protective layer is different from the filling layer; a bit line structure is formed, and the bit line structure is formed on the surface of the substrate.
  • first isolation layer The bottom of the second groove; forming a first isolation layer, the first isolation layer being located in the second groove and on the top surface of the bit line structure; removing part of the filling layer, leaving the remaining filling layer It is flush with the upper surface of the first isolation layer; a word line structure is formed, and the word line structure surrounds the channel columnar structure and is distributed at intervals along the second direction; an isolation structure is formed, and the isolation structure is located on the second Within the groove and between adjacent word line structures.
  • the first dielectric layer is located on the top surface of the bit line structure and the sidewall of the channel columnar structure
  • the method of forming the protective layer includes: forming the first protective layer, The first protective layer is located on the top surface of the substrate; a portion of the first dielectric layer is patterned to expose part of the inner wall of the second groove; a second protective layer is formed, and the second protective layer is located on The inner wall of the second groove and the side wall of the first protective layer, the first protective layer and the second protective layer constitute the protective layer.
  • the method of forming the word line structure includes: after forming the protective layer, patterning the first dielectric layer so that the top surface of the first dielectric layer is flush with the top surface of the first isolation layer. flat; forming a second dielectric layer, the second dielectric layer is located on the top surface of the first dielectric layer and covers part of the sidewalls of the channel columnar structure; forming an initial word line structure, the initial word line structure fills Fill the first groove and the second groove; pattern the initial word line structure using the protective layer as a mask until the top surface of the first isolation layer is exposed and the initial word line remains structure as the word line structure.
  • the step of removing part of the filling layer includes: before forming the protective layer, removing the first dielectric layer and part of the filling layer in the same step; the top surface of the filling layer and the first dielectric layer The top surface of the layer is flush; after forming the protective layer, the first dielectric layer and part of the filling layer are removed in the same step; the remaining filling layer is flush with the upper surface of the first isolation layer.
  • the method of forming the isolation structure includes: forming a first isolation structure, the first isolation structure is located on the top surface of the first isolation layer, the sidewalls of the word line structure and the sidewalls of the protective layer. ; Form a second isolation structure, the second isolation structure fills the third groove, and the first isolation structure and the second isolation structure constitute the isolation structure.
  • the method of forming the protective layer includes: before patterning the substrate, further including: removing part of the filling layer, forming a first initial protective layer on the top surface of the filling layer; patterning the first An initial protective layer and the substrate are used to form the second groove, and the remaining first initial protective layer serves as a first protective layer; a second protective layer is formed, and the second protective layer is located in the second groove.
  • the inner wall of the groove and the side wall of the first protective layer, the first protective layer and the second protective layer constitute the protective layer.
  • a first dielectric layer the first dielectric layer is located on the top surface of the bit line structure and the side wall of the channel columnar structure
  • the method of forming the word line structure includes: forming an initial word line structure , the initial word line structure is located on the top surface of the first dielectric layer and the first isolation layer and the bottom surface of the protective layer; the protective layer is used as a mask to pattern the initial word line structure and the The first isolation layer is exposed until the top surface of the first isolation layer is exposed, and the initial word line structure remains as the word line structure.
  • the step of removing part of the filling layer includes: removing part of the filling layer before patterning the substrate; and removing part of the filling layer after forming the protective layer and before forming an initial word line structure.
  • the method of forming the isolation structure includes: forming a first isolation structure, the first isolation structure is located on the top surface of the first isolation layer, the side walls of the word line structure and the side walls of the protective layer , the first isolation structure and the protective layer constitute the isolation structure.
  • the method of forming the protective layer includes: forming a first protective layer, the first protective layer is located on the top surface of the substrate; forming a second protective layer, the second protective layer is located on the first protective layer.
  • the second protective layer is located on the side wall of the second groove, and the first protective layer and the second protective layer constitute the protective layer.
  • the word line structure also includes: a first dielectric layer, the first dielectric layer is located on the top surface of the bit line structure and the side wall of the channel columnar structure.
  • the method of forming the word line structure includes: removing the Part of the first dielectric layer and the filling layer so that the top surface of the first dielectric layer is flush with the top surface of the first isolation layer; a second dielectric layer is formed, and the second dielectric layer is located where The top surface of the first dielectric layer covers part of the sidewall of the channel columnar structure; an initial word line structure is formed, and the initial word line structure fills the first groove and the second groove, so The top surface of the initial word line structure is flush with the bottom surface of the first protective layer; the initial word line structure and the first isolation layer are patterned using the protective layer as a mask until the bit line structure is exposed. On the top surface, the initial word line structure remains as the word line structure.
  • the method of forming the isolation structure includes: forming a first isolation structure and a second isolation structure, the first isolation structure being surrounded by the first isolation layer, the word line structure and the second isolation structure. There is an air gap, the second isolation structure is located between the word line structures, and the top surface of the second isolation structure is flush with the top surface of the word line structure.
  • the method of forming the bit line structure includes: forming a fourth groove, the fourth groove is located on the bottom surface of the second groove; forming the first bit line conductive layer using a metal silicide process, the The first bit line conductive layer is located on the surface of the fourth groove facing the substrate; a second bit line conductive layer is formed, and the second bit line conductive layer fills the fourth groove, and the first bit line conductive layer is A bit line conductive layer and the second bit line conductive layer constitute the bit line structure.
  • a second aspect of the present disclosure provides a semiconductor structure, including: a substrate, a channel columnar structure, the channel columnar structure is located in the substrate, and the channel columnar structures are spaced apart along a first direction and a second direction. Cloth; bit line structure, the bit line structure is connected with the channel columnar structure, the bit line structure is arranged in the substrate at intervals along the second direction, and the bit line structure is located in the channel The bottom surface of the columnar structure; a first isolation layer, the first isolation layer is located on the top surface of the bit line structure; a filling layer, the filling layer is located in the substrate, and the top surface of the filling layer is in contact with the The top surface of the first isolation layer is flush; a word line structure that surrounds the channel columnar structure and is spaced apart along the second direction; an isolation structure that is located at least adjacent to the between word line structures.
  • the isolation structure includes a first isolation structure and a second isolation structure
  • the first isolation structure is an air gap surrounded by the first isolation layer, the word line structure and the second isolation structure, so
  • the second isolation structure is located between the word line structures, and a top surface of the second isolation structure is flush with a top surface of the word line structure.
  • the isolation structure includes: a protective layer located on the top surface and part of the side walls of the channel columnar structure; a first isolation structure located on the top surface of the first isolation layer , the sidewalls of the word line structure and the sidewalls of the protective layer.
  • the isolation structure includes: a first isolation structure, the first isolation structure is located on the top surface of the first isolation layer and a side wall of the word line structure; a second isolation structure, the second isolation structure Located on the top surface of the channel columnar structure and between the channel columnar structure and the first isolation structure.
  • the bit line structure includes: a first line conductive layer, the first line conductive layer is located in the substrate, and the first line conductive layer is in contact with the bottom surface of the channel columnar structure; Two bit line conductive layers, the second bit line conductive layer is located on the top surface of the first bit line conductive layer.
  • the top surface of part of the second bit line conductive layer is lower than the bottom surface of the channel columnar structure, and the bottom surface of the first isolation structure is lower than the bottom surface of the channel columnar structure.
  • a word line structure surrounding the channel columnar structure is formed to form a fully surrounding gate transistor structure, and after forming the word line structure, adjacent word lines are also formed.
  • An isolation structure is formed between the structures. The isolation structure can increase the insulation between adjacent word lines and thus improve the performance of the semiconductor structure. That is, the performance of the semiconductor structure can be improved while satisfying the density efficiency of the semiconductor structure.
  • 1 to 18 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 19 to 31 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • 32 to 40 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by yet another embodiment of the present disclosure.
  • the present disclosure provides a method for manufacturing a semiconductor structure.
  • a word line structure surrounding a channel columnar structure By forming a word line structure surrounding a channel columnar structure, a fully surrounding gate transistor structure is formed.
  • an isolation structure between word line structures By forming an isolation structure between word line structures, it is possible to avoid gaps between adjacent word lines. electrical connections, so that the performance requirements of the semiconductor structure can be met while meeting the integration density of the semiconductor structure.
  • FIG. 1 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 100; a channel columnar structure 110, the channel columnar structure 110 is located in the substrate 100, and the channel columnar structure 110 is spaced apart along the first direction X and the second direction Y; bit lines Structure 120, the bit line structure 120 is connected with the channel column structure 110, the bit line structure 120 is arranged at intervals in the substrate 100 along the second direction Y, and the bit line structure 120 is located on the bottom surface of the channel column structure 110; the word line structure 130, the word The line structures 130 surround the channel column structure 110 and are spaced apart along the second direction Y.
  • a dielectric layer 140 is also formed around the channel columnar structure 110 , and the dielectric layer 140 surrounds the channel columnar structure 110 to avoid direct contact between the channel columnar structure 110 and the word line structure 130 .
  • the word line structure 130 surrounding the channel columnar structure 110 By forming the word line structure 130 surrounding the channel columnar structure 110, a full surrounding gate structure can be formed, thereby meeting the performance requirements of the semiconductor structure while meeting the integration density of the semiconductor structure.
  • FIG. 2 to FIG. 4 are cross-sectional views along the dotted line direction of FIG. 1 according to an embodiment of the present disclosure.
  • a substrate 100 is provided.
  • the substrate 100 includes first grooves 150 spaced apart along the first direction X in the substrate 100 and a filling layer 160 located in the first grooves 150 .
  • the first groove 150 can be formed through a self-aligned double patterning (SADP) process. In other embodiments, the first groove 150 can also be formed through a self-aligned quadruple patterning process.
  • the first groove 150 is formed by a patterning technology (Self Aligned Quadruple Patterning, SAQP for short) process. The pattern of the first groove 150 can be formed more accurately through SADP or SAQP technology.
  • the material of the substrate 100 may be silicon, germanium or silicon germanium, and the material of the substrate 100 may also be doped.
  • the substrate 100 may be made of silicon.
  • the substrate 100 is doped with trace amounts of trivalent elements, such as boron, indium, gallium or aluminum, to form a P-type substrate.
  • the substrate 100 is doped with trace amounts of pentavalent elements, such as phosphorus, antimony. , arsenic, etc., so that an N-type substrate can be formed.
  • the selection of doping elements of the substrate 100 can be considered based on actual needs and product performance. This disclosure does not limit the materials of the substrate 100 and the doped elements.
  • the material of the filling layer 160 may be an insulating material such as silicon oxide or silicon nitride.
  • the filling layer 160 also covers the top surface of the substrate 100 , and the filling layer 160 located on the top surface of the substrate 100 can be removed by chemical grinding to expose the top surface of the substrate 100 .
  • the substrate 100 is patterned to form second grooves 170 , the second grooves 170 are spaced apart along the second direction Y, and the second grooves 170 are located in the first grooves 150 (refer to FIG. 3 )
  • the first groove 150 and the second groove 170 form a channel columnar structure 110 ; a protective layer 180 is formed on the surface of the substrate 100 , and the protective layer 180 is different from the filling layer 160 .
  • a first protective layer 181 is formed, and the first protective layer 181 is located on the top surface of the substrate 100 .
  • the material of the first protective layer 181 may be silicon nitride and other materials.
  • the material of silicon nitride is relatively hard, so that the morphology of the first protective layer 181 will not change significantly in subsequent steps. Therefore, when subsequent patterning is performed using the first protective layer 181 as a mask, the pattern formed will be more accurate.
  • a first dielectric layer 190 is formed.
  • the first dielectric layer 190 is located on the sidewall of the channel columnar structure 110.
  • the first dielectric layer 190 can be formed by thermally oxidizing the channel columnar structure 110.
  • the first dielectric layer 190 is formed by thermal oxidation of the channel columnar structure 110.
  • Layer 190 is used to protect channel pillar structure 110 during subsequent formation of bit line structures.
  • the first dielectric layer 190 is also located on the bottom surface of the second groove 170, and the first dielectric layer 190 located on the bottom surface of the second groove 170 can be removed by etching back to expose the surface of the substrate 100.
  • the channel columnar structure 110 can be protected from contamination when the bit line structure is subsequently formed.
  • bit line structure 120 is formed; the bit line structure 120 is formed at the bottom of the second groove 170 .
  • a fourth groove 200 is formed, and the fourth groove 200 is located on the bottom surface of the second groove 170 .
  • the width of the fourth groove 200 along the first direction less, thereby facilitating the formation of a continuous first bit line conductive layer 121, thereby increasing the transmission rate of the bit line structure 120.
  • the width of the fourth groove 200 along the first direction X may be equal to the spacing between adjacent channel columnar structures 110 .
  • the shape of the cross-sectional view of the fourth groove 200 along the first direction may also be a rectangle.
  • a metal silicide process is used to form the first line conductive layer 121 , and the first line conductive layer 121 is located on the surface of the fourth groove 200 facing the substrate 100 .
  • the first line conductive layer 121 is formed in the substrate 100 by forming a metal layer on the surface of the substrate 100 and performing a rapid thermal annealing process and a selective wet etching process.
  • the material of the metal layer may be metals such as titanium and cobalt. After forming the first line conductive layer 121, the metal layer is also removed. Forming the first line conductive layer 121 through a metal silicide process can reduce the resistance of the first line conductive layer 121 .
  • a second bit line conductive layer 122 is formed.
  • the second bit line conductive layer 122 fills the fourth groove 200 .
  • the first bit line conductive layer 121 and the second bit line conductive layer 122 constitute the bit line structure 120 .
  • the bit line structure 120 is located on the bottom surface of the first dielectric layer 190 .
  • the material of the second bit line conductive layer 122 may be metal. By setting the material of the second bit line conductive layer 122 to metal, the conduction speed of the bit line structure 120 can be improved, thereby improving the response speed of the semiconductor structure.
  • a first isolation layer 210 is formed.
  • a first initial isolation layer 211 is formed.
  • the first initial isolation layer 211 fills the second groove 170 (refer to FIG. 9 ), and the material of the first initial isolation layer 211 may be the same as the material of the filling layer 160 , thereby reducing the amount of material used in the production process. type, and provides a basis for subsequent removal of part of the filling layer 160 and the first initial isolation layer 211 in the same step.
  • the first initial isolation layer 211 is patterned to form the first isolation layer 210 ; part of the filling layer 160 is removed, and the remaining filling layer 160 is flush with the upper surface of the first isolation layer 210 .
  • the process of patterning the first initial isolation layer 211 also includes: patterning a portion of the first dielectric layer 190 to expose a portion of the second groove 170 (refer to Figure 9)
  • the inner wall of the first dielectric layer 190 is flush with the top surface of the first isolation layer 210 .
  • the first dielectric layer 190 and part of the filling layer 160 can be removed in the same step; the top surface of the filling layer 160 and the first dielectric layer 190 The top surface is flush.
  • the first dielectric layer 190 , the first isolation layer 210 and the filling layer 160 may all be made of silicon oxide. Therefore, in the process of forming the patterned first initial isolation layer 211 Part of the first dielectric layer 190 and part of the filling layer 160 are also removed; in other embodiments, the materials of the first dielectric layer 190, the first isolation layer 210 and the filling layer 160 are different, so by separately patterning the first dielectric layer 190. The first isolation layer 210 and the filling layer 160 until the top surfaces of the first dielectric layer 190, the first isolation layer 210 and the filling layer 160 are flush. Patterning the first dielectric layer 190, the first isolation layer 210 and the filling layer 160 provides a process basis for subsequent formation of the word line structure.
  • a second protective layer 182 is formed.
  • the second protective layer 182 is located on the inner wall of the second groove 170 and the side wall of the first protective layer 181 .
  • the first protective layer 181 and the second protective layer 182 constitute the protective layer 180 .
  • the material of the second protective layer 182 is the same as the material of the first protective layer 181, which can be silicon nitride or other materials.
  • the second protective layer 182 can be formed by depositing silicon nitride.
  • the second protective layer 182 also covers the entire surface of the first isolation layer 210 , and the first isolation layer 210 can be removed by etching back. A portion of the second protective layer 182 on the surface to expose the first isolation layer 210 .
  • a word line structure 130 is formed, and the word line structure 130 is formed at the bottom of the second groove 170 .
  • the first dielectric layer 190 and part of the filling layer 160 are removed in the same step; the remaining filling layer 160 is flush with the upper surface of the first isolation layer 210 .
  • the materials of the first dielectric layer 190 and the filling layer 160 can be the same, so by removing the first dielectric layer 190 and the filling layer 160 in the same step, the process steps in the entire production process can be reduced, and the removal can be The height difference between the surfaces of the first dielectric layer 190 and the filling layer 160 is small, thereby increasing the reliability of the formed semiconductor structure.
  • a second dielectric layer 220 is formed.
  • the second dielectric layer 220 is located on the top surface of the first dielectric layer 190 and covers part of the sidewalls of the channel columnar structure 110 .
  • the second dielectric layer 220 can be formed by thermal oxidation; in other embodiments, the second dielectric layer 220 can also be formed by deposition.
  • the second dielectric layer 220 may serve as the dielectric layer 140 (refer to FIG. 1 ), thereby avoiding direct contact between the word line structure and the channel pillar structure 110 .
  • an initial word line structure 131 is formed, and the initial word line structure 131 fills the first groove 150 and the second groove 170 .
  • the material of the initial word line structure 131 can be a metal material such as tungsten. By setting the material of the initial word line structure 131 to a metal material, the transmission rate of the word line structure can be improved.
  • the protective layer 180 is used as a mask to pattern the initial word line structure 131 until the top surface of the first isolation layer 210 is exposed, and the remaining initial word line structure 131 serves as the word line structure 130 .
  • patterning the initial word line structure 131 includes: removing the initial word line structure 131 between the protective layer 180 and the initial word line structure 131 exposed by the protective layer 180 to form words spaced apart along the second direction Y.
  • Line structure 130 includes word line structures 130 located on the sidewalls of channel columnar structures 110 distributed along the first direction X and channel columnar structures 110 spaced apart along the second direction Y.
  • the word line structure 130 is formed to form the word line structure 130 surrounding the channel pillar structure 110. By forming the word line structure 130 surrounding the channel pillar structure 110, the integration density of the semiconductor structure can be increased.
  • an isolation structure 230 is formed.
  • the isolation structure 230 is located in the second groove 170 and between adjacent word line structures 130 .
  • a first isolation structure 231 is formed.
  • the first isolation structure 231 is located on the top surface of the first isolation layer 210 , the sidewalls of the word line structure 130 and the sidewalls of the protective layer 180 .
  • first isolation structure 231 adjacent word line structures 130 can be isolated, thereby avoiding interference between adjacent word line structures 130, thereby improving the reliability of the semiconductor structure.
  • the protective layer 180 (refer to Figure 17) is removed to form a third groove (not shown in the figure); a second isolation structure 232 is formed, and the second isolation structure 232 fills the third groove, and the first isolation
  • the structure 231 and the second isolation structure 232 constitute the isolation structure 230 .
  • the protective layer 180 can be etched away through the top surface along the BB direction cross-section, and then the corresponding material is deposited to form the second isolation structure 232.
  • the second isolation structure 232 can serve as a protective layer for the word line structure 130. , thereby reducing the stress on the word line structure 130 when the semiconductor structure is subjected to stress, thereby improving the reliability of the semiconductor structure.
  • the embodiment of the present disclosure forms a fully surrounding gate transistor structure by forming a word line structure 130 surrounding the channel columnar structure 110, and after forming the word line structure 130, an isolation structure 230 is also formed between adjacent word line structures 130.
  • the isolation structure 230 can increase the insulation between adjacent word line structures 130 so as to improve the performance of the semiconductor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a method of manufacturing a semiconductor structure.
  • the method of manufacturing the semiconductor structure is substantially the same as the previous embodiment.
  • the main differences include: a different method of forming a protective layer and a different structure of the protective layer.
  • the manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the previous embodiment can be referred to the corresponding description of the previous embodiment, and will not be described in detail below.
  • FIG. 19 is a top view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS. 20 to 30 are cross-sectional views along the dotted line direction of FIG. 19 .
  • the semiconductor structure includes: a substrate 300; channel column structures 310 spaced along the first direction X and the second direction Y; a bit line structure 320 extending along the first direction; and a word line structure extending along the second direction Y. 330; Dielectric layer 340 surrounding the surface of the channel columnar structure 310.
  • a substrate 300 is provided, and the substrate 300 includes: first grooves 350 spaced apart along the first direction X.
  • forming the filling layer 360 includes removing part of the filling layer 360 before patterning the substrate 300 . Removing part of the filling layer 360 provides a process basis for subsequent formation of the first initial protective layer 383 (refer to FIG. 23 ).
  • a first protective layer 381 is formed, and the first protective layer 381 is located on the top surface of the filling layer 360 .
  • the first initial protective layer 383 and the substrate 300 are patterned to form the second groove 370 , and the remaining first initial protective layer 383 serves as the first protective layer 381 .
  • the first groove 350 (refer to FIG. 20 ) and the second groove 370 surround the channel columnar structure 310 .
  • patterning the first initial protective layer 383 further includes forming a mask layer 384 , and the mask layer 384 may be made of the same material as the first initial protective layer 383 .
  • forming the second groove 370 also includes: forming a first dielectric layer 390.
  • the first dielectric layer 390 is located on the sidewall of the channel columnar structure 310.
  • the first dielectric layer 390 protects the channel when the bit line structure is subsequently formed. Column structure 310 is not affected.
  • a fourth groove 400 is formed.
  • the fourth groove 400 is located on the bottom surface of the second groove 370 .
  • the formation of the fourth groove 400 provides space and a process basis for the subsequent formation of the bit line structure.
  • a metal silicide process is used to form the first bit line conductive layer 321.
  • the first bit line conductive layer 321 is located on the surface of the fourth groove 400 facing the substrate 300; the second bit line conductive layer 322 is formed.
  • the second bit line conductive layer 322 fills the fourth groove 400, and the first bit line conductive layer 321 and the second bit line conductive layer 322 constitute the bit line structure 320.
  • Forming the first line conductive layer 321 through a metal silicide process can reduce the resistance of the first line conductive layer 321 .
  • the contact resistance between the bit line structure 320 and the substrate 300 can be reduced by forming the second bit line conductive layer 322 .
  • the bit line structure 320 is located on the bottom surface of the first dielectric layer 390 .
  • a first isolation layer 410 is formed.
  • the first isolation layer 410 is located in the second groove 370 and is located on the top surface of the bit line structure 320 .
  • the first isolation layer 410 can be formed by first filling the second groove 370 and then etching back.
  • a second protective layer 382 is formed.
  • the second protective layer 382 is located on the inner wall of the second groove 370 and the side wall of the first protective layer 381 .
  • the first protective layer 381 and the second protective layer 382 constitute the protective layer 380 .
  • the protective layer 380 can be used as a part of the isolation structure, and the protective layer 380 can also be used as a mask for subsequent formation of the word line structure.
  • the second protective layer 382 is also located on the sidewalls of the mask layer 384 .
  • the step of removing part of the filling layer 360 may further include: removing part of the filling layer 360 after forming the protective layer 380 and before forming the initial word line structure. Removing part of the filling layer 360 provides a process basis and space for subsequent formation of the initial word line structure.
  • a second dielectric layer 420 is also formed.
  • the second dielectric layer 420 can be formed by oxidizing part of the channel columnar structure 310 .
  • the dielectric layer 420 is located in the channel columnar structure 310; in another embodiment, a second dielectric layer can be formed by deposition, and the second dielectric layer is located on the sidewall of the channel columnar structure.
  • the second dielectric layer 420 is used to avoid direct contact between the word line structure and the channel pillar structure 310 .
  • second dielectric layer 420 is part of dielectric layer 340 (see Figure 19).
  • an initial word line structure 331 is formed.
  • the initial word line structure 331 is located on the top surface of the first dielectric layer 390 and the first isolation layer 410 and the bottom surface of the protective layer 380 .
  • the protective layer 380 is used as a mask to pattern the initial word line structure 331 until the top surface of the first isolation layer 410 is exposed, and the remaining initial word line structure 331 serves as the word line structure 330 .
  • the word line structure 330 includes a word line structure 330 located between the word line structures 330 on the sidewalls of the channel columnar structures 310 distributed along the first direction X and the channel columnar structures 310 spaced apart along the second direction Y to form a wraparound
  • the word line structure 330 of the channel columnar structure 310 can increase the integration density of the semiconductor structure by forming the wordline structure 330 surrounding the channel columnar structure 310 .
  • forming the isolation structure 430 may include: forming a first isolation structure 431 located on the top surface of the first isolation layer 410 , the sidewalls of the word line structure 330 and the sidewalls of the protective layer 380 .
  • An isolation structure 431 and protective layer 380 constitute the isolation structure 430.
  • mask layer 384 may also be part of isolation structure 430 .
  • the first initial protective layer 383 is formed before forming the channel columnar structure 310, and then the channel columnar structure 310 is formed. At this time, part of the top surface of the partial filling layer 360 includes the first protective layer 381, and then the third protective layer 383 is formed.
  • the second protective layer 382, the second protective layer 382 and the first protective layer 381 together serve as the protective layer 380. In the subsequent process of forming the word line structure 330, the protective layer 380 also serves as a mask.
  • Embodiments of the present disclosure form the word line structure 130 surrounding the channel columnar structure 110 to form a fully surrounding gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance of the semiconductor structure.
  • Yet another embodiment of the present disclosure also provides a method of manufacturing a semiconductor structure.
  • the method of manufacturing the semiconductor structure is substantially the same as the previous embodiment.
  • the main differences include: a method of forming the protective layer is different, and the structure of the protective layer is different.
  • the manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the previous embodiment can be referred to the corresponding description of the previous embodiment, and will not be described in detail below.
  • FIG. 32 is a top view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS. 33 to 40 are cross-sectional views along the dotted line direction of FIG. 32 .
  • the semiconductor structure includes: a substrate 500; channel column structures 510 spaced along the first direction X and the second direction Y; a bit line structure 520 extending along the first direction X; and a word line extending along the second direction Y.
  • a substrate 500 is provided.
  • the substrate 500 includes a filling layer 560.
  • the substrate 500 also includes second grooves 570 and one of the second grooves 570 spaced apart along the second direction Y (refer to Figure 32).
  • the channel columnar structure 510 between.
  • a method of forming a protective layer may include forming a first protective layer 581 located on the top surface of the substrate 500 .
  • the first dielectric layer 590 is used to protect the channel columnar structure 510 from subsequent formation of the bit line structure. Affected.
  • the bit line structure 520 is formed.
  • the method of forming the bit line structure 520 may include: forming a fourth groove (not shown in the figure), the fourth groove is located on the second groove 570 Bottom surface:
  • the first bit line conductive layer 521 is formed using a metal silicide process, and the first bit line conductive layer 521 is located on the surface of the fourth groove facing the substrate 500; the second bit line conductive layer 522 is formed, and the second bit line conductive layer 522 is formed.
  • the layer 522 fills the fourth groove, and the first bit line conductive layer 521 and the second bit line conductive layer 522 form the bit line structure 520 .
  • Forming the first bit line conductive layer 521 through a metal silicide process can reduce the resistance of the bit line structure 520, and forming the second bit line conductive layer 522 filling the fourth groove can reduce the resistance between the bit line structure 520 and the substrate 500. contact resistance, thereby improving the performance of the semiconductor structure.
  • a first isolation layer 610 is formed, the first isolation layer 610 is located in the second groove 570 , and the top surface of the first isolation layer 610 is lower than the bottom surface of the first protective layer 581 .
  • the method of forming the first isolation layer 610 may be to first form a first initial isolation layer that fills the second groove 570 , and then etching back the first initial isolation layer to form the first isolation layer 610 . During the process of etching back the first initial isolation layer, it also includes removing part of the first dielectric layer 590 and the filling layer 560 in the same step, so that the top surface of the first dielectric layer 590 is flush with the top surface of the first isolation layer 610 flat.
  • the first isolation layer 610 after forming the first isolation layer 610 , it also includes forming a second dielectric layer 620 .
  • the second dielectric layer 620 is located on the top surface of the first dielectric layer 590 and covers part of the sidewalls of the channel columnar structure 510 .
  • the second dielectric layer 620 can be formed by a thermal oxidation method.
  • the second dielectric layer 620 can be formed by oxidizing part of the sidewalls of the channel column structure 510.
  • the second dielectric layer 620 formed by the thermal oxidation method has a higher density, thereby serving as a dielectric layer 540 (refer to FIG. 32).
  • an initial word line structure 531 is formed.
  • the initial word line structure 531 fills the first groove and the second groove 570.
  • the top surface of the initial word line structure 531 is flush with the bottom surface of the first protective layer 581. .
  • the initial word line structure 531 includes a word line conductive layer 532 and a word line protective layer 533.
  • the word line conductive layer 532 is used to transmit signals
  • the word line protective layer 533 is used to protect the word line conductive layer 532. .
  • a second protective layer 582 is formed.
  • the second protective layer 582 is located on the sidewall of the first protective layer 581.
  • the second protective layer 582 is located on the top surface of the second groove 570.
  • the first protective layer 581 and the second protective layer 582 are formed on the sidewall of the first protective layer 581.
  • Layer 582 constitutes protective layer 580.
  • the protective layer 580 is used as a mask to pattern the initial word line structure 531 and the first isolation layer 610 until the top surface of the bit line structure 520 is exposed, and the remaining initial word line structure 531 serves as the word line structure 530 .
  • the initial word line structure 531 is patterned to form spaced word line structures 530, and to provide a process basis for subsequent formation of isolation structures with air gaps.
  • a first isolation structure 631 and a second isolation structure 632 are formed.
  • the first isolation structure 631 is an air gap surrounded by the first isolation layer 610, the word line structure 530 and the second isolation structure 632.
  • the second isolation structure 632 It is located between the word line structures 530 , and the top surface of the second isolation structure 632 is flush with the top surface of the word line structure 530 .
  • the second protective layer 582 is formed only on the substrate 500 when the second protective layer 582 is formed.
  • the protective layer 580 on the surface, and the isolation structure 630 with an air gap is subsequently formed when the isolation structure 630 is formed, thereby reducing the parasitic capacitance between adjacent word line structures 530.
  • Embodiments of the present disclosure form a word line structure 530 surrounding the channel columnar structure 510 to form a fully surrounding gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance of the semiconductor structure.
  • Embodiments of the present disclosure also provide a semiconductor structure, which can be formed using some or all of the above steps.
  • the manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. What needs to be explained are the same or corresponding parts of the previous embodiment. Reference can be made to the corresponding description of the previous embodiment and will not be described again.
  • Figures 1, 19 and 32 are top views of semiconductor structures provided by different embodiments of the present disclosure.
  • Figures 18, 29 and 36 are respectively Cross-sectional views along the dotted line direction in Figure 1, Figure 19 and Figure 32 provided by different embodiments of the present disclosure.
  • the semiconductor structure includes: a substrate 100; a channel columnar structure 110, the channel columnar structure 110 is located in the substrate 100, and the channel columnar structure 110 is spaced along the first direction X and the second direction Y.
  • bit line structure 120 the bit line structure 120 is connected with the channel column structure 110, the bit line structure 120 is arranged at intervals in the substrate 100 along the second direction Y, and the bit line structure 120 is located on the bottom surface of the channel column structure 110;
  • An isolation layer 210 the first isolation layer 210 is located on the top surface of the bit line structure 120;
  • a filling layer 160 the filling layer 160 is located in the substrate 100, and the top surface of the filling layer 160 is flush with the top surface of the first isolation layer 210 ;
  • Word line structure 130 the word line structure 130 surrounds the channel column structure 110, and is spaced apart along the second direction Y;
  • Isolation structure 230 the isolation structure 230 is at least located between adjacent word line structures 130;
  • Dielectric layer 140 dielectric layer 140 surrounds the channel columnar structure 110 surface.
  • the word line structure 130 By arranging the word line structure 130 to surround the channel columnar structure 110, a fully surrounding gate transistor structure can be formed, thereby improving the integration density of the semiconductor structure and satisfying the performance of the semiconductor structure.
  • the channel column structure 110 includes a first doping region, a channel region and a second doping region arranged in sequence.
  • the first doping region is in contact with the bit line structure 120, and the channel region and the second doping region are in contact with the bit line structure 120.
  • the impurity region is located between adjacent word line structures 130, and the doping ions of the first doping region, the channel region and the second doping region are the same.
  • a junctionless transistor can be formed by doping the channel columnar structure 110 with the same ion type.
  • the doping ions in the first doping region, the channel region and the second doping region are of the same type, for example, doping ions. They are all N-type ions.
  • the doping ions in the first doping region, the channel region and the second doping region can be the same.
  • "no junction" here refers to no PN junction, that is, there is no PN junction in the transistor composed of the channel columnar structure 110. Since the device is a junctionless transistor, it is helpful to avoid the use of ultra-steep source-drain concentration gradient doping process.
  • the phenomenon of making ultra-steep PN junctions in the nanoscale range can avoid problems such as threshold voltage drift and increase in leakage current caused by doping mutations. It is also conducive to suppressing the short channel effect and can still be achieved in the scale range of a few nanometers. work, thus helping to further improve the integration density and electrical performance of semiconductor structures. It can be understood that the additional doping here refers to the doping performed in order to make the doping ion type of the first doping region and the second doping region different from the doping ion type of the channel region.
  • the bit line structure 120 includes: a first bit line conductive layer 121 located within the substrate 100 , and the first bit line conductive layer 121 and the channel pillar structure 110 The bottom surface is in contact with the second bit line conductive layer 122, and the second bit line conductive layer 122 is located on the top surface of the first bit line conductive layer 121.
  • the first bit line conductive layer 121 the resistance of the bit line structure 120 can be reduced, and by forming the second bit line conductive layer 122, the transmission speed of the bit line structure 120 can be increased.
  • the top surface of the second bit line conductive layer 122 is lower than the bottom surface of the channel pillar structure 110
  • the bottom surface of the first isolation layer 210 is lower than the bottom surface of the channel pillar structure 110 .
  • the top surface of the second bit line conductive layer 122 is lower than the bottom surface of the channel pillar structure 110
  • part of the first isolation layer 210 is surrounded by the first bit line conductive layer 121 , thereby increasing the word line structure 130 and the bit line structure 120 insulation properties between.
  • a first dielectric layer 190 and a second dielectric layer 220 are also included.
  • the first dielectric layer 190 is located on the sidewall of the channel columnar structure 110
  • the second dielectric layer 220 is located on the first dielectric layer 190 .
  • the second dielectric layer 220 can serve as the dielectric layer 140 to avoid direct contact between the channel column structure 110 and the word line structure 130 .
  • the isolation structure 230 includes: a first isolation structure 231 located on the top surface of the first isolation layer 210 and the sidewall of the word line structure 130; a second isolation structure 232, The second isolation structure 232 is located on the top surface of the channel columnar structure 110 and between the channel columnar structure 110 and the first isolation structure 231 .
  • first isolation structure 231 adjacent word line structures 130 can be isolated to avoid interference between adjacent word line structures 130, thereby improving the reliability of the semiconductor structure.
  • the second isolation structure 232 the word line structure can be reduced The structure 130 is subjected to stress, thereby improving the reliability of the semiconductor structure.
  • the embodiment of the present disclosure forms a fully surrounding gate transistor structure by forming a word line structure 130 surrounding the channel columnar structure 110, and after forming the word line structure 130, an isolation structure 230 is also formed between adjacent word line structures 130.
  • the isolation structure 230 can increase the insulation between adjacent word line structures 130 so as to improve the performance of the semiconductor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance of the semiconductor structure.
  • Another embodiment of the present disclosure also provides another semiconductor structure, which is substantially the same as the previous embodiment, and the main differences include: the isolation structure.
  • the manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the previous embodiment can be referred to the corresponding description of the previous embodiment, and will not be described in detail below.
  • the semiconductor structure includes: a substrate 300; a channel columnar structure 310; a bit line structure 320 connected to the channel columnar structure 310; a first isolation layer 410, An isolation layer 410 is located on the top surface of the bit line structure 320; a filling layer 360, the filling layer 360 is located in the substrate 300, and the top surface of the filling layer 360 is flush with the top surface of the first isolation layer 410; the word line structure 330, The word line structure 330 surrounds the channel column structure 310; the isolation structure 430 is located at least between adjacent word line structures 330; and the dielectric layer 340 surrounds the surface of the channel column structure 310.
  • the bit line structure 320 includes: a first line conductive layer 321, the first line conductive layer 321 is located in the substrate 300, and the first line conductive layer 321 is in contact with the bottom surface of the channel columnar structure 310;
  • the line conductive layer 322 and the second bit line conductive layer 322 are located on the top surface of the first line conductive layer 321.
  • the isolation structure 430 may include: a protective layer 380 located on the top surface and part of the sidewall of the channel columnar structure 310; a first isolation structure 431 located on the first The top surface of the isolation layer 410 , the sidewalls of the word line structure 330 and the sidewalls of the protective layer 380 .
  • the word line structure 330 can be isolated from the outside world, thereby protecting the word line structure 330, and reducing the stress on the word line structure 330, thereby improving the reliability of the semiconductor structure.
  • the protective layer 380 may include: a first protective layer 381 and a second protective layer 382 .
  • the semiconductor structure further includes: a first dielectric layer 390 and a second dielectric layer 420.
  • the first dielectric layer 390 is located on the sidewall of the channel columnar structure 310
  • the second dielectric layer 420 is located on the sidewall of the channel columnar structure 310.
  • the second dielectric layer 420 can serve as the dielectric layer 340, thereby avoiding direct contact between the channel column structure 310 and the word line structure 330.
  • the semiconductor structure further includes: a mask layer 384 .
  • the mask layer is located on the top surface of the channel columnar structure 310 and can play a role in protecting the channel columnar structure 310 .
  • Embodiments of the present disclosure form a word line structure 330 surrounding the channel columnar structure 310 to form a fully surrounding gate transistor structure, thereby improving the integration density of the semiconductor structure while meeting the performance of the semiconductor structure.
  • Another embodiment of the present disclosure also provides another semiconductor structure, which is substantially the same as the previous embodiment, and the main differences include: the isolation structure.
  • the manufacturing method of a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the previous embodiment can be referred to the corresponding description of the previous embodiment, and will not be described in detail below.
  • the semiconductor structure includes: a substrate 500; a channel columnar structure 510; a bit line structure 520 connected to the channel columnar structure 510; a first isolation layer 610, An isolation layer 610 is located on the top surface of the bit line structure 520; a filling layer 560, the filling layer 560 is located in the substrate 500, and the top surface of the filling layer 560 is flush with the top surface of the first isolation layer 610; the word line structure 530, The word line structure 330 surrounds the channel column structure 510; the isolation structure 630 is located at least between adjacent word line structures 530; and the dielectric layer 540 surrounds the surface of the channel column structure 510.
  • the isolation structure 630 includes a first isolation structure 631 and a second isolation structure 632.
  • the first isolation structure 631 is surrounded by the first isolation layer 610, the word line structure 530 and the second isolation structure 632.
  • There is an air gap the second isolation structure 632 is located between the word line structures 530, and the top surface of the second isolation structure 632 is flush with the top surface of the word line structure 530.
  • the bit line structure 520 includes: a first bit line conductive layer 521 located within the substrate 500 , and the first bit line conductive layer 521 and the channel pillar structure 510 The bottom surface is in contact with the second bit line conductive layer 522, and the second bit line conductive layer 522 is located on the top surface of the first bit line conductive layer 521.
  • the word line structure 530 includes a stacked word line conductive layer 532 and a word line protective layer 533 .
  • the semiconductor structure also includes: a first dielectric layer 590 and a second dielectric layer 620.
  • the first dielectric layer 590 is located on the sidewall of the channel columnar structure 510.
  • the second dielectric layer 620 is located on the first dielectric layer 590.
  • the dielectric layer 620 can serve as the dielectric layer 540 to avoid direct contact between the channel pillar structure 510 and the word line structure 530 .
  • Embodiments of the present disclosure form a word line structure 530 surrounding the channel columnar structure 510 to form a fully surrounding gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance of the semiconductor structure.
  • a word line structure surrounding a channel columnar structure is formed to form a fully surrounding gate transistor structure, and after the word line structure is formed, an adjacent gate transistor structure is formed.
  • An isolation structure is formed between the word line structures. The isolation structure can increase the insulation between adjacent word lines and thereby improve the performance of the semiconductor structure. That is, the performance of the semiconductor structure can be improved while satisfying the density efficiency of the semiconductor structure.

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Abstract

本公开提供一种半导体结构的制作方法及其结构，其中，半导体结构的制作方法包括：提供衬底，衬底包括衬底内沿第一方向间隔分布第一凹槽以及位于第一凹槽内的填充层；图形化衬底，形成第二凹槽，且第二凹槽位于第一凹槽的顶面；在衬底表面沉积保护层，保护层与填充层不同；形成位线结构，位线结构形成在第二凹槽的底部；形成第一隔离层，第一隔离层位于第二凹槽内且位于位线结构的顶面；去除部分填充层，剩余填充层与第一隔离层上表面平齐，第一凹槽和第二凹槽形成通道柱状结构；形成字线结构，字线结构环绕通道柱状结构；形成隔离结构，隔离结构位于第二凹槽内且位于相邻的字线结构之间。

Description

一种半导体结构的制作方法及其结构
本公开基于申请号为202210556179.3、申请日为2022年05月20日、申请名称为“一种半导体结构的制作方法及其结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及其结构。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，在对动态存储器阵列结构中晶体管的排布方式以及如何缩小动态存储器阵列结构中单个功能器件的尺寸进行研究的同时，也需要提高小尺寸的功能器件的电学性能。
利用垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构作为动态存储器选择晶体管(access transistor)时，其占据的面积可以达到4F 2(F：在给定工艺条件下可获得的最小图案尺寸)，原则上可以实现更高的密度效率。
然而目前有必要提高半导体结构的性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及其结构。
本公开的第一方面提供了一种半导体结构的制作方法，包括：提供衬底，所述衬底包括衬底内沿第一方向间隔分布第一凹槽以及位于所述第一凹槽内的填充层；图形化所述衬底，形成第二凹槽，所述第二凹槽沿第二方向间隔分布，且所述第二凹槽位于所述第一凹槽的顶面，所述第一凹槽和所述第二凹槽形成通道柱状结构；在所述衬底表面形成保护层，所述保护层与所述填充层不同；形成位线结构，所述位线结构形成在所述第二凹槽的底部；形成第一隔离层，所述第一隔离层位于所述第二凹槽内且位于所述位线结构的顶面；去除部分所述填充层，剩余所述填充层与所述第一隔离层上表面平齐；形成字线结构，所述字线结构环绕所述通道柱状结构，且沿第二方向间隔分布；形成隔离结构，所述隔离结构位于所述第二凹槽内且位于相邻的所述字线结构之间。
其中，还包括：第一介质层，所述第一介质层位于所述位线结构的顶面及所述通道柱状结构的侧壁，形成所述保护层的方法包括：形成第一保护层，所述第一保护层位于所述衬底的顶面；图形化部分所述第一介质层，以暴露部分所述第二凹槽的内壁；形成第二保护层，所述第二保护层位于所述第二凹槽的内壁及所述第一保护层的侧壁，所述第一保护层与所述第二保护层构成所述保护层。
其中，形成所述字线结构的方法包括：形成所述保护层后，图形化所述第一介质层，以使所述第一介质层的顶面与所述第一隔离层的顶面齐平；形成第二介质层，所述第二介质层位于所述第一介质层的顶面，且覆盖部分所述通道柱状结构的侧壁；形成初始字线结构，所述初始字线结构填充满所述第一凹槽及所述第二凹槽；以所述保护层为掩膜图形化所述初始字线结构，直至暴露所述第一隔离层的顶面，剩余所述初始字线结构作为所述字线结构。
其中，去除部分所述填充层的步骤包括：形成所述保护层前，在同一步中去除所述第一介质层及部分所述填充层；所述填充层的顶面与所述第一介质层的顶面齐平；形成所述保护层后，在同一步中去除所述第一介质层及部分所述填充层；剩余 所述填充层与所述第一隔离层的上表面齐平。
其中，形成所述隔离结构的方法包括：形成第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面、所述字线结构的侧壁及所述保护层的侧壁；形成第二隔离结构，所述第二隔离结构填充满所述第三凹槽，所述第一隔离结构及所述第二隔离结构构成所述隔离结构。
其中，形成所述保护层的方法包括：图形化所述衬底前，还包括：去除部分所述填充层，在所述填充层的顶面形成第一初始保护层；图形化所述第一初始保护层及所述衬底，以形成所述第二凹槽，剩余所述第一初始保护层作为第一保护层；形成第二保护层，所述第二保护层位于所述第二凹槽的内壁及所述第一保护层的侧壁，所述第一保护层与所述第二保护层构成所述保护层。
其中，还包括：第一介质层，所述第一介质层位于所述位线结构的顶面及所述通道柱状结构的侧壁，形成所述字线结构的方法包括：形成初始字线结构，所述初始字线结构位于所述第一介质层及所述第一隔离层的顶面及所述保护层的底面；以所述保护层为掩膜图形化所述初始字线结构及所述第一隔离层，直至暴露所述第一隔离层的顶面，剩余所述初始字线结构作为所述字线结构。
其中，去除部分所述填充层的步骤包括：图形化所述衬底前，去除部分所述填充层；形成所述保护层之后，形成初始字线结构之前，去除部分所述填充层。
其中，形成所述隔离结构的方法包括：形成第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面，所述字线结构的侧壁及所述保护层的侧壁，所述第一隔离结构及所述保护层构成所述隔离结构。
其中，形成所述保护层的方法包括：形成第一保护层，所述第一保护层位于所述衬底的顶面；形成第二保护层，所述第二保护层位于所述第一保护层的侧壁，所述第二保护层位于所述第二凹槽的顶面，所述第一保护层及所述第二保护层构成所述保护层。
其中，还包括：第一介质层，所述第一介质层位于所述位线结构的顶面及所述通道柱状结构的侧壁，形成所述字线结构的方法包括：在同一步中去除部分所述第一介质层及所述填充层，以使所述第一介质层的顶面与所述第一隔离层上表面齐平；形成第二介质层，所述第二介质层位于所述第一介质层的顶面，且覆盖部分所述通道柱状结构的侧壁；形成初始字线结构，所述初始字线结构填充满所述第一凹槽及所述第二凹槽，所述初始字线结构的顶面与所述第一保护层的底面齐平；以所述保护层为掩膜图形化所述初始字线结构及第一隔离层，直至暴露所述位线结构的顶面，剩余所述初始字线结构作为所述字线结构。
其中，形成所述隔离结构的方法包括：形成第一隔离结构及第二隔离结构，所述第一隔离结构为所述第一隔离层、所述字线结构及所述第二隔离结构围成的空气间隙，所述第二隔离结构位于所述字线结构之间，且所述第二隔离结构的顶面与所述字线结构的顶面齐平。
其中，形成所述位线结构的方法包括：形成第四凹槽，所述第四凹槽位于所述第二凹槽的底面；采用金属硅化物工艺的形成第一位线导电层，所述第一位线导电层位于所述第四凹槽朝向所述衬底的表面；形成第二位线导电层，所述第二位线导电层填充满所述第四凹槽，所述第一位线导电层及所述第二位线导电层构成所述位线结构。
本公开的第二方面提供了一种半导体结构，包括：衬底，通道柱状结构，所述通道柱状结构位于所述衬底内，且所述通道柱状结构沿第一方向及第二方向间隔排布；位线结构，所述位线结构与所述通道柱状结构连通，所述位线结构沿所述第二方向间隔排布于所述衬底内，且所述位线结构位于所述通道柱状结构底面；第一隔 离层，所述第一隔离层位于所述位线结构的顶面；填充层，所述填充层位于所述衬底内，且所述填充层的顶面与所述第一隔离层的顶面齐平；字线结构，所述字线结构环绕所述通道柱状结构，且沿所述第二方向间隔分布；隔离结构，所述隔离结构至少位于相邻的所述字线结构之间。
其中，所述隔离结构包括第一隔离结构及第二隔离结构，所述第一隔离结构为所述第一隔离层、所述字线结构及所述第二隔离结构围成的空气间隙，所述第二隔离结构位于所述字线结构之间，且所述第二隔离结构的顶面与所述字线结构的顶面齐平。
其中，所述隔离结构包括：保护层，所述保护层位于所述通道柱状结构的顶面及部分侧壁；第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面，所述字线结构的侧壁及所述保护层的侧壁。
其中，所述隔离结构包括：第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面、所述字线结构的侧壁；第二隔离结构，所述第二隔离结构位于所述通道柱状结构的顶面及所述通道柱状结构与所述第一隔离结构之间。
其中，所述位线结构包括：第一位线导电层，所述第一位线导电层位于所述衬底内，且所述第一位线导电层与所述通道柱状结构底面接触；第二位线导电层，所述第二位线导电层位于所述第一位线导电层顶面。
其中，部分第二位线导电层的顶面低于所述通道柱状结构底面，且所述第一隔离结构的底面低于所述通道柱状结构的底面。
本公开实施例所提供的半导体结构的制作方法及其结构中，通过形成环绕通道柱状结构的字线结构以形成全环绕栅极晶体管结构，且在形成字线结构之后还在相邻的字线结构之间形成隔离结构，通过隔离结构可以增加相邻字线之间的绝缘性从而可以提高半导体结构的性能，即，在满足半导体结构密度效率的同时提高半导体结构的性能。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1至图18为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图；
图19至图31为本公开另一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图；
图32至图40为本公开又一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，随着集成密度的不断增加，如何平衡半导体结构中的单个功能器件的尺寸和小尺寸功能器件的电学性能成为一个问题，因此有必要提供一种半 导体结构的制作方法及其结构，以在满足半导体结构集成密度的同时满足半导体结构的性能需求。
本公开实施提供一种半导体结构的制作方法，通过形成环绕通道柱状结构的字线结构以形成全环绕栅极晶体管结构，通过在字线结构之间形成隔离结构，可以避免相邻字线之间的电连接，从而可以在满足半导体结构的集成密度的同时满足半导体结构的性能需求。
参考图1，图1为本公开实施例提供的一种半导体结构的俯视图。
在一些实施例中，半导体结构包括：衬底100；通道柱状结构110，通道柱状结构110位于衬底100内，且通道柱状结构110沿第一方向X及第二方向Y间隔排布；位线结构120，位线结构120与通道柱状结构110连通，位线结构120沿第二方向Y间隔排布于衬底100内，且位线结构120位于通道柱状结构110底面；字线结构130，字线结构130环绕通道柱状结构110，且沿第二方向Y间隔分布。
在一些实施例中，通道柱状结构110的周围还形成有介质层140，介质层140包绕通道柱状结构110一圈，以避免通道柱状结构110与字线结构130直接接触。
通过形成包绕通道柱状结构110的字线结构130可以形成全环绕栅极结构，从而可以在满足半导体结构的集成密度的同时满足半导体结构的性能需求。
参考图2至图4，图2至图4为本公开实施例沿图1虚线方向的剖视图。
提供衬底100，衬底100包括衬底100内沿第一方向X间隔分布第一凹槽150以及位于第一凹槽150内的填充层160。
在一些实施例中，参考图3，可以通过自对准双重图形技术(Self-aligned Double Patterning，SADP)工艺形成第一凹槽150，在另一些实施例中，还可以通过自对准四重图形技术(Self Aligned Quadruple Patterning，简称SAQP)工艺形成第一凹槽150。通过SADP或者SAQP技术可以使形成的第一凹槽150的图形更精确。
在一些实施例中，衬底100的材料可以是硅、锗或者锗化硅等材料，且还可以在衬底100的材料中进行掺杂，以衬底100的材料是硅为例，在衬底100中掺杂微量的三价元素，例如：硼、铟、镓或铝等，从而可以形成P型基底；同理，在衬底100中掺杂微量的五价元素，例如：磷、锑、砷等，从而可以形成N型基底，衬底100掺杂元素的选择可以根据实际的需求及产品性能等方面进行考量，本公开不对衬底100的材料及掺杂的元素进行限制。
在一些实施例中，参考图4，填充层160的材料可以是氧化硅或者氮化硅等绝缘材料。
在一些实施例中，填充层160还覆盖衬底100的顶面，可以通过化学研磨的方式去除掉位于衬底100顶面的填充层160以暴露衬底100的顶面。
参考图5至图12，图形化衬底100，形成第二凹槽170，第二凹槽170沿第二方向Y间隔分布，且第二凹槽170位于第一凹槽150(参考图3)的顶面，第一凹槽150和第二凹槽170形成通道柱状结构110；在衬底100表面形成保护层180，保护层180与填充层160不同。
参考图5，形成第一保护层181，第一保护层181位于衬底100的顶面。
在一些实施例中，第一保护层181的材料可以是氮化硅等材料，氮化硅的材料较硬，从而在后续步骤中，第一保护层181的形貌不会发生大的改变，从而后续以第一保护层181为掩膜进行图形化时，形成的图案更加精确。
参考图6，形成第一介质层190，第一介质层190位于通道柱状结构110的侧壁；在一些实施例中可以通过热氧化通道柱状结构110的方式形成第一介质层190，第一介质层190用于在后续形成位线结构的时候保护通道柱状结构110。
在一些实施例中，第一介质层190还位于第二凹槽170的底面，可以通过回刻蚀 的方式去除位于第二凹槽170底面的第一介质层190以暴露衬底100的表面，通过保留通道柱状结构110侧壁的第一介质层190可以保护通道柱状结构110在后续形成位线结构的时候不被污染。
参考图7至图9，形成位线结构120；位线结构120形成在第二凹槽170的底部。
示例性的，参考图7，形成第四凹槽200，第四凹槽200位于第二凹槽170的底面。
在一些实施例中，第四凹槽200在沿第一方向X上的宽度可以大于相邻通道柱状结构110之间间距，从而在后续形成位线结构120的过程中需要金属硅化的基底材料较少，从而便于形成连续第一位线导电层121，进而提高位线结构120的传输速率。在另一些实施例中，第四凹槽200在沿第一方向X上的宽度可以等于相邻通道柱状结构110之间间距。
在一些实施例中，第四凹槽200在沿第一方向X(参考图1)上的剖面图的形状可以是椭圆，可以是半圆，在另一些实施例中，第四凹槽200在沿第一方向X上的剖面图的形状还可以是矩形。
参考图8，采用金属硅化物工艺的形成第一位线导电层121，第一位线导电层121位于第四凹槽200朝向衬底100的表面。
在一些实施例中，通过在衬底100表面形成一层金属层，并通过快速热退火处理以及选择性湿法刻蚀处理，从而在衬底100内形成第一位线导电层121。金属层的材料可以是例如钛、钴等金属。形成第一位线导电层121之后还包括去除金属层。通过金属硅化物工艺的方式形成第一位线导电层121可以降低第一位线导电层121的电阻。
参考图9，形成第二位线导电层122，第二位线导电层122填充满第四凹槽200，第一位线导电层121及第二位线导电层122构成位线结构120。位线结构120位于第一介质层190的底面。
在一些实施例中，第二位线导电层122的材料可以是金属，通过设置第二位线导电层122的材料为金属可以提高位线结构120的传导速度，从而提高半导体结构的响应速度。
参考图10及图11，形成第一隔离层210。
示例性的，参考图10，形成第一初始隔离层211。
在一些实施例中，第一初始隔离层211填充满第二凹槽170(参考图9)，第一初始隔离层211的材料可以与填充层160的材料相同，从而可以减少生产过程中的材料种类，且为后续在同一步中去除部分填充层160及第一初始隔离层211提供基础。
参考图10和图11，图形化第一初始隔离层211，以形成第一隔离层210；去除部分填充层160，剩余填充层160与第一隔离层210上表面平齐。
在一些实施例中，参考图10和图11，图形化第一初始隔离层211的过程中，还包括：图形化部分第一介质层190，以暴露部分第二凹槽170(参考图9)的内壁，且第一介质层190的顶面与第一隔离层210的顶面齐平。
在一些实施例中，参考图11，形成保护层180(参考图12)前，可以在同一步中去除第一介质层190及部分填充层160；填充层160的顶面与第一介质层190的顶面齐平。
在一些实施例中，参考图10和图11，第一介质层190、第一隔离层210及填充层160的材料可以相同都为氧化硅，故在形成图形化第一初始隔离层211的过程中还去除部分第一介质层190及部分填充层160；在另一些实施例中，第一介质层190、第一隔离层210及填充层160的材料不同，故通过分别图形化第一介质层190、第一隔离层210及填充层160，直至第一介质层190、第一隔离层210及填充层160的顶 面齐平。通过图形化第一介质层190、第一隔离层210及填充层160为后续形成字线结构提供工艺基础。
参考图12，形成第二保护层182，第二保护层182位于第二凹槽170的内壁及第一保护层181的侧壁，第一保护层181与第二保护层182构成保护层180。
在一些实施例中，第二保护层182的材料与第一保护层181的材料相同，都可以为氮化硅等材料，可以通过沉积氮化硅的方式形成第二保护层182。
在一些实施例中，参考图12，沉积形成第二保护层182的过程中，第二保护层182还覆盖第一隔离层210的整个表面，可以通过回刻蚀的方式去除第一隔离层210表面的部分第二保护层182，以暴露第一隔离层210。
参考图13至图16，形成字线结构130，字线结构130形成在第二凹槽170的底部。
示例性的，参考图13，形成保护层180后，还包括在同一步中去除第一介质层190及部分填充层160；剩余填充层160与第一隔离层210的上表面齐平。
可以理解的是，第一介质层190及填充层160的材料可以相同，故通过在同一步中去除第一介质层190及填充层160可以减少整个生产过程中的工艺步骤，且可以使去除后的第一介质层190及填充层160表面的高度差较小，从而增加形成的半导体结构的可靠性。
参考图14，形成第二介质层220，第二介质层220位于第一介质层190的顶面，且覆盖部分通道柱状结构110的侧壁。
在一些实施例中，可以通过热氧化法形成第二介质层220；在另一些实施例中，还可以通过沉积的方式形成第二介质层220。第二介质层220可以作为介质层140(参考图1)，从而可以避免字线结构与通道柱状结构110直接接触。
参考图15，形成初始字线结构131，初始字线结构131填充满第一凹槽150及第二凹槽170。
在一些实施例中，初始字线结构131的材料可以是钨等金属材料，通过设置初始字线结构131的材料为金属材料可以提高字线结构的传输速率。
参考图15和图16，以保护层180为掩膜图形化初始字线结构131，直至暴露第一隔离层210的顶面，剩余初始字线结构131作为字线结构130。
在一些实施例中，图形化初始字线结构131包括：去除位于保护层180之间初始字线结构131及保护层180暴露的初始字线结构131，以形成沿第二方向Y间隔分布的字线结构130，可以理解的是，字线结构130包括位于通道柱状结构110沿第一方向X分布的侧壁上的字线结构130及沿第二方向Y间隔分布的通道柱状结构110之间的字线结构130，以形成包绕通道柱状结构110的字线结构130，通过形成包绕通道柱状结构110的字线结构130可以提高半导体结构的集成密度。
参考图17及图18，形成隔离结构230，隔离结构230位于第二凹槽170内且位于相邻的字线结构130之间。
参考图17，形成第一隔离结构231，第一隔离结构231位于第一隔离层210的顶面、字线结构130的侧壁及保护层180的侧壁。通过形成第一隔离结构231可以将相邻字线结构130进行隔离，从而避免相邻字线结构130之间产生干扰，从而提高半导体结构的可靠性。
参考图18，去除保护层180(参考图17)，以形成第三凹槽(图中未示出)；形成第二隔离结构232，第二隔离结构232填充满第三凹槽，第一隔离结构231及第二隔离结构232构成隔离结构230。在一些实施例中，可以通过沿BB方向剖面的顶面刻蚀掉保护层180，然后在沉积相应的材料以形成第二隔离结构232，第二隔离结构232可以作为字线结构130的保护层，从而在半导体结构受到应力作用时，降低字线 结构130受到的应力作用，从而提高半导体结构的可靠性。
本公开实施例通过形成包绕通道柱状结构110的字线结构130以形成全环绕栅极晶体管结构，且在形成字线结构130之后还在相邻的字线结构130之间形成隔离结构230，通过隔离结构230可以增加相邻字线结构130之间的绝缘性从而可以提高半导体结构的性能，从而在满足半导体结构的性能的同时提高半导体结构的集成密度。
本公开另一实施例还提供一种半导体结构的制作方法，该半导体结构的制作方法与前述实施例大致相同，主要区别包括：形成保护层的方法不同，且保护层的结构不同。以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图19至图30，图19为本公开实施例提供的一种半导体结构的俯视图，图20至图30为沿图19虚线方向的剖视图。
参考图19，半导体结构包括：衬底300；沿第一方向X及第二方向Y间隔的通道柱状结构310；沿第一方向延伸的位线结构320；沿第二方向Y延伸的字线结构330；环绕通道柱状结构310表面的介质层340。
参考图20，提供衬底300，衬底300包括：沿第一方向X间隔分布的第一凹槽350。
参考图21，形成填充层360，在图形化衬底300之前还包括：去除部分填充层360。通过去除部分填充层360为后续形成第一初始保护层383(参考图23)提供工艺基础。
参考图23，形成第一保护层381，第一保护层381位于填充层360顶面。
参考图22和图23，图形化第一初始保护层383及衬底300，以形成第二凹槽370，剩余第一初始保护层383作为第一保护层381。第一凹槽350(参考图20)及第二凹槽370围成通道柱状结构310。
在一些实施例中，参考图23，图形化第一初始保护层383之前还包括形成掩膜层384，掩膜层384可以与第一初始保护层383的材料相同。
参考图24，形成第二凹槽370之后还包括：形成第一介质层390，第一介质层390位于通道柱状结构310的侧壁，通过第一介质层390保护后续形成位线结构的时候通道柱状结构310不受影响。
继续参考图24，形成第四凹槽400，第四凹槽400位于第二凹槽370的底面，通过形成第四凹槽400为后续形成位线结构提供空间及工艺基础。
参考图24和25，采用金属硅化物工艺的形成第一位线导电层321，第一位线导电层321位于第四凹槽400朝向衬底300的表面；形成第二位线导电层322，第二位线导电层322填充满第四凹槽400，第一位线导电层321及第二位线导电层322构成位线结构320。通过金属硅化物工艺的方式形成第一位线导电层321可以降低第一位线导电层321的电阻。通过形成第二位线导电层322可以降低位线结构320与衬底300之间的接触电阻。位线结构320位于第一介质层390的底面。
参考图26，形成第一隔离层410，第一隔离层410位于第二凹槽370内，且位于位线结构320的顶面。在一些实施例中，可以通过先填充满第二凹槽370，再回刻蚀的方式形成第一隔离层410。
参考图27，形成第二保护层382，第二保护层382位于第二凹槽370的内壁及第一保护层381的侧壁，第一保护层381与第二保护层382构成保护层380。保护层380可以作为隔离结构的一部分，且保护层380还可以作为后续形成字线结构的掩膜。
在一些实施例中，参考图27，第二保护层382还位于掩膜层384的侧壁。
参考图28，在一些实施例中，去除部分填充层360的步骤还可以包括：形成保护 层380之后，形成初始字线结构之前，去除部分填充层360。通过去除部分填充层360为后续形成初始字线结构提供工艺基础，提供空间。
在一些实施例中，参考图28，去除填充层360后，还包括形成第二介质层420，在一些实施例中，可以通过氧化部分通道柱状结构310的方式形成第二介质层420，第二介质层420位于通道柱状结构310内；在另一实施例中，可以通过沉积的方式形成第二介质层，第二介质层位于通道柱状结构的侧壁。第二介质层420用于避免字线结构与通道柱状结构310直接接触。
在一些实施例中，第二介质层420为介质层340(参考图19)的一部分。
参考图29，形成初始字线结构331，初始字线结构331位于第一介质层390及第一隔离层410的顶面及保护层380的底面。
参考图30，以保护层380为掩膜图形化初始字线结构331，直至暴露第一隔离层410的顶面，剩余初始字线结构331作为字线结构330。字线结构330包括位于通道柱状结构310沿第一方向X分布的侧壁上的字线结构330及沿第二方向Y间隔分布的通道柱状结构310之间的字线结构330，以形成包绕通道柱状结构310的字线结构330，通过形成包绕通道柱状结构310的字线结构330可以提高半导体结构的集成密度。
参考图31，形成隔离结构430，可以包括：形成第一隔离结构431，第一隔离结构431位于第一隔离层410的顶面，字线结构330的侧壁及保护层380的侧壁，第一隔离结构431及保护层380构成隔离结构430。通过形成隔离结构430可以将字线结构330与外界隔离开，从而可以起到保护字线结构330的作用，且可以降低字线结构130受到的应力作用，从而提高半导体结构的可靠性。
在一些实施例中，参考图31，掩膜层384也可以作为隔离结构430的一部分。
本公开实施例通过在形成通道柱状结构310之前先形成第一初始保护层383，然后再形成通道柱状结构310，此时部分填充层360的部分顶面包括第一保护层381，然后再形成第二保护层382，第二保护层382和第一保护层381一起作为保护层380，在后续形成字线结构330的过程中，保护层380还作为掩膜。
本公开实施例通过形成包绕通道柱状结构110的字线结构130以形成全环绕栅极晶体管结构，从而在满足半导体结构的性能的同时提高半导体结构的集成密度。
本公开又一实施例还提供一种半导体结构的制作方法，该半导体结构的制作方法与前述实施例大致相同，主要区别包括：形成保护层的方法不同，且保护层的结构不同。以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图32至图40，图32为本公开实施例提供的一种半导体结构的俯视图，图33至图40为沿图32虚线方向的剖视图。
参考图32，半导体结构包括：衬底500；沿第一方向X及第二方向Y间隔的通道柱状结构510；沿第一方向X延伸的位线结构520；沿第二方向Y延伸的字线结构530；环绕通道柱状结构表面的介质层540。
参考图33，提供衬底500，衬底500上包括填充层560，衬底500上还包括沿第二方向Y(参考图32)间隔排布的第二凹槽570及第二凹槽570之间的通道柱状结构510。
在一些实施例中，参考图33，形成保护层的方法可以包括：形成第一保护层581，第一保护层581位于衬底500的顶面。
在一些实施例中，参考图34，还包括在通道柱状结构510的侧壁上形成第一介质层590，第一介质层590用于后续在形成位线结构的过程中保护通道柱状结构510不 受影响。
参考图34，形成位线结构520，在一些实施例中，形成位线结构520的方法可以包括：形成第四凹槽(图中未示出)，第四凹槽位于第二凹槽570的底面；采用金属硅化物工艺的形成第一位线导电层521，第一位线导电层521位于第四凹槽朝向衬底500的表面；形成第二位线导电层522，第二位线导电层522填充满第四凹槽，第一位线导电层521及第二位线导电层522构成位线结构520。
通过金属硅化物工艺形成第一位线导电层521可以减低位线结构520的电阻，通过形成填充满第四凹槽的第二位线导电层522可以降低位线结构520与衬底500之间的接触电阻，从而可以提高半导体结构的性能。
参考图35，形成第一隔离层610，第一隔离层610位于第二凹槽570内，且第一隔离层610的顶面低于第一保护层581的底面。在一些实施例中，形成第一隔离层610的方法可以是先形成填充满第二凹槽570的第一初始隔离层，再回刻蚀第一初始隔离层以形成第一隔离层610。在回刻蚀第一初始隔离层的过程中，还包括同一步中去除部分第一介质层590及填充层560，以使第一介质层590的顶面与第一隔离层610的上表面齐平。
参考图35，在形成第一隔离层610后还包括：形成第二介质层620，第二介质层620位于第一介质层590的顶面，且覆盖部分通道柱状结构510的侧壁。在一些实施例中，可以通过热氧化法形成第二介质层620，通过氧化部分通道柱状结构510的侧壁以形成第二介质层620，通过热氧化法形成第二介质层620具有较高的致密度，从而可以作为介质层540(参考图32)。
参考图36及图37，形成初始字线结构531，初始字线结构531填充满第一凹槽及第二凹槽570，初始字线结构531的顶面与第一保护层581的底面齐平。
在一些实施例中，参考图37初始字线结构531包括字线导电层532及字线保护层533，字线导电层532用于传递信号，字线保护层533用于保护字线导电层532。
参考图38，形成第二保护层582，第二保护层582位于第一保护层581的侧壁，第二保护层582位于第二凹槽570的顶面，第一保护层581及第二保护层582构成保护层580。通过形成第二保护层582为后续图形化初始字线结构531提供掩膜，通过控制第二保护层581的宽度可以控制后续形成的相邻字线结构之间间距。
参考图38和图39，以保护层580为掩膜图形化初始字线结构531及第一隔离层610，直至暴露位线结构520的顶面，剩余初始字线结构531作为字线结构530。通过图形化初始字线结构531以形成间隔排布的字线结构530，且为后续形成具有空气间隙的隔离结构提供工艺基础。
参考图40，形成第一隔离结构631及第二隔离结构632，第一隔离结构631为第一隔离层610、字线结构530及第二隔离结构632围成的空气间隙，第二隔离结构632位于字线结构530之间，且第二隔离结构632的顶面与字线结构530的顶面齐平。通过形成具有空气间隙的隔离结构630可以减少相邻字线结构530之间的寄生电容，从而可以提高半导体结构的电学性能。
本公开实施例通过在形成初始字线结构531的时候形成填充满第一凹槽及第二凹槽570的初始字线结构531，从而在形成第二保护层582的时候形成仅位于衬底500表面的保护层580，且后续在形成隔离结构630的时候形成具有空气间隙的隔离结构630，从而可以减少相邻字线结构530之间的寄生电容。
本公开实施例通过形成包绕通道柱状结构510的字线结构530以形成全环绕栅极晶体管结构，从而在满足半导体结构的性能的同时提高半导体结构的集成密度。
本公开实施例还提供一种半导体结构，可以采用上述部分或者全部步骤形成。以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要 说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图1、图18、图19、图30、图32及图40，图1、图19及图32为本公开不同实施例提供的半导体结构的俯视图，图18、图29及图36分别为本公开不同实施例提供的沿图1、图19及图32虚线方向的剖视图。
示例性的，参考图1及图18，半导体结构包括：衬底100；通道柱状结构110，通道柱状结构110位于衬底100内，且通道柱状结构110沿第一方向X及第二方向Y间隔排布；位线结构120，位线结构120与通道柱状结构110连通，位线结构120沿第二方向Y间隔排布于衬底100内，且位线结构120位于通道柱状结构110底面；第一隔离层210，第一隔离层210位于位线结构120的顶面；填充层160，填充层160位于衬底100内，且填充层160的顶面与第一隔离层210的顶面齐平；字线结构130，字线结构130环绕通道柱状结构110，且沿第二方向Y间隔分布；隔离结构230，隔离结构230至少位于相邻的字线结构130之间；介质层140，介质层140环绕通道柱状结构110表面。
通过设置字线结构130环绕通道柱状结构110可以形成全环绕栅极晶体管结构，从而可以提高半导体结构的集成密度，且还可以满足半导体结构的性能。
在一些实施例中，通道柱状结构110包括依次排列的第一掺杂区、沟道区以及第二掺杂区，第一掺杂区与位线结构120相接触，沟道区及第二掺杂区位于相邻的字线结构130之间，且第一掺杂区、沟道区及第二掺杂区的掺杂离子相同。
通过对通道柱状结构110掺杂相同的离子类型可以形成无结晶体管，无结晶体管即第一掺杂区、沟道区和第二掺杂区中的掺杂离子的类型相同，例如掺杂离子均为N型离子，进一步地，第一掺杂区、沟道区和第二掺杂区中的掺杂离子可以相同。其中，此处的“无结”指的是无PN结，即通道柱状结构110构成的晶体管中没有PN结，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。可以理解的是，此处额外的掺杂指的是，为了让第一掺杂区和第二掺杂区的掺杂离子类型与沟道区的掺杂离子类型不同而进行的掺杂。
在一些实施例中，参考图18，位线结构120包括：第一位线导电层121，第一位线导电层121位于衬底100内，且第一位线导电层121与通道柱状结构110底面接触；第二位线导电层122，第二位线导电层122位于第一位线导电层121顶面。通过形成第一位线导电层121可以降低位线结构120的电阻，通过形成第二位线导电层122可以提高位线结构120的传输速度。
在一些实施例中，参考图18，第二位线导电层122的顶面低于通道柱状结构110底面，且第一隔离层210的底面低于通道柱状结构110的底面。换句话说，第二位线导电层122的顶面低于通道柱状结构110的底面，部分第一隔离层210被第一位线导电层121环绕，从而增加字线结构130和位线结构120之间的绝缘性能。
在一些实施例中，参考图1及图18，还包括第一介质层190及第二介质层220，第一介质层190位于通道柱状结构110的侧壁，第二介质层220位于第一介质层190上，第二介质层220可以作为介质层140，从而避免通道柱状结构110与字线结构130直接接触。
在一些实施例中，参考图18，隔离结构230包括：第一隔离结构231，第一隔离结构231位于第一隔离层210的顶面、字线结构130的侧壁；第二隔离结构232，第二隔离结构232位于通道柱状结构110的顶面及通道柱状结构110与所述第一隔离结 构231之间。通过形成第一隔离结构231可以将相邻字线结构130进行隔离，从而避免相邻字线结构130之间产生干扰，从而提高半导体结构的可靠性，通过形成第二隔离结构232可以降低字线结构130受到的应力作用，从而提高半导体结构的可靠性。
本公开实施例通过形成包绕通道柱状结构110的字线结构130以形成全环绕栅极晶体管结构，且在形成字线结构130之后还在相邻的字线结构130之间形成隔离结构230，通过隔离结构230可以增加相邻字线结构130之间的绝缘性从而可以提高半导体结构的性能，从而在满足半导体结构的性能的同时提高半导体结构的集成密度。
本公开另一实施例还提供另一种半导体结构，该半导体结构与前述实施例大致相同，主要区别包括：隔离结构的不同。以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图19及图31，在另一些实施例中，半导体结构包括：衬底300；通道柱状结构310；位线结构320，位线结构320与通道柱状结构310连通；第一隔离层410，第一隔离层410位于位线结构320的顶面；填充层360，填充层360位于衬底300内，且填充层360的顶面与第一隔离层410的顶面齐平；字线结构330，字线结构330环绕通道柱状结构310；隔离结构430，隔离结构430至少位于相邻的字线结构330之间；介质层340，介质层340环绕通道柱状结构310表面。
参考图31，位线结构320包括：第一位线导电层321，第一位线导电层321位于衬底300内，且第一位线导电层321与通道柱状结构310底面接触；第二位线导电层322，第二位线导电层322位于第一位线导电层321顶面。
在一些实施例中，参考图31，隔离结构430可以包括：保护层380，保护层380位于通道柱状结构310的顶面及部分侧壁；第一隔离结构431，第一隔离结构431位于第一隔离层410的顶面，字线结构330的侧壁及保护层380的侧壁。通过形成隔离结构430可以将字线结构330与外界隔离开，从而可以起到保护字线结构330的作用，且可以降低字线结构330受到的应力作用，从而提高半导体结构的可靠性。
在一些实施例中，参考图31，保护层380可以包括：第一保护层381及第二保护层382。
在一些实施例中，参考图19及图31，半导体结构还包括：第一介质层390及第二介质层420，第一介质层390位于通道柱状结构310的侧壁，第二介质层420位于第一介质层390上，第二介质层420可以作为介质层340，从而避免通道柱状结构310与字线结构330直接接触。
在一些实施例中，参考图31，半导体结构还包括：掩膜层384，掩膜层位于通道柱状结构310的顶面可以起到保护通道柱状结构310的作用。
本公开实施例通过形成包绕通道柱状结构310的字线结构330以形成全环绕栅极晶体管结构，从而在满足半导体结构的性能的同时提高半导体结构的集成密度。
本公开另一实施例还提供另一种半导体结构，该半导体结构与前述实施例大致相同，主要区别包括：隔离结构的不同。以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图32及图40，在另一些实施例中，半导体结构包括：衬底500；通道柱状结构510；位线结构520，位线结构520与通道柱状结构510连通；第一隔离层610，第一隔离层610位于位线结构520的顶面；填充层560，填充层560位于衬底500内，且填充层560的顶面与第一隔离层610的顶面齐平；字线结构530，字线结构330环绕通道柱状结构510；隔离结构630，隔离结构630至少位于相邻的字线结构530之间；介质层540，介质层540环绕通道柱状结构510表面。
在一些实施例中，参考图40，隔离结构630包括第一隔离结构631及第二隔离结构632，第一隔离结构631为第一隔离层610、字线结构530及第二隔离结构632围成的空气间隙，第二隔离结构632位于字线结构530之间，且第二隔离结构632的顶面与字线结构530的顶面齐平。通过设置具有空气间隙的隔离结构630，从而可以减少相邻字线结构530之间的寄生电容。
在一些实施例中，参考图40，位线结构520包括：第一位线导电层521，第一位线导电层521位于衬底500内，且第一位线导电层521与通道柱状结构510底面接触；第二位线导电层522，第二位线导电层522位于第一位线导电层521顶面。
在一些实施例中，参考图40，字线结构530包括层叠设置的字线导电层532及字线保护层533。
参考图40，半导体结构还包括：第一介质层590及第二介质层620，第一介质层590位于通道柱状结构510的侧壁，第二介质层620位于第一介质层590上，第二介质层620可以作为介质层540，从而避免通道柱状结构510与字线结构530直接接触。
本公开实施例通过形成包绕通道柱状结构510的字线结构530以形成全环绕栅极晶体管结构，从而在满足半导体结构的性能的同时提高半导体结构的集成密度。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的一种半导体结构的制作方法及其结构中，通过形成环绕通道柱状结构的字线结构以形成全环绕栅极晶体管结构，且在形成字线结构之后还在 相邻的字线结构之间形成隔离结构，通过隔离结构可以增加相邻字线之间的绝缘性从而可以提高半导体结构的性能，即，在满足半导体结构密度效率的同时提高半导体结构的性能。

Claims (19)

  1. 一种半导体结构的制作方法，包括：
    提供衬底，所述衬底包括衬底内沿第一方向间隔分布第一凹槽以及位于所述第一凹槽内的填充层；
    图形化所述衬底，形成第二凹槽，所述第二凹槽沿第二方向间隔分布，且所述第二凹槽位于所述第一凹槽的顶面，所述第一凹槽和所述第二凹槽形成通道柱状结构；
    在所述衬底表面形成保护层，所述保护层与所述填充层不同；
    形成位线结构，所述位线结构形成在所述第二凹槽的底部；
    形成第一隔离层，所述第一隔离层位于所述第二凹槽内且位于所述位线结构的顶面；
    去除部分所述填充层，剩余所述填充层与所述第一隔离层上表面平齐；
    形成字线结构，所述字线结构环绕所述通道柱状结构，且沿第二方向间隔分布；
    形成隔离结构，所述隔离结构位于所述第二凹槽内且位于相邻的所述字线结构之间。
  2. 根据权利要求1所述的半导体结构的制作方法，还包括：第一介质层，所述第一介质层位于所述位线结构的顶面及所述通道柱状结构的侧壁，形成所述保护层的方法包括：
    形成第一保护层，所述第一保护层位于所述衬底的顶面；
    图形化部分所述第一介质层，以暴露部分所述第二凹槽的内壁；
    形成第二保护层，所述第二保护层位于所述第二凹槽的内壁及所述第一保护层的侧壁，所述第一保护层与所述第二保护层构成所述保护层。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述字线结构的方法包括：
    形成所述保护层后，图形化所述第一介质层，以使所述第一介质层的顶面与所述第一隔离层的顶面齐平；
    形成第二介质层，所述第二介质层位于所述第一介质层的顶面，且覆盖部分所述通道柱状结构的侧壁；
    形成初始字线结构，所述初始字线结构填充满所述第一凹槽及所述第二凹槽；
    以所述保护层为掩膜图形化所述初始字线结构，直至暴露所述第一隔离层的顶面，剩余所述初始字线结构作为所述字线结构。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，去除部分所述填充层的步骤包括：
    形成所述保护层前，在同一步中去除所述第一介质层及部分所述填充层；所述填充层的顶面与所述第一介质层的顶面齐平；
    形成所述保护层后，在同一步中去除所述第一介质层及部分所述填充层；剩余所述填充层与所述第一隔离层的上表面齐平。
  5. 根据权利要求3所述的半导体结构的制作方法，其中，形成所述隔离结构的方法包括：
    形成第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面、所述字线结构的侧壁及所述保护层的侧壁；
    去除所述保护层，以形成第三凹槽；
    形成第二隔离结构，所述第二隔离结构填充满所述第三凹槽，所述第一隔离结构及所述第二隔离结构构成所述隔离结构。
  6. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述保护层的方法包 括：
    图形化所述衬底前，还包括：去除部分所述填充层，在所述填充层的顶面形成第一初始保护层；
    图形化所述第一初始保护层及所述衬底，以形成所述第二凹槽，剩余所述第一初始保护层作为第一保护层；
    形成第二保护层，所述第二保护层位于所述第二凹槽的内壁及所述第一保护层的侧壁，所述第一保护层与所述第二保护层构成所述保护层。
  7. 根据权利要求6所述的半导体结构的制作方法，还包括：第一介质层，所述第一介质层位于所述位线结构的顶面及所述通道柱状结构的侧壁，形成所述字线结构的方法包括：
    形成初始字线结构，所述初始字线结构位于所述第一介质层及所述第一隔离层的顶面及所述保护层的底面；
    以所述保护层为掩膜图形化所述初始字线结构，直至暴露所述第一隔离层的顶面，剩余所述初始字线结构作为所述字线结构。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，去除部分所述填充层的步骤包括：
    图形化所述衬底前，去除部分所述填充层；
    形成所述保护层之后，形成初始字线结构之前，去除部分所述填充层。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，形成所述隔离结构的方法包括：
    形成第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面，所述字线结构的侧壁及所述保护层的侧壁，所述第一隔离结构及所述保护层构成所述隔离结构。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述保护层的方法包括：
    形成第一保护层，所述第一保护层位于所述衬底的顶面；
    形成第二保护层，所述第二保护层位于所述第一保护层的侧壁，所述第二保护层位于所述第二凹槽的顶面，所述第一保护层及所述第二保护层构成所述保护层。
  11. 根据权利要求10所述的半导体结构的制作方法，还包括：第一介质层，所述第一介质层位于所述位线结构的顶面及所述通道柱状结构的侧壁，形成所述字线结构的方法包括：
    在同一步中去除部分所述第一介质层及所述填充层，以使所述第一介质层的顶面与所述第一隔离层上表面齐平；
    形成第二介质层，所述第二介质层位于所述第一介质层的顶面，且覆盖部分所述通道柱状结构的侧壁；
    形成初始字线结构，所述初始字线结构填充满所述第一凹槽及所述第二凹槽，所述初始字线结构的顶面与所述第一保护层的底面齐平；
    以所述保护层为掩膜图形化所述初始字线结构及所述第一隔离层，直至暴露所述位线结构的顶面，剩余所述初始字线结构作为所述字线结构。
  12. 根据权利要求10所述的半导体结构的制作方法，其中，形成所述隔离结构的方法包括：
    形成第一隔离结构及第二隔离结构，所述第一隔离结构为所述第一隔离层、所述字线结构及所述第二隔离结构围成的空气间隙，所述第二隔离结构位于所述字线结构之间，且所述第二隔离结构的顶面与所述字线结构的顶面齐平。
  13. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述位线结构的方法包括：
    形成第四凹槽，所述第四凹槽位于所述第二凹槽的底面；
    采用金属硅化物工艺的形成第一位线导电层，所述第一位线导电层位于所述第四凹槽朝向所述衬底的表面；
    形成第二位线导电层，所述第二位线导电层填充满所述第四凹槽，所述第一位线导电层及所述第二位线导电层构成所述位线结构。
  14. 一种半导体结构，包括：
    衬底；
    通道柱状结构，所述通道柱状结构位于所述衬底内，且所述通道柱状结构沿第一方向及第二方向间隔排布；
    位线结构，所述位线结构与所述通道柱状结构连通，所述位线结构沿所述第二方向间隔排布于所述衬底内，且所述位线结构位于所述通道柱状结构底面；
    第一隔离层，所述第一隔离层位于所述位线结构的顶面；
    填充层，所述填充层位于所述衬底内，且所述填充层的顶面与所述第一隔离层的顶面齐平；
    字线结构，所述字线结构环绕所述通道柱状结构，且沿所述第二方向间隔分布；
    隔离结构，所述隔离结构至少位于相邻的所述字线结构之间。
  15. 根据权利要求14所述的半导体结构，其中，所述隔离结构包括第一隔离结构及第二隔离结构，所述第一隔离结构为所述第一隔离层、所述字线结构及所述第二隔离结构围成的空气间隙，所述第二隔离结构位于所述字线结构之间，且所述第二隔离结构的顶面与所述字线结构的顶面齐平。
  16. 根据权利要求14所述的半导体结构，其中，所述隔离结构包括：
    保护层，所述保护层位于所述通道柱状结构的顶面及部分侧壁；
    第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面，所述字线结构的侧壁及所述保护层的侧壁。
  17. 根据权利要求14所述的半导体结构，其中，所述隔离结构包括：
    第一隔离结构，所述第一隔离结构位于所述第一隔离层的顶面、所述字线结构的侧壁；
    第二隔离结构，所述第二隔离结构位于所述通道柱状结构的顶面及所述通道柱状结构与所述第一隔离结构之间。
  18. 根据权利要求14所述的半导体结构，其中，所述位线结构包括：
    第一位线导电层，所述第一位线导电层位于所述衬底内，且所述第一位线导电层与所述通道柱状结构底面接触；
    第二位线导电层，所述第二位线导电层位于所述第一位线导电层顶面。
  19. 根据权利要求18所述的半导体结构，其中，部分第二位线导电层的顶面低于所述通道柱状结构底面，且所述第一隔离结构的底面低于所述通道柱状结构的底面。
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