WO2024045266A1 - 半导体结构的制作方法及其结构 - Google Patents

半导体结构的制作方法及其结构 Download PDF

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Publication number
WO2024045266A1
WO2024045266A1 PCT/CN2022/124151 CN2022124151W WO2024045266A1 WO 2024045266 A1 WO2024045266 A1 WO 2024045266A1 CN 2022124151 W CN2022124151 W CN 2022124151W WO 2024045266 A1 WO2024045266 A1 WO 2024045266A1
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layer
dielectric layer
forming
word line
electrode structure
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PCT/CN2022/124151
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English (en)
French (fr)
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唐怡
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长鑫存储技术有限公司
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Priority to US18/508,244 priority Critical patent/US20240090191A1/en
Publication of WO2024045266A1 publication Critical patent/WO2024045266A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure and its structure.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and its structure, which can at least improve the performance of the semiconductor structure.
  • the embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming stacked structures spaced apart along a first direction on the surface of the substrate and located between adjacent stacked structures.
  • the stacked structure includes a first interlayer dielectric layer, an initial active layer and a second interlayer dielectric layer; etching part of the initial active layer to form a first trench; Forming a metal conductive layer in the first trench, the metal conductive layer being in contact with the remaining initial active layer; etching part of the metal conductive layer to form an array along the first direction and the second direction Arranged lower electrode structure; the first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface.
  • forming the lower electrode structure further includes etching the first interlayer dielectric layer and the second interlayer dielectric layer located on the top and bottom surfaces of the lower electrode structure to form a third interlayer dielectric layer. Two trenches, the second trench exposes part of the surface of the lower electrode structure; a capacitive dielectric layer is formed, and the capacitive dielectric layer covers the inner wall of the second trench; an upper electrode structure is formed, and the upper electrode structure Located on the surface of the capacitive dielectric layer and filling the second trench, the lower electrode structure, the capacitive dielectric layer and the upper electrode structure form a capacitor.
  • the step of forming the capacitive dielectric layer includes: forming the capacitive dielectric layer covering the sidewalls of the first isolation layer to form all the capacitive dielectric layers sharing the capacitive dielectric layer in the first direction. Describe the capacitor.
  • the method further includes: etching the remaining initial active layer to form a third trench; and forming an oxide semiconductor layer located on the third trench. In the three trenches, the oxide semiconductor layer is in contact with the remaining metal conductive layer.
  • the method further includes: etching the oxide semiconductor layer and the remaining metal conductive layer to form a fourth trench, and the fourth trench will The stacked structures are spaced apart along the second direction.
  • the manufacturing method of the semiconductor structure further includes: forming a second isolation layer, the second isolation layer being located on adjacent adjacent areas arranged along the second direction. between the lower electrode structures; after forming the fourth trench, a third isolation layer is formed, and the third isolation layer fills the fourth trench.
  • the material of the oxide semiconductor layer includes: indium gallium zinc oxide or zinc tin oxide.
  • forming the oxide semiconductor layer further includes: forming a word line, the word line surrounds the surface of the oxide semiconductor layer, and the word line is along the first direction or the third direction. Extending in one of the two directions; forming a bit line, the bit line surrounds the surface of the oxide semiconductor layer, the bit line is spaced from the word line, and the bit line is along the first direction or the extends in the other of the second directions.
  • the method of forming the word line includes: forming a first word line surrounding a surface of the oxide semiconductor layer; forming a second word line covering the surface of the oxide semiconductor layer; The first word lines are arranged along the sidewalls in the second direction.
  • the metal conductive layer includes one or more metal materials selected from titanium, nickel, tungsten, and titanium nitride.
  • the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate; active structures located on the surface of the substrate and arranged at intervals along the first direction and the second direction, and the third One direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface; lower electrode structures are spaced apart along the first direction and the second direction, and the lower electrode structures are in contact with the The source structure is contact-connected; a first isolation layer, the first isolation layer is located between the active structures adjacent in the first direction, and the projection of the active structure on the substrate surface is consistent with the The projected portion of the first isolation layer on the surface of the substrate overlaps.
  • a capacitive dielectric layer the capacitive dielectric layer includes: a first side, the first side is in contact with the top surface and the bottom surface of the lower electrode structure; a second side, the first side is in contact with the top surface and bottom surface of the lower electrode structure; Two side surfaces are directly opposite to the first side surface and are spaced apart from the first side surface; a third side surface is a side wall arranged along the third direction with the first side surface and the second side surface.
  • Contact connection, and the first side, the second side and the third side enclose a receiving space; an upper electrode structure, the upper electrode structure is connected with the first side, the second side and the The third side is in contact connection, and the upper electrode structure fills the accommodation space.
  • the lower electrode structure, the capacitive dielectric layer and the upper electrode structure form a capacitor.
  • the projection of the upper electrode structure on the substrate is within the projection of the lower electrode structure within the substrate.
  • the material of the active structure includes an oxide semiconductor.
  • the method further includes: a word line surrounding the active structure and extending along one of the first direction or the second direction; a bit line, The bit lines surround the active structure, are spaced apart from the word lines, and extend along the other of the first direction or the second direction.
  • the technical solution provided by the embodiments of the present disclosure at least has the following advantages: by forming stacked structures spaced along the first direction on the surface of the substrate and first isolation layers located between adjacent stacked structures, the initial layer of the stacked structure is etched.
  • the source layer is to form a first trench, a metal conductive layer is formed in the first trench, the metal conductive layer is in contact with the remaining initial active layer, and a portion of the metal conductive layer is etched to form a lower electrode structure arranged in an array, Therefore, the process difficulty of the formation process of the semiconductor structure can be reduced and the performance of the semiconductor structure can be improved.
  • 1 to 22 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by embodiments of the present disclosure.
  • the present disclosure provides a method for manufacturing a semiconductor structure by forming a first isolation layer between stacked structures spaced along a first direction on a substrate surface, and then etching the initial active layer to form a first trench. trench, and form a metal conductive layer in the first trench.
  • the semiconductor structure can be reduced by etching the initial active layer and forming the lower electrode structure. volume, improving the space utilization of semiconductor structures.
  • FIGS. 1 to 22 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 1 is a top view of the semiconductor structure
  • FIG. 2 is a cross-sectional view along the direction AA in FIG. 1 .
  • a substrate 100 is provided, and stacked structures 110 arranged at intervals along the first direction 130.
  • Initial active layer 140 and second interlayer dielectric layer 150 are provided.
  • the substrate 100 is a semiconductor material, and the semiconductor material includes but is not limited to any one of a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate.
  • the substrate 100 can also be an ion-doped substrate.
  • the doping ions are N-type ions or P-type ions.
  • the N-type ions can be phosphorus ions, arsenic ions or antimony ions
  • the P-type ions can be boron ions, indium ions or antimony ions. Boron fluoride ion.
  • the material of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 can be the same, and both can be insulating materials such as silicon oxide.
  • the dielectric layer 150 can provide a basis for subsequent formation of bit lines, and can also isolate the initial active layers 140 arranged at intervals in the first direction X by the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 .
  • the material of the initial active layer 140 may be silicon carbide or polysilicon semiconductor material.
  • the formation of the initial active layer 140 may provide a process basis for the subsequent formation of an active structure arranged in an array.
  • a portion of the initial active layer 140 is etched to form a first trench 160 .
  • the formation of the first trench 160 can provide a process basis for the subsequent formation of a lower electrode structure.
  • the method of etching part of the initial active layer 140 may be by using wet etching to etch the initial active layer 140 through the sidewalls of the stacked structure 110 .
  • a metal conductive layer 170 is formed in the first trench 160 .
  • the metal conductive layer 170 is in contact with the remaining initial active layer 140 .
  • the metal conductive layer 170 may serve as a lower electrode structure.
  • the metal conductive layer 170 includes one or more metal materials among titanium, nickel, tungsten, and titanium nitride.
  • the material of the metal conductive layer can be titanium, nickel, tungsten, and titanium nitride, wherein One or more materials can improve the conductivity of the metal conductive layer 170, thereby improving the transmission rate of the semiconductor structure.
  • the material of the metal conductive layer 170 can also include metal semiconductors.
  • part of the metal conductive layer 170 can also serve as the drain of the active structure.
  • a portion of the metal conductive layer 170 is etched to form a lower electrode structure 180 arranged in an array along the first direction X and the second direction Y; the first direction X is perpendicular to the surface of the substrate 100, and the second direction Y is parallel to the substrate. 100 surfaces.
  • the manufacturing method of the semiconductor structure may further include: forming a second isolation layer 190 , and the second isolation layer 190 is located in a phase arranged along the second direction Y. between adjacent lower electrode structures 180 .
  • the insulation between adjacent lower electrode structures 180 can be improved, and it can also function to fill the semiconductor structure.
  • the material of the second isolation layer 190 may be insulating materials such as silicon oxide and silicon nitride.
  • forming the lower electrode structure 180 further includes: etching the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 located on the top and bottom surfaces of the lower electrode structure 180 , To form the second trench 200, the second trench 200 exposes part of the surface of the lower electrode structure 180; to form the capacitive dielectric layer 210, which covers the inner wall of the second trench 200; to form the upper electrode structure 220, the upper electrode structure 220 is located on the surface of the capacitive dielectric layer 210 and fills the second trench 200.
  • the lower electrode structure 180, the capacitive dielectric layer 210 and the upper electrode structure 220 form the capacitor 230.
  • Forming the second trench 200 provides a basis for forming the capacitive dielectric layer 210 and the upper electrode structure 220 .
  • Data is stored by forming the capacitor 230 and forming different states of the capacitor 230.
  • the capacitor 230 when the capacitor 230 stores charge, it can represent the '1' state of the semiconductor structure, and when it does not store charge, it can represent the '0' state of the semiconductor structure. state, where the '0' state can represent a low level and the '1' state can represent a high level.
  • wet etching may be used to etch the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 , and the materials of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 may be Therefore, the second interlayer dielectric layer 150 and the first interlayer dielectric layer 130 located on the top and bottom surfaces of the lower electrode structure 180 can be etched in the same step at the same time, thereby reducing the process steps of the manufacturing method of the semiconductor structure. , and can ensure the consistency of the second trench 200 above and below the lower electrode structure 180 .
  • the length of the first interlayer dielectric layer 130 is shorter than the length of the lower electrode structure 180 , so that the surface of the formed capacitive dielectric layer will not be exposed during subsequent etching of the remaining initial active layer 140 , thereby improving the The reliability of the semiconductor structure, and by controlling the length of the etched first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, can control the length of the formed capacitive dielectric layer and the upper electrode structure, so that the capacitive dielectric layer can be avoided Contacting the gate or word line of the active structure can improve the reliability of the semiconductor structure.
  • the length of the etched first interlayer dielectric layer and the second interlayer dielectric layer can also be equal to the length of the metal conductive layer, thereby increasing the length of the capacitive dielectric layer and the upper electrode structure, thereby increasing the length of the capacitive dielectric layer and the upper electrode structure.
  • the facing area of the lower electrode structure and the upper electrode structure of the semiconductor structure can thereby improve the performance of the semiconductor structure.
  • the capacitive dielectric layer 210 and the upper electrode structure 220 are formed.
  • the step of forming the capacitive dielectric layer may include: forming the capacitive dielectric layer 210 covering the sidewalls of the first isolation layer 120 to form the capacitive dielectric layer 210 on the first isolation layer 120 .
  • the process difficulty and process steps of the semiconductor structure can be reduced by forming the capacitor 230 that shares the capacitance dielectric layer 210 in the first direction X.
  • the capacitance dielectric can be formed directly by deposition. layer 210, and by forming the capacitor 230 sharing the capacitive dielectric layer 210 in the first direction X, the space utilization of the semiconductor structure can be improved.
  • the material of the lower electrode structure 180 may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper or tungsten; the material of the capacitor dielectric layer 210 may include: ZrO, AlO, ZrNbO, ZrHfO, ZrAlO Any one or any combination thereof; the material of the upper electrode structure 220 includes a compound formed of one or two of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, silicon nitride Titanium or other conductive materials, or the material of the upper electrode structure 220 can also be conductive semiconductor materials, such as polysilicon, silicon germanium, etc.
  • the relative area between the lower electrode structure 180 and the upper electrode structure 220 of the capacitor 230, the distance between the lower electrode structure 180 and the upper electrode structure 220, and the material of the capacitor dielectric layer 210 may all affect the capacity of the capacitor 230.
  • the relative area between the lower electrode structure 180 and the upper electrode structure 220 of the capacitor 230, the distance between the lower electrode structure 180 and the upper electrode structure 220, and the material of the capacitive dielectric layer 210 can be set according to actual needs.
  • FIG. 9 is a top view of the structure corresponding to the schematic diagram in FIG. 8 , and is not processed based on the semiconductor structure corresponding to FIG. 8 . It is only a schematic structural diagram of the semiconductor structure from different viewing angles.
  • forming the lower electrode structure 180 also includes: etching the remaining initial active layer 140 to form a third trench 240; forming an oxide semiconductor layer 250, which is located in the third trench.
  • the oxide semiconductor layer 250 is in contact with the remaining metal conductive layer 170.
  • a foundation can be provided for the subsequent formation of the oxide semiconductor layer 250.
  • the oxide semiconductor layer 250 can be used as an active structure of the semiconductor structure.
  • the oxide semiconductor layer 250 can be improved. The mobility of carriers and the activity of carriers in the active structure can thereby improve the response speed of the semiconductor structure and improve the performance of the semiconductor structure.
  • the material of the oxide semiconductor layer 250 may include: indium gallium zinc oxide or zinc tin oxide.
  • the oxide The ion mobility of the semiconductor layer 250 can thereby improve the performance of the subsequent oxide semiconductor layer 250 as a channel region.
  • the material of the oxide semiconductor layer 250 may also be indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium Indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide and other similar materials Or multiple.
  • forming the oxide semiconductor layer 250 also includes etching the oxide semiconductor layer 250 and the remaining metal conductive layer 170 to form a fourth trench 260 .
  • the fourth trench 260 connects the stacked structure 110 along the Second direction Y interval.
  • the fourth trench 260 corresponds to the second isolation layer 190 one-to-one, and the fourth trench 260 exposes the end surface of the second isolation layer 190 .
  • Spaced active structures and capacitors 230 can be formed by etching the oxide semiconductor layer 250 and the remaining metal conductive layer 170, in which the spaced oxide semiconductor layers 250 serve as active structures and the spaced metal conductive layers 170 serve as Lower electrode structure 180 of capacitor 230.
  • a third isolation layer 270 is formed.
  • the third isolation layer 270 fills the fourth trench 260, and adjacent active structures can be isolated by forming the third isolation layer 270. Open, avoiding electrical connection between adjacent active structures, thereby improving the reliability of the semiconductor structure.
  • forming the oxide semiconductor layer 250 further includes: forming a word line 280 surrounding the surface of the oxide semiconductor layer 250 , and the word line 280 is along the first direction X or the second direction Y.
  • a bit line 290 is formed, the bit line 290 surrounds the surface of the oxide semiconductor layer 250, the bit line 290 is spaced from the word line 280, and the bit line 290 extends along the other of the first direction X or the second direction Y .
  • the method of forming the word line 280 may include: forming a first word line 281 surrounding the surface of the oxide semiconductor layer 250 ; forming a second word line 282 covering the surface of the oxide semiconductor layer 250
  • the first word lines 281 are arranged along the sidewalls of the second direction Y.
  • the contact area between the word line 280 and the oxide semiconductor layer 250 can be increased.
  • the second word line 282 it can provide a space for the subsequent formation of conductive pillars corresponding to the word line 280. Touch the basics.
  • the first word line may only cover part of the surface of the active structure.
  • the first word line may only cover the top and bottom surfaces of the active structure, or may be covered with The top and bottom surfaces of the source structure and one of the side surfaces connected to the top and bottom surfaces.
  • first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 are etched to expose a portion of the surface of the oxide semiconductor layer 250 to provide a process basis for later forming word lines.
  • the remaining first interlayer dielectric layer The dielectric layer 130 and the second interlayer dielectric layer 150 can serve as an isolation structure between the word line and the capacitor 230, thereby avoiding direct contact between the word line and the capacitor 230, thereby improving the reliability of the semiconductor structure.
  • forming the first word line 281 also includes forming a gate dielectric layer 300 covering the exposed surface of the oxide semiconductor layer 250 , the remaining first interlayer dielectric layer 130 and the second layer.
  • forming the gate dielectric layer 300 on the surface of the interlayer dielectric layer 150 and the surface of the first isolation layer 120, direct contact between the first word line 281 and the oxide semiconductor layer 250 can be avoided, thereby avoiding semiconductor structural abnormalities.
  • the material of the gate dielectric layer 300 can be an insulating material such as silicon oxide, silicon nitride, or hafnium oxide.
  • the material of the gate dielectric layer 300 can be selected according to the required dielectric constant of the gate dielectric layer 300 . .
  • the thickness of the gate dielectric layer 300 may be 8-20 nm. It can be understood that, under other conditions being equal, the thinner the thickness of the gate dielectric layer 300, the better the performance of the semiconductor structure. , but the reliability of the semiconductor structure is lower, and the current tunneling effect is more likely to occur. The corresponding thickness of the gate dielectric layer 300 is thicker, and the reliability of the semiconductor structure is higher, but the performance of the semiconductor structure will decrease. By setting the thickness of the gate dielectric layer 300 to 8 to 20 nm, a certain degree of reliability can be ensured while improving the performance of the semiconductor structure.
  • Forming the gate dielectric layer 300 and the first isolation layer 120 can also help the oxide semiconductor layer 250 to isolate oxygen and water vapor in the air, thereby improving the reliability of the semiconductor structure.
  • Some embodiments also include: forming a first word line 281, which is directly opposite the exposed oxide semiconductor layer 250, and a gate dielectric is also included between the first word line 281 and the oxide semiconductor layer 250. Layer 300.
  • Figure 16 is a cross-sectional view along the BB direction in Figure 1.
  • Figure 16 does not include any process steps based on Figure 15, but is only a cross-sectional view of the semiconductor structure from different viewing angles.
  • the stacked structure 110 is etched along the second direction Y to form a fifth trench 310 .
  • the fifth trench 310 exposes the sidewalls of the first word line 281 .
  • the second word line 281 can be formed. Lines provide the basis for craftsmanship.
  • a second word line 282 is formed, and the second word line 282 fills the fifth trench 310 .
  • the second word line 282 and the first isolation layer 120 are etched.
  • the lengths of the second word lines 282 arranged along the first direction X are sequentially reduced in the second direction Y, and also That is to say, the length of the second word line 282 gradually decreases from the direction approaching the substrate 100 to the direction away from the substrate 100 .
  • the second word line 282 closest to the substrate 100 is called the first sub-word line
  • the second word line 282 located in the middle is called the second sub-word line.
  • the farthest second word line 282 becomes the third sub-word line, wherein, along the second direction, the length of the first sub-word line is greater than the length of the second sub-word line, which is greater than the length of the third sub-word line, so that subsequent Conductive pillars can be formed on the portion of the first sub-word line that is longer than the second sub-word line, and conductive pillars can be formed on the portion of the second sub-word line that is longer than the third sub-word line, so that signals from different word lines 280 can be extracted. Or provide corresponding electrical signals to different word lines 280 .
  • a portion of the first word line 281 and the gate dielectric layer 300 are etched to expose a portion of the surface of the oxide semiconductor layer 250 , thereby providing a process basis for subsequent formation of bit lines.
  • a bit line 320 is formed to provide a basis for reading data and writing data of the semiconductor structure.
  • the bit line 320 may be in contact with multiple oxide semiconductor layers 250 arranged along the first direction. That is, the bit line 320 may By transmitting signals to a plurality of oxide semiconductor layers 250 arranged along the first direction X, the stacking density of the semiconductor structure can be increased and the space utilization of the semiconductor structure can be improved.
  • the extending direction of the bit line 320 intersects the extending direction of the word line 280, and there is only one intersection point between the bit line 320 and a word line 280, that is, through a word line 280 and a bit line 320 may select an oxide semiconductor layer 250 .
  • forming the bit line 320 further includes: forming a fourth isolation layer 330, the fourth isolation layer 330 covers part of the surface of the oxide semiconductor layer 250, and the fourth isolation layer 330 and the word line 280 are along a third direction. Side wall contact connection in Z arrangement.
  • a fourth initial isolation layer is formed, the fourth initial isolation layer is located between the first isolation layer 120 and the oxide semiconductor layer 250; the fourth initial isolation layer is etched, and the fourth initial isolation layer remains as the fourth Isolation layer 330.
  • etching the fourth initial isolation layer also includes: etching the first isolation layer 120 .
  • the formed bit line 320 may also cover the sidewall of the first isolation layer 120 .
  • the manufacturing method of the semiconductor structure also includes: forming a conductive pillar 340, a conductive pillar 340 is connected to a word line 280, and the word line 280 can be controlled by providing an electrical signal to the conductive pillar 340 through the conductive pillar 340.
  • electrical signals are provided to the word lines 280 connected to the conductive pillars 340. That is to say, different word lines can be controlled by controlling different conductive pillars 340. 280.
  • the volume of the semiconductor structure can be reduced and the space utilization of the semiconductor structure can be improved.
  • Embodiments of the present disclosure also provide a semiconductor structure, which can be formed through some or all steps of the above-mentioned method for manufacturing a semiconductor structure.
  • the same or corresponding parts can be referred to the above-mentioned embodiments, which will not be described in detail below.
  • the present invention will be described below with reference to the accompanying drawings. The semiconductor structure provided in the disclosed embodiment will be described.
  • the semiconductor structure includes: a substrate 100; active structures 350 located on the surface of the substrate 100 and arranged at intervals along the first direction X and the second direction Y.
  • the first direction X is perpendicular to On the surface of the substrate 100, the second direction Y is parallel to the surface of the substrate 100; the lower electrode structures 180 are arranged at intervals along the first direction X and the second direction Y, and the lower electrode structures 180 are in contact with the active structure 350; the first isolation layer 120 , the first isolation layer 120 is located between adjacent active structures 350 in the first direction X, and the projection of the active structure 350 on the surface of the substrate 100 partially overlaps with the projection of the first isolation layer 120 on the surface of the substrate 100 .
  • a capacitive dielectric layer 210 is also included.
  • the capacitive dielectric layer 210 includes: a first side that is in contact with the top and bottom surfaces of the lower electrode structure 180; a second side that is in contact with the first side. The side is directly opposite and spaced from the first side; the third side is in contact with the side walls arranged along the third direction of the first side and the second side, and the first side, the second side and the third side are Encircling the accommodation space; the upper electrode structure 220 is in contact with the first side, the second side and the third side, and the upper electrode structure 220 fills the accommodation space, the lower electrode structure 180, the capacitive dielectric layer 210 and the upper Electrode structure 220 forms capacitor 230.
  • the capacitive dielectric layer 210 covers part of the surface of the lower electrode structure 180 , the capacitive dielectric layer 210 covers the sidewalls of the first interlayer dielectric layer 130 and the second interlayer dielectric layer, and the capacitive dielectric layer 210 also covers the first isolation layer.
  • the upper electrode structure 220 covers the surface of the capacitor dielectric layer 210, the distance between the lower electrode structure 180 and the upper electrode structure 220 of the capacitor 230 and the material of the capacitor dielectric layer 210 may affect the capacity of the capacitor 230, so it can
  • the distance between the lower electrode structure 180 and the upper electrode structure 220 of the capacitor 230, the facing area between the lower electrode structure 180 and the upper electrode structure 220, and the material of the capacitive dielectric layer 210 are set according to actual requirements.
  • the capacitive dielectric layer 210 may also cover the sidewalls of the first isolation layer 120 to form a capacitor 230 sharing the capacitive dielectric layer 210 along the first direction X.
  • the process steps of the semiconductor structure can be reduced, and by arranging the capacitor 230 sharing the capacitive dielectric layer 210, the space utilization of the semiconductor structure can also be improved.
  • the projection of the upper electrode structure 220 on the substrate 100 is within the projection of the lower electrode structure 180 within the substrate 100 .
  • the length of the upper electrode structure 220 is shorter than the length of the lower electrode structure 180 .
  • the material of active structure 350 may be an oxide semiconductor.
  • the activity of carriers in the active structure 350 can be increased, thereby increasing the carrier mobility in the active structure 350 . It can be understood that the active structure 350 corresponds to the oxide semiconductor layer 250 in the above-mentioned method of manufacturing a semiconductor structure.
  • the word line 280 may also be included.
  • the word line 280 surrounds the surface of the active structure 350 and extends along one of the first direction X or the second direction Y; the bit line 320 .
  • Lines 320 surround the surface of active structure 350, bit lines 320 are spaced apart from word lines 280, and bit lines 320 extend along the other of the first direction X or the second direction Y.
  • the semiconductor structure further includes: a gate dielectric layer 300 located on the surface of the active structure 350 .
  • a gate dielectric layer 300 By forming the gate dielectric layer 300, direct contact between the word line 280 and the active structure 350 can be avoided, thereby avoiding semiconductor structural abnormalities.
  • the word line 280 includes: a first word line 281 and a second word line 282, the first word line 281 is arranged around the active structure 350, and the second word line 282 covers the sidewall of the first word line 281.
  • the contact area between the word line 280 and the active structure 350 can be increased, and by forming the second word line 282, a contact basis can be provided for the subsequent formation of conductive pillars corresponding to the word line 280. .
  • the first word line 281 surrounds the surface of the gate dielectric layer 300 .
  • the semiconductor structure further includes: a first interlayer dielectric layer 130 and a second interlayer dielectric layer 150.
  • a first interlayer dielectric layer 130 and a second interlayer dielectric layer 150 By providing the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, the capacitance 230 and the word value can be improved.
  • the insulation of the wire 280 can also play a supporting role in the semiconductor structure, thereby avoiding deformation of the semiconductor structure and improving the reliability of the semiconductor structure.
  • the semiconductor structure may further include: a third isolation layer 270 , the third isolation layer 270 is located between adjacent active structures 350 in the second direction Y, and the adjacent active structures 350 can be separated by the third isolation layer 270 The active structures 350 are isolated to avoid electrical connection between adjacent active structures 350, thereby improving the reliability of the semiconductor structure.
  • the semiconductor structure may further include: a fourth isolation layer 330, the fourth isolation layer 330 covers part of the surface of the active structure 350, and the fourth isolation layer 330 and the word line 280 are arranged along the third direction Z. Side wall contact connection.
  • the fourth isolation layer 330 By forming the fourth isolation layer 330, the bit line 320 and the word line 280 can be isolated, thereby avoiding electrical connection between the bit line 320 and the word line 280, thereby improving the reliability of the semiconductor structure.
  • the semiconductor structure may also include: a conductive pillar 340.
  • a conductive pillar 340 is correspondingly connected to a word line 280.
  • the conductive pillar 340 can control the conduction and conduction of the word line 280 by providing an electrical signal to the conductive pillar 340.
  • signals are provided to different conductive pillars 340, thereby providing electrical signals to the word lines 280 connected to the conductive pillars 340. That is to say, different word lines 280 can be controlled by controlling different conductive pillars 340.
  • the embodiment of the present disclosure disposes the active structure 350 on the surface of the substrate 100, disposes the lower electrode structure 180 to be in contact with the active structure 350, and disposes the first isolation layer 120 between adjacent active structures 350.
  • the projection of the structure 350 on the surface of the substrate 100 partially overlaps with the projection of the first isolation layer 120 on the surface of the substrate 100 . That is to say, the length of the active structure 350 is smaller than that of the first isolation layer 120 , thereby reducing the volume of the semiconductor structure and improving the efficiency of the semiconductor structure. Structural space utilization.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构的制作方法及半导体结构，其中，半导体结构的制作方法包括：提供基底；在基底表面形成沿第一方向间隔排布的堆叠结构及位于相邻堆叠结构之间的第一隔离层，堆叠结构包括第一层间介质层、初始有源层和第二层间介质层；刻蚀部分初始有源层，以形成第一沟槽；在第一沟槽中形成金属导电层，金属导电层与保留的初始有源层接触连接；刻蚀部分金属导电层，以形成沿第一方向和第二方向阵列排布的下电极结构；第一方向垂直于基底表面，第二方向平行于基底表面，可以提高半导体结构的性能。

Description

半导体结构的制作方法及其结构
交叉引用
本公开要求于2022年08月29日递交的名称为“半导体结构的制作方法及其结构”、申请号为202211042653.7的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构的制作方法及其结构。
背景技术
随着半导体结构的不断发展，其关键尺寸不断减小，但由于光刻机的限制，其关键尺寸的缩小存在极限，因此如何在一片晶圆上做出更高存储密度的芯片，是众多科研工作者和半导体从业人员的研究方向。二维或平面半导体器件中，存储单元均是水平方向上排列，因此，二维或平面半导体器件的集成密度可以由单位存储单元所占据的面积决定，则二维或平面半导体器件的集成密度极大地受到形成精细图案的技术影响，使得二维或平面半导体器件的集成密度的持续增大存在极限。因而，半导体器件的发展走向三维半导体器件。
然而在三维半导体器件中，仍然在不断追求更好的性能。
发明内容
本公开实施例提供一种半导体结构的制作方法及其结构，至少可以提高半导体结构的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制作方法，包括：提供基底；在所述基底表面形成沿第一方向间隔排布的堆叠结构及位于相邻堆叠结构之间的第一隔离层，所述堆叠结构包括第一层间介质层、初始有源层和第二层间介质层；刻蚀部分所述初始有源层，以形成第一沟槽；在所述第一沟槽中形成金属导电层，所述金属导电层与保留的所述初始有源层接触连接；刻蚀部分所述金属导电层，以形成沿所述第一方向和第二方向阵列排布的下电极结构；所述第一方向垂直于所述基底表面，所述第二方向平行于所述基底表面。
在一些实施例中，形成所述下电极结构之后还包括：刻蚀位于所述下电极结构顶面及底面的所述第一层间介质层及所述第二层间介质层，以形成第二沟槽，所述第二沟槽露出部分所述下电极结构的表面；形成电容介质层，所述电容介质层覆盖所述第二沟槽的内壁；形成上电极结构，所述上电极结构位于所述电容介质层的表面，且填充满所述第二沟槽，所述下电极结构、电容介质层及所述上电极结构构成电容。
在一些实施例中，形成所述电容介质层的步骤包括：形成覆盖所述第一隔离层侧壁的所述电容介质层，以形成在所述第一方向上共用所述电容介质层的所述电容。
在一些实施例中，形成所述下电极结构之后还包括：刻蚀剩余的所述初始有源层，以形成第三沟槽；形成氧化物半导体层，所述氧化物半导体层位于所述第三沟槽内，所述氧化 物半导体层与剩余的所述金属导电层接触连接。
在一些实施例中，形成所述氧化物半导体层后，还包括：刻蚀所述氧化物半导体层及剩余的所述金属导电层，以形成第四沟槽，所述第四沟槽将所述堆叠结构沿所述第二方向间隔。
在一些实施例中，刻蚀部分所述金属导电层后，所述半导体结构的制作方法还包括：形成第二隔离层，所述第二隔离层位于沿所述第二方向排布的相邻的所述下电极结构之间；形成所述第四沟槽后，形成第三隔离层，所述第三隔离层填充满所述第四沟槽。
在一些实施例中，所述氧化物半导体层的材料包括：铟镓锌氧化物或锌锡氧化物。
在一些实施例中，形成所述氧化物半导体层后还包括：形成字线，所述字线环绕所述氧化物半导体层的表面，且所述字线沿所述第一方向或者所述第二方向中的一者延伸；形成位线，所述位线环绕所述氧化物半导体层的表面，所述位线与所述字线间隔，且所述位线沿所述第一方向或者所述第二方向中的另一者延伸。
在一些实施例中，形成所述字线的方法包括：形成第一字线，所述第一字线环绕所述氧化物半导体层的表面；形成第二字线，所述第二字线覆盖所述第一字线沿所述第二方向排布的侧壁。在一些实施例中，所述金属导电层包括：钛、镍、钨、氮化钛中其中一种或多种金属材料。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：基底；位于所述基底表面，沿第一方向和第二方向间隔排布的有源结构，所述第一方向垂直于所述基底表面，所述第二方向平行于所述基底表面；沿所述第一方向和所述第二方向间隔排布的下电极结构，所述下电极结构与所述有源结构接触连接；第一隔离层，所述第一隔离层位于在所述第一方向上相邻的所述有源结构之间，且所述有源结构在所述基底表面的投影与所述第一隔离层在所述基底表面的投影部分重叠。
在一些实施例中，还包括：电容介质层，所述电容介质层包括：第一侧面，所述第一侧面与所述下电极结构的顶面和底面接触连接；第二侧面，所述第二侧面与所述第一侧面正对，且与所述第一侧面间隔；第三侧面，所述第三侧面与所述第一侧面及所述第二侧面沿第三方向排布的侧壁接触连接，且所述第一侧面、所述第二侧面及所述第三侧面围成容纳空间；上电极结构，所述上电极结构与所述第一侧面、所述第二侧面及所述第三侧面接触连接，且所述上电极结构填充满所述容纳空间，所述下电极结构、所述电容介质层及所述上电极结构构成电容。
在一些实施例中，所述上电极结构在所述基底上的投影位于所述下电极结构在所述基底内的投影内。
在一些实施例中，所述有源结构的材料包括氧化物半导体。
在一些实施例中，还包括：字线，所述字线环绕所述有源结构，且所述字线沿所述第一方向或者所述第二方向中的一者延伸；位线，所述位线环绕所述有源结构，所述位线与所述字线间隔，且所述位线沿所述第一方向或者所述第二方向中的另一者延伸。
本公开实施例提供的技术方案至少具有以下优点：通过在基底表面形成沿第一方向间 隔排布的堆叠结构以及位于相邻堆叠结构之间的第一隔离层，通过刻蚀堆叠结构的初始有源层以形成第一沟槽，在第一沟槽内形成金属导电层，金属导电层与保留的初始有源层接触连接，通过刻蚀部分金属导电层以形成阵列排布的下电极结构，从而可以降低半导体结构的形成工艺的工艺难度，提高半导体结构的性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图22为本公开实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
本公开实施提供一种半导体结构的制作方法，通过在基底表面形成沿第一方向间隔的堆叠结构相邻堆叠结构之间的第一隔离层，再刻蚀初始有源层，以形成第一沟槽，并在第一沟槽内形成金属导电层，通过刻蚀金属导电层以形成阵列排布的下电极结构，通过刻蚀初始有源层并形成下电极结构的方式可以减小半导体结构的体积，提高半导体结构的空间利用率。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图1至图22，图1至图22为本公开实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
参考图1及图2，其中，图1为半导体结构的俯视图，图2为沿图1中AA方向的剖视图。
具体的，提供基底100，在基底100表面形成沿第一方向X间隔排布的堆叠结构110及位于相邻堆叠结构110之间的第一隔离层120，堆叠结构110包括第一层间介质层130、初始有源层140和第二层间介质层150。
在一些实施例中，基底100为半导体材料，半导体材料包括但不限于硅衬底、锗衬底、锗硅衬底或碳化硅衬底的任一种。基底100还可以是离子掺杂衬底，掺杂离子为N型离子或者P型离子，N型离子具体可以为磷离子、砷离子或者锑离子，P型离子具体可以为硼离子、铟离子或者氟化硼离子。
在一些实例中，第一层间介质层130的材料可以与第二层间介质层150的材料相同，都可以为氧化硅等绝缘材料，通过形成第一层间介质层130和第二层间介质层150可以为后续形成位线提供基础，且还可以通过第一层间介质层130和第二层间介质层150将在第一方 向X上的间隔排布的初始有源层140隔离。
初始有源层140的材料可以是碳化硅或者多晶硅半导体材料，通过形成初始有源层140可以为后续形成阵列排布的有源结构提供工艺基础。
参考图3，刻蚀部分初始有源层140，以形成第一沟槽160，通过形成第一沟槽160可以为后续形成下电极结构提供工艺基础。
在一些实施例中，刻蚀部分初始有源层140方法可以是通过采用湿法刻蚀的方式，通过堆叠结构110的侧壁对初始有源层140进行刻蚀。
参考图4，在第一沟槽160中形成金属导电层170，金属导电层170与保留的初始有源层140接触连接，金属导电层170可以作为下电极结构。
在一些实施例中，金属导电层170包括：钛、镍、钨、氮化钛中其中一种或多种金属材料，通过设置金属导电层的材料为钛、镍、钨、氮化钛中其中一种或多种可以提高金属导电层170的导电能力，从而可以提高半导体结构的传输速率，金属导电层170的材料还可以包括金属半导体。
在一些实施例中，当金属导电层170的材料为金属半导体材料时，部分金属导电层170还可以作为有源结构的漏极。
参考图5，刻蚀部分金属导电层170，以形成沿第一方向X和第二方向Y阵列排布的下电极结构180；第一方向X垂直于基底100表面，第二方向Y平行于基底100表面。通过刻蚀金属导电层170作为下电极结构180，也就说是，将部分原有的初始有源层占用的空间用来形成电容结构的一部分，从而可以减小半导体结构的体积提高半导体结构的空间利用率。
参考图6，在一些实施例中，刻蚀部分金属导电层170后，半导体结构的制作方法还可以包括：形成第二隔离层190，第二隔离层190位于沿第二方向Y排布的相邻的下电极结构180之间。通过形成第二隔离层190可以提高相邻下电极结构180之间的绝缘性，且还可以起到填充半导体结构的作用。
在一些实施例中，第二隔离层190的材料可以是氧化硅、氮化硅等绝缘材料。
参考图7至图9，在一些实施例中，形成下电极结构180之后还包括：刻蚀位于下电极结构180顶面及底面的第一层间介质层130及第二层间介质层150，以形成第二沟槽200，第二沟槽200露出部分下电极结构180的表面；形成电容介质层210，电容介质层210覆盖第二沟槽200的内壁；形成上电极结构220，上电极结构220位于电容介质层210的表面，且填充满第二沟槽200，下电极结构180、电容介质层210及上电极结构220构成电容230。通过形成第二沟槽200为形成电容介质层210及上电极结构220提供基础。通过形成电容230，并通过形成电容230的不同状态来进行数据的存储，例如电容230存储有电荷的时候可以表征半导体结构的‘1’状态，没有存储电荷的时候可以表征半导体结构的‘0’状态，其中，‘0’状态可以表征低电平，‘1’状态可以表征高电平。
在一些实施例中，可以采用湿法刻蚀的方式刻蚀第一层间介质层130及第二层间介质层150，第一层间介质层130及第二层间介质层150的材料可以相同，因此可以在同一步中，同时刻蚀位于下电极结构180顶面及底面的第二层间介质层150及第一层间介质层130，从 而可以减小半导体结构的制作方法的工艺步骤，且能确保下电极结构180上方及下方的第二沟槽200的一致性。
参考图7，在一些实施例中，刻蚀第一层间介质层130及第二层间介质层150的过程中，可以仅暴露部分下电极结构180的表面，也就是说，刻蚀去除的第一层间介质层130的长度小于下电极结构180的长度，从而可以使得后续在刻蚀剩余的初始有源层140的过程中不会暴露已经形成好的电容介质层的表面，从而可以提高半导体结构的可靠性，且通过控制刻蚀的第一层间介质层130及第二层间介质层150的长度进而可以控制形成的电容介质层及上电极结构的长度，从而可以避免电容介质层与有源结构的栅极或者字线接触，从而可以提高半导体结构的可靠性。在另一些实施例中，刻蚀的第一层间介质层和第二层间介质层的长度也可以等于金属导电层的长度，从而可以提高电容介质层及上电极结构的长度，进而可以提高半导体结构的下电极结构与上电极结构的正对面积，进而可以提高半导体结构的性能。
参考图8，形成电容介质层210及上电极结构220，在一些实施例中，形成电容介质层的步骤可以包括：形成覆盖第一隔离层120侧壁的电容介质层210，以形成在第一方向X上共用电容介质层210的电容230，通过形成在第一方向X上共用电容介质层210的电容230可以减少半导体结构的工艺难度及工艺步骤，可以通过直接采用沉积的方式以形成电容介质层210，且通过形成在第一方向X上共用电容介质层210的电容230可以提高半导体结构的空间利用率。
下电极结构180的材料可以包括氮化钛、氮化钽、铜或钨等金属材料中的任一种或任意组合；电容介质层210的材料可以包括：ZrO，AlO，ZrNbO，ZrHfO，ZrAlO中的任一种或其任一组合；上电极结构220的材料包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛、硅化钛、硅化镍、硅氮化钛或者其他导电材料，或者，上电极结构220的材料也可以为导电的半导体材料，如多晶硅，锗硅等。
可以理解的是，电容230的下电极结构180与上电极结构220之间的相对面积、下电极结构180及上电极结构220之间的距离及电容介质层210的材料都可能影响电容230的容量的大小，故可以根据实际的需求设置电容230的下电极结构180与上电极结构220之间的相对面积、下电极结构180及上电极结构220之间的距离及电容介质层210的材料。
可以理解的是，图9为图8示意图对应的结构的俯视图，并未在图8对应的半导体结构的基础上有进行处理，仅是半导体结构的不同视角结构示意图。
参考图10及图11，形成下电极结构180之后还包括：刻蚀剩余的初始有源层140，以形成第三沟槽240；形成氧化物半导体层250，氧化物半导体层250位于第三沟槽240内，氧化物半导体层250与剩余的金属导电层170接触连接。通过刻蚀剩余的初始有源层140可以为后续形成氧化物半导体层250提供基础，通过形成氧化物半导体层250可以作为半导体结构的有源结构，通过氧化物半导体层250作为有源结构可以提高有源结构内载流子的迁移率及载流子的活性，从而提高半导体结构的响应速度，提高半导体结构的性能。
在一些实施例中，氧化物半导体层250的材料可以包括：铟镓锌氧化物或锌锡氧化物，通过设置氧化物半导体层的材料为铟镓锌氧化物或锌锡氧化物可以提高氧化物半导体层250的离子迁移率，从而可以提高后续氧化物半导体层250作为沟道区的性能。氧化物半导体层 250的材料还可以是铟锌氧化物、铟镓硅氧化物、铟钨氧化物、铟氧化物、锡氧化物、钛氧化物、镁锌氧化物、锆铟锌氧化物、铪铟锌氧化物、锡铟锌氧化物、铝锡铟锌氧化物、硅铟锌氧化物、铝锌锡氧化物、镓锌锡氧化物、锆锌锡氧化物等其他类似的材料中的一种或者多种。
参考图12及图13，形成氧化物半导体层250之后还包括：刻蚀氧化物半导体层250及剩余的金属导电层170，以形成第四沟槽260，第四沟槽260将堆叠结构110沿第二方向Y间隔。第四沟槽260与第二隔离层190一一对应，且第四沟槽260露出第二隔离层190的端面。通过刻蚀氧化物半导体层250及剩余的金属导电层170可以形成间隔的有源结构和电容230，其中间隔排布的氧化物半导体层250作为有源结构，间隔排布的金属导电层170作为电容230的下电极结构180。
在一些实施例中，形成第四沟槽260后，形成第三隔离层270，第三隔离层270填充满第四沟槽260，通过形成第三隔离层270可以将相邻的有源结构隔离开，避免相邻的有源结构出现电连接，从而可以提高半导体结构的可靠性。
参考图14至图21，形成氧化物半导体层250之后还包括：形成字线280，字线280环绕氧化物半导体层250的表面，且字线280沿第一方向X或者第二方向Y中的一者延伸；形成位线290，位线290环绕氧化物半导体层250的表面，位线290与字线280间隔，且位线290沿第一方向X或者第二方向Y中的另一者延伸。通过形成环绕氧化物半导体层250表面的字线280可以增加字线280与氧化物半导体层250之间的接触面积，从而增加字线280对氧化物半导体层250的控制能力，通过形成环绕氧化物半导体层250的位线可以降低位线290与氧化物半导体层250之间的接触电阻，进而可以提高半导体结构的性能。
参考图14至图19，形成字线280的方法可以包括：形成第一字线281，第一字线281环绕氧化物半导体层250的表面；形成第二字线282，第二字线282覆盖第一字线281沿第二方向Y排布的侧壁。通过形成环绕氧化物半导体层250的第一字线281可以提高字线280与氧化物半导体层250的接触面积，通过形成第二字线282可以为后续形成与字线280对应连接的导电柱提供接触基础。在另一些实施例中，第一字线可以仅覆盖有源结构的部分表面，以有源结构的形状为长方体为例，第一字线可以仅覆盖有源结构顶面和底面，或者覆盖有源结构顶面、底面和与顶面及底面连接的其中一个侧面。
参考图14，刻蚀部分第一层间介质层130和第二层间介质层150，以暴露部分氧化物半导体层250的表面，从而为后形成字线提供工艺基础，剩余的第一层间介质层130和第二层间介质层150可以作为字线与电容230之间的隔离结构，从而可以避免字线与电容230直接接触，从而可以提高半导体结构的可靠性。
参考图15，形成第一字线281之前还包括：形成栅极介质层300，栅极介质层300覆盖暴露的氧化物半导体层250的表面、剩余的第一层间介质层130和第二层间介质层150的表面及第一隔离层120的表面，通过形成栅极介质层300可以避免第一字线281与氧化物半导体层250直接接触，从而可以避免半导体结构异常。
在一些实施例中，栅极介质层300的材料可以是氧化硅、氮化硅或者氧化铪等绝缘材料，可以根据栅极介质层300所需的介电常数进行选择栅极介质层300的材料。
在一些实施例中，栅极介质层300的厚度可以是8～20nm，可以理解的是，在其他条件相同的情况下，栅极介质层300的厚度越薄，半导体结构的性能也就越好，但是半导体结构的可靠性也就越低，越容易发生电流隧穿效应，相应的栅极介质层300的厚度越厚，半导体结构的可靠性也就越高，但是半导体结构的性能会下降，通过设置栅极介质层300的厚度为8～20nm，可以在提高半导体结构性能的同时保证一定的可靠性。
通过形成栅极介质层300和第一隔离层120还可以帮助氧化物半导体层250隔绝空气中的氧气和水蒸汽，从而可以提高半导体结构的可靠性。
在一些实施例中还包括：形成第一字线281，第一字线281与暴露的氧化物半导体层250正对，第一字线281与氧化物半导体层250之间还包括：栅极介质层300。
参考图16，图16为图1中沿BB方向上的剖视图，图16并未在图15的基础上有进行工艺步骤，仅是半导体结构的不同视角的剖面图。
参考图17，沿第二方向Y刻蚀堆叠结构110以形成第五沟槽310，第五沟槽310暴露第一字线281的侧壁，通过形成第五沟槽310可以为形成第二字线提供工艺基础。
参考图18，形成第二字线282，第二字线282填充满第五沟槽310。
参考图19，刻蚀第二字线282和第一隔离层120，在一些实施例中，沿第一方向X排布的第二字线282在第二方向Y上的长度依次减小，也就是说，自靠近基底100的方向朝向远离基底100的方向上，第二字线282的长度依次减小。以图示中三条第二字线282为例，将离基底100最近的第二字线282称为第一子字线，位于中间的第二字线282称为第二子字线，离基底100最远的第二字线282成为第三子字线，其中，沿第二方向上，第一子字线的长度大于第二子字线的长度大于第三子字线的长度，从而后续可以在第一子字线长于第二子字线的部分上形成导电柱，在第二子字线长于第三子字线的部分上形成导电柱，从而可以将不同字线280的信号引出，或者向不同的字线280提供相应的电信号。
参考图20，刻蚀部分第一字线281及栅极介质层300，以暴露部分氧化物半导体层250的部分表面，从而为后续形成位线提供工艺基础。
参考图21，形成位线320，通过形成位线320为半导体结构的读出数据及写入数据提供基础。
在一些实施例中，以位线320沿第一方向延伸为例，一位线320可以与多个沿第一方向排布的多个氧化物半导体层250接触连接，也就是一位线320可以向多个沿第一方向X排布的氧化物半导体层250传输信号，从而可以提高半导体结构的堆叠密度，提高半导体结构的空间利用率。
然而，可以理解的是，位线320的延伸方向与字线280的延伸方向相交，且一位线320与一字线280的交点只有一个，也就是说，通过一字线280和一位线320可以选中一氧化物半导体层250。
在一些实施例中，形成位线320之前还包括：形成第四隔离层330，第四隔离层330覆盖部分氧化物半导体层250的表面，且第四隔离层330与字线280沿第三方向Z排布的侧壁接触连接。通过形成第四隔离层330可以将位线320与字线280隔离开，从而可以避免位 线320与字线280之间出现电连接，从而可以提高半导体结构可靠性。
在一些实施例中，形成第四初始隔离层，第四初始隔离层位于第一隔离层120与氧化物半导体层250之间；刻蚀第四初始隔离层，剩余第四初始隔离层作为第四隔离层330。
在一些实施例中，刻蚀第四初始隔离层的同时还包括：刻蚀第一隔离层120。形成位线320的过程中，形成的位线320还可以覆盖第一隔离层120的侧壁。
参考图1及图22，半导体结构的制作方法还包括：形成导电柱340，一导电柱340与一字线280对应连接，通过导电柱340可以通过向导电柱340提供电信号进而控制字线280的导通与断开，通过向不同的导电柱340提供信号，从而向与该导电柱340连通的字线280提供电信号，也就是说可以通过控制不同的导电柱340进而控制不同的字线280。
本公开实施例通过在基底100表面形成沿第一方向X间隔的堆叠结构110及相邻堆叠结构110之间的第一隔离层120，再刻蚀初始有源层140，以形成第一沟槽160，并在第一沟槽160内形成金属导电层170，通过刻蚀金属导电层170以形成阵列排布的下电极结构180，通过刻蚀初始有源层140并形成下电极结构180的方式可以减小半导体结构的体积，提高半导体结构的空间利用率。
本公开实施例还提供一种半导体结构，可以通过上述半导体结构的制作方法的部分步骤或者全部步骤形成，相同或者相应的部分可以参考上述实施例，以下将不再赘述，以下将参考附图对本公开实施例提供的半导体结构进行说明。
参考图1、图19、图21及图22，半导体结构包括：基底100；位于基底100表面，沿第一方向X和第二方向Y间隔排布的有源结构350，第一方向X垂直于基底100表面，第二方向Y平行于基底100表面；沿第一方向X和第二方向Y间隔排布的下电极结构180，下电极结构180与有源结构350接触连接；第一隔离层120，第一隔离层120位于在第一方向X上相邻的有源结构350之间，且有源结构350在基底100表面的投影与第一隔离层120在基底100表面的投影部分重叠。
在一些实施例中，还包括：电容介质层210，电容介质层210包括：第一侧面，第一侧面与下电极结构180的顶面和底面接触连接；第二侧面，第二侧面与第一侧面正对，且与第一侧面间隔；第三侧面，第三侧面与第一侧面及第二侧面沿第三方向排布的侧壁接触连接，且第一侧面、第二侧面及第三侧面围成容纳空间；上电极结构220，上电极结构220与第一侧面、第二侧面及第三侧面接触连接，且上电极结构220填充满容纳空间，下电极结构180、电容介质层210及上电极结构220构成电容230。换句话说，电容介质层210覆盖下电极结构180的部分表面、电容介质层210覆盖第一层间介质层130及第二层间介质层的侧壁且电容介质层210还覆盖第一隔离层120的表面，上电极结构220覆盖电容介质层210的表面，电容230的下电极结构180与上电极结构220之间的距离及电容介质层210的材料都可能影响电容230的容量大小，故可以通过根据实际的需求设置电容230的下电极结构180与上电极结构220之间的间距、下电极结构180与上电极结构220之间的正对面积以及电容介质层210的材料。
在一些实施例中，电容介质层210还可以覆盖第一隔离层120的侧壁，以形成沿第一方向X共用电容介质层210的电容230。通过设置电容介质层210覆盖第一隔离层120的侧 壁可以减少半导体结构的工艺步骤，且通过设置共用电容介质层210的电容230还可以提高半导体结构的空间利用率。
在一些实施例中，上电极结构220在基底100上的投影位于下电极结构180在基底100内的投影内。换句话说，在第三方向Z上，上电极结构220的长度小于下电极结构180的长度，通过设置上电极结构220的长度小于下电极结构180的长度可以减小半导体结构的制作难度，且可以在避免在形成字线280的过程中暴露电容介质层210，从而提高半导体结构的可靠性。
在一些实施例中，有源结构350的材料可以为氧化物半导体。通过设置有源结构350的材料为氧化物半导体可以提高有源结构350内的载流子的活性，从而可以提高有源结构350内的载流子迁移率。可以理解的是，有源结构350与上述半导体结构的制作方法中的氧化物半导体层250对应。
在一些实施例中，还可以包括：字线280，字线280环绕有源结构350的表面，且字线280沿第一方向X或者第二方向Y中的一者延伸；位线320，位线320环绕有源结构350的表面，位线320与字线280间隔，且位线320沿第一方向X或者第二方向Y中的另一者延伸。通过设置字线280环绕有源结构350的表面可以控制有源结构350的导通，通过设置位线320环绕有源结构350的表面可以通过位线320实现半导体结构的读写。
在一些实施例中，半导体结构还包括：栅极介质层300，栅极介质层300位于有源结构350的表面。通过形成栅极介质层300可以避免字线280与有源结构350直接接触，从而避免半导体结构异常。
在一些实施例中，字线280包括：第一字线281和第二字线282，第一字线281环绕有源结构350设置，第二字线282覆盖第一字线281的侧壁。通过形成环绕有源结构350的第一字线281可以提高字线280与有源结构350的接触面积，通过形成第二字线282可以为后续形成与字线280对应连接的导电柱提供接触基础。
在一些实施例中，第一字线281环绕栅极介质层300的表面。
在一些实施例中，半导体结构还包括：第一层间介质层130和第二层间介质层150，通过设置第一层间介质层130和第二层间介质层150可以提高电容230和字线280的绝缘性，且还可以对半导体结构起到支撑作用，从而避免半导体结构变形，提高半导体结构的可靠性。
在一些实施例中，半导体结构还可以包括：第三隔离层270，第三隔离层270位于在第二方向Y上相邻的有源结构350之间，通过第三隔离层270可以将相邻的有源结构350隔离开，避免相邻的有源结构350出现电连接，从而可以提高半导体结构的可靠性。
在一些实施例中，半导体结构还可以包括：第四隔离层330，第四隔离层330覆盖部分有源结构350的表面，且第四隔离层330与字线280沿第三方向Z排布的侧壁接触连接。通过形成第四隔离层330可以将位线320与字线280隔离开，从而可以避免位线320与字线280之间出现电连接，从而可以提高半导体结构可靠性。
在一些实施例中，半导体结构还可以包括：导电柱340，一导电柱340与一字线280对应连接，通过导电柱340可以通过向导电柱340提供电信号进而控制字线280的导通与断 开，通过向不同的导电柱340提供信号，从而向与该导电柱340连通的字线280提供电信号，也就是说可以通过控制不同的导电柱340进而控制不同的字线280。
本公开实施例通过设置有源结构350位于基底100表面，通过设置下电极结构180与有源结构350接触连接，通过设置位于相邻有源结构350之间的第一隔离层120，且有源结构350在基底100表面的投影与第一隔离层120在基底100表面的投影部分重叠，也就是说，有源结构350的长度小于第一隔离层120，从而可以缩小半导体结构的体积，提高半导体结构的空间利用率。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种半导体结构的制作方法，其特征在于，包括：
    提供基底；
    在所述基底表面形成沿第一方向间隔排布的堆叠结构及位于相邻堆叠结构之间的第一隔离层，所述堆叠结构包括第一层间介质层、初始有源层和第二层间介质层；
    刻蚀部分所述初始有源层，以形成第一沟槽；
    在所述第一沟槽中形成金属导电层，所述金属导电层与保留的所述初始有源层接触连接；
    刻蚀部分所述金属导电层，以形成沿所述第一方向和第二方向阵列排布的下电极结构；
    所述第一方向垂直于所述基底表面，所述第二方向平行于所述基底表面。
  2. 根据权利要求1所述的半导体结构的制作方法，其特征在于，形成所述下电极结构之后还包括：
    刻蚀位于所述下电极结构顶面及底面的所述第一层间介质层及所述第二层间介质层，以形成第二沟槽，所述第二沟槽露出部分所述下电极结构的表面；
    形成电容介质层，所述电容介质层覆盖所述第二沟槽的内壁；
    形成上电极结构，所述上电极结构位于所述电容介质层的表面，且填充满所述第二沟槽，所述下电极结构、电容介质层及所述上电极结构构成电容。
  3. 根据权利要求2所述的半导体结构的制作方法，其特征在于，形成所述电容介质层的步骤包括：形成覆盖所述第一隔离层侧壁的所述电容介质层，以形成在所述第一方向上共用所述电容介质层的所述电容。
  4. 根据权利要求1所述的半导体结构的制作方法，其特征在于，形成所述下电极结构之后还包括：
    刻蚀剩余的所述初始有源层，以形成第三沟槽；
    形成氧化物半导体层，所述氧化物半导体层位于所述第三沟槽内，所述氧化物半导体层与剩余的所述金属导电层接触连接。
  5. 根据权利要求4所述的半导体结构的制作方法，其特征在于，形成所述氧化物半导体层后，还包括：
    刻蚀所述氧化物半导体层及剩余的所述金属导电层，以形成第四沟槽，所述第四沟槽将所述堆叠结构沿所述第二方向间隔。
  6. 根据权利要求5所述的半导体结构的制作方法，其特征在于，刻蚀部分所述金属导电层后，所述半导体结构的制作方法还包括：形成第二隔离层，所述第二隔离层位于沿所述第二方向排布的相邻的所述下电极结构之间；
    形成所述第四沟槽后，形成第三隔离层，所述第三隔离层填充满所述第四沟槽。
  7. 根据权利要求4所述的半导体结构的制作方法，其特征在于，所述氧化物半导体层的材料包括：铟镓锌氧化物或锌锡氧化物。
  8. 根据权利要求4所述的半导体结构的制作方法，其特征在于，形成所述氧化物半导体层 后还包括：形成字线，所述字线环绕所述氧化物半导体层的表面，且所述字线沿所述第一方向或者所述第二方向中的一者延伸；
    形成位线，所述位线环绕所述氧化物半导体层的表面，所述位线与所述字线间隔，且所述位线沿所述第一方向或者所述第二方向中的另一者延伸。
  9. 根据权利要求8所述的半导体结构的制作方法，其特征在于，形成所述字线的方法包括：
    形成第一字线，所述第一字线环绕所述氧化物半导体层的表面；
    形成第二字线，所述第二字线覆盖所述第一字线沿所述第二方向排布的侧壁。
  10. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述金属导电层包括：钛、镍、钨、氮化钛中其中一种或多种金属材料。
  11. 一种半导体结构，其特征在于，包括：
    基底；
    位于所述基底表面，沿第一方向和第二方向间隔排布的有源结构，所述第一方向垂直于所述基底表面，所述第二方向平行于所述基底表面；
    沿所述第一方向和所述第二方向间隔排布的下电极结构，所述下电极结构与所述有源结构接触连接；
    第一隔离层，所述第一隔离层位于在所述第一方向上相邻的所述有源结构之间，且所述有源结构在所述基底表面的投影与所述第一隔离层在所述基底表面的投影部分重叠。
  12. 根据权利要求11所述的半导体结构，其特征在于，还包括：电容介质层，所述电容介质层包括：第一侧面，所述第一侧面与所述下电极结构的顶面和底面接触连接；第二侧面，所述第二侧面与所述第一侧面正对，且与所述第一侧面间隔；第三侧面，所述第三侧面与所述第一侧面及所述第二侧面沿第三方向排布的侧壁接触连接，且所述第一侧面、所述第二侧面及所述第三侧面围成容纳空间；
    上电极结构，所述上电极结构与所述第一侧面、所述第二侧面及所述第三侧面接触连接，且所述上电极结构填充满所述容纳空间，所述下电极结构、所述电容介质层及所述上电极结构构成电容。
  13. 根据权利要求12所述的半导体结构，其特征在于，所述上电极结构在所述基底上的投影位于所述下电极结构在所述基底内的投影内。
  14. 根据权利要求11所述的半导体结构，其特征在于，所述有源结构的材料包括氧化物半导体。
  15. 根据权利要求11所述的半导体结构，其特征在于，还包括：字线，所述字线环绕所述有源结构，且所述字线沿所述第一方向或者所述第二方向中的一者延伸；
    位线，所述位线环绕所述有源结构，所述位线与所述字线间隔，且所述位线沿所述第一方向或者所述第二方向中的另一者延伸。
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