WO2023284123A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2023284123A1
WO2023284123A1 PCT/CN2021/120429 CN2021120429W WO2023284123A1 WO 2023284123 A1 WO2023284123 A1 WO 2023284123A1 CN 2021120429 W CN2021120429 W CN 2021120429W WO 2023284123 A1 WO2023284123 A1 WO 2023284123A1
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WIPO (PCT)
Prior art keywords
electrode layer
layer
lower electrode
dielectric layer
semiconductor
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PCT/CN2021/120429
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English (en)
French (fr)
Inventor
肖德元
张丽霞
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长鑫存储技术有限公司
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Priority to KR1020227031204A priority Critical patent/KR20220130242A/ko
Priority to EP21912333.8A priority patent/EP4148792A4/en
Priority to JP2022548072A priority patent/JP7457140B2/ja
Priority to US17/669,544 priority patent/US20230019891A1/en
Publication of WO2023284123A1 publication Critical patent/WO2023284123A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • Embodiments of the present application relate to a semiconductor structure and a manufacturing method thereof.
  • the aspect ratio of the capacitors is getting higher and higher while the capacitance of the capacitors in the semiconductor devices is increased. Due to limitations of process equipment and size of semiconductor devices, the dimensional accuracy of forming a capacitor with a high aspect ratio is not high, which affects the electrical performance of the capacitor.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • An embodiment of the present application provides a semiconductor structure, including: a substrate and a memory cell on the substrate, the memory cell includes: a first dielectric layer and a metal bit line in the first dielectric layer, and the The first dielectric layer exposes the surface of the metal bit line; a semiconductor channel, the semiconductor channel is located on a part of the surface of the metal bit line, and the semiconductor channel is electrically connected to the metal bit line toward the bottom surface of the metal bit line; A word line, the word line is arranged around a partial area of the semiconductor channel; a second dielectric layer, the second dielectric layer is located between the metal bit line and the word line, and is also located away from the word line One side of the base; a first lower electrode layer and a second lower electrode layer stacked on the top surface of the semiconductor channel away from the metal bit line, the first lower electrode layer and the top of the semiconductor channel Face-to-face contact; upper electrode layer, the upper electrode layer is located on the top surface of the second lower electrode layer, and surrounds the first lower electrode layer and the second lower
  • an embodiment of the present application also provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a memory cell on the substrate, and the process steps of forming the memory cell include: providing a first dielectric layer and The metal bit line in the first dielectric layer, and the first dielectric layer exposes the surface of the metal bit line; forming a semiconductor channel, the semiconductor channel is located on a part of the surface of the metal bit line, and the semiconductor channel faces the metal bit line
  • the bottom surface of the metal bit line is electrically connected to the metal bit line; a word line is formed, and the word line is arranged around a part of the semiconductor channel; a second dielectric layer is formed, and the second dielectric layer is located on the metal bit line.
  • first lower electrode layer the first lower electrode layer is in contact with the top surface of the semiconductor channel
  • second Two lower electrode layers the second lower electrode layer is located on the top surface of the first lower electrode layer
  • an upper electrode layer is formed, the upper electrode layer is located on the top surface of the second lower electrode layer, and surrounds the The first lower electrode layer and the second lower electrode layer are formed
  • a capacitor dielectric layer is formed, and the capacitor dielectric layer is located between the upper electrode layer and the first lower electrode layer, and is also located Between the upper electrode layer and the second lower electrode layer.
  • FIG. 1 is a schematic diagram of a cross-sectional structure corresponding to a semiconductor structure provided by an embodiment of the present application
  • FIGS. 2 to 6 are schematic diagrams of five cross-sectional structures of the structure composed of the first lower electrode layer, the second lower electrode layer and the capacitor dielectric layer in the semiconductor structure provided by an embodiment of the present application;
  • FIG. 7 to FIG. 22 are schematic cross-sectional structure diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by another embodiment of the present application.
  • embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • the channel region of the semiconductor channel is vertically arranged on the surface of the metal bit line, so that the semiconductor structure includes a vertical all-around gate (GAA, Gate-All-Around) transistor, which is beneficial to save the semiconductor channel in parallel to the metal bit line.
  • GAA vertical all-around gate
  • the layout space in the line surface direction (usually the horizontal direction), thereby increasing the integration density of the semiconductor structure in the horizontal direction.
  • the lower electrode layer is formed by stacking the first lower electrode layer and the second lower electrode layer, which is beneficial to increase the overall height of the lower electrode layer of the capacitor to increase the depth and width of the capacitor Ratio, thereby increasing the facing area of the upper electrode layer and the lower electrode layer in the capacitor to increase the capacitance of the capacitor.
  • the orthographic projection of the bottom surface of the second lower electrode layer on the substrate is located within the orthographic projection of the top surface of the first lower electrode layer on the substrate, so that the second lower electrode layer is aligned with the first lower electrode layer, that is, to ensure that the second lower electrode layer
  • the bottom surface of the electrode layer is in full contact with the top surface of the first lower electrode layer, avoiding the misalignment between the bottom surface of the second lower electrode layer and the top surface of the first lower electrode layer, thereby improving the capacitance capacity while improving the dimensional accuracy of the capacitance to improve
  • the formation quality of the capacitor ensures that the capacitor has good electrical properties.
  • the capacitive dielectric layer also covers the top surface of the first lower electrode layer exposed by the second lower electrode layer, preventing the upper electrode layer from contacting the first lower electrode layer through the top surface of the first lower electrode layer exposed by the second lower electrode layer, To further ensure that the capacitor has good electrical properties.
  • FIG. 1 is a schematic diagram of a cross-sectional structure corresponding to a semiconductor structure provided by an embodiment of the present application
  • Figures 2 to 6 show the common structure of the first lower electrode layer, the second lower electrode layer and the capacitor dielectric layer in the semiconductor structure provided by an embodiment of the present application. Five cross-sectional schematic diagrams of the formed structure.
  • the semiconductor structure includes: a substrate 110 and a memory cell 100 located on the substrate 110, the memory cell 100 includes: a first dielectric layer 103 and a metal bit line 101 located in the first dielectric layer 103, and the first The dielectric layer 103 exposes the surface of the metal bit line 101; the semiconductor channel 102, the semiconductor channel 102 is located on a part of the surface of the metal bit line 101, and the semiconductor channel 102 is electrically connected to the metal bit line 101 toward the bottom surface of the metal bit line 101; the word line 104, the word line 104 is set around a part of the semiconductor channel 102; the second dielectric layer 105, the second dielectric layer 105 is located between the metal bit line 101 and the word line 104, and is also located on the side of the word line 104 away from the substrate 110; in the semiconductor channel 102
  • the first lower electrode layer 116 and the second lower electrode layer 126 are stacked away from the top surface of the metal bit line 101, the first lower electrode layer 116 is in contact with the top surface of the semiconductor
  • the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110; , and also cover the side surfaces of the first lower electrode layer 116 and the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 .
  • the semiconductor channel 102 includes a first doped region I, a channel region II and a second doped region III arranged in sequence, the first doped region I and the metal bit line 101 electrical connection; the word line 104 is arranged around the channel region II; the first lower electrode layer 116 is in contact with the side of the second doped region III away from the channel region II.
  • the semiconductor structure includes a vertical GAA (Gate-All-Around) transistor, and the metal bit line 101 is located between the substrate 110 and the GAA transistor, a 3D (3Dimensions) stacked memory device can be formed, It is beneficial to increase the integration density of the semiconductor structure.
  • the capacitor in the semiconductor structure is composed of the first lower electrode layer 116, the second lower electrode layer 126, the capacitor dielectric layer 136 and the upper electrode layer 146, wherein the lower electrode layer of the capacitor is composed of the first lower electrode layer 116 and the second electrode layer.
  • the two lower electrode layers 126 are stacked.
  • the first lower electrode layer 116 and the second lower electrode layer 116 with a lower height can be formed step by step.
  • the electrode layer 126 because the height of the first lower electrode layer 116 and the second lower electrode layer 126 is relatively low, helps to avoid the inclination or collapse of the first lower electrode layer 116 and the second lower electrode layer 126, and improves the overall stability of the lower electrode layer.
  • the second lower electrode layer 126 is aligned with the first lower electrode layer 116, that is, the misalignment between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116 is avoided, thereby improving the capacity while , improve the dimensional accuracy of the capacitor to improve the quality of the capacitor and ensure that the capacitor has good electrical properties.
  • the semiconductor structure will be described in more detail below with reference to FIG. 1 .
  • the substrate 110 may be a logic circuit structure layer with several logic circuits.
  • the first dielectric layer 103 may include: an interlayer dielectric layer 120, the interlayer dielectric layer 120 is located on the surface of the substrate 110, and the metal bit line 101 is located on a part of the surface of the interlayer dielectric layer 120 away from the substrate 110; an isolation layer 130, the isolation layer 130 is located
  • the metal bit line 101 exposes the surface of the interlayer dielectric layer 120 and covers the sidewall of the metal bit line 101 .
  • the logical circuit structure layer may be a laminated structure.
  • Part of the surface of the interlayer dielectric layer 120 away from the logic circuit structure layer may have a plurality of metal bit lines 101 arranged at intervals, and each metal bit line 101 may be electrically connected to at least one first doped region I, as shown in FIG. 1 Taking each metal bit line 101 in contact with two first doped regions I as an example, the number of first doped regions I in contact with each metal bit line 101 can be reasonably set according to actual electrical requirements.
  • the top surface of the metal bit line 101 can be flush with the top surface of the isolation layer 130 , which is beneficial to provide good support for other structures located on the top surface of the metal bit line 101 and the top surface of the isolation layer 130 .
  • the interlayer dielectric layer 120 is used to realize the insulation between the logic circuit structure layer and the metal bit lines 101 , and the interlayer dielectric layer 120 is beneficial to prevent electric leakage between adjacent metal bit lines 101 .
  • the material of the interlayer dielectric layer 120 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon carbonitride.
  • the isolation layer 130 is located between the adjacent metal bit lines 101 and is used to realize the insulation between the adjacent metal bit lines 101 .
  • the material of the isolation layer 130 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon carbonitride.
  • the interlayer dielectric layer 120 and the isolation layer 130 have an integrated structure, thereby improving the interface state defects between the interlayer dielectric layer 120 and the isolation layer 130, improving the performance of the semiconductor structure, and the material of the interlayer dielectric layer 120
  • the material of the isolation layer 130 is the same as that of the isolation layer 130 , which is beneficial to reduce the manufacturing process steps of the semiconductor structure, and reduce the manufacturing cost and complexity of the semiconductor structure.
  • the interlayer dielectric layer and the isolation layer may have a layered structure, and the materials of the interlayer dielectric layer and the isolation layer may be different.
  • the material of the metal bit line 101 is metal, and the benefits of such setting include: on the one hand, the resistivity of the metal bit line 101 of the metal material is generally small, which is beneficial to reduce the resistance of the metal bit line 101 and improve the electrical conductivity of the metal bit line 101.
  • the transmission rate of the signal reduces the parasitic capacitance of the metal bit line 101, and reduces heat loss to reduce power consumption;
  • the semiconductor structure can also include a circuit structure, and the circuit structure has a metal conductive layer for realizing electrical connection, For example, M0 layer, M1 layer, M2 layer, etc. commonly referred to by those skilled in the art, can use the process steps of the metal conductive layer to form the metal bit line 101 at the same time as the metal conductive layer is formed. In this way, the manufacturing process steps of the semiconductor structure can be saved. Reduce the cost of semiconductor structures.
  • the material of the metal bit line 101 may be a single metal, a metal compound or an alloy.
  • the single metal can be copper, aluminum, tungsten, gold or silver, etc.
  • the metal compound can be tantalum nitride or titanium nitride
  • the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold or silver.
  • the material of the metal bit line 101 can also be at least one of nickel, cobalt or platinum.
  • the material of the metal bit line 101 is copper.
  • the semiconductor structure may include a plurality of metal bit lines 101 arranged at intervals, and each metal bit line 101 extends along a first direction; each metal bit line 101 may be electrically connected to at least two semiconductor channels 102 .
  • the material of the semiconductor channel 102 includes at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide, Indium Tungsten Oxide) or ITO (Indium Tin Oxide), the semiconductor channel
  • IGZO Indium Gallium Zinc Oxide
  • IWO Tin-doped Indium Oxide, Indium Tungsten Oxide
  • ITO Indium Tin Oxide
  • the material of the semiconductor channel 102 is IGZO
  • the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is conducive to improving the carrier mobility of the channel region II in the semiconductor channel 102.
  • efficiency which is beneficial to reduce the leakage current when the semiconductor structure is working, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure.
  • the retention time of the memory cells configured with all-surrounding gate transistors formed by the IGZO semiconductor channel 102 can exceed 400s, which is beneficial to reduce the refresh rate and power consumption of the memory.
  • the semiconductor channel 102 is a cylindrical structure, and the side surface of the semiconductor channel 102 is a smooth transition surface, which is beneficial to avoid tip discharge or leakage in the semiconductor channel 102 and further improves the electrical performance of the semiconductor structure.
  • the semiconductor channel may also be an elliptical columnar structure, a square columnar structure or other irregular structures. It can be understood that when the semiconductor channel structure is a square columnar structure, the corners formed by the adjacent surfaces of the side walls of the square columnar structure can be rounded corners, which can also avoid the problem of tip discharge.
  • the square columnar structure can be a cube columnar structure or a cuboid columnar structure.
  • the first doped region I constitutes one of the source or the drain of the transistor device
  • the second doped region III constitutes the other of the source or the drain of the transistor device.
  • the semiconductor elements in the first doped region I, the channel region II and the second doped region III are the same, that is, the first doped region I, the channel region II and the second doped region III have an integral structure, which is beneficial to improve
  • the interface state defects between the first doped region I and the channel region II are improved, and the interface state defects between the channel region II and the second doped region III are improved to improve the performance of the semiconductor structure.
  • the semiconductor channel may also have a three-layer structure, and each layer structure is correspondingly used as a first doped region, a channel region and a third doped region.
  • the first doped region I may include: a first metal-semiconductor layer 112, the first metal-semiconductor layer 112 is in contact with the metal bit line 101, and the resistivity of the first metal-semiconductor layer 112 is smaller than that of the first metal-semiconductor layer 112 The resistivity of the first doped region I. In this way, it is beneficial to reduce the resistivity of the first doped region I, and the first metal-semiconductor layer 112 forms an ohmic contact with the first doped region I other than the first metal-semiconductor layer 112, avoiding direct contact between the metal bit line 101 and the semiconductor material.
  • the Schottky barrier contact formed by the contact, the ohmic contact is conducive to reducing the contact resistance between the first doped region I and the metal bit line 101, thereby reducing the energy consumption when the semiconductor structure is working, and improving the RC delay effect, so as to Improving the electrical performance of semiconductor structures.
  • the semiconductor material of the first doped region may also directly contact the metal bit line, that is, the first doped region does not include the first metal-semiconductor layer.
  • the metal element in the first metal-semiconductor layer 112 includes at least one of cobalt, nickel or platinum.
  • the material of the semiconductor channel 102 as IGZO as an example, correspondingly, the material of the first metal-semiconductor layer 112 may be IGZO containing nickel, IGZO containing cobalt, IGZO containing cobalt-nickel, or IGZO containing platinum.
  • the first metal-semiconductor layer 112 may also be doped with nitrogen.
  • the semiconductor element in the first metal-semiconductor layer 112 is the same as the semiconductor element in the first doped region I outside the first metal-semiconductor layer 112, that is, the first doped region I has an integral structure, and the first metal-semiconductor layer 112 is a part of the first doped region I, which is beneficial to improve the interface state defects between the first metal-semiconductor layer 112 and the first doped region I except the first metal-semiconductor layer 112, and improve the performance of the semiconductor structure.
  • the semiconductor element in the first metal-semiconductor layer may also be different from the semiconductor element in the first doped region outside the first metal-semiconductor layer, for example, the semiconductor element in the first metal-semiconductor layer
  • the semiconductor element may be silicon or germanium.
  • the first doped region is a double-layer structure including the first metal semiconductor layer.
  • the semiconductor channel 102 is in contact with the metal bit line 101 , that is, the first doped region I is located on the surface of the metal bit line 101 .
  • the semiconductor structure may further include: a metal layer 108 located on the surface of the metal bit line 101 not covered by the semiconductor channel 102 , and the metal layer 108 is composed of metal elements in the first metal semiconductor layer 112 . It can be understood that the metal layer 108 is formed simultaneously in the process step of forming the first metal-semiconductor layer 112 , and the material of the metal layer 108 may be at least one of cobalt, nickel or platinum.
  • the material of the metal bit line 101 is at least one of nickel, cobalt or platinum, then correspondingly, in the manufacturing process steps of the semiconductor structure, the Part of the metal bit line 101 reacts with the first doped region I to form the first metal-semiconductor layer 112.
  • the metal bit line 101 and the first metal-semiconductor layer 112 have an integrated structure, which is beneficial to further reduce the metal bit line.
  • Contact resistance between the wire 101 and the first metal-semiconductor layer 112 may provide a metal element for forming the first metal semiconductor layer 112 .
  • the second doped region III may include: a second metal-semiconductor layer 122, the second metal-semiconductor layer 122 is in contact with the lower electrode layer 116, and the resistivity of the material of the second metal-semiconductor layer 122 is smaller than that of the second metal-semiconductor layer 122 The resistivity of the outer second doped region III. In this way, it is beneficial to reduce the resistivity of the second doped region III; and an ohmic contact is formed between the second metal semiconductor layer 122 and the capacitor structure, which is beneficial to reduce the contact resistance between the second doped region III and the capacitor structure, thereby The energy consumption of the semiconductor structure is reduced to improve the electrical performance of the semiconductor structure.
  • the metal element in the second metal-semiconductor layer 122 includes at least one of cobalt, nickel or platinum.
  • the metal elements in the first metal-semiconductor layer 112 and the metal elements in the second metal-semiconductor layer 122 may be the same. In other embodiments, the metal elements in the first metal-semiconductor layer and the metal elements in the second metal-semiconductor layer may also be different.
  • the semiconductor element in the second metal-semiconductor layer 122 is the same as the semiconductor element in the second doped region III outside the second metal-semiconductor layer 122, that is, the second doped region III has an integral structure, and the second metal The semiconductor layer 122 is a part of the second doped region III, which is conducive to improving the interface state defects between the second metal semiconductor layer 122 and the second doped region III except the second metal semiconductor layer 122, and improving the stability of the semiconductor structure. performance.
  • the semiconductor element in the second metal-semiconductor layer may also be different from the semiconductor element in the second doped region outside the second metal-semiconductor layer, for example, the semiconductor element in the second metal-semiconductor layer
  • the semiconductor element may be silicon or germanium, and correspondingly, the second doped region is a double-layer structure including a second metal semiconductor layer.
  • the second metal semiconductor layer 122 includes at least one of cobalt silicide, nickel silicide or platinum silicide.
  • the second metal-semiconductor layer 122 may also be doped with nitrogen.
  • the width of the semiconductor channel 102 is in the range of nanoscale, and when the semiconductor channel 102 is used to form a channel of a junctionless transistor (Junctionless Transistor), it is beneficial to form a nanoscale junctionless transistor.
  • the channel that is, the dopant ions in the first doped region I, the channel region II and the second doped region III are of the same type, for example, the doped ions are all N-type ions or all are P-type ions, further, Doping ions in the first doped region I, the channel region II and the second doped region III may be the same.
  • no junction here refers to no PN junction, that is, there is no PN junction in the transistor formed by the semiconductor channel 102, and such benefits include: III is additionally doped, thereby avoiding the problem that the doping process of the first doped region I and the second doped region III is difficult to control, especially as the size of the transistor is further reduced, if the first doped region is additionally I and the second doping region III are doped, and the doping concentration is more difficult to control; on the other hand, since the device is a junctionless transistor, it is beneficial to avoid the use of an ultra-steep source-drain concentration gradient doping process, and it can be fabricated in the nanoscale range The phenomenon of ultra-steep PN junction, so it can avoid the threshold voltage drift and leakage current increase caused by doping mutation, and it is also beneficial to suppress the short channel effect, and it can still work in the scale of a few nanometers, so it helps Further improve the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping
  • the concentration of doping ions in the first doping region I and the concentration of doping ions in the second doping region III may both be greater than the doping concentration of doping ions in the channel region II.
  • the doping ions are N-type ions or P-type ions, specifically, the N-type ions are at least one of arsenic ions, phosphorus ions or antimony ions; the P-type ions are at least one of boron ions, indium ions or gallium ions .
  • the word line 104 includes a gate dielectric layer 114 , and the gate dielectric layer 114 can surround the entire sidewall surface of the semiconductor channel 102 , which is beneficial to avoid leakage of the semiconductor channel 102 and improve the electrical performance of the GAA transistor.
  • the gate dielectric layer may only cover the sidewall surface of the semiconductor channel in the channel region, or the gate dielectric layer may cover the channel region and the sidewall surface of the semiconductor channel in the first doped region, or the gate dielectric layer
  • the layer covers the channel region and the sidewall surface of the semiconductor channel of the second doped region, wherein the gate dielectric layer is arranged around the second doped region, that is, when it is located on the sidewall surface of the semiconductor channel of the second doped region, the gate dielectric layer
  • the layer can protect the surface of the second doping region and avoid process damage to the surface of the second doping region during the manufacturing process, thereby helping to further improve the electrical performance of the semiconductor structure.
  • the word line 104 further includes a gate conductive layer 124 disposed around a part of the semiconductor channel 102 , and the gate dielectric layer 14 is located between the semiconductor channel 102 and the gate conductive layer 124 .
  • the gate conductive layer 124 is disposed around the channel region II, and is located on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II.
  • the material of the gate dielectric layer 114 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride
  • the material of the gate conductive layer 124 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum. A sort of.
  • the semiconductor structure may include a plurality of word lines 104 arranged at intervals, and each word line 104 extends along a second direction.
  • the second direction is different from the first direction.
  • the first direction may be the same as the second direction. vertical.
  • each word line 104 can be arranged around the channel region II of at least one semiconductor channel 102. In FIG. 1, each word line 104 surrounds two semiconductor channels 102 as an example. According to actual electrical requirements, the number of semiconductor channels 102 surrounded by each word line 104 is reasonably set.
  • the second dielectric layer 105 is used to isolate the metal layer 108 and the word line 104 to isolate the metal bit line 101 from the word line 104 , and is also used to isolate the adjacent word line 104 from the adjacent metal layer 108 . That is to say, the second dielectric layer 105 is located between the metal layer 108 and the word lines 104 , and is also located in the space between the adjacent word lines 104 and the space between the adjacent metal layers 108 .
  • the second dielectric layer 105 may include: a third dielectric layer 115, the third dielectric layer 115 is located between the metal layer 108 and the word line 104 and in the interval between the adjacent metal layers 108, so that the metal layer 108 and the word line 104 insulation between the metal layer 108 and the word line 104, to further prevent the electrical interference between the metal bit line 101 and the word line 104; the fourth dielectric layer 125, the fourth dielectric layer 125 is located in the adjacent word Between the lines 104 and in contact with the third dielectric layer 115, it is used to realize the insulation between the adjacent word lines 104 and prevent the electrical interference between the adjacent word lines 104; the fourth dielectric layer 125 is also located far away from the word lines 104 The surface of the base 110 is used to support other conductive structures located on the surface of the fourth dielectric layer 125 away from the base 110 , and realize the insulation between the word line 104 and other conductive structures.
  • the top surface of the fourth dielectric layer 125 can be flush with the top surface of the second doped region III, which is beneficial to provide good support for other structures located on the top surface of the fourth dielectric layer 125 and the top surface of the second doped region III.
  • the material of the third dielectric layer 115 is the same as that of the fourth dielectric layer 125 , which can be at least one of silicon oxide, silicon nitride, silicon carbon oxynitride, or silicon oxynitride. In other embodiments, the material of the third dielectric layer and the material of the fourth dielectric layer may also be different.
  • the second dielectric layer can also be other stacked film structure, and the specific structure of the stacked film structure is related to the manufacturing process steps, as long as the second dielectric layer can serve the purpose of isolation.
  • the capacitor includes: a first lower electrode layer 116 , a second lower electrode layer 126 , a capacitor dielectric layer 136 and an upper electrode layer 146 .
  • the capacitor will be described in detail below with reference to FIGS. 1 to 6 .
  • each word line 104 constitutes the lower electrode layer of the capacitor, and each word line 104 extends along the second direction.
  • each word line 104 surrounds two semiconductor channels. 102, and the first lower electrode layer 116 and the second lower electrode layer 126 also extend along the second direction as an example.
  • each lower electrode layer corresponds to a word line 104, that is, each lower electrode layer is in contact with the side of each second doped region III surrounded by the word line 104 corresponding to the lower electrode layer away from the channel region II.
  • each lower electrode layer is in contact with the top surfaces of the second doped regions III of the two semiconductor channels 102 as an example.
  • the thickness of the first lower electrode layer 116 may be greater than the thickness of the second lower electrode layer 126; in other examples, in the direction perpendicular to the surface of the substrate 110, the first The thickness of the lower electrode layer 116 may also be less than or equal to the thickness of the second lower electrode layer 126 .
  • the material of the first lower electrode layer 116 may be the same as that of the second lower electrode layer 126 .
  • the materials of the first lower electrode layer 116 and the second lower electrode layer 126 may also be different.
  • the upper electrode layer 146 also extends along the second direction.
  • the upper electrode layer 146 corresponds to the lower electrode layer one by one, and the orthographic projection of the upper electrode layer 146 on the substrate 110 covers the orthographic projection of the lower electrode layer on the substrate 110.
  • the orthographic projection of the electrode layer on the substrate 110 covers the orthographic projection of the word line 104 on the substrate 110 .
  • each lower electrode layer may only be in contact with one side of the second doped region away from the channel region, and the upper electrode layer may correspond to the lower electrode layer one by one or one upper electrode layer may correspond to multiple lower electrode layers.
  • a lower electrode layer can be in contact with a plurality of second doped regions away from the side of the channel region, and the upper electrode layer can only correspond to one semiconductor channel, that is, a lower electrode layer corresponds to a plurality of upper electrode layers , so that the upper electrode layer or the lower electrode layer of adjacent capacitors can be connected to different potentials, which is beneficial to realize multiple control of adjacent capacitors.
  • the lower electrode layer is composed of the first lower electrode layer 116 and the second lower electrode layer 126 which are stacked, which is beneficial to increase the overall height of the lower electrode layer, so as to increase the capacitance capacity of the capacitor while forming a lower height in steps.
  • the way of the first lower electrode layer 116 and the second lower electrode layer 126 avoids the inclination or collapse of the first lower electrode layer 116 and the second lower electrode layer 126, and improves the overall stability of the lower electrode layer.
  • the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, ensuring that the bottom surface of the second lower electrode layer 126 is completely consistent with the top surface of the first lower electrode layer 116. contact, to avoid dislocation between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, and improve the dimensional accuracy of the capacitor.
  • the width of the bottom surface of the first bottom electrode layer 116 is smaller than the maximum width of the semiconductor channel 102 along the extending direction of the metal bit line 101 . In other embodiments, the width of the bottom surface of the first lower electrode layer may be greater than or equal to the maximum width of the semiconductor channel.
  • the first lower electrode layer 116 includes: the first lower conductive column 113, the first lower conductive column 113 is in contact with the second doped region III; the first lower conductive block 123, the first lower conductive block One end of 123 is in contact with the first lower conductive pillar 113 , and the other end is in contact with the second lower electrode layer 126 .
  • the second lower electrode layer 126 includes: the second lower conductive column 133, the second lower conductive column 133 is in contact with the first lower conductive block 123; the second lower conductive block 143, one end of the second lower conductive block 143 is connected to the second lower conductive block
  • the pillar 133 is in contact, and the other end is in contact with the capacitive dielectric layer 136 .
  • the first lower conductive pillar 113 covers the entire top surface of the second doped region III, and along the direction away from the substrate 110, the cross-sectional area of the first lower conductive pillar 113 in a direction parallel to the surface of the substrate 110 gradually increases, and the orthographic projection of the top surface of the first lower conductive pillar 113 on the substrate 110 coincides with the orthographic projection of the bottom surface of the first lower conductive block 123 on the substrate 110, ensuring that the second doped region III and the first lower electrode At the same time, it is beneficial to increase the volume of the first lower electrode layer 116 to reduce the resistance of the first lower electrode layer 116 itself, thereby reducing the contact area between the second doped region III and the first lower electrode layer. The contact resistance between the electrode layers 116.
  • the orthographic projection of the bottom surface of the second lower conductive pillar 133 on the substrate 110 is located at the first lower conductive pillar 133.
  • the orthographic projection of the bottom surface of the block 123 on the substrate 110 it is beneficial to increase the volume of the second lower electrode layer 126 while avoiding the dislocation between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, In order to reduce the resistance of the second lower electrode layer 126 itself, it is beneficial to reduce the contact resistance between the second lower electrode layer 126 and the first lower electrode layer 116 .
  • the orthographic projection of the top surface of the second lower conductive pillar 133 on the substrate 110 coincides with the orthographic projection of the bottom surface of the second lower conductive block 143 on the substrate 110 .
  • the orthographic projection of the top surface of the first lower conductive post on the base can cover the orthographic projection of the bottom surface of the first lower conductive block on the base
  • the orthographic projection of the top surface of the second lower conductive post on the base can cover the orthographic projection of the bottom surface of the second lower conductive post on the base.
  • first lower conductive pillar 113 and the first lower conductive block 123 are integrated, and the second lower conductive pillar 133 and the second lower conductive block 143 are integrally structured, thereby improving the first lower conductive pillar 113 and the first lower conductive pillar 113.
  • the materials of the conductive block 123 , the second lower conductive pillar 133 and the second lower conductive block 143 can be the same, which is beneficial to reduce the manufacturing process steps of the semiconductor structure and reduce the manufacturing cost and complexity of the semiconductor structure.
  • the materials of the first lower conductive column 113, the first lower conductive block 123, the second lower conductive column 133 and the second lower conductive block 143 can be platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, At least one of tantalum nitride, titanium nitride or ruthenium.
  • the first lower conductive column and the first lower conductive block may not have an integrated structure, and the second lower conductive column and the second lower conductive block may not have an integrated structure, that is, the first lower conductive column, the first lower conductive
  • the materials of the conductive block, the second lower conductive column and the second lower conductive block can also be different.
  • both the cross-sectional shape of the first lower electrode layer 116 and the cross-sectional shape of the second lower electrode layer 126 can be rectangular; referring to FIG. 6, the cross-sectional shape of the first lower electrode layer 116 and the second The cross-sectional shape of the lower electrode layer 126 may be an inverted trapezoid.
  • the capacitor dielectric layer 136 includes: a first capacitor dielectric layer 156, the first capacitor dielectric layer 156 covers the side of the first lower electrode layer 116; a second capacitor dielectric layer 166, the second capacitor dielectric layer 166 covers The top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 ; the third capacitor dielectric layer 176 , and the third capacitor dielectric layer 176 covers the top surface and side surfaces of the second lower electrode layer 126 .
  • the first capacitive dielectric layer 156, the second capacitive dielectric layer 166 and the third capacitive dielectric layer 176 cover the surfaces of the first lower electrode layer 116 and the second lower electrode layer 126 together, so as to isolate the upper electrode layer 146 from the first lower electrode layer 116 and the second lower electrode layer 126.
  • the second capacitive dielectric layer 166 covers the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126, so as to prevent the top surface of the first lower electrode layer 116 exposed by the upper electrode layer 146 from the second lower electrode layer 126 from contacting with the top surface of the first lower electrode layer 116.
  • the first lower electrode layer 116 is in contact with each other to further ensure that the capacitor has good electrical performance.
  • the capacitive dielectric layer 136 may further include: a fourth capacitive dielectric layer 186, the fourth capacitive dielectric layer 186 is connected to the bottom surface of the first capacitive dielectric layer 156, and moves away from the axis perpendicular to the surface of the substrate 110 away from the first lower electrode layer 116 direction; the upper electrode layer 146 (refer to FIG. 1 ) is also located on the surface of the fourth capacitor dielectric layer 186 .
  • the first lower electrode layer 116 will expose the second doped region III.
  • the fourth capacitive dielectric layer 186 is connected to the bottom surface of the first capacitive dielectric layer 156, and extends away from the first lower electrode layer 116 in the direction of the axis perpendicular to the surface of the substrate 110, which facilitates the realization of
  • the isolation between the upper electrode layer 146 and the second doped region III ensures good electrical properties of the semiconductor structure.
  • the fourth capacitor dielectric layer 186 and the first capacitor dielectric layer 156 are integrally formed, which is conducive to improving the interface state defects between the fourth capacitor dielectric layer 186 and the first capacitor dielectric layer 156, and improving the fourth capacitance.
  • Dielectric layer 186 and the overall isolation effect of the first capacitor dielectric layer 156, and the material of the fourth capacitor dielectric layer 186 and the first capacitor dielectric layer 156 is the same, so it is beneficial to reduce the manufacturing process steps of the semiconductor structure and reduce the manufacturing cost of the semiconductor structure. cost and complexity.
  • the fourth capacitor dielectric layer and the first capacitor dielectric layer may have a layered structure, and the material of the fourth capacitor dielectric layer may be different from that of the first capacitor dielectric layer.
  • the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 has a first capacitive dielectric layer 156, and the second capacitive dielectric layer 166 is located on the top surface of the first capacitive dielectric layer 156, to cover the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 .
  • the second capacitive dielectric layer 166 also extends away from the second lower electrode layer 126 along the axis perpendicular to the surface of the substrate 110 to further improve the isolation effect between the upper electrode layer 146 and the top surface of the first lower electrode layer 116 .
  • the second capacitive dielectric layer 166 is in contact with the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 , and is perpendicular to the surface of the substrate 110 away from the second lower electrode layer 126
  • the axial direction of the first bottom electrode layer 116 is extended to realize the isolation between the upper electrode layer 146 and the top surface of the first lower electrode layer 116 .
  • the second capacitive dielectric layer 166 and the third capacitive dielectric layer 176 can be integrally formed, which is conducive to improving the interface state defects between the second capacitive dielectric layer 166 and the third capacitive dielectric layer 176, and improving the connection between the second capacitive dielectric layer 166 and the third capacitive dielectric layer 176.
  • the overall isolation effect of the third capacitor dielectric layer 176, and the material of the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176 are the same, so that it is beneficial to reduce the manufacturing process steps of the semiconductor structure, and reduce the manufacturing cost and complexity of the semiconductor structure .
  • the second capacitor dielectric layer and the third capacitor dielectric layer may have a layered structure, and the material of the second capacitor dielectric layer may be different from that of the third capacitor dielectric layer.
  • the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 has a first capacitor dielectric layer 156
  • the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166 is an integrated structure, which is beneficial to improve the interface state defects between the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166, and improve the overall isolation effect between the first capacitor dielectric layer 156 and the second capacitor dielectric layer 166
  • the second The first capacitive dielectric layer 156 is made of the same material as the second capacitive dielectric layer 166 , which is beneficial to reduce the manufacturing process steps of the semiconductor structure and reduce the manufacturing cost and complexity of the semiconductor structure.
  • the first capacitor dielectric layer and the second capacitor dielectric layer may have a layered structure, and the material of the first capacitor dielectric layer may be different from that of the second capacitor dielectric layer.
  • the structure except the first lower electrode layer 116 in the dotted line box a is the fourth capacitive dielectric layer 186
  • the structure in the dotted line box b except the second lower electrode layer 126 is the second capacitive dielectric layer 166 .
  • the relative permittivity of the material of the capacitor dielectric layer 136 is greater than the relative permittivity of the material of the second dielectric layer 105, which is beneficial to further improve the connection between the first lower electrode layer 116 and the second lower electrode layer 126 and the upper electrode layer.
  • the isolation effect between layers 146 improves the electrical performance of the capacitor in the semiconductor structure.
  • the materials of the first capacitor dielectric layer 156, the second capacitor dielectric layer 166, the third capacitor dielectric layer 176 and the fourth capacitor dielectric layer 186 all include silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide , barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or strontium barium titanate and other high dielectric constant materials.
  • the second capacitor dielectric layers 166 between adjacent capacitors are spaced apart from each other as an example. In fact, the second capacitor dielectric layers 166 of adjacent capacitors can be connected to each other. ; Take the space between the fourth capacitor dielectric layers 186 between adjacent capacitors as an example, in fact, the fourth capacitor dielectric layers 186 of adjacent capacitors can be in contact with each other.
  • the upper electrode layer 146 includes: a first upper electrode layer 196, the first upper electrode layer 196 surrounds the first lower electrode layer 116, and is located on the side of the first capacitor dielectric layer 156; the second upper electrode layer 106, The second upper electrode layer 106 surrounds the second lower electrode layer 116 and is located on the surface of the third capacitive dielectric layer 176 , and the bottom surface of the second upper electrode layer 106 is in contact with the top surface of the first upper electrode layer 196 .
  • Both the material of the first upper electrode layer 196 and the material of the second upper electrode layer 106 can be at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium . In other embodiments, the materials of the first upper electrode layer and the second upper electrode layer may also be different.
  • the overall material of the lower electrode layer 116 and the overall material of the upper electrode layer 136 may be the same. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different.
  • the semiconductor structure may include two memory cells 100 stacked on the substrate 110 .
  • two memory cells 100 stacked on the substrate 110 are taken as an example, and the number of memory cells 100 stacked on the substrate 110 can be reasonably set according to actual electrical requirements. Since multiple storage units 100 can be stacked on the same substrate 110, increasing the size of the semiconductor structure in the thickness direction can increase the array density of the semiconductor structure, improve the storage performance of the semiconductor structure, and reduce the plane size of the semiconductor structure.
  • the purpose of 3D stacking It can be understood that the array density refers to the density of the memory cells 100 within the semiconductor structure.
  • the semiconductor structure further includes: an insulating layer 107, the insulating layer 107 is located on the surface of the second dielectric layer 105, and the capacitance composed of the first lower electrode layer 116, the second lower electrode layer 126, the capacitor dielectric layer 136 and the upper electrode layer 146 Located in the insulating layer 107 , the insulating layer 107 is used to support the capacitor, avoid capacitor collapse, and is also used to isolate the upper electrode layer 146 of the adjacent capacitor 106 .
  • the insulating layer 107 is a stacked film structure, and includes a first insulating layer 117 and a second insulating layer 127 .
  • the first insulating layer 117 is located between adjacent first upper electrode layers 196 for electrical insulation between adjacent first upper electrode layers 196;
  • the second insulating layer 127 is located between adjacent second upper electrode layers 106 , and cover the upper surface of the first insulating layer 117 , for realizing electrical insulation between adjacent second upper electrode layers 106 .
  • the material of the first insulating layer 117 is the same as that of the second insulating layer 127 , which can be at least one of silicon nitride, silicon oxynitride, silicon oxycarbonitride or silicon oxide. In other embodiments, the material of the first insulating layer and the material of the second insulating layer may also be different.
  • the channel region II of the semiconductor channel 102 is vertically arranged on the metal bit line 101, so that there are GAA transistors in the semiconductor structure, thereby forming a 3D stacked memory device, which is beneficial to improving the integration density of the semiconductor structure.
  • the lower electrode layer of the capacitor in the semiconductor structure is composed of the first lower electrode layer 116 and the second lower electrode layer 126 stacked, which is beneficial to increase the overall height of the lower electrode layer of the capacitor to increase the capacitance of the capacitor.
  • the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, so that the second lower electrode layer 126 is aligned with the first lower electrode layer 116 , to avoid the misalignment between the bottom surface of the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, so as to improve the capacitance capacity while improving the dimensional accuracy of the capacitance, so as to improve the formation quality of the capacitance and ensure that the capacitance has good electrical properties. performance.
  • the semiconductor structure provided by this embodiment can be applied to a 4F ⁇ 2 memory, where F is a feature size
  • the memory can be RRAM (Static Random Access Memory), MRAM (Magnetoresistive Random Access Memory) or PCRAM (Phase Change Random Access Memory), DRAM (Dynamic Random Access Memory) memory or SRAM (SRAM, Static Random Access Memory) memory can also be applied to memory computing (IMC, In Memory Computing), which allows users to store data in memory and process information at a faster speed .
  • RRAM Static Random Access Memory
  • MRAM Magneticoresistive Random Access Memory
  • PCRAM Phase Change Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • the memory can be a DRAM memory
  • the metal bit line 101 mentioned in the above embodiment is the bit line of the DRAM memory
  • the word line 104 is the word line of the DRAM memory
  • the capacitor structure is the storage capacitor of the DRAM memory .
  • another embodiment of the present application provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.
  • FIG. 7 to 22 are structural schematic diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by another embodiment of the present application.
  • the manufacturing method of the semiconductor structure provided by this embodiment will be described in detail below in conjunction with the accompanying drawings. The same or corresponding parts will not be described in detail below.
  • a substrate 110 is provided on which a memory cell 100 is formed. Specifically, forming the storage unit 100 includes the following steps:
  • the substrate 110 may be a logic circuit structure layer, and a first dielectric layer 120 and metal bit lines 101 located in the first dielectric layer 120 are provided, and the first dielectric layer 120 exposes the surface of the metal bit lines 101 .
  • the surface interlayer dielectric layer 120 covering the entire surface of the logic circuit structure layer is formed to protect the logic circuit structure layer and prevent interference between the logic circuit structure layer and the subsequent metal bit lines 101 formed on the interlayer dielectric layer 120. electrical interference.
  • a plurality of metal bit lines 101 separated from each other are formed on the surface of the interlayer dielectric layer 120, and the metal bit lines 101 expose part of the surface of the interlayer dielectric layer 120; an isolation layer 130 is formed, and the isolation layer 130 is located at the interlayer dielectric layer exposed by the metal bit line 101 120 and cover the sidewall of the metal bit line 101 .
  • the surface of the logic circuit structure layer may also have an initial dielectric layer; the initial dielectric layer is patterned to form several mutually separated grooves in the initial dielectric layer, and the initial dielectric layer located under the grooves
  • the dielectric layer is used as an interlayer dielectric layer, and the initial dielectric layer located between adjacent trenches is used as an isolation layer.
  • the isolation layer and the initial dielectric layer have an integral structure; then, metal bit lines filling the trenches are formed.
  • a first metal layer 118 is formed on the surface of the metal bit line 101 .
  • the first metal layer 118 is used to react with the region of the subsequently formed semiconductor channel close to the metal bit line 101 to provide metal elements for the subsequent formation of the first metal semiconductor layer to reduce the resistivity of the semiconductor channel.
  • the material of the first metal layer 118 includes at least one of cobalt, nickel or platinum.
  • the first metal layer 118 covers the entire surface of the metal bit line 101 , which can avoid etching damage to the metal bit line 101 caused by the process of etching the first metal layer 118 .
  • the first metal layer may only be located on a part of the surface of the metal bit line, and the position of the first metal layer corresponds to the position of the subsequently formed semiconductor channel.
  • the first metal layer may not be formed on the surface of the metal bit line, and the semiconductor channel may be directly formed on a part of the surface of the metal bit line subsequently.
  • the material of the metal bit line is at least one of nickel, cobalt, or platinum, that is, the metal bit line can provide metal elements for the subsequent formation of the first metal semiconductor layer, and there is no need to place metal elements on the surface of the metal bit line A first metal layer is formed.
  • a semiconductor channel 102 is formed, the semiconductor channel 102 is located on a part of the surface of the metal bit line 101 , and the bottom surface of the semiconductor channel 102 facing the metal bit line 101 is electrically connected to the metal bit line 101 .
  • the semiconductor channel 102 is in contact with the first metal layer 118; in other embodiments, the semiconductor channel may be in direct contact with the metal bit line.
  • the process steps of forming the semiconductor channel 102 include the following steps:
  • an initial channel layer 132 is formed, and the initial channel layer 132 is located on the metal bit line 101 and on the substrate 110 .
  • the first metal layer 118 is formed on the surface of the metal bit line 101 , and the initial channel layer 132 covers the surface of the first metal layer 118 .
  • the initial channel layer may directly cover the surface of the metal bit line.
  • the method for forming the initial channel layer 132 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition or chemical vapor deposition of metal organic compounds.
  • the material of the initial channel layer 132 is IGZO, IWO or ITO.
  • a patterned mask layer 109 is formed on the surface of the initial channel layer 132 .
  • the mask layer 109 is used to define the position and size of the subsequently formed semiconductor channel 102 .
  • the material of the mask layer 109 may be silicon nitride, silicon carbonitride or silicon carbonitride. In other embodiments, the material of the mask layer may also be photoresist.
  • the initial channel layer 132 (refer to FIG. 8 ) is patterned using the mask layer 109 as a mask to form the semiconductor channel 102 .
  • the semiconductor channel 102 includes a first doped region I, a channel region II and a second doped region III arranged in sequence.
  • the semiconductor channel 102 can be used to form a channel of a junctionless transistor , which avoids the threshold voltage shift and leakage current increase caused by doping mutation, and is also beneficial to suppress the short channel effect.
  • the initial channel layer 132 can be pre-doped before the patterning process, and the doping process can be doped with N-type ions or P-type ions; or the initial channel layer 132 can be patterned Doping is then performed to form a semiconductor channel 102 with a suitable ion distribution.
  • the semiconductor channel 102 can be rounded by thermal oxidation, etching and/or hydrogen annealing treatment (corner-rounding) to form a cylindrical semiconductor channel 102, which is beneficial to avoid
  • the semiconductor channel 102 has a phenomenon of tip discharge or electric leakage.
  • a gate dielectric layer 114 is formed on the entire sidewall of the semiconductor channel 102 .
  • the gate dielectric layer 114 exposes the surface of the first metal layer 118 other than directly under the semiconductor channel 102 .
  • the gate dielectric layer 114 is used to protect the semiconductor channel 102 during the subsequent annealing process, preventing the material of the subsequent semiconductor channel 102 from reacting with the metal material.
  • the gate dielectric layer 114 is also located on the end surface of the second doped region III away from the substrate 110, and in the subsequent step of forming the fourth dielectric layer, the gate dielectric layer 114 located on the end surface of the second doped region III away from the substrate 110 is also removed.
  • the dielectric layer 114 facilitates subsequent formation of a metal layer on the end face of the second doped region III away from the substrate 110 .
  • the gate dielectric layer covering the end surface of the second doped region may be removed by an etching process.
  • the gate dielectric layer may be formed only on the sidewall surface of the semiconductor channel in the channel region, or the gate dielectric layer may be formed on the channel region and the sidewall surfaces of the semiconductor channel in the first doped region, or, A gate dielectric layer is formed on the channel region and the sidewall surfaces of the semiconductor channel in the second doped region.
  • a third dielectric layer 115 is formed.
  • the third dielectric layer 115 is located on the surface of the first metal layer 118 away from the substrate 110 and is located in the space between adjacent first metal layers 118 .
  • the third dielectric layer 115 is located on the surface of the isolation layer 130 and the sidewall surface of the gate dielectric layer 114 corresponding to the first doped region I (refer to FIG. 9 ), for isolating the first metal layer 118 from the subsequently formed word Wire.
  • the third dielectric layer 115 is a whole film layer structure, which is used to prevent electrical interference between the first metal layer 118 and the metal bit line 101 and the subsequently formed word line.
  • the step of forming the third dielectric layer 115 includes: forming an initial first dielectric layer on the surface of the metal bit line 101 away from the substrate 110; performing a planarization process on the initial first dielectric layer and etching back to a preset thickness to form a third dielectric layer. Dielectric layer 115.
  • an initial gate conductive layer 134 is formed on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II (refer to FIG. 10), and the initial gate conductive layer 134 surrounds the channel region II, and the initial gate conductive layer 134 is the entire Mask layer structure.
  • the method for forming the initial gate conductive layer 134 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition or chemical vapor deposition of metal organic compounds.
  • the initial gate conductive layer 134 is planarized and etched so that the initial gate conductive layer 134 is located on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II.
  • the initial gate conductive layer 134 (refer to FIG. 12) is patterned to form mutually spaced gate conductive layers 124, so that the gate conductive layers 124 of different semiconductor channels 102 on the same metal bit line 101 can be connected to different potentials, Therefore, it is beneficial to realize diversified control on the semiconductor channel.
  • the patterning method includes photolithography.
  • each gate dielectric layer 114 can be arranged around the channel region II of at least one semiconductor channel 102.
  • each gate dielectric layer 114 surrounds two semiconductor channels 102 as an example. According to actual electrical requirements, the number of semiconductor channels 102 surrounded by each gate dielectric layer 114 is reasonably set.
  • the gate dielectric layer 114 and the gate conductive layer 124 together form the word line 104 , so the word line 104 is also arranged around the two semiconductor channels 102 .
  • a fourth dielectric layer 125 is formed, the fourth dielectric layer 125 is located in the interval between adjacent gate conductive layers 124 for preventing electrical interference between adjacent gate conductive layers 124, and the fourth dielectric layer 125 is also located
  • the surface of the gate conductive layer 124 away from the substrate 110 is used to support other conductive structures subsequently formed on the surface of the fourth dielectric layer 125 away from the substrate 110 , and realize the insulation between the gate conductive layer 124 and other conductive structures.
  • the fourth dielectric layer 125 is planarized, and the gate dielectric layer 114 located on the end surface of the mask layer 109 away from the substrate 110 is removed, so that the fourth dielectric layer 125 exposes the The second doped region III is away from the mask layer 109 on the end surface of the substrate 110 .
  • the third dielectric layer 115 and the fourth dielectric layer 125 together form the second dielectric layer 105
  • the second dielectric layer 105 is located between the metal bit line 101 and the word line 104, and is also located on the word line 104 away from the substrate 110 side.
  • the materials of the third dielectric layer 115 and the fourth dielectric layer 125 are the same, so that it is beneficial to reduce the types of materials required for the manufacturing process of the semiconductor structure, and reduce the manufacturing cost and complexity of the semiconductor structure.
  • the second dielectric layer 105 also exposes the top surface of the mask layer 109 .
  • the mask layer 109 is removed to expose the top surface of the second doped region III (refer to FIG. 10 ), and a second metal layer is formed on the exposed top surface of the second doped region III.
  • the second metal layer is used to react with the second doped region III to provide metal elements for the subsequent formation of the second metal semiconductor layer 122 to reduce the resistivity of the semiconductor channel 102 .
  • the material of the second metal layer includes at least one of cobalt, nickel or platinum.
  • the manufacturing method may further include: performing a first annealing treatment, the first metal layer 118 reacts with the first doped region I, so as to convert the first doped region I facing the metal bit line 101 into a first metal semiconductor layer 112 , the resistivity of the material of the first metal-semiconductor layer 112 is smaller than the resistivity of the material of the first doped region I other than the first metal-semiconductor layer 112 .
  • the first metal layer 118 that reacts with the first doped region I becomes a part of the first doped region I, and the first metal layer 118 that does not react with the first doped region I serves as the metal layer 108 .
  • a part of the thickness of the first metal layer 118 may remain between the metal bit line 101 and the first metal-semiconductor layer 112, and the remaining first metal layer 118 is used as the metal layer 108, that is, the metal layer 108 may be
  • the surface of the metal bit line 101 located outside the first metal semiconductor layer 112 may also be located between the first metal semiconductor layer 112 and the metal bit line 101 .
  • the second annealing treatment is performed, and the second metal layer reacts with the second doped region III to convert the exposed part of the thickness of the second doped region III into the second doped region III.
  • Two metal-semiconductor layers 122 , and the resistivity of the material of the second metal-semiconductor layer 122 is smaller than the resistivity of the second doped region III outside the second metal-semiconductor layer 122 .
  • rapid thermal annealing is used for the annealing treatment, and the process parameters of the rapid thermal annealing include: annealing the semiconductor structure under N 2 atmosphere, the annealing temperature is 600° C.-850° C., and the annealing time is 10 seconds-60 seconds. Due to the moderate annealing temperature, it is beneficial to fully react the first metal layer 118 with the first doped region I, so that the second metal layer fully reacts with the second doped region III to form the first metal semiconductor with relatively small resistivity. layer 112 and the second metal-semiconductor layer 122 .
  • the moderate annealing temperature it is beneficial to prevent metal elements in the first metal layer 118 and the second metal layer from diffusing into the channel region II.
  • performing annealing treatment under N 2 atmosphere is beneficial to avoid oxidation of the first metal layer 118 , the second metal layer and the semiconductor channel 102 .
  • the first annealing treatment and the second annealing treatment are performed simultaneously, which is beneficial to simplify the manufacturing process of the semiconductor structure.
  • the first annealing treatment can be performed; after the second metal layer is formed on the second doped region, the second annealing treatment can be performed.
  • a first semiconductor layer may also be formed on the surface of the first metal layer, the material of the first semiconductor layer is silicon or germanium, and the first semiconductor layer is formed during the first annealing process. layer reacts with the first metal layer to form a first metal semiconductor layer; before forming the second metal layer, a second semiconductor layer is formed on the top surface of the second doped region, the material of the second semiconductor layer is silicon or germanium, and During the second annealing process, the second semiconductor layer reacts with the second metal layer to form a second metal semiconductor layer.
  • a first lower electrode layer 116 is formed, and the first lower electrode layer 116 is in contact with the top surface of the semiconductor channel 102;
  • a second lower electrode layer 126 is formed, and the second lower electrode layer 126 is located on the first lower electrode layer 116 top surface;
  • upper electrode layer 146 and upper electrode layer 146 is positioned at second lower electrode layer 126 top surface, and surrounds first lower electrode layer 116 and second lower electrode layer 126;
  • capacitive dielectric layer 136 capacitive dielectric layer 136 is located between the upper electrode layer 146 and the first lower electrode layer 116 , and is also located between the upper electrode layer 146 and the second lower electrode layer 126 ;
  • the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 is within the orthographic projection of the top surface of the first lower electrode layer 126 on the substrate 110; , and also cover the side surfaces of the first lower electrode layer 116 and the top surface of the first lower electrode layer 116 exposed by the second lower electrode layer 126 .
  • first lower electrode layer 116, the second lower electrode layer 126, the capacitor dielectric layer 136 and the upper electrode layer 146 includes the following steps:
  • a first lower electrode layer 116 is formed.
  • the top surface of the first lower electrode layer 116 includes a central region c and a peripheral region d surrounding the central region c.
  • a sacrificial layer 137 is formed on the side of the second doped region III away from the channel region II, and the sacrificial layer 137 has a first through hole e penetrating through the sacrificial layer 137 and exposing the second doped region III;
  • the first lower electrode layer 116 is filled with the first through hole e.
  • the first through hole e includes a first trench and a second trench which are connected, and the first trench exposes the surface of the second doped region III.
  • the step of forming the first trench and the second trench may include: forming an initial sacrificial layer on the surface of the second dielectric layer 105; forming a patterned mask layer on the surface of the initial sacrificial layer; As a mask, etch the initial sacrificial layer with a partial thickness to form a second trench; in the area corresponding to the second trench, etch the part of the initial sacrificial layer exposed by the second trench to expose the second doped region On the surface III, a first groove with a gradually increasing cross-sectional area is formed in a direction parallel to the surface of the substrate at 110 .
  • the cross-sectional shape of the first through hole e may also be a rectangle or an inverted trapezoid.
  • each word line 104 extends along the second direction
  • each word line 104 surrounds two semiconductor channels 102
  • the first trench and the second trench also extend along the second direction.
  • the first through hole e formed by the first trench and the second trench corresponds to a word line 104, that is, each first through hole e exposes each word line 104 surrounded by the corresponding first through hole e.
  • each first through hole e exposes the top surface of the second doped region III of two semiconductor channels 102 as an example.
  • each first through hole may only expose a side of the second doped region away from the channel region.
  • a first capacitive dielectric film 119 is formed, and the first capacitive dielectric film 119 covers the top and side surfaces of the first lower electrode layer 116 .
  • the process step of forming the first capacitive dielectric film 119 includes: removing the sacrificial layer 137 to form a first initial capacitive dielectric film continuous on the entire surface, and the first initial capacitive dielectric film also covers the top of the first lower electrode layer 116 The surface and side surfaces, that is, the first initial capacitor dielectric film also covers the top surface of the fourth dielectric layer 125 , the gate dielectric layer 114 and the second doped region III (refer to FIG. 10 ) exposed by the first lower electrode layer 116 .
  • the fourth capacitor dielectric layer 186 is connected to the bottom surface of the first capacitor dielectric film 119, and is vertically away from the first lower electrode layer 116 extending in the axial direction of the surface of the substrate 110 .
  • the aspect ratio of the first lower electrode layer 116 itself can be smaller in the direction perpendicular to the surface of the substrate 110, so as to improve the stability of the structure of the first lower electrode layer 116 itself.
  • the first lower electrode layer 116 is not easy to tilt or collapse, so as to improve the overall stability of the semiconductor structure.
  • the first lower electrode layer 116 before forming the first lower electrode layer 116, it further includes: forming a fourth capacitor dielectric layer 186 on the second dielectric layer 105, and the fourth capacitor dielectric layer 186 has a The opening of the capacitor dielectric layer 186, and the opening exposes at least part of the top surface of the second doped region III (refer to FIG. 10 ); in the process step of forming the first lower electrode layer 116, the first lower electrode layer 116 fills the opening; A first capacitive dielectric film 119 covering the top and side surfaces of the first lower electrode layer 116 is formed.
  • a third via hole can be formed that penetrates the sacrificial layer and at least exposes the entire top surface of the second doped region; forms an initial first capacitive dielectric layer on the sidewall and bottom of the third via hole; The initial first capacitor dielectric layer at the bottom of the three through holes, the remaining first capacitor dielectric layer is used as the first capacitor dielectric layer, and the first capacitor dielectric layer surrounds the fourth through hole; the first lower electrode layer filling the fourth through hole is formed , that is, there is no second capacitive dielectric layer on the top surface of the first lower electrode layer, and the remaining sacrificial layer is used as the first insulating layer.
  • the first insulating layer 117 covering the first capacitor dielectric film 119 is formed, and the first insulating layer 117 exposes the top surface of the first capacitor dielectric film 119 .
  • the fourth capacitor dielectric layers 186 between adjacent capacitors are spaced apart from each other, that is, there is a first insulating layer 117 between adjacent fourth capacitor dielectric layers 186 .
  • the first initial capacitor dielectric film may not be patterned, that is, the first initial capacitor dielectric film includes a first capacitor dielectric layer and a fourth capacitor dielectric layer , and the fourth capacitor dielectric layers of adjacent capacitors are in contact with each other.
  • a first upper electrode layer 196 is formed, the first upper electrode layer 196 surrounds the first lower electrode layer 116, and the first capacitive dielectric film 119 is located between the first upper electrode layer 196 and the first lower electrode layer 116 .
  • the first insulating layer 117 is patterned to form a second through hole f surrounding the first lower electrode layer 116, and the second through hole f exposes the side of the first capacitor dielectric film 119;
  • the first upper electrode layer 196 is patterned to form a second through hole f surrounding the first lower electrode layer 116, and the second through hole f exposes the side of the first capacitor dielectric film 119;
  • the first upper electrode layer 196 is patterned to form a second through hole f surrounding the first lower electrode layer 116, and the second through hole f exposes the side of the first capacitor dielectric film 119;
  • the first upper electrode layer 196 is patterned to form a second through hole f surrounding the first lower electrode layer 116, and the second through hole f exposes the side of the first capacitor dielectric film 119;
  • the first upper electrode layer 196 is patterned to form a second through hole f surrounding the first lower electrode layer 116, and the second through hole f exposes the side of the first capacitor dielectric film 119;
  • the first capacitive dielectric film 119 located in the central region c (refer to FIG. 16 ) is removed to expose the top surface of the first lower electrode layer 116 in the central region c.
  • the second lower electrode layer 126 is formed, and the second lower electrode layer 126 is in contact with the top surface of the first lower electrode layer 116 in the central region c (referring to FIG. 16 );
  • the three capacitor dielectric layers 176 cover the top and side surfaces of the second lower electrode layer 126 .
  • the first capacitive dielectric film 119 located on the side of the first lower electrode layer 116 serves as the first capacitive dielectric layer 156, and the remaining first capacitive dielectric film 119 located on the top surface of the first lower electrode layer 116 As the second capacitive dielectric layer 166 , that is, the first capacitive dielectric layer 156 and the second capacitive dielectric layer 166 are integrally formed.
  • a support layer 147 is formed on the surface jointly formed by the top surface of the first insulating layer 117, the top surface of the first upper electrode layer 196, the top surface of the second capacitor dielectric layer 166, and the top surface of the first lower electrode 116; Form a fifth through hole g that penetrates the support layer 147 and exposes the central region c of the first lower electrode 116 (refer to FIG.
  • the orthographic projection of the bottom surface of the second lower electrode layer 126 formed in the fifth through hole g on the substrate 110 is located at the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110 It is beneficial to improve the alignment accuracy between the second lower electrode layer 126 and the first lower electrode layer 116, avoid the dislocation between the second lower electrode layer 126 and the top surface of the first lower electrode layer 116, thereby improving the final formation
  • the dimensional accuracy of the capacitor can be improved to improve the quality of the capacitor and ensure that the capacitor has good electrical properties.
  • the method steps for forming the fifth through hole g are the same as the method steps for forming the first through hole e, and will not be repeated here.
  • a third capacitive dielectric layer 176 is formed on the exposed surface of the second lower electrode layer 126 .
  • the support layer 147 (refer to FIG. 20 ) is removed to form a continuous third initial capacitor dielectric film, that is, the third initial capacitor dielectric film not only covers the exposed surface of the second lower electrode layer 126, but also covers the first insulating layer 126.
  • the remaining first capacitive dielectric film 119 located on the side and top surface of the first lower electrode layer 116 serves as the first capacitive dielectric layer 156 .
  • the method steps for forming the second lower electrode layer 126 and the third initial capacitive dielectric film are the same as those in the above-mentioned embodiments, and will not be repeated here.
  • the third initial capacitor dielectric film positioned on the sidewall and top surface of the second lower electrode layer 126 is reserved as the third capacitor dielectric layer 176, but also the top surface of the first capacitor dielectric layer 156 is retained.
  • the third initial capacitor dielectric film on the top surface of the first upper electrode layer 196 is used as the second capacitor dielectric layer 166, that is, the second capacitor dielectric layer 166 and the third capacitor dielectric layer 176 are integrally formed, and the second capacitor dielectric layer 166 extends away from the second bottom electrode layer 126 along the axis perpendicular to the surface of the substrate 110 . In this way, it is beneficial to strengthen the insulating effect between the second upper electrode layer 106 and the first lower electrode layer 116 formed subsequently.
  • the second capacitive dielectric layer when the top surface of the first lower electrode layer does not have the second capacitive dielectric layer, before forming the second lower electrode layer, can be formed at least in the peripheral area of the top surface of the first lower electrode layer. layer film as the second capacitor dielectric layer, and then form the second lower electrode layer, or, when forming the third capacitor dielectric layer 176, the third initial capacitor dielectric film is not patterned, or, when forming the third capacitor dielectric layer 176 , at least retain the third initial capacitive dielectric film located on the sidewall and top surface of the second lower electrode layer 126 and the peripheral area of the top surface of the first lower electrode layer.
  • the second capacitor dielectric layers 166 between adjacent capacitors are spaced apart from each other, that is, there is a second insulating layer 127 between adjacent second capacitor dielectric layers 166 as an example. In fact, adjacent The two capacitor dielectric layers 166 of the capacitor can be in contact with each other.
  • the second insulating layer 127 covering the third capacitive dielectric layer 176 is formed; the second insulating layer 127 is patterned to form the sixth via hole surrounding the second lower electrode layer 126, and the second The six through holes expose the side and top surface of the third capacitor dielectric layer 176 and expose the top surface of the first upper electrode layer 196; the second upper electrode layer 106 filled with the sixth through hole is formed.
  • the first insulating layer 117 and the second insulating layer 127 together constitute the insulating layer 107 .
  • the first insulating layer 117 is located between adjacent first upper electrode layers 196 for electrical insulation between adjacent first upper electrode layers 196;
  • the second insulating layer 127 is located between adjacent second upper electrode layers 106 , and cover the upper surface of the first insulating layer 117 , for realizing electrical insulation between adjacent second upper electrode layers 106 .
  • the first upper electrode layer 196 and the second upper electrode layer 106 jointly constitute the upper electrode layer 146; the first capacitor dielectric layer 156, the second capacitor dielectric layer 166, the third capacitor dielectric layer 176 and the fourth capacitor dielectric layer 186 jointly The capacitor dielectric layer 136 is formed; the first lower electrode layer 116 , the second lower electrode layer 126 , the capacitor dielectric layer 136 and the upper electrode layer 146 together constitute the capacitor in the semiconductor structure.
  • next memory unit 100 may be formed on the side of the memory unit 100 away from the substrate 110 .
  • forming the lower electrode layer of the capacitor step by step is conducive to improving the stability of the lower electrode layer itself and improving the capacitance.
  • the aspect ratio to increase the capacitance of the capacitor.
  • the orthographic projection of the bottom surface of the second lower electrode layer 126 on the substrate 110 be located within the orthographic projection of the top surface of the first lower electrode layer 116 on the substrate 110, the bottom surface of the second lower electrode layer is prevented from colliding with the top surface of the first lower electrode layer.
  • the dislocation between the planes so as to improve the capacitance of the capacitor while improving the dimensional accuracy of the capacitor, so as to ensure that the capacitor has good electrical performance.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • the lower electrode layer of the capacitor in the semiconductor structure is composed of the first lower electrode layer and the second lower electrode layer stacked, which is beneficial to increase the overall height of the lower electrode layer of the capacitor to improve the capacitance.
  • the aspect ratio thereby increasing the facing area of the upper electrode layer and the lower electrode layer in the capacitor, so as to increase the capacitance of the capacitor.
  • the channel region of the semiconductor channel is vertically arranged on the surface of the metal bit line, that is, the extension direction of the channel region is perpendicular to the surface of the metal bit line, which is beneficial to save the semiconductor channel on the premise that the size of the semiconductor channel does not need to be reduced.
  • the layout space is parallel to the surface of the metal bit line (usually the horizontal direction), so as to increase the integration density of the semiconductor structure in the horizontal direction.

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Abstract

本申请实施例提供一种半导体结构及其制造方法，半导体结构包括：基底和位于基底上的存储单元，存储单元包括第一介质层和位于第一介质层内的金属位线；半导体通道位于金属位线部分表面；字线环绕半导体通道的部分区域设置；第二介质层位于金属位线与字线之间和位于字线远离基底的一侧；在半导体通道远离金属位线的顶面堆叠设置的第一下电极层和第二下电极层，第一下电极层与半导体通道顶面相接触；上电极层位于第二下电极层顶面，且包绕第一下电极层和第二下电极层；电容介质层位于上电极层与第一下电极层之间，且还位于上电极层与第二下电极层之间。

Description

半导体结构及其制造方法
相关申请的交叉引用
本申请基于申请号为202110807121.7，申请日为2021年07月16日、申请名称为“半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及一种半导体结构及其制造方法。
背景技术
随着对半导体器件具有高性能和低成本的需求的增加，对半导体器件的高集成密度和高存储容量的需求也增加。
然而，随着半导体器件集成密度的增加，在提高半导体器件中电容的电容容量的同时，电容的深宽比也越来越高。由于工艺设备以及半导体器件尺寸的限制，形成深宽比高的电容的尺寸精度不高，影响电容的电学性能。
因此，在提高半导体结构的集成密度的同时，需要设计一种既能提高电容容量，也能提高电容的尺寸精度的半导体器件。
发明内容
本申请实施例提供一种半导体结构及其制造方法。
本申请实施例提供一种半导体结构，包括：基底以及位于所述基底上的存储单元，所述存储单元包括：第一介质层以及位于所述第一介质层内的金属位线，且所述第一介质层露出所述金属位线表面；半导体通道，所述半导体通道位于所述金属位线的部分表面，所述半导体通道朝向所述金属位线的底面与所述金属位线电连接；字线，所述字线环绕所述半导体通道的部分区域设置；第二介质层，所述第二介质层位于所述金属位线与所述字线之间，且还位于所述字线远离所述基底的一侧；在所述半导体通道远离所述金属位线的顶面堆叠设置的第一下电极层以及第二下电极层，所述第一下电极层与所述半导体通道的顶面相接触；上电极层，所述上电极层位于所述第二下电极层的顶面，且包绕所述第一下电极层以及所述第二下电极层；电容介质层，所述电容介质层位于所述上电极层与所述第一下电极层之间，且还位于所述上电极层与所述第二下电极层之间。
相应地，本申请实施例还提供一种半导体结构的制造方法，包括：提供基底；在所述基底上形成存储单元，形成所述存储单元的工艺步骤包括：提供第一介质层以及位于所述第一介质层内的金属位线，且所述第一介质层露出所述金属位线表面；形成半导体通道，所述半导体通道位于所述金属位线的部分表面上，所述半导体通道朝向所述金属位线的底面与所述金属位线电连接；形成字线，所述字线环绕所述半导体通道的部分区 域设置；形成第二介质层，所述第二介质层位于所述金属位线与所述字线之间，且还位于所述字线远离所述基底的一侧；形成第一下电极层，所述第一下电极层与所述半导体通道的顶面相接触；形成第二下电极层，所述第二下电极层位于所述第一下电极层顶面；形成上电极层，所述上电极层位于所述第二下电极层的顶面，且包绕所述第一下电极层以及所述第二下电极层形成；形成电容介质层，所述电容介质层所述电容介质层位于所述上电极层与所述第一下电极层之间，且还位于所述上电极层与所述第二下电极层之间。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例提供的半导体结构对应的剖面结构示意图；
图2至图6为本申请一实施例提供的半导体结构中第一下电极层、第二下电极层和电容介质层共同构成的结构的五种剖面结构示意图；
图7至图22为本申请另一实施例提供的半导体结构的制造方法中各步骤对应的剖面结构示意图。
具体实施方式
由背景技术可知，现有技术中在提高半导体器件的集成密度的同时，半导体结构中的电容的电容容量和尺寸精度均有待提高。
为解决上述问题，本申请实施例提供一种半导体结构及其制造方法。在半导体结构中，半导体通道的沟道区垂直设置在金属位线表面，使得半导体结构包括垂直的全环绕栅极(GAA，Gate-All-Around)晶体管，有利于节省半导体通道在平行于金属位线表面方向(通常为水平方向)上的布局空间，从而提高半导体结构在水平方向上的集成密度。此外，通过改变电容中下电极层的构造，具体地，由第一下电极层和第二下电极层堆叠构成下电极层，有利于提高电容下电极层的整体高度，以提高电容的深宽比，从而提高电容中上电极层和下电极层的正对面积，以提高电容的电容容量。而且，第二下电极层底面在基底上的正投影位于第一下电极层顶面在基底上的正投影内，使得第二下电极层与第一下电极层对准，即保证第二下电极层底面与第一下电极层顶面完全接触，避免第二下电极层底面与第一下电极层顶面之间的错位，从而在提高电容容量的同时，提高电容的尺寸精度，以提高电容的形成质量，保证电容具有良好的电学性能。进一步地，电容介质层还覆盖第二下电极层露出的第一下电极层顶面，避免上电极层通过第二下电极层露出的第一下电极层顶面与第一下电极层接触，以进一步保证电容具有良好的电学性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例 中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请一实施例提供一种半导体结构，以下将结合附图对本申请一实施例提供的半导体结构进行详细说明。图1为本申请一实施例提供的半导体结构对应的剖面结构示意图，图2至图6为本申请一实施例提供的半导体结构中第一下电极层、第二下电极层和电容介质层共同构成的结构的五种剖面结构示意图。
参考图1至图6，半导体结构包括：基底110以及位于基底110上的存储单元100，存储单元100包括：第一介质层103以及位于第一介质层103内的金属位线101，且第一介质层103露出金属位线101表面；半导体通道102，半导体通道102位于金属位线101的部分表面，半导体通道102朝向金属位线101的底面与金属位线101电连接；字线104，字线104环绕半导体通道102的部分区域设置；第二介质层105，第二介质层105位于金属位线101与字线104之间，且还位于字线104远离基底110的一侧；在半导体通道102远离金属位线101的顶面堆叠设置的第一下电极层116以及第二下电极层126，第一下电极层116与半导体通道102的顶面相接触；上电极层146，上电极层146位于第二下电极层126的顶面，且包绕第一下电极层116以及第二下电极层126；电容介质层136，电容介质层136位于上电极层146与第一下电极层116之间，且还位于上电极层146与第二下电极层126之间。
具体地，第二下电极层126底面在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内；电容介质层136覆盖第二下电极层126顶面和侧面，且还覆盖第一下电极层116侧面以及第二下电极层126露出的第一下电极层116顶面。
在沿基底110指向金属位线101的方向上，半导体通道102包括依次排列的第一掺杂区I、沟道区II以及第二掺杂区III，第一掺杂区I与金属位线101电连接；字线104环绕沟道区II设置；第一下电极层116与第二掺杂区III远离沟道区II的一侧相接触。
由于半导体结构包括垂直的全环绕栅极(GAA，Gate-All-Around)晶体管，且金属位线101位于基底110与全环绕栅极晶体管之间，因而能够构成3D(3Dimensions)堆叠的存储器件，有利于提高半导体结构的集成密度。此外，半导体结构中的电容由第一下电极层116、第二下电极层126、电容介质层136和上电极层146共同构成，其中，电容的下电极层由第一下电极层116和第二下电极层126堆叠构成，一方面，在垂直于基底110表面的方向上，在制备高度较高的下电极层时，可以分步形成高度较低的第一下电极层116和第二下电极层126，由于第一下电极层116和第二下电极层126的高度较低，有利于避免第一下电极层116和第二下电极层126的倾斜或者坍塌，提高下电极层整体的稳定性，且能够形成深宽比大且电容容量大的电容；另一方面，第二下电极层126底面在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内，使得第二下电极层126与第一下电极层116对准，即避免第二下电极层126底面与第一下电极层116顶面之间的错位，从而在提高电容容量的同时，提高电容的尺寸精度，以提高电容的形成质量，保证电容具有良好的电学性能。
以下将结合图1对半导体结构进行更为详细的说明。
本实施例中，基底110可以为逻辑电路结构层，具有若干逻辑电路。
第一介质层103可以包括：层间介质层120，层间介质层120位于基底110表面，且金属位线101位于层间介质层120远离基底110的部分表面；隔离层130，隔离层130位于金属位线101露出的层间介质层120表面，且覆盖金属位线101侧壁。
具体地，逻辑电路结构层可以为叠层结构。层间介质层120远离逻辑电路结构层的部分表面可以具有多个间隔排布的金属位线101，每一金属位线101可与至少一个第一掺杂区I相接触电连接，图1中以每一金属位线101与2个第一掺杂区I相接触作为示例，可根据实际电学需求，合理设置与每一金属位线101相接触电连接的第一掺杂区I的数量。金属位线101顶面可以与隔离层130顶面齐平，有利于给位于金属位线101顶面和隔离层130顶面的其他结构提供良好的支撑作用。
层间介质层120用于实现逻辑电路结构层和金属位线101之间的绝缘，且层间介质层120有利于防止相邻金属位线101之间的漏电。其中，层间介质层120的材料包括氧化硅、氮化硅、碳氮化硅或者碳氮氧化硅中的至少一种。
隔离层130位于相邻金属位线101之间，用于实现相邻金属位线101之间的绝缘。其中，隔离层130的材料包括氧化硅、氮化硅、碳氮化硅或者碳氮氧化硅中的至少一种。
本实施例中，层间介质层120与隔离层130为一体结构，从而改善层间介质层120与隔离层130之间的界面态缺陷，改善半导体结构的性能，且层间介质层120的材料与隔离层130的材料相同，如此，有利于减少半导体结构的制作工艺步骤，降低半导体结构的制造成本和复杂度。在其他实施例中，层间介质层与隔离层可以为分层结构，层间介质层的材料与隔离层的材料可以不同。
金属位线101的材料为金属，这样设置的好处包括：一方面，金属材料的金属位线101的电阻率一般较小，有利于降低金属位线101的电阻，提高金属位线101中的电学信号的传输速率，降低金属位线101的寄生电容，且降低热损耗以降低功耗；另一方面，半导体结构还可以包括电路结构，且电路结构中具有用于实现电连接的金属导电层，如本领域技术人员常称的M0层、M1层、M2层等，可以利用金属导电层的工艺步骤，在形成金属导电层的同时制作金属位线101，如此，可节省半导体结构制作工艺步骤，降低半导体结构的成本。
金属位线101的材料可以为单金属、金属化合物或者合金。其中，单金属可以为铜、铝、钨、金或者银等；金属化合物可以为氮化钽或者氮化钛；合金可以为铜、铝、钨、金或者银中至少2者构成的合金材料。此外，金属位线101的材料还可以为镍、钴或者铂中的至少一种。
在一些实施例中，金属位线101的材料为铜。
半导体结构可以包括多个间隔排布的金属位线101，且每一金属位线101沿第一方 向延伸；每一金属位线101可与至少2个半导体通道102电连接。
半导体通道102的材料至少包括IGZO(铟镓锌氧化物，Indium Gallium Zinc Oxide)、IWO(掺钨氧化铟，Indium Tungsten Oxide)或者ITO(氧化铟锡，Indium Tin Oxide)中的一种，半导体通道102由上述材料组成时，有利于提高半导体通道102的载流子迁移率，从而有利于半导体通道102更高效地传递电信号。
在一个例子中，半导体通道102的材料为IGZO，IGZO的载流子迁移率是多晶硅的载流子迁移率的20～50倍，有利于提高半导体通道102中沟道区II的载流子迁移率，从而有利于降低半导体结构工作时的漏电流，以降低半导体结构的功耗和提高半导体结构的工作效率。此外，由IGZO半导体通道102构成的全环绕栅极晶体管配置的存储器单元的保留时间可超过400s，有利于降低存储器的刷新率和功耗。
本实施例中，半导体通道102为圆柱状结构，则半导体通道102的侧面为平滑过渡表面，有利于避免半导体通道102发生尖端放电或者漏电的现象，进一步改善半导体结构的电学性能。需要说明的是，在其他实施例中，半导体通道也可以为椭圆柱状结构、方柱状结构或者其他不规则结构。可以理解的是，半导体通道结构为方柱状结构时，方柱状结构的侧壁相邻面构成的拐角可以为圆滑化的拐角，同样能够避免尖端放电问题，方柱状结构可以为正方体柱状结构或者长方体柱状结构。
第一掺杂区I构成晶体管器件的源极或者漏极中的一者，第二掺杂区III构成晶体管器件的源极或者漏极中的另一者。第一掺杂区I、沟道区II和第二掺杂区III中的半导体元素相同，即第一掺杂区I、沟道区II以及第二掺杂区III为一体结构，有利于改善第一掺杂区I和沟道区II之间的界面态缺陷，和改善沟道区II和第二掺杂区III之间的界面态缺陷，以改善半导体结构的性能。可以理解的是，在其他实施例中，半导体通道也可以为三层结构，且每一层结构相应作为第一掺杂区、沟道区以及第三掺杂区。
其中，第一掺杂区I可以包括：第一金属半导体层112，第一金属半导体层112与金属位线101相接触，且第一金属半导体层112的电阻率小于第一金属半导体层112以外的第一掺杂区I的电阻率。如此，有利于降低第一掺杂区I的电阻率，且第一金属半导体层112与第一金属半导体层112以外的第一掺杂区I构成欧姆接触，避免金属位线101与半导体材料直接接触而形成的肖特基势垒接触，欧姆接触有利于降低第一掺杂区I与金属位线101之间的接触电阻，从而降低半导体结构工作时的能耗，且改善RC延迟效应，以提高半导体结构的电学性能。可以理解的是，在其他实施例中，第一掺杂区的半导体材料也可以直接与金属位线相接触，即第一掺杂区不包括第一金属半导体层。
具体地，第一金属半导体层112中的金属元素包括钴、镍或者铂中的至少一种。以半导体通道102的材料为IGZO为例，相应的，第一金属半导体层112的材料可以为含镍的IGZO、含钴的IGZO、含钴镍的IGZO或者含铂的IGZO等。此外，第一金属半导体层112内还可以掺杂有氮元素。
第一金属半导体层112中的半导体元素与第一金属半导体层112之外的第一掺杂区 I中的半导体元素相同，即第一掺杂区I整体为一体结构，则第一金属半导体层112为第一掺杂区I的一部分，有利于改善第一金属半导体层112与除第一金属半导体层112之外的第一掺杂区I之间的界面态缺陷，改善半导体结构的性能。需要说明的是，在其他实施例中，第一金属半导体层中的半导体元素也可以与第一金属半导体层之外的第一掺杂区中的半导体元素不同，例如第一金属半导体层中的半导体元素可以为硅或者锗，相应的，第一掺杂区为包括第一金属半导体层的双层结构。
在一些实施例中，半导体通道102与金属位线101相接触，即第一掺杂区I位于金属位线101表面。进一步地，半导体结构还可以包括：金属层108，金属层108位于半导体通道102未覆盖的金属位线101表面，且金属层108由第一金属半导体层112内的金属元素构成。可以理解的是，金属层108为形成第一金属半导体层112工艺步骤中同时形成的，金属层108的材料可以为钴、镍或者铂中的至少一种。
另外，在另一些实施例中，金属位线101的材料为镍、钴或者铂中的至少一种，则相应的，在半导体结构的制造工艺步骤中，与第一掺杂区I相接触的金属位线101中的部分区域与第一掺杂区I发生反应，以形成第一金属半导体层112，如此，金属位线101与第一金属半导体层112为一体结构，有利于进一步降低金属位线101与第一金属半导体层112之间的接触电阻。即，金属位线101可以为形成第一金属半导体层112提供金属元素。
第二掺杂区III可以包括：第二金属半导体层122，第二金属半导体层122与下电极层116相接触，且第二金属半导体层122的材料的电阻率小于第二金属半导体层122之外的第二掺杂区III的电阻率。如此，有利于降低第二掺杂区III的电阻率；且第二金属半导体层122与电容结构之间形成欧姆接触，有利于降低第二掺杂区III与电容结构之间的接触电阻，从而降低半导体结构工作时的能耗，以提高半导体结构的电学性能。
第二金属半导体层122中的金属元素包括钴、镍或者铂中的至少一种。本实施例中，第一金属半导体层112中的金属元素与第二金属半导体层122中的金属元素可以相同。在其他实施例中，第一金属半导体层中的金属元素与第二金属半导体层中的金属元素也可以不同。
此外，第二金属半导体层122中的半导体元素与第二金属半导体层122之外的第二掺杂区III中的半导体元素相同，即第二掺杂区III整体为一体结构，则第二金属半导体层122为第二掺杂区III的一部分，有利于改善第二金属半导体层122与除第二金属半导体层122之外的第二掺杂区III之间的界面态缺陷，改善半导体结构的性能。需要说明的是，在其他实施例中，第二金属半导体层中的半导体元素也可以与第二金属半导体层之外的第二掺杂区中的半导体元素不同，例如第二金属半导体层中的半导体元素可以为硅或者锗，相应的，第二掺杂区为包括第二金属半导体层的双层结构。
以半导体元素为硅为例，第二金属半导体层122包括硅化钴、硅化镍或者硅化铂中的至少一种。此外，第二金属半导体层122中还可以掺杂有氮元素。
在沿金属位线101的延伸方向上，半导体通道102的宽度处于纳米尺度范围内，则半导体通道102用于构成无结晶体管(Junctionless Transistor)的沟道时，有利于形成纳米级的无结晶体管沟道，即第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子的类型相同，例如掺杂离子均为N型离子或者均为P型离子，进一步地，第一掺杂区I、沟道区II和第二掺杂区III中的掺杂离子可以相同。其中，此处的“无结”指的是无PN结，即半导体通道102构成的晶体管中没有PN结，这样的好处包括：一方面，无需对第一掺杂区I和第二掺杂区III进行额外的掺杂，从而避免了对第一掺杂区I和第二掺杂区III的掺杂工艺难以控制的问题，尤其是随着晶体管尺寸进一步缩小，若额外对第一掺杂区I和第二掺杂区III进行掺杂，掺杂浓度更加难以控制；另一方面，由于器件为无结晶体管，有利于避免采用超陡峭源漏浓度梯度掺杂工艺，在纳米尺度范围内制作超陡峭PN结的现象，因而可以避免掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应，在几纳米的尺度范围内仍然可以工作，因而有助于进一步提高半导体结构的集成密度和电学性能。可以理解的是，此处额外的掺杂指的是，为了让第一掺杂区I和第二掺杂区III的掺杂离子类型与沟道区的掺杂离子类型不同而进行的掺杂。
进一步地，第一掺杂区I的掺杂离子的浓度和第二掺杂区III的掺杂离子的浓度可以均大于沟道区II的掺杂离子的掺杂浓度。掺杂离子为N型离子或者P型离子，具体地，N型离子为砷离子、磷离子或者锑离子中的至少一种；P型离子为硼离子、铟离子或者镓离子中的至少一种。
字线104包括栅介质层114，栅介质层114可以环绕半导体通道102的整个侧壁表面，如此，有利于避免半导体通道102漏电，提高GAA晶体管的电学性能。
在其他实施例中，栅介质层可仅覆盖沟道区的半导体通道的侧壁表面，或者，栅介质层覆盖沟道区和第一掺杂区的半导体通道的侧壁表面，或者，栅介质层覆盖沟道区和第二掺杂区的半导体通道的侧壁表面，其中，栅介质层环绕第二掺杂区设置，即位于第二掺杂区的半导体通道的侧壁表面时，栅介质层能够对第二掺杂区表面起到保护作用，避免在制造工艺过程中对第二掺杂区表面造成的工艺损伤，从而有利于进一步改善半导体结构的电学性能。
字线104还包括栅导电层124，栅导电层124环绕半导体通道102的部分区域设置，且栅介质层14位于半导体通道102与栅导电层124之间。
具体地，栅导电层124环绕沟道区II设置，且位于沟道区II对应的栅介质层114的侧壁表面。
其中，栅介质层114的材料包括氧化硅、氮化硅或者氮氧化硅中的至少一种，栅导电层124的材料包括多晶硅、氮化钛、氮化钽、铜、钨或者铝中的至少一种。
本实施例中，半导体结构可以包括多个间隔排布的字线104，且每一字线104沿第二方向延伸，第二方向与第一方向不同，例如第一方向可以与第二方向相垂直。此外， 对于每一字线104而言，每一字线104可环绕至少一个半导体通道102的沟道区II设置，图1中以每一字线104环绕2个半导体通道102作为示例，可根据实际电学需求，合理设置每一字线104环绕的半导体通道102的数量。
第二介质层105用于隔离金属层108和字线104，以隔离金属位线101与字线104，且还用于隔离相邻的字线104和相邻金属层108。也就是说，第二介质层105位于金属层108与字线104之间，且还位于相邻字线104的间隔中和相邻金属层108的间隔中。
第二介质层105可以包括：第三介质层115，第三介质层115位于金属层108与字线104之间以及相邻的金属层108的间隔中，以使得金属层108与字线104之间绝缘，防止金属层108与字线104之间的电干扰，以进一步防止金属位线101与字线104之间的电干扰；第四介质层125，第四介质层125位于相邻的字线104之间且与第三介质层115相接触，用于实现相邻字线104之间的绝缘，防止相邻字线104之间的电干扰；第四介质层125还位于字线104远离基底110的表面，用于支撑位于第四介质层125远离基底110的表面上的其他导电结构，并实现字线104与其他导电结构之间的绝缘。
第四介质层125顶面可以与第二掺杂区III顶面齐平，有利于给位于第四介质层125顶面和第二掺杂区III顶面的其他结构提供良好的支撑作用。
本实施例中，第三介质层115的材料和第四介质层125的材料相同，均可以为氧化硅、氮化硅、碳氮氧化硅或者氮氧化硅中的至少一种。在其他实施例中，第三介质层的材料和第四介质层的材料也可以不同。
可以理解的是，在其他实施例中，第二介质层也可以为其它堆叠膜层结构，堆叠膜层结构的具体结构与制造工艺步骤有关，保证第二介质层能够起到隔离目的即可。
电容包括：第一下电极层116、第二下电极层126、电容介质层136和上电极层146，以下将结合图1至图6对电容做具体的介绍。
本实施例中，第一下电极层116和第二下电极层126构成电容的下电极层，每一字线104沿第二方向延伸，图1中以每一字线104环绕2个半导体通道102，且第一下电极层116和第二下电极层126也沿第二方向延伸作为示例。具体地，每一下电极层与一字线104对应，即每一下电极层和与该下电极层对应的字线104环绕的每一第二掺杂区III远离沟道区II的一侧相接触，图1中以每一下电极层与2个半导体通道102的第二掺杂区III的顶面相接触位示例。
在一些例子中，在垂直于基底110表面方向上，第一下电极层116的厚度可以大于第二下电极层126的厚度；在另一些例子中，在垂直于基底110表面方向上，第一下电极层116的厚度还可以小于或等于第二下电极层126的厚度。此外，第一下电极层116的材料可以与第二下电极层126的材料相同。且由于第一下电极层116与第二下电极层126分步制作，则第一下电极层116与第二下电极层126的材料也可以不同。
此外，上电极层146也沿第二方向延伸，上电极层146与下电极层一一对应，且上 电极层146在基底110上的正投影覆盖下电极层在基底110上的正投影，下电极层在基底110上的正投影覆盖字线104在基底110上的正投影。
在其他实施例中，每一下电极层也可以只与一个第二掺杂区远离沟道区的一侧相接触，上电极层可以与下电极层一一对应或者一个上电极层与多个下电极层对应；或者一个下电极层可以与多个第二掺杂区远离沟道区的一侧相接触，上电极层可以只与一个半导体通道对应，即一个下电极层对应多个上电极层，使得相邻的电容中的上电极层可以连接不同的电位或者下电极层可以连接不同的电位，有利于实现对相邻电容的多元化控制。
其中，下电极层由堆叠设置的第一下电极层116和第二下电极层126组成，有利于提高下电极层的整体高度，以提高电容的电容容量的同时，以分步形成高度较低的第一下电极层116和第二下电极层126的方式，避免第一下电极层116和第二下电极层126的倾斜或者坍塌，提高下电极层整体的稳定性。第二下电极层126底面在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内，保证第二下电极层126底面与第一下电极层116顶面完全接触，避免第二下电极层126底面与第一下电极层116顶面之间的错位，提高电容的尺寸精度。
在一些例子中，在沿金属位线101的延伸方向上，第一下电极层116的底面宽度小于半导体通道102的最大宽度。在其他实施例中，第一下电极层的底面宽度可以大于或者等于半导体通道的最大宽度。
参考图1至图4，第一下电极层116包括：第一下导电柱113，第一下导电柱113与第二掺杂区III相接触；第一下导电块123，第一下导电块123一端与第一下导电柱113相接触，另一端与第二下电极层126相接触。第二下电极层126包括：第二下导电柱133，第二下导电柱133与第一下导电块123相接触；第二下导电块143，第二下导电块143一端与第二下导电柱133相接触，另一端与电容介质层136相接触。在一些例子中，第一下导电柱113覆盖第二掺杂区III的整个顶面，且沿远离基底110的方向上，第一下导电柱113在平行于基底110表面的方向上的截面面积逐渐增大，而且第一下导电柱113顶面在基底110上的正投影与第一下导电块123底面在基底110上的正投影重合，在保证第二掺杂区III与第一下电极层116之间最大的接触面积的同时，有利于增大第一下电极层116的体积，以降低第一下电极层116自身的电阻，从而有利于降低第二掺杂区III与第一下电极层116之间的接触电阻。
沿远离基底110的方向上，第二下导电柱133在平行于基底110表面的方向上的截面面积逐渐增大，而且第二下导电柱133底面在基底110上的正投影位于第一下导电块123底面在基底110上的正投影内，有利于在避免第二下电极层126底面与第一下电极层116顶面之间的错位的同时，增大第二下电极层126的体积，以降低第二下电极层126自身的电阻，从而有利于降低第二下电极层126与第一下电极层116之间的接触电阻。此外，第二下导电柱133顶面在基底110上的正投影与第二下导电块143底面在基底110上的正投影重合。
在其他实施例中，第一下导电柱顶面在基底上的正投影可以覆盖第一下导电块底面在基底上的正投影，第二下导电柱顶面在基底上的正投影可以覆盖第二下导电块底面在基底上的正投影。
本实施例中，第一下导电柱113和第一下导电块123为一体结构，第二下导电柱133和第二下导电块143为一体结构，从而改善第一下导电柱113和第一下导电块123之间的界面态缺陷，以及第二下导电柱133和第二下导电块143之间的界面态缺陷，以改善半导体结构的性能，且第一下导电柱113、第一下导电块123、第二下导电柱133和第二下导电块143的材料可以相同，如此，有利于减少半导体结构的制作工艺步骤，降低半导体结构的制造成本和复杂度。其中，第一下导电柱113、第一下导电块123、第二下导电柱133和第二下导电块143的材料均可以为镍化铂、钛、钽、钴、多晶硅、铜、钨、氮化钽、氮化钛或者钌中的至少一种。
在其他实施例中，第一下导电柱和第一下导电块可以不为一体结构，第二下导电柱和第二下导电块可以不为一体结构，即第一下导电柱、第一下导电块、第二下导电柱和第二下导电块的材料也可以不同。
在其他实施例中，参考图5，第一下电极层116的剖面形状和第二下电极层126的剖面形状均可以为矩形；参考图6，第一下电极层116的剖面形状和第二下电极层126的剖面形状均可以为倒梯形。
参考图2至图6，电容介质层136包括：第一电容介质层156，第一电容介质层156覆盖第一下电极层116的侧面；第二电容介质层166，第二电容介质层166覆盖第二下电极层126露出的第一下电极层116顶面；第三电容介质层176，第三电容介质层176覆盖第二下电极层126的顶面以及侧面。
第一电容介质层156、第二电容介质层166和第三电容介质层176共同覆盖第一下电极层116和第二下电极层126的表面，以隔离上电极层146与第一下电极层116和第二下电极层126。此外，第二电容介质层166覆盖第二下电极层126露出的第一下电极层116顶面，以避免上电极层146通过第二下电极层126露出的第一下电极层116顶面与第一下电极层116接触，以进一步保证电容具有良好的电学性能。
进一步地，电容介质层136还可以包括：第四电容介质层186，第四电容介质层186与第一电容介质层156底面相连，且向远离第一下电极层116垂直于基底110表面的轴线方向延伸；上电极层146(参考图1)还位于第四电容介质层186表面。在一些例子中，在沿金属位线101的延伸方向上，当第一下电极层116的底面宽度小于半导体通道102的最大宽度时，第一下电极层116会露出第二掺杂区III的部分顶面，第四电容介质层186与第一电容介质层156底面相连，且向远离第一下电极层116垂直于基底110表面的轴线方向延伸，如此有利于通过第四电容介质层186实现上电极层146和第二掺杂区III之间的隔离，以保证半导体结构良好的电学性能。
本实施例中，第四电容介质层186与第一电容介质层156为一体成型结构，有利于 改善第四电容介质层186与第一电容介质层156之间的界面态缺陷，提高第四电容介质层186与第一电容介质层156整体的隔离效果，且第四电容介质层186与第一电容介质层156的材料相同，如此，有利于减少半导体结构的制作工艺步骤，降低半导体结构的制造成本和复杂度。在其他实施例中，第四电容介质层与第一电容介质层可以为分层结构，第四电容介质层的材料与第一电容介质层的材料可以不同。
在一些实施例中，参考图2，第二下电极层126露出的第一下电极层116顶面具有第一电容介质层156，第二电容介质层166位于第一电容介质层156顶面，以覆盖第二下电极层126露出的第一下电极层116顶面。此外，第二电容介质层166还向远离第二下电极层126垂直于基底110表面的轴线方向延伸，以进一步提高上电极层146与第一下电极层116顶面之间的隔离效果。
在另一些实施例中，参考图3，第二电容介质层166与第二下电极层126露出的第一下电极层116顶面相接触，且向远离第二下电极层126垂直于基底110表面的轴线方向延伸，以实现上电极层146与第一下电极层116顶面之间的隔离。
第二电容介质层166与第三电容介质层176可以为一体成型结构，有利于改善第二电容介质层166与第三电容介质层176之间的界面态缺陷，提高第二电容介质层166与第三电容介质层176整体的隔离效果，且第二电容介质层166与第三电容介质层176的材料相同，如此，有利于减少半导体结构的制作工艺步骤，降低半导体结构的制造成本和复杂度。在其他实施例中，第二电容介质层与第三电容介质层可以为分层结构，第二电容介质层的材料与第三电容介质层的材料可以不同。
在又一些例子中，参考图4至图6，第二下电极层126露出的第一下电极层116顶面具有第一电容介质层156，且第一电容介质层156与第二电容介质层166为一体成型结构，有利于改善第一电容介质层156与第二电容介质层166之间的界面态缺陷，提高第一电容介质层156与第二电容介质层166整体的隔离效果，且第一电容介质层156与第二电容介质层166的材料相同，如此，有利于减少半导体结构的制作工艺步骤，降低半导体结构的制造成本和复杂度。在其他实施例中，第一电容介质层与第二电容介质层可以为分层结构，第一电容介质层的材料与第二电容介质层的材料可以不同。
需要说明的是，图2至图6中，虚线框a中除第一下电极层116之外的结构为第四电容介质层186，虚线框b中除第二下电极层126之外的结构为第二电容介质层166。
本实施例中，电容介质层136的材料的相对介电常数大于第二介质层105的材料的相对介电常数，有利于进一步提高第一下电极层116和第二下电极层126与上电极层146之间的隔离效果，提高半导体结构中电容的电学性能。
其中，第一电容介质层156、第二电容介质层166、第三电容介质层176和第四电容介质层186的材料均包括氧化硅、氧化钽、氧化铪、氧化锆、氧化铌、氧化钛、氧化钡、氧化锶、氧化钇、氧化镧、氧化镨或者钛酸锶钡等高介电常数材料。
需要说明的是，图2至图6中以相邻电容之间的第二电容介质层166之间相互间隔， 为示例，实际上相邻电容的第二电容介质层166之间可以相互接触连接；以相邻电容之间的第四电容介质层186之间相互间隔，为示例，实际上相邻电容的第四电容介质层186之间可以相互接触连接。
继续参考图1，上电极层146包括：第一上电极层196，第一上电极层196环绕第一下电极层116，且位于第一电容介质层156的侧面；第二上电极层106，第二上电极层106环绕第二下电极层116，位于第三电容介质层176表面，且第二上电极层106底面与第一上电极层196顶面相接触。
第一上电极层196的材料和第二上电极层106的材料均可以为镍化铂、钛、钽、钴、多晶硅、铜、钨、氮化钽、氮化钛或者钌中的至少一种。在其他实施例中，第一上电极层的材料和第二上电极层的材料也可以不同。
本实施例中，下电极层116整体的材料和上电极层136整体的材料可以相同。在其他实施例中，下电极层的材料和上电极层的材料也可以不同。
在一些实施例中，半导体结构可以包括2个在基底110上堆叠设置的存储单元100。图1中以在基底110上堆叠设置的2个存储单元100作为示例，可根据实际电学需求，合理设置在基底110上堆叠设置的存储单元100的数量。由于多个存储单元100可以在同一基底110上叠加设置，使得增加半导体结构的厚度方向的尺寸即可增加半导体结构的阵列密度，提升半导体结构的存储性能，减小半导体结构的平面尺寸，以实现3D堆叠的目的。可以理解的是，阵列密度指的是存储单元100位于半导体结构内的密度。
进一步地，半导体结构还包括：绝缘层107，绝缘层107位于第二介质层105表面，且第一下电极层116、第二下电极层126、电容介质层136和上电极层146组成的电容位于绝缘层107内，绝缘层107用于支撑电容，避免电容坍塌，还用于隔离相邻电容106的上电极层146。
本实施例中，绝缘层107为堆叠膜层结构，且包括第一绝缘层117和第二绝缘层127。第一绝缘层117位于相邻第一上电极层196之间，用于实现相邻第一上电极层196之间的电绝缘；第二绝缘层127位于相邻第二上电极层106之间，且覆盖第一绝缘层117上表面，用于实现相邻第二上电极层106之间的电绝缘。
其中，第一绝缘层117的材料和第二绝缘层127的材料相同，均可以为氮化硅、氮氧化硅、碳氮氧化硅或者氧化硅中的至少一种。在其他实施例中，第一绝缘层的材料和第二绝缘的材料也可以不同。
综上所述，半导体通道102的沟道区II垂直设置在金属位线101上，使得半导体结构中具有GAA晶体管，因而能够构成3D堆叠的存储器件，有利于提高半导体结构的集成密度。与此同时，半导体结构中电容的下电极层由堆叠设置的第一下电极层116和第二下电极层126组成，有利于提高电容下电极层的整体高度，以提高电容的电容容量。而且，第二下电极层126底面在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内，使得第二下电极层126与第一下电极层116对准，避免第二下电极 层126底面与第一下电极层116顶面之间的错位，从而在提高电容容量的同时，提高电容的尺寸精度，以提高电容的形成质量，保证电容具有良好的电学性能。
此外，本实施例提供的半导体结构可应用于4F 2的存储器，F是特征尺寸，存储器可以为RRAM(Static Random Access Memory)、MRAM(Magnetoresistive Random Access Memory)或PCRAM(Phase Change Random Access Memory)、DRAM(Dynamic Random Access Memory)存储器或者SRAM(SRAM，Static Random Access Memory)存储器，还可以应用于内存计算(IMC，In Memory Computing)，即允许用户在存储器中存储数据并以更快的速度处理信息。在一个具体实施例中，存储器可以为DRAM存储器，上述实施例中提及的金属位线101为DRAM存储器的位线，字线104为DRAM存储器的字线，且电容结构为DRAM存储器的存储电容。
相应地，本申请另一实施例提供一种半导体结构的制造方法，可用于形成上述半导体结构。
图7至图22为本申请另一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图，以下将结合附图对本实施例提供的半导体结构的制造方法进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图7至图22，提供基底110，在基底110上形成存储单元100。具体地，形成存储单元100包括如下步骤：
参考图7，基底110可以为逻辑电路结构层，提供第一介质层120以及位于第一介质层120内的金属位线101，且第一介质层120露出金属位线101表面。
具体地，形成整面覆盖逻辑电路结构层的表面层间介质层120，用于保护逻辑电路结构层，防止逻辑电路结构层与后续在层间介质层120上形成的金属位线101之间的电干扰。
在层间介质层120表面形成若干相互分立的金属位线101，且金属位线101露出层间介质层120部分表面；形成隔离层130，隔离层130位于金属位线101露出的层间介质层120表面，且覆盖金属位线101侧壁。
有关金属位线101的材料可参考前述实施例的相应说明，在此不再赘述。
可以理解的是，在其他实施例中，逻辑电路结构层表面也可以具有初始介质层；图形化初始介质层，以在初始介质层内形成若干相互分立的沟槽，且位于沟槽下方的初始介质层作为层间介质层，位于相邻沟槽之间的初始介质层作为隔离层，如此，隔离层与初始介质层为一体结构；然后，形成填充满沟槽的金属位线。
参考图8，在金属位线101表面形成第一金属层118。
第一金属层118用于与后续形成的半导体通道靠近金属位线101的区域发生反应，为后续形成第一金属半导体层提供金属元素，以降低半导体通道的电阻率。其中，第一金属层118的材料包括钴、镍或者铂中的至少一种。
本实施例中，第一金属层118覆盖金属位线101整个表面，可避免刻蚀第一金属层118的工艺对金属位线101带来刻蚀损伤。在其他实施例中，第一金属层也可以仅位于金属位线的部分表面，且第一金属层的位置与后续形成的半导体通道位置相对应。
在其他实施例中，也可以不在金属位线表面形成第一金属层，后续直接在金属位线的部分表面形成半导体通道即可。此外，在一些实施例中，金属位线的材料为镍、钴或者铂中的至少一者，即金属位线可以为后续形成第一金属半导体层提供金属元素，则也无需在金属位线表面形成第一金属层。
参考图9和图10，形成半导体通道102，半导体通道102位于金属位线101的部分表面上，半导体通道102朝向金属位线101的底面与金属位线101电连接。本实施例中，半导体通道102与第一金属层118相接触；在其他实施例中，半导体通道可以与金属位线直接相接触。
具体地，形成半导体通道102的工艺步骤包括如下步骤：
参考图9，形成初始通道层132，初始通道层132位于金属位线101上以及基底110上。
在一些实施例中，相邻金属位线101之间具有隔离层130，则初始通道层132覆盖隔离层130表面。
本实施例中，金属位线101表面形成有第一金属层118，初始通道层132覆盖第一金属层118表面。在其他实施例中，初始通道层可以直接覆盖金属位线表面。
具体地，形成初始通道层132的方法包括化学气相沉积、物理气相沉积、原子层沉积或者金属有机化合物化学气相沉淀。其中，初始通道层132的材料为IGZO、IWO或者ITO。
继续参考图9，在初始通道层132表面形成图形化的掩膜层109。
掩膜层109用于定义后续形成的半导体通道102的位置和尺寸。掩膜层109的材料可以为氮化硅、碳氮化硅或者碳氮氧化硅。在其他实施例中，掩膜层的材料也可以为光刻胶。
参考图10，以掩膜层109为掩膜对初始通道层132(参考图8)进行图形化处理，形成半导体通道102。
在沿基底110指向金属位线101的方向上，半导体通道102包括依次排列的第一掺杂区I、沟道区II和第二掺杂区III。
其中，半导体通道102中的第一掺杂区I、沟道区II和第二掺杂区III中掺杂同种类型的掺杂离子，则半导体通道102可以用于构成无结晶体管的沟道，避免了掺杂突变所产生的阈值电压漂移和漏电流增加等问题，还有利于抑制短沟道效应。
可以理解的是，可以在进行图形化处理之前，预先对初始通道层132进行掺杂处理， 掺杂处理可以掺杂N型离子或者P型离子；也可以在对初始通道层132进行图形化处理之后进行掺杂处理，以形成具有合适离子分布的半导体通道102。
本实施例中，可以通过热氧化、蚀刻和/或氢退火处理对半导体通道102进行圆角处理(corner-rounding)，以形成圆柱状结构的半导体通道102，在半导体结构工作时，有利于避免半导体通道102发生尖端放电或者漏电的现象。
参考图11，在半导体通道102的整个侧壁形成栅介质层114。栅介质层114露出半导体通道102正下方的以外的第一金属层118表面。栅介质层114用于在后续的退火处理过程中保护半导体通道102，防止后续半导体通道102的材料与金属材料发生反应。
本实施例中，栅介质层114还位于第二掺杂区III远离基底110的端面，后续形成第四介质层的步骤中，一并去除位于第二掺杂区III远离基底110的端面的栅介质层114，便于后续在第二掺杂区III远离基底110的端面上形成金属层。在其他实施例中，可以通过刻蚀工艺去除覆盖第二掺杂区的端面的栅介质层。
在其他实施例中，可仅在沟道区的半导体通道的侧壁表面形成栅介质层，或者，在沟道区和第一掺杂区的半导体通道的侧壁表面形成栅介质层，或者，在沟道区和第二掺杂区的半导体通道的侧壁表面形成栅介质层。
继续参考图11，形成第三介质层115，第三介质层115位于第一金属层118远离基底110的表面，以及位于相邻第一金属层118的间隔中。
具体地，第三介质层115位于隔离层130表面以及与第一掺杂区I(参考图9)对应的栅介质层114的侧壁表面，用于隔离第一金属层118与后续形成的字线。第三介质层115为整面膜层结构，用于防止为第一金属层118和金属位线101与后续形成的字线之间的电干扰。
形成第三介质层115的步骤包括：在金属位线101远离基底110的表面上形成初始第一介质层；对初始第一介质层进行平坦化处理和回刻蚀至预设厚度，形成第三介质层115。
参考图12，在沟道区II(参考图10)对应的栅介质层114的侧壁表面形成初始栅导电层134，且初始栅导电层134环绕沟道区II，初始栅导电层134为整面膜层结构。
具体地，形成初始栅导电层134的方法包括化学气相沉积、物理气相沉积、原子层沉积或者金属有机化合物化学气相沉淀。此外，通过对初始栅导电层134进行平坦化处理和蚀刻，使得初始栅导电层134位于沟道区II对应的栅介质层114的侧壁表面。
参考图13，图形化初始栅导电层134(参考图12)，形成相互间隔的栅导电层124，使得位于同一金属位线101上的不同半导体通道102的栅导电层124可以连接不同的电位，从而有利于实现对半导体通道的多元化控制。其中，图形化处理的方法包括光刻。
对于每一栅介质层114而言，每一栅介质层114可环绕至少一个半导体通道102的沟道区II设置，图13中以每一栅介质层114环绕2个半导体通道102作为示例，可根 据实际电学需求，合理设置每一栅介质层114环绕的半导体通道102的数量。
栅介质层114和栅导电层124共同组成字线104，因而字线104也是环绕2个半导体通道102设置。
参考图14，形成第四介质层125，第四介质层125位于相邻栅导电层124的间隔中，用于防止相邻栅导电层124之间的电干扰，且第四介质层125还位于栅导电层124远离基底110的表面，用于支撑后续在第四介质层125远离基底110的表面上形成的其他导电结构，并实现栅导电层124与其他导电结构之间的绝缘。
此外，在形成第四介质层125之后，对第四介质层125进行平坦化处理，并将位于掩膜层109远离基底110端面上的栅介质层114去除，使得第四介质层125露出位于第二掺杂区III远离基底110的端面上的掩膜层109。
本实施例中，第三介质层115和第四介质层125共同组成第二介质层105，第二介质层105位于金属位线101与字线104之间，且还位于字线104远离基底110的一侧。且第三介质层115和第四介质层125的材料相同，如此，有利于减少半导体结构的制作工艺所需要的材料种类，降低半导体结构的制造成本和复杂度。此外，第二介质层105还露出掩膜层109顶面。
参考图14至图15，去除掩膜层109，以暴露出第二掺杂区III(参考图10)顶面，在暴露出的第二掺杂区III顶面形成第二金属层。
第二金属层用于与第二掺杂区III发生反应，为后续形成第二金属半导体层122提供金属元素，以降低半导体通道102的电阻率。其中，第二金属层的材料包括钴、镍或者铂中的至少一种。
制造方法还可以包括：进行第一退火处理，第一金属层118与第一掺杂区I发生反应，以将朝向金属位线101的部分厚度的第一掺杂区I转化为第一金属半导体层112，第一金属半导体层112的材料的电阻率小于第一金属半导体层112以外的第一掺杂区I的材料的电阻率。
其中，与第一掺杂区I发生反应的第一金属层118成为第一掺杂区I的一部分，未与第一掺杂区I发生反应的第一金属层118作为金属层108。可以理解的是，金属位线101与第一金属半导体层112之间还可以残留有部分厚度的第一金属层118，该残留的第一金属层118作为金属层108，即金属层108既可以位于第一金属半导体层112以外的金属位线101表面，还可以位于第一金属半导体层112与金属位线101之间。
本实施例中，在进行第一退火处理的同时，进行第二退火处理，第二金属层与第二掺杂区III发生反应，以将露出的部分厚度的第二掺杂区III转化为第二金属半导体层122，且第二金属半导体层122的材料的电阻率小于第二金属半导体层122以外的第二掺杂区III的电阻率。
具体地，采用快速热退火进行退火处理，快速热退火的工艺参数包括：在N 2氛围 下对半导体结构进行退火处理，退火温度为600℃～850℃，退火时长为10秒～60秒。由于退火温度适中，有利于使得第一金属层118与第一掺杂区I充分反应，使得第二金属层与第二掺杂区III充分反应，以形成电阻率相对较小的第一金属半导体层112和第二金属半导体层122。此外，由于退火温度适中，有利于避免第一金属层118和第二金属层中的金属元素扩散至沟道区II内。此外，在N 2氛围下进行退火处理，有利于避免第一金属层118、第二金属层和半导体通道102被氧化。
本实施例中，第一退火处理和第二退火处理是同时进行的，有利于简化半导体结构的制造工艺工序。在其他实施例中，在第一金属层上形成半导体通道后，即可进行第一退火处理；在第二掺杂区上形成第二金属层后，再进行第二退火处理。
另外，在其他实施例中，在形成半导体通道之前，也可以在第一金属层表面形成第一半导体层，第一半导体层的材料为硅或者锗，且在第一退火处理过程中第一半导体层与第一金属层发生反应以形成第一金属半导体层；在形成第二金属层之前，在第二掺杂区顶面形成第二半导体层，第二半导体层的材料为硅或者锗，且在第二退火处理过程中第二半导体层与第二金属层发生反应以形成第二金属半导体层。
参考图16至图22，形成第一下电极层116，第一下电极层116与半导体通道102的顶面相接触；形成第二下电极层126，第二下电极层126位于第一下电极层116顶面；形成上电极层146，上电极层146位于第二下电极层126顶面，且包绕第一下电极层116以及第二下电极层126；形成电容介质层136，电容介质层136位于上电极层146与第一下电极层116之间，且还位于上电极层146与第二下电极层126之间；。
具体地，第二下电极层126底面在基底110上的正投影位于第一下电极层126顶面在基底110上的正投影内；电容介质层136覆盖第二下电极层126顶面和侧面，且还覆盖第一下电极层116侧面以及第二下电极层126露出的第一下电极层116顶面。
具体地，形成第一下电极层116、第二下电极层126、电容介质层136以及上电极层146包括如下步骤：
参考图16，形成第一下电极层116，第一下电极层116顶面包括中心区c以及环绕中心区c的外围区d。
具体地，在第二掺杂区III远离沟道区II的一侧形成牺牲层137，且牺牲层137内具有贯穿牺牲层137且露出第二掺杂区III的第一通孔e；形成填充满第一通孔e的第一下电极层116。
第一通孔e包括相连通的第一沟槽和第二沟槽，第一沟槽露出第二掺杂区III表面。
具体地，形成第一沟槽和第二沟槽的步骤可以包括：在第二介质层105表面形成初始牺牲层；在初始牺牲层表面形成图形化的掩膜层；以图形化的掩膜层为掩膜，刻蚀部分厚度的初始牺牲层，以形成第二沟槽；在第二沟槽对应的区域，刻蚀第二沟槽暴露出的部分初始牺牲层，至露出第二掺杂区III表面，形成在平行于110基底表面的方向上 的截面面积逐渐增大第一沟槽。
在其他实施例中，第一通孔e的截面形状也可以为矩形或者倒梯形。
本实施例中，每一字线104沿第二方向延伸，每一字线104环绕2个半导体通道102，且第一沟槽和第二沟槽也沿第二方向延伸。具体地，第一沟槽和第二沟槽组成的第一通孔e与一字线104对应，即每一第一通孔e露出与该第一通孔e对应的字线104环绕的每一第二掺杂区III远离沟道区II的一侧，图16中以每一第一通孔e露出2个半导体通道102的第二掺杂区III的顶面为示例。
在其他实施例中，每一第一通孔也可以只露出一个第二掺杂区远离沟道区的一侧。
参考图17，形成第一电容介质膜119，第一电容介质膜119覆盖第一下电极层116顶面以及侧面。
在一些实施例中，形成第一电容介质膜119的工艺步骤包括：去除牺牲层137，形成整面连续的第一初始电容介质膜，第一初始电容介质膜还覆盖第一下电极层116顶面以及侧面，即第一初始电容介质膜还覆盖第一下电极层116露出的第四介质层125、栅介质层114和第二掺杂区III(参考图10)的顶面。
图形化第一初始电容介质膜，形成第一电容介质膜119以及第四电容介质层186，第四电容介质层186与第一电容介质膜119底面相连，且向远离第一下电极层116垂直于基底110表面的轴线方向延伸。
由于后续会形成第二下电极层126，因此在垂直于基底110表面的方向上，第一下电极层116自身的深宽比可以较小，以提高第一下电极层116自身结构的稳定性，在后续形成其他膜层以及刻蚀其他膜层时，第一下电极层116不易倾斜或者倒塌，以提高半导体结构整体的稳定性。
在另一些实施例中，参考图18，在形成第一下电极层116之前，还包括：在第二介质层105上形成第四电容介质层186，且第四电容介质层186具有贯穿第四电容介质层186的开口，且开口露出至少部分第二掺杂区III(参考图10)的顶面；在形成第一下电极层116的工艺步骤中，第一下电极层116填充满开口；形成覆盖第一下电极层116顶面以及侧面的第一电容介质膜119。
在其他实施例中，可以形成具有贯穿牺牲层且至少露出第二掺杂区整个顶面的第三通孔；在第三通孔的侧壁和底部形成初始第一电容介质层；去除位于第三通孔底部的初始第一电容介质层，剩余第一电容介质层作为第一电容介质层，第一电容介质层围成第四通孔；形成填充满第四通孔的第一下电极层，即第一下电极层顶面不具有第二电容介质层，剩余牺牲层作为第一绝缘层。
参考图17和图18，形成覆盖第一电容介质膜119的第一绝缘层117，且第一绝缘层117露出第一电容介质膜119顶面。
本实施例中，相邻电容之间的第四电容介质层186之间相互间隔，即相邻第四电容 介质层186之间具有第一绝缘层117。在其他实施例中，形成整面连续的第一初始电容介质膜之后，可以不对第一初始电容介质膜进行图形化，即第一初始电容介质膜包括第一电容介质层和第四电容介质层，且相邻电容的第四电容介质层相互接触连接。
参考图19，形成第一上电极层196，第一上电极层196包绕第一下电极层116，且第一电容介质膜119位于第一上电极层196与第一下电极层116之间。
具体地，图形化第一绝缘层117，以形成环绕第一下电极层116的第二通孔f，且第二通孔f露出第一电容介质膜119侧面；形成填充满第二通孔f的第一上电极层196。
结合参考图19和图20，去除位于中心区c(参考图16)的第一电容介质膜119，露出中心区c的第一下电极层116顶面。
参考图20至图22，形成第二下电极层126，第二下电极层126与中心区c(参考图16)的第一下电极层116顶面相接触；形成第三电容介质层176，第三电容介质层176覆盖第二下电极层126的顶面以及侧面。
在一些实施例中，参考图21，位于第一下电极层116侧面的第一电容介质膜119作为第一电容介质层156，位于第一下电极层116顶面的剩余第一电容介质膜119作为第二电容介质层166，即第一电容介质层156和第二电容介质层166为一体成型结构。
具体地，参考图20，在第一绝缘层117顶面、第一上电极层196顶面、第二电容介质层166顶面以及第一下电极116顶面共同构成的表面形成支撑层147；形成具有贯穿支撑层147且露出第一下电极116中心区c(参考图16)的第五通孔g，由于第五通孔g在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内，则后续在第五通孔g中形成的第二下电极层126底面在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内，有利于提高第二下电极层126和第一下电极层116之间的对准精度，避免第二下电极层126与第一下电极层116顶面之间的错位，从而提高最终形成的电容的尺寸精度，以提高电容的形成质量，保证电容具有良好的电学性能。
其中，形成第五通孔g的方法步骤与形成第一通孔e的方法步骤相同，在此不做赘述。
参考图21，在第二下电极层126暴露出的表面形成第三电容介质层176。
具体地，去除支撑层147(参考图20)，形成整面连续的第三初始电容介质膜，即第三初始电容介质膜不仅覆盖第二下电极层126暴露出的表面，还覆盖第一绝缘层117顶面、第一上电极层196顶面、第二电容介质层166顶面共同构成的表面；图形化第三初始电容介质膜，仅保留位于第二下电极层126侧壁和顶面的第三初始电容介质膜作为第三电容介质层176。
在另一些实施例中，参考图22，位于第一下电极层116侧面和顶面的剩余第一电容介质膜119均作为第一电容介质层156。
具体地，形成第二下电极层126和第三初始电容介质膜的方法步骤与上述实施例相 同，在此不做赘述。
图形化第三初始电容介质膜时，不仅保留位于第二下电极层126侧壁和顶面的第三初始电容介质膜作为第三电容介质层176，还保留位于第一电容介质层156顶面和第一上电极层196部分顶面的第三初始电容介质膜作为第二电容介质层166，即第二电容介质层166和第三电容介质层176为一体成型结构，且第二电容介质层166向远离第二下电极层126垂直于基底110表面的轴线方向延伸。如此，有利于加强后续形成的第二上电极层106与第一下电极层116之间的绝缘效果。
在其他实施例中，当第一下电极层顶面不具有第二电容介质层时，在形成第二下电极层之前，至少可以在第一下电极层顶面的外围区形成第二电容介质层膜作为第二电容介质层，然后再形成第二下电极层，或者，形成第三电容介质层176时，不对第三初始电容介质膜进行图形化，或者，形成第三电容介质层176时，至少保留位于第二下电极层126侧壁和顶面和第一下电极层顶面的外围区的第三初始电容介质膜。
需要说明的是，图22中以相邻电容之间的第二电容介质层166之间相互间隔，即相邻第二电容介质层166之间具有第二绝缘层127为示例，实际上相邻电容的二电容介质层166之间可以相互接触连接。
进一步地，参考图21和图22，形成覆盖第三电容介质层176的第二绝缘层127；图形化第二绝缘层127，以形成环绕第二下电极层126的第六通孔，且第六通孔露出第三电容介质层176侧面和顶面，并露出第一上电极层196顶面；形成填充满第六通孔的第二上电极层106。
第一绝缘层117和第二绝缘层127共同构成绝缘层107。第一绝缘层117位于相邻第一上电极层196之间，用于实现相邻第一上电极层196之间的电绝缘；第二绝缘层127位于相邻第二上电极层106之间，且覆盖第一绝缘层117上表面，用于实现相邻第二上电极层106之间的电绝缘。
其中，第一上电极层196和第二上电极层106共同构成上电极层146；第一电容介质层156、第二电容介质层166、第三电容介质层176和第四电容介质层186共同构成电容介质层136；第一下电极层116、第二下电极层126、电容介质层136和上电极层146共同构成半导体结构中的电容。
进一步地，参考图1，在形成一个存储单元100之后，可以在存储单元100远离基底110的一侧形成下一个存储单元100。
综上所述，通过分步形成电容的下电极层，即分步形成第一下电极层116和第二下电极层126，有利于在提高下电极层自身结构的稳定性的同时，提高电容的深宽比，以提高电容的电容容量。此外，通过使得第二下电极层126底面在基底110上的正投影位于第一下电极层116顶面在基底110上的正投影内，避免第二下电极层底面与第一下电极层顶面之间的错位，从而在提高电容容量的同时，提高电容的尺寸精度，以保证电容具有良好的电学性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例提供了一种半导体结构及其制造方法。本申请实施例提供的技术方案中，半导体结构中的电容的下电极层由堆叠设置的第一下电极层和第二下电极层组成，有利于提高电容下电极层的整体高度，以提高电容的深宽比，从而提高电容中上电极层和下电极层的正对面积，以提高电容的电容容量。进一步地，半导体通道的沟道区垂直设置在金属位线表面，即沟道区的延伸方向垂直于金属位线表面，在无需对半导体通道的尺寸进行缩小的前提下，有利于节省半导体通道在平行于金属位线表面方向(通常为水平方向)上的布局空间，从而提高半导体结构在水平方向上的集成密度。

Claims (19)

  1. 一种半导体结构，包括：
    基底以及位于所述基底上的存储单元，所述存储单元包括：
    第一介质层以及位于所述第一介质层内的金属位线，且所述第一介质层露出所述金属位线表面；
    半导体通道，所述半导体通道位于所述金属位线的部分表面，所述半导体通道朝向所述金属位线的底面与所述金属位线电连接；
    字线，所述字线环绕所述半导体通道的部分区域设置；
    第二介质层，所述第二介质层位于所述金属位线与所述字线之间，且还位于所述字线远离所述基底的一侧；
    在所述半导体通道远离所述金属位线的顶面堆叠设置的第一下电极层以及第二下电极层，所述第一下电极层与所述半导体通道的顶面相接触；
    上电极层，所述上电极层位于所述第二下电极层的顶面，且包绕所述第一下电极层以及所述第二下电极层；电容介质层，所述电容介质层位于所述上电极层与所述第一下电极层之间，且还位于所述上电极层与所述第二下电极层之间。
  2. 如权利要求1所述的半导体结构，其中，所述第二下电极层底面在所述基底上的正投影位于所述第一下电极层顶面在所述基底上的正投影内。
  3. 如权利要求1所述的半导体结构，其中，所述电容介质层覆盖所述第二下电极层顶面和侧面，且还覆盖所述第一下电极层侧面以及所述第二下电极层露出的所述第一下电极层顶面。
  4. 如权利要求1所述的半导体结构，其中，所述电容介质层包括：
    第一电容介质层，所述第一电容介质层覆盖所述第一下电极层的侧面；
    第二电容介质层，所述第二电容介质层覆盖所述第二下电极层露出的所述第一下电极层顶面；
    第三电容介质层，所述第三电容介质层覆盖所述第二下电极层的顶面以及侧面。
  5. 如权利要求4所述的半导体结构，其中，所述第一电容介质层与所述第二电容介质层为一体成型结构。
  6. 如权利要求4所述的半导体结构，其中，所述电容介质层还包括：第四电容介质层，所述第四电容介质层与所述第一电容介质层底面相连，且向远离所述第一下电极层垂直于所述基底表面的轴线方向延伸；所述上电极层还位于所述第四电容介质层表面。
  7. 如权利要求6所述的半导体结构，其中，所述第四电容介质层与所述第一电容介质层为一体成型结构。
  8. 如权利要求4所述的半导体结构，其中，所述第二电容介质层还位于所述第一电容介质层顶面，且向远离所述第二下电极层垂直于所述基底表面的轴线方向延伸。
  9. 如权利要求4所述的半导体结构，其中，所述上电极层包括：
    第一上电极层，所述第一上电极层环绕所述第一下电极层，且位于所述第一电容介质层的侧面；
    第二上电极层，所述第二上电极层环绕所述第二下电极层，位于所述第三电容介质层 表面，且所述第二上电极层底面与所述第一上电极层顶面相接触。
  10. 如权利要求1所述的半导体结构，其中，所述电容介质层的材料的相对介电常数大于所述第二介质层的材料的相对介电常数。
  11. 如权利要求1所述的半导体结构，其中，所述半导体结构包括至少2个在所述基底上堆叠设置的所述存储单元。
  12. 如权利要求1所述的半导体结构，其中，所述半导体通道的材料至少包括IGZO、IWO或者ITO中的一种或多种；所述半导体通道构成无结晶体管的沟道。
  13. 如权利要求1所述的半导体结构，其中，在沿所述基底指向所述金属位线的方向上，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区；所述第一掺杂区与所述金属位线电连接；所述字线环绕所述沟道区设置；所述第一下电极层与所述第二掺杂区远离所述沟道区的一侧相接触。
  14. 如权利要求1所述的半导体结构，其中，所述字线包括：
    栅介质层，所述栅介质层环绕所述半导体通道的整个侧壁表面；
    栅导电层，所述栅导电层环绕所述半导体通道的部分区域设置，且所述栅介质层位于所述半导体通道与所述栅导电层之间。
  15. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底上形成存储单元，形成所述存储单元的工艺步骤包括：
    提供第一介质层以及位于所述第一介质层内的金属位线，且所述第一介质层露出所述金属位线表面；
    形成半导体通道，所述半导体通道位于所述金属位线的部分表面上，所述半导体通道朝向所述金属位线的底面与所述金属位线电连接；
    形成字线，所述字线环绕所述半导体通道的部分区域设置；
    形成第二介质层，所述第二介质层位于所述金属位线与所述字线之间，且还位于所述字线远离所述基底的一侧；
    形成第一下电极层，所述第一下电极层与所述半导体通道的顶面相接触；
    形成第二下电极层，所述第二下电极层位于所述第一下电极层顶面；
    形成上电极层，所述上电极层位于所述第二下电极层的顶面，且包绕所述第一下电极层以及所述第二下电极层；
    形成电容介质层，所述电容介质层位于所述上电极层与所述第一下电极层之间，且还位于所述上电极层与所述第二下电极层之间。
  16. 如权利要求15所述的制造方法，其中，形成所述第一下电极层、所述第二下电极层、所述电容介质层以及所述上电极层的工艺步骤包括：
    形成所述第一下电极层，所述第一下电极层顶面包括中心区以及环绕中心区的外围区；
    形成第一电容介质膜，所述第一电容介质膜覆盖所述第一下电极层顶面以及侧面；
    形成第一上电极层，所述第一上电极层包绕所述第一下电极层，且所述第一电容介质膜位于所述第一上电极层与所述第一下电极层之间；
    去除位于所述中心区的所述第一电容介质膜，露出所述中心区的所述第一下电极层顶面，位于所述第一下电极层侧面的所述第一电容介质膜作为第一电容介质层，位于所述第一下电极层顶面的剩余所述第一电容介质膜作为第二电容介质层；
    形成第二下电极层，所述第二下电极层与所述中心区的所述第一下电极层顶面相接触；
    形成第三电容介质层，所述第三电容介质层覆盖所述第二下电极层的顶面以及侧面。
  17. 如权利要求16所述的制造方法，其中，形成所述第一电容介质膜的工艺步骤包括：
    形成整面连续的第一初始电容介质膜，所述第一初始电容介质膜还覆盖所述第一下电极层顶面以及侧面；
    图形化所述第一初始电容介质膜，形成所述第一电容介质膜以及第四电容介质层，所述第四电容介质层与所述第一电容介质膜底面相连，且向远离所述第一下电极层垂直于所述基底表面的轴线方向延伸。
  18. 如权利要求16所述的制造方法，其中，在沿所述基底指向所述金属位线的方向上，所述半导体通道包括依次排列的第一掺杂区、沟道区以及第二掺杂区；形成所述第一下电极层、所述第一电容介质膜以及所述第一上电极层的工艺步骤包括：
    在所述第二掺杂区远离所述沟道区的一侧形成牺牲层，且所述牺牲层内具有贯穿所述牺牲层且露出所述第二掺杂区的第一通孔；
    形成填充满所述第一通孔的所述第一下电极层；
    去除所述牺牲层，且形成所述第一电容介质膜；
    形成覆盖所述第一电容介质膜的第一绝缘层，且所述第一绝缘层露出所述第一电容介质膜顶面；
    图形化所述第一绝缘层，以形成环绕所述第一下电极层的第二通孔，且所述第二通孔露出所述第一电容介质膜侧面；
    形成填充满所述第二通孔的所述第一上电极层。
  19. 如权利要求16所述的制造方法，其中，在形成所述第一下电极层之前，还包括：在所述第二介质层上形成第四电容介质层，且所述第四电容介质层具有贯穿所述第四电容介质层的开口；在形成所述第一下电极层的工艺步骤中，所述第一下电极层填充满所述开口。
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