WO2023245803A1 - 半导体结构及其制作方法、存储器 - Google Patents

半导体结构及其制作方法、存储器 Download PDF

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Publication number
WO2023245803A1
WO2023245803A1 PCT/CN2022/108167 CN2022108167W WO2023245803A1 WO 2023245803 A1 WO2023245803 A1 WO 2023245803A1 CN 2022108167 W CN2022108167 W CN 2022108167W WO 2023245803 A1 WO2023245803 A1 WO 2023245803A1
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sub
pillar
active
active pillar
layer
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PCT/CN2022/108167
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English (en)
French (fr)
Inventor
肖德元
邵光速
白卫平
邱云松
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长鑫存储技术有限公司
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Priority to US18/095,292 priority Critical patent/US20230413528A1/en
Publication of WO2023245803A1 publication Critical patent/WO2023245803A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure, a manufacturing method thereof, and a memory.
  • the memory array architecture of dynamic random access memory is an array composed of memory cells (i.e., 1T1C memory cells) including a transistor and a capacitor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • a semiconductor structure including: a substrate, a plurality of active pillars located above the substrate, a memory structure, and a plurality of transistors;
  • the plurality of active pillars are arranged in an array along the first direction and the second direction; each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar.
  • Source pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; the material of the first sub-active pillar contains a first element, and the material contains the first element
  • the resistivity of the first sub-active pillar is less than the resistivity of the first sub-active pillar whose material does not include the first element;
  • the storage structure covers the sidewall of the first sub-active pillar
  • the channel structure of each transistor is located in the second sub-active pillar, and the extending direction of the channel structure is the same as the extending direction of the second sub-active pillar.
  • the first element includes an N-type doping element or a P-type doping element, and the material of the first sub-active pillar includes a semiconductor material; or the first element includes a metal element, and the first sub-active pillar includes a semiconductor material.
  • the material of a sub-active pillar includes a compound of the metal element.
  • the substrate includes an isolation structure, and a plurality of the active pillars are located on the isolation structure.
  • the storage structure includes:
  • the second electrode layer is located in the gap of the dielectric layer and covers the surface of the dielectric layer.
  • the semiconductor structure further includes: a first protective layer surrounding the top sidewall of the second sub-active pillar;
  • the first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars;
  • Each of the first protection pillars is located between the tops of two adjacent second sub-active pillars in the first direction, and covers two opposite side walls of the two adjacent second sub-active pillars;
  • Each second protection pillar extends along the first direction, covers the sidewall of the top of the second sub-active pillar that is not covered by the first protection pillar, and covers the sidewall of the first protection pillar.
  • the diameter width of the middle part of the second sub-active pillar is smaller than the diameter width of the top part of the second sub-active pillar and/or the diameter width of the bottom part of the second sub-active pillar;
  • the transistor includes: a gate oxide layer arranged around the second active sub-pillar, a gate electrode arranged around the gate oxide layer, and two opposite ends of the second active pillar respectively.
  • the side of the gate electrode away from the gate oxide layer is flush with the side wall of the second protection pillar away from the gate oxide layer.
  • the semiconductor structure further includes:
  • a plurality of bit lines are located on the transistor and are electrically connected to the top of the second sub-active pillar.
  • a memory including: one or more semiconductor structures as described in any one of the above solutions of the disclosure.
  • a method of manufacturing a semiconductor structure including:
  • a substrate is provided, and a plurality of active pillars arranged in an array along a first direction and a second direction are formed on the substrate; each active pillar includes a first sub-active pillar and is located on the first sub-active pillar. a second sub-active pillar on the sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;
  • a first element is added to the first sub-active column, and the resistivity of the first sub-active column containing the first element is smaller than that of the first sub-active column that does not contain the first element. resistivity;
  • a plurality of transistors are formed, a channel structure of the transistor is located in the second sub-active pillar, and the extending direction of the channel structure is the same as the extending direction of the second sub-active pillar.
  • the first element includes an N-type or P-type doping element. Adding the first element to the first sub-active column includes: adding N to the first sub-active column through a diffusion or ion implantation process. Type or P-type doping elements;
  • the first element includes a metal element
  • adding the first element to the first sub-active pillar includes: forming a metal layer containing the metal element covering the sidewall of the first sub-active pillar; using An annealing process causes the metal layer and the first sub-active pillar to react to form a metal compound.
  • a plurality of active pillars arranged in an array along the first direction and the second direction are formed on the substrate, including:
  • a plurality of semiconductor pillars arranged in an array along a first direction and a second direction are formed on the substrate; each semiconductor pillar includes a first part, a second part located on the first part, and a second part located on the first part. part three on part two;
  • the support layer and the second protective layer are removed to obtain the second sub-active pillar.
  • a plurality of semiconductor pillars arranged in an array along the first direction and the second direction are formed on the substrate, including:
  • each first trench and/or the second trench is enlarged to form the plurality of semiconductor pillars.
  • forming the support layer includes:
  • Part of the second insulating layer is removed along the second direction to form a first shallow trench, the bottom surface of the first shallow trench is flush with the top surface of the semiconductor pillar, and within the first shallow trench Filling the first insulating material;
  • Part of the second insulating layer is removed along the first direction to form a second shallow trench, the bottom surface of the second shallow trench is flush with the top surface of the semiconductor pillar, and the top surface of the semiconductor pillar is exposed. surface; filling the second insulating material in the second shallow trench;
  • the second insulating material that has not been removed and the second shallow trench are filled with the second insulating material to form the support layer.
  • forming the second protective layer includes:
  • the storage structure is formed on at least the side wall of the first sub-active column, including:
  • a second conductive layer is formed in the gap of the dielectric layer.
  • the method further includes: forming a first protective layer surrounding the top sidewall of the second sub-active pillar;
  • the forming the first protective layer includes:
  • Part of the first insulating material on the top of the second sub-active pillar is removed to form a plurality of first grooves, each of the first grooves exposes two adjacent second sub-sections in the first direction.
  • a plurality of second protective pillars are formed on the side walls of the second groove, and the first protective pillars and the second protective pillars together constitute the first protective layer.
  • forming the transistor includes:
  • a source electrode and a drain electrode are respectively formed at the bottom and top of the second sub-active pillar;
  • An isolation structure is formed between the second protection pillars and between the gate electrodes.
  • forming the gate electrode covering the gate oxide layer includes:
  • part of the gate conductive material is removed, and the remaining gate conductive material forms the gate.
  • the sidewall in the middle part of the second sub-active pillar is removed to form the second sub-active pillar with a recess and a recessed space corresponding to the recess. ; In the recessed space, at least a gate oxide layer surrounding the recess is formed.
  • Figure 1 is a schematic circuit connection diagram of a DRAM transistor provided in an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 3 to 31 are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to a dynamic random access memory. The following only takes the dynamic random access memory as an example for description.
  • the size of memory cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the demand for ions and leakage current in dynamic random access memory , the memory architecture has changed from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and then from Buried Channel Array Transistor. channel array transistor to vertical channel array transistor (Vertical Channel Array Transistor).
  • the dynamic random access memory is composed of multiple memory cell structures.
  • Each memory cell structure mainly consists of a transistor and a memory cell controlled by the transistor.
  • (storage capacitor), that is, the structure of dynamic random access memory includes a transistor (T, Transistor) and a capacitor (C, Capacitor) (1T1C); its main working principle is to use the amount of charge stored in the capacitor to Represents whether a binary bit is l or 0.
  • Figure 1 is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of the present disclosure; as shown in Figure 1, the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), and the source region of the transistor T is connected to One of the electrode plates of the capacitor C is electrically connected, and the other electrode plate of the capacitor C can be connected to a reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line). Connection; applying a voltage through the word line WL controls the transistor T to be turned on or off, and the bit line BL is configured to perform a read or write operation on the transistor T when the transistor T is turned on.
  • the size of dynamic random access memory is constantly shrinking.
  • the resistance between the capacitor and the transistor in the memory unit is getting larger and larger, which affects the signal transmission of the memory unit.
  • the size of the capacitor also changes with the size of the memory unit. The shrinkage makes the process of aligning capacitors and transistors increasingly difficult.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 2, the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • each active pillar includes a first sub-active pillar and a a second sub-active pillar on the first sub-active pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;
  • the channel structure of the transistor is located in the second sub-active pillar, and the extension direction of the channel structure is the same as the extension direction of the second sub-active pillar.
  • the first direction and the second direction are expressed as two orthogonal directions parallel to the top surface of the substrate;
  • the third direction is a direction perpendicular to the top surface of the substrate, that is, the third direction is the The extension direction of the active pillar; wherein, the top surface of the substrate can be understood as a plane perpendicular to the extension direction of the active pillar.
  • the angle between the first direction and the second direction ranges from 0 to 90 degrees.
  • the first direction may be perpendicular to the second direction. It can be understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the semiconductor pillars along the first direction and the second direction.
  • the first direction is represented by the X direction in the drawings; the second direction is represented by the Y direction in the drawings; and the third direction is represented by the Z direction in the drawings.
  • FIG. 3 to 31 are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 2, FIG. 3 to FIG. 31.
  • Step S201 is executed, referring to Figures 3 to 14, to form a plurality of active pillars.
  • forming a plurality of active pillars arranged in an array along the first direction and the second direction on the substrate includes the following steps:
  • each semiconductor pillar includes a first part, a second part located on the first part, and a second part located on the first part. a third part upon said second part;
  • Step a is performed, referring to Figures 3 to 6, to form a plurality of semiconductor pillars.
  • each first trench and/or the second trench is enlarged to form the plurality of semiconductor pillars.
  • the material of the semiconductor substrate 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.
  • a first etching is performed on the top surface of the semiconductor substrate 100 through a photolithography-etching process (LE, Lithography-Etch) to form a plurality of first pixels spaced apart along a first direction in the semiconductor substrate.
  • a trench T1; here, each first trench T1 extends along the second direction.
  • the first trench T1 divides the semiconductor substrate 100 into a plurality of semiconductor strips 102 .
  • the first trench T1 is located in the semiconductor substrate. That is to say, the depth of the first trench T1 along the third direction is smaller than the thickness of the semiconductor substrate 100 along the third direction.
  • the first etching includes but is not limited to a dry plasma etching process.
  • the first trench T1 includes but is not limited to a Shallow Trench Isolation (STI) structure.
  • STI Shallow Trench Isolation
  • a first insulating material 201 is formed in the first trench T1; wherein the top surface of the first insulating material 201 is substantially flush with the top surface of the semiconductor substrate 100; here, the first insulating material 201 is formed in the first trench T1.
  • An insulating material 201 is configured to provide support.
  • the constituent material of the first insulating material 201 includes but is not limited to silicon oxide (SiO 2 ).
  • the method of forming the first insulating material 201 includes but is not limited to physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition) and other processes. .
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD Atomic Layer Deposition
  • the first trench T1 includes but is not limited to a Shallow Trench Isolation (STI) structure.
  • STI Shallow Trench Isolation
  • a second etching is performed on the top surface of the semiconductor substrate 100 through a photolithography-etching process to form a plurality of second trenches T2 spaced apart along the second direction in the semiconductor substrate 100;
  • each second trench T2 extends along the first direction.
  • the second trench T2 divides each semiconductor strip 102 into a plurality of semiconductor pillars 103 .
  • the second trench T2 is located in the semiconductor substrate. That is to say, the depth of the second trench T2 along the third direction is smaller than the thickness of the semiconductor substrate 100 along the third direction.
  • the second etching includes but is not limited to a dry plasma etching process.
  • the second trench T2 includes but is not limited to a shallow trench isolation structure.
  • an enlargement process is performed on the bottom of each second trench T3; here, the enlargement process can be understood as etching the bottom of the second trench T2 along the second direction, so that the second The diameter width of the bottom of the trench T2 along the second direction is greater than the diameter width of the top of the corresponding trench along the second direction.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • the etchant is passed into the bottom of the second trench T2, and through anisotropic etching of the etchant, the bottom of the second trench T2 is enlarged along the Y-axis. The width of the direction.
  • lateral etching is performed by controlling plasma to form a trench structure with an enlarged diameter and width at the bottom of the second trench T2.
  • each first trench T1 may also be enlarged during the process of forming the first trench T1; here, the enlarging process of the bottom of each second trench T2 is used as an example. .
  • a BOSCH etching process is used to enlarge the bottom of each first trench and/or the second trench.
  • a normal etching process is first used to form a trench with a consistent width along the third direction, for example, a shallow trench isolation process is used to form the second trench (the trench shape at this time can refer to the second trench in Figure 3 (understand the shape of a trench), and then use the BOSCH etching process to enlarge the bottom of the second trench to form a third trench with an enlarged bottom as shown in FIG. 5 .
  • the depth of the second trench T2 along the third direction and the depth of the first trench T1 along the third direction may be the same or different.
  • the depth of the second trench T2 along the third direction is substantially the same as the depth of the first trench T1 along the third direction. In this way, the adjustment of process parameters during the manufacturing process can be reduced and the process difficulty can be reduced.
  • the etching process causes the plurality of cubic pillars located on the substrate 101 to be The bottom area is etched, and the size of the bottom area of the cubic pillar is reduced, thereby forming the active pillar 103, see FIG. 5 .
  • each semiconductor pillar 103 is still a whole, including a first part 1031, a second part 1032 located on the first part, and a third part 1033 located on the second part.
  • the first part 1031 , the second part 1032 , and the third part 1033 in each semiconductor column 103 are only configured to regionally divide the semiconductor column 103 along the extension direction of the semiconductor column 103 , and do not mean that the semiconductor column 103 is divided into regions.
  • the first part 1031, the second part 1032, and the third part 1033 may be separated or have different structures with obvious stacking interfaces.
  • the maximum diameter width of the first portion 1031 along the first direction is smaller than the minimum diameter width of the second portion 1032 along the first direction; and/or, the first portion 1031 has a maximum diameter along the first direction.
  • the maximum diameter width in the second direction is smaller than the minimum diameter width of the second portion 1032 along the second direction.
  • the maximum diameter width of the first part 1031 of the semiconductor pillar along the Y-axis direction is smaller than the minimum diameter width of the second part 1032 of the semiconductor pillar along the Y-axis direction.
  • the semiconductor pillars by forming the semiconductor pillars with a smaller bottom diameter and width, it is easier to oxidize the plurality of semiconductor pillars to form active pillars in the subsequent process, so as to form an active pillar between each active pillar and the substrate.
  • Corresponding oxidation pillars are provided so that the storage structure (eg, capacitor) formed on part of the sidewall of the active pillar can be isolated, thereby reducing the leakage problem of the storage structure (eg, capacitor) during use.
  • a first insulating material 201 is formed in the second trench; wherein the top surface of the first insulating material 201 is substantially flush with the top surface of the semiconductor substrate 100 .
  • the constituent material of the first insulating material 201 includes but is not limited to silicon oxide (SiO 2 ).
  • the method of forming the first insulating material 201 includes but is not limited to PVD, CVD and other processes.
  • CMP Chemical Mechanical Polishing
  • forming the support layer includes:
  • Part of the second insulating layer is removed along the second direction to form a first shallow trench, the bottom surface of the first shallow trench is flush with the top surface of the semiconductor pillar, and within the first shallow trench Filling the first insulating material;
  • Part of the second insulating layer is removed along the first direction to form a second shallow trench, the bottom surface of the second shallow trench is flush with the top surface of the semiconductor pillar, and the top surface of the semiconductor pillar is exposed. surface; filling the second insulating material in the second shallow trench;
  • the second insulating material that has not been removed and the second shallow trench are filled with the second insulating material to form the support layer.
  • the first insulating material 201 (refer to FIG. 6 ) has been filled between the plurality of semiconductor pillars 103 to obtain a first insulating layer 211 .
  • a second insulating material is deposited to cover the first insulating layer 211 and the top surface of the semiconductor pillar 103 to obtain the second insulating layer 212 .
  • the method of forming the second insulating layer 212 includes but is not limited to PVD, CVD and other processes.
  • the material of the second insulating layer 212 and the first insulating layer 211 may be different.
  • the component material of the second insulating layer 212 includes, but is not limited to, silicon nitride or carbon; the component material of the first insulating layer 211 includes, but is not limited to, silicon oxide.
  • a portion of the second insulating layer 212 is removed along the second direction through a photolithography-etching process to form a first shallow trench ST1 .
  • the bottom surface of the first shallow trench ST1 is in contact with the semiconductor pillar 103 .
  • the top surface is flush.
  • the first shallow trench ST1 does not expose the top surface of the semiconductor pillar 103 .
  • the first insulating material 201 is filled in the first shallow trench ST1 through processes including but not limited to PVD, CVD, etc.
  • the first insulating material 201 is made of the same material as the first insulating layer 211 .
  • the constituent material of the first insulating material 201 includes but is not limited to silicon oxide.
  • a portion of the second insulating layer 212 and a portion of the first insulating material 201 are removed along the first direction through a photolithography-etching process to form a second shallow trench ST2.
  • the bottom surface of ST2 is flush with the top surface of the semiconductor pillar 103 .
  • the second shallow trench ST2 exposes the top surface of the semiconductor pillar 103 .
  • the second insulating material 202 is filled in the second shallow trench ST2 through processes including but not limited to PVD, CVD, and the like.
  • the second insulating layer 212 that has not been removed and the second shallow trench are filled with the second insulating material 202 to form the support layer 2121.
  • the second insulating material 202 is made of the same material as the second insulating layer 212 and is different from the first insulating material 201 .
  • the component material of the second insulating material 202 includes but is not limited to silicon nitride or carbon; the component material of the first insulating material 201 includes but is not limited to silicon oxide.
  • the support layer 2121 is configured to protect the top surface of the active pillar 103; at the same time, the support layer 2121 covering the top surface of the active pillar 103 integrally forms a network structure, which is beneficial to the protection of the active pillar 103.
  • the semiconductor pillars 103 provide effective support. That is to say, the support layer 2121 not only protects the top surface of the active pillar 103, but also supports the plurality of semiconductor pillars 103 arranged in the array, so as to facilitate the formation of a stable semiconductor structure.
  • forming the second protective layer includes:
  • an etching process is used to remove part of the first insulating material 201 to form a third shallow trench ST3; the bottom surface of the third shallow trench ST3 is flush with the bottom surface of the third portion 1033, exposing all The side wall of the third part 1033.
  • the etching process used may include a dry etching process and the like.
  • the support layer 2121 is used as a mask to etch the first insulating material 201 between the grids of the support layer 2121 along the Z-axis direction (refer to FIG. 11), and the The first insulating material 201 (refer to FIG. 11) between the third portions 1033 forms a third shallow trench ST3.
  • a sacrificial material 203 is deposited in the third shallow trench ST3 through processes including but not limited to PVD, CVD, etc.
  • the sacrificial material 203 covers the sidewalls, bottom surface and the third shallow trench ST3.
  • the material of the sacrificial material 203 is different from the material of the first insulating material 201 .
  • the component material of the sacrificial material 203 includes, but is not limited to, silicon nitride or carbon; the component material of the first insulating layer 211 includes, but is not limited to, silicon oxide.
  • an etching process is used to remove the sacrificial material 203 covering the bottom surface of the third shallow trench ST3 (refer to Figure 13), leaving at least the sacrificial material covering the sidewalls of the third portion 1033 to obtain the second protection.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • longitudinal etching is performed by controlling plasma to remove the sacrificial material 203 covering the bottom surface of the third shallow trench ST3, while at least retaining the side covering the third portion 1033. Wall sacrificial material 203.
  • the second protective layer covers the side wall of the third part 1033, which can reduce unnecessary contamination of the third part 1033 during subsequent manufacturing processes.
  • the third part 1033 is configured to form the channel structure of the transistor in the subsequent process. It can be understood that the channel structure has a crucial impact on the performance of the semiconductor structure, and is covered by the second protective layer.
  • the sidewalls of the third part 1033 and the support layer 2121 cover the top surface of the third part 1033 to avoid contamination of the third part 1033 in subsequent processes and avoid unnecessary damage to the channel structure of the transistor. defect.
  • an etching process is used to remove the remaining first insulating material 201 (refer to Figure 14) covering between the active pillars 103, exposing the sidewalls of the part 1031, the sidewalls of the second part 1032, and part of the top surface of the substrate 101 .
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • the semiconductor pillar 103 (refer to FIG. 15 ) is subjected to an oxidation treatment, so that the first part 1031 (refer to FIG. 15 ) is completely oxidized into the oxidized pillar 104 , and the second part 1032 (refer to FIG. 15 ) is oxidized into an oxide layer 106.
  • the semiconductor pillar 103 is oxidized through an oxidation process, so that the first part 1031 is entirely oxidized into the oxide pillar 104, and the surface of the exposed second part 1032 of the semiconductor pillar is oxidized into the oxide layer 106, and at the same time, The top surface of the substrate 101 is also oxidized to form a substrate oxide layer 105 .
  • the oxide pillar 104 and the oxide layer 106 are made of the same material.
  • the constituent materials of the oxide pillar 104 and the oxide layer 106 include, but are not limited to, silicon oxide.
  • the size of the transition portion between the bottom of the semiconductor pillar 103 and the substrate 101, that is, the first portion 1031, is smaller and is easy to be completely oxidized.
  • the second part 1032 is relatively small in size and only the surface is oxidized.
  • the unoxidized portions of the third portion 1033 (see FIG. 15 ) and the second portion 1032 , that is, between the active pillar 401 and the substrate 101 are oxidized by the oxidized pillar.
  • each of the active pillars 401 is still a whole, including a first sub-active pillar 402 and a second sub-active pillar 403 located on the first sub-active pillar 402; each of the active pillars 401 is a whole.
  • the first sub-active pillar 402 and the second sub-active pillar 403 in the source pillar 401 are only configured to regionally divide the active pillar 401 along the extension direction of the active pillar 401, and do not mean that the active pillar 401 is divided into regions.
  • the first sub-active pillar 402 and the second sub-active pillar 403 may be separated or have different structures with obvious stacking interfaces.
  • the active pillar 401 is formed after the semiconductor pillar 103 is oxidized, the first sub-active pillar 402 and the second sub-active pillar 403 have been formed simultaneously.
  • each second sub-active column 403 is still a whole.
  • the second sub-active pillar 403 includes a second sub-active pillar bottom 4033, a second sub-active pillar middle portion 4032 located on the second sub-active pillar bottom 4033, and a second sub-active pillar middle portion 4032 located on the second sub-active pillar bottom 4033.
  • the pillar top 4031 is only configured to regionally divide the second sub-active pillar 403 along the extension direction of the second sub-active pillar 403, and does not mean that the second sub-active pillar bottom 4033,
  • the middle part 4032 of the second sub-active pillar and the top part 4031 of the second sub-active pillar may be separated or have different structures with obvious stacking interfaces.
  • the first insulating material 201 is filled in the gaps between the oxide layer and the oxidation pillar, and in the gaps between the second protective layer 213 and the grid-like gaps of the support layer 2121 The first insulating material 201 is filled.
  • the method of filling the first insulating material 201 includes but is not limited to PVD, CVD and other processes.
  • the materials of the first insulating material 201, the oxide pillar 104 (refer to FIG. 16) and the oxide layer 106 (refer to FIG. 16) may be the same or different.
  • the constituent material of the first insulating material 201 includes but is not limited to silicon oxide.
  • the first insulating material 201 , the oxide pillar 104 , and the oxide layer 106 may be made of the same material.
  • the first insulating material 201 is shown as the first insulating material 201 .
  • the first insulating material 201 can be filled between the plurality of oxidation pillars 104, between the plurality of active pillars 401, and in the grid-like gaps of the support layer 2121, so that the first insulation The material 201 is flush with the top surface of the support layer 2121 .
  • an etching process is used to remove the first insulating material 201 in the grid-like gaps of the support layer 2121 and in the gaps of the second protective layer 213 , and to remove the first insulating material 201 in the first sub-active layer.
  • the first insulating material 201 between the pillars 402 exposes the sidewalls of the first sub-active pillars 402; at the same time, the first insulating material remaining on the substrate 101 that has not been removed becomes the first insulating material 201 between the pillars 402.
  • the isolation structure 107 is described.
  • the first sub-active pillar 402 can penetrate deep into the isolation structure 107 and penetrate the isolation structure 107 along the extension direction of the first sub-active pillar 402 .
  • the bottom of the first sub-active pillar 402 has a portion that is deep into the isolation structure 107 , and the isolation structure 107 can provide stable support for the first sub-active pillar 402 .
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • the first insulating material 201 between the plurality of oxidation pillars 104 together with the oxidation pillars 104 and the substrate oxide layer 105 form an isolation structure 107 on the substrate 101 .
  • the composition material of the isolation structure 107 includes, but is not limited to, silicon oxide.
  • the isolation structure 107 can improve the leakage problem between the functional devices above the isolation structure 107 (such as the first sub-active pillar 402, the memory structure 315 described in FIG. 21 below) and the substrate 101.
  • the support layer 2121 and the second protective layer 213 are removed to obtain the second sub-active pillar 403 .
  • the filling dielectric layers in the gaps between the second sub-active pillars 403 need to be removed, leaving only the second sub-active pillars 403 .
  • the gap between the second sub-active pillars 403 is filled with the support layer 2121, and in the process of forming the storage structure 315, the portion between the support layers 2121 is filled with The first electrode layer 3151, the dielectric layer 3152, and the second electrode layer 3153 all need to be removed.
  • an etching process is used to remove the supporting layer 2121; parts of the first electrode layer 3151, dielectric layer 3152, and second electrode layer 3153 filled between the supporting layers 2121 are removed, leaving at least the first sub-layer 3151 covered.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • longitudinal etching is performed by controlling plasma to remove the dielectric layer filling the gap between the second sub-active pillars 403 to form the second sub-active pillar. Pillar 403 , and the sidewalls and top surface of the second sub-active pillar 403 are exposed.
  • the active pillar 401 when forming the active pillar 401 (refer to FIG. 16 above), the first sub-active pillar 402 and the second sub-active pillar 403 have been simultaneously formed; here, only the second sub-active pillar 403 is formed.
  • the filling dielectric layer in the gap between the pillars 403 needs to be removed (refer to the above-mentioned Figures 20 and 21), exposing the side walls and top surface of the second sub-active pillar 403, so as to facilitate the subsequent process.
  • the channel structure CH, source S, and drain D of the transistor 400 are formed in the second sub-active pillar 403, and a gate 405 and a gate oxide layer 404 are formed around the second sub-active pillar 403 (refer to the following Refer to Figure 31).
  • each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar.
  • a memory cell is formed on the sidewall of the first sub-active pillar, and the channel structure, source and drain of the transistor are formed in the second sub-active pillar and surround the second sub-active pillar.
  • the pillars form the gate and the gate oxide layer. In other words, forming the memory structure and the transistor on the same active pillar can reduce the difficulty of aligning the memory cell and the transistor, thereby reducing the process difficulty.
  • Execute step S202 continue to refer to FIG. 18, and add a first element to the first sub-active column.
  • the first element includes an N-type or P-type doping element. Adding the first element to the first sub-active column includes: adding N to the first sub-active column through a diffusion or ion implantation process. Type or P-type doping elements;
  • the first element includes a metal element
  • adding the first element to the first sub-active pillar includes: forming a metal layer containing the metal element covering the sidewall of the first sub-active pillar; using A rapid thermal annealing process causes the metal layer and the first sub-active pillar to react to form a metal compound.
  • the first element may include an N-type or P-type doping element, and a vapor phase diffusion process is used to remove the first doping element from the first sub-active pillar.
  • the sidewalls of 402 are incorporated into the first sub-active pillar 402 .
  • the N-type doping element may include at least one of nitrogen (N) element, phosphorus (P) element, arsenic (As) element, antimony (Sb) element, etc.;
  • the P-type doping element may include At least one of boron (B) element, gallium (Ga) element, indium (In) element, etc.
  • the first element includes phosphorus.
  • a gas phase diffusion process is used to pass in a gas containing phosphorus at a temperature of 800°C-1200°C. The gas is in contact with the first sub-active pillar 402.
  • a thin layer of medium containing phosphorus element is first formed on the sidewall surface of the first sub-active pillar 402.
  • the phosphorus element in the thin layer of medium diffuses to the Inside the first sub-active pillar 402, a phosphorus element is added to the first sub-active pillar 402; the first sub-active pillar 402 with a phosphorus element is added to the first sub-active pillar 402 without a phosphorus element.
  • Source pillar 402 has lower resistivity.
  • the first element includes an N-type or P-type doping element according to transistors of different conductivity types (refer to the transistor 400 in FIG. 31 below).
  • the transistor structure is an N-type transistor
  • the first element is an N-type doping element
  • the N-type doping element is, for example, phosphorus, arsenic, or antimony
  • the transistor structure When it is a P-type transistor, the first element is a P-type doping element, and the P-type doping element is, for example, boron, gallium, or indium.
  • the first element may include a metal element, and a thin film deposition process is used to form a metal layer containing the metal element covering the sidewalls of the first sub-active pillar 402 .
  • An annealing process such as Rapid Thermal Processing (RTP) is used to react the metal layer and the first sub-active pillar 402 to form a metal compound.
  • RTP Rapid Thermal Processing
  • the constituent materials of the metal elements include cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag) and At least one of gold (Au) and the like.
  • the first element includes cobalt
  • a thin film deposition process is used to form a metal layer containing cobalt covering the sidewall of the first sub-active pillar 402, and a rapid thermal annealing process is used, so that the metal layer containing cobalt
  • the metal layer of the element reacts with the first sub-active pillar 402 to form a cobalt compound.
  • the cobalt element is added to the first sub-active pillar 402 to form a cobalt compound.
  • the first sub-active pillar 402 with the cobalt element added has the following properties compared to the first sub-active pillar 402 without cobalt element. Lower resistivity.
  • the degree of reaction between the metal layer and the first sub-active pillar can be adjusted by adjusting the thin film deposition process and/or rapid thermal annealing process parameters according to actual needs, and the formed metal compound can be controlled.
  • Shape For example, the metal layer may only react with the surface of the first sub-active pillar, and the surface layer of the first sub-active pillar is formed as the metal compound; the metal layer may also react with the first sub-active pillar. The sub-active pillar reacts completely, and the entire first sub-active pillar is formed into the metal compound.
  • a first element is added to the first sub-active pillar to reduce the resistivity of the first sub-active pillar, thereby reducing the resistance between the first sub-active pillar and the memory structure, and thereby reducing the resistance between the first sub-active pillar and the memory structure. Reduce signal transmission delays, ultimately improving the performance of semiconductor structures.
  • Execute step S203 refer to Figure 19 to Figure 20 to form a storage structure.
  • the storage structure is formed on at least the sidewall of the first sub-active pillar, including:
  • a second conductive layer is formed in the gap of the dielectric layer.
  • a first conductive layer 3151 covering the sidewalls of the first sub-active pillar 402 is formed;
  • the first conductive layer is configured as the lower electrode of the capacitor; the dielectric layer is configured as the dielectric of the capacitor; and the second conductive layer is configured as the upper electrode of the capacitor.
  • the constituent materials of the first conductive layer 3151 may include but are not limited to ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).
  • Ru ruthenium
  • RuO ruthenium oxide
  • TiN titanium nitride
  • the first conductive layer may be formed on the sidewall of the first sub-active pillar through a selective deposition process, or may be formed through other deposition processes.
  • the selective deposition process refers to selectively depositing the first conductive layer on the sidewall of the first sub-active pillar.
  • the other deposition processes include but are not limited to PVD, CVD, ALD and other processes.
  • forming the first conductive layer 3151 covering the sidewalls of the first sub-active pillar 402 includes:
  • a first conductive layer 3151 covering the sidewalls of the first sub-active pillar 402 is formed.
  • a dielectric layer 3152 covering at least the sidewalls of the first conductive layer 3151 is formed; a second conductive layer 3153 is formed in the gap of the dielectric layer 3152 .
  • the constituent materials of the dielectric layer include high-k materials.
  • High-k materials generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value.
  • the material of the dielectric layer may include, but is not limited to, aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), hafnium oxide (HfO 2 ), strontium titanate (SrTiO 3 ), etc.
  • the constituent materials of the second conductive layer may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.
  • the method of forming the second conductive layer includes but is not limited to PVD, CVD and other processes.
  • the method of forming the first conductive layer and the second electrode layer in the above embodiments can also be understood as using a selective deposition process to form a conductive layer on conductive layer (CoC, Conductive on Conductive); here, the selective deposition process Including but not limited to ALD process, etc.
  • the material configured to form the first conductive layer can be formed only on the sidewalls of the first sub-active pillars, or on other parts of the active column.
  • the material chosen is not formed on the top surface of the isolation structure.
  • Step S204 is executed, and multiple transistors are formed with reference to FIGS. 22 to 31 .
  • the method further includes: forming a first protective layer surrounding the top sidewall of the second sub-active pillar;
  • the forming the first protective layer includes:
  • Part of the first insulating material on the top of the second sub-active pillar is removed to form a plurality of first grooves, each of the first grooves exposes two adjacent second sub-sections in the first direction.
  • a plurality of second protective pillars are formed on the side walls of the second groove, and the first protective pillars and the second protective pillars together constitute the first protective layer.
  • a first insulating material 201 is formed between the second sub-active pillars 403; wherein the top surface of the first insulating material 201 is flush with the top surface of the second sub-active pillar 403. .
  • the constituent material of the first insulating material 201 includes but is not limited to silicon oxide.
  • the method of forming the first insulating material 201 includes but is not limited to PVD, CVD, ALD and other processes.
  • part of the first insulating material on the top 4031 of the second sub-active pillar is removed through a photolithography-etching process to form a plurality of first recesses arranged in an array along the first direction and the second direction.
  • Groove R1 each first groove R1 exposes two opposite side walls of the two second sub-active pillar tops 4031 adjacent in the first direction, and each first groove
  • the bottom surface of R1 is substantially flush with the bottom surface of the second sub-active pillar top 4031. That is to say, the depth of the first groove R1 along the third direction is substantially equivalent to the thickness of the second sub-active pillar top 4031 along the third direction.
  • the first etching includes but is not limited to a dry plasma etching process.
  • the second insulating material is filled in the first groove R1 to form a plurality of first protection pillars 2211; wherein the top surface of the first protection pillar 2211 is in contact with the top surface of the second sub-active pillar.
  • the top surface of 4031 is substantially flush; here, the first protection pillar 2211 is configured to protect the side wall of the top 4031 of the second sub-active pillar.
  • the method of forming the material of the first protective pillar 2211 includes but is not limited to PVD, CVD and other processes.
  • the composition material of the first protective pillar 2211 and the composition material of the first insulating material 201 may be different.
  • the first protective pillar 2211 is made of a material including, but not limited to, silicon nitride or carbon; a material of the first insulating material 201 is made of, but is not limited to, silicon oxide.
  • the first protection pillar 2211 is formed using a shallow trench isolation process including but not limited to.
  • the remaining first insulating material 201 on the top 4031 of the second sub-active pillar is removed through an etching process to form a plurality of second grooves R2 extending along the first direction.
  • Each of the second grooves R2 extends along the first direction.
  • the two grooves R2 at least expose other side walls of the second sub-active pillar top 4031 that are not covered by the first protection pillar 2211 (can be understood as two adjacent second sub-active pillars in the second direction).
  • the two opposite side walls of the sub-active pillar top 4031), and the bottom surface of each second groove R2 is substantially flush with the bottom surface of the second sub-active pillar top 4031. That is to say, the depth of the second groove R2 along the third direction is substantially equivalent to the thickness of the second sub-active pillar top 4031 along the third direction.
  • the first etching includes but is not limited to a dry plasma etching process.
  • the second protective pillar 2212 is formed through a spacer process.
  • a second insulating material is deposited on the sidewall and bottom surface of the second groove R2 through processes including but not limited to PVD, CVD, and at the same time on the top surface of the first protection pillar 2211 and the top surface of the second sub-active pillar.
  • a second insulating material is deposited on the top surface of 4031.
  • Each second protection pillar 2212 extends along the first direction and is configured to protect the sidewall of the top 4031 of the second sub-active pillar.
  • the first protection pillar 2211 and the second protection pillar 2212 together form the first protection layer 221.
  • the first protection layer 221 surrounds the top 4031 of the second sub-active pillar to protect the All side walls of the top 4031 of the second sub-active pillar.
  • composition material of the second protective pillar 2212 and the composition material of the first insulating material 201 may be different.
  • the component material of the second protective pillar 2212 includes, but is not limited to, silicon nitride or carbon; the component material of the first insulating material 201 includes, but is not limited to, silicon oxide.
  • the second protective pillar 2212 is formed using a dry etching process.
  • longitudinal etching is performed by controlling plasma to remove the second insulating material on the bottom surface of the second groove R2, and simultaneously remove the second insulating material on the top of the first protective pillar 2211.
  • the second insulating material on the top surface of the second sub-active pillar top 4031 and the second insulating material on the side wall of the second groove form the second protection pillar 2212.
  • the second protective pillar 2212 formed through a sidewall process not only protects the sidewall of the top 4031 of the second sub-active pillar, but can also be configured as a mask to form the gate electrode 405 (reference Figure 30 below).
  • the second protective pillar 2212 formed through the spacer process serves as a mask, and can further reduce the size of the mask based on the existing photolithography process to form a smaller-sized semiconductor structure.
  • Using the first protective layer as a mask can reduce one photolithography process step, thereby reducing process cost and difficulty. Since the second protection pillar formed through the spacer process is self-aligned based on the second sub-active pillar, the alignment of the gate electrode formed in the subsequent process (refer to Figure 30 below) can be improved. accuracy and process window.
  • forming a transistor includes:
  • a source electrode and a drain electrode are respectively formed at the bottom and top of the second sub-active pillar;
  • An isolation structure is formed between the second protection pillars and between the gate electrodes.
  • the second sub-active pillar is removed.
  • the first insulating material 201 corresponding to the middle part of the pillar 4032 exposes the sidewall of the middle part of the second sub-active pillar 4032; and the top surface of the first insulating material 201 that has not been removed here is in contact with the second sub-active pillar.
  • the bottom surface of the middle portion 4032 is substantially flush. That is to say, the depth of the unremoved first insulating material 201 along the third direction is substantially equal to the thickness of the second sub-active pillar bottom 4033 along the third direction.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • a wet etching process is used to remove the first insulating material between the middle portions 4032 of the second sub-active pillars through isotropic removal, exposing the sidewalls of the middle portions 4032 of the second sub-active pillars. ; and the first insulating material 201 that has not been removed covers the sidewall of the second sub-active pillar bottom 4033.
  • a gate oxide layer 404 covering the sidewalls of the second sub-active pillar middle portion 4032 is formed.
  • the gate oxide layer 404 can be formed around the sidewalls of each second sub-active pillar middle portion 4032 by in-situ oxidizing the sidewalls of the second sub-active pillar middle portions 4032.
  • a gate oxide layer 404 may also be deposited on the sidewall surrounding the middle portion 4032 of each second sub-active pillar through an ALD process.
  • the material of the gate oxide layer 404 includes but is not limited to silicon oxide.
  • a gate 405 covering the gate oxide layer is formed.
  • forming the gate 405 covering the gate oxide layer 404 includes:
  • the gate conductive material forms the gate electrode 405 .
  • Gate conductive materials are filled in the gaps of the gate oxide layer 404 through electrochemical plating (ECP, Electro-Chemical Plating), PVD, CVD and other processes.
  • ECP Electro-Chemical Plating
  • PVD Physical Plating
  • CVD chemical vapor deposition
  • the gate conductive material can also be filled in the gap between the first protective layers 221, and the top surface of the gate conductive material is flush with the top surface of the second sub-active pillar top 4031. flat.
  • the constituent materials of the gate conductive material include at least one of cobalt, nickel, tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, aluminum-copper, silver, gold, etc. one.
  • Each gate 405 extends along the first direction to physically connect the gates of each transistor in each row of transistors arranged along the second direction to each other; and adjacent gates arranged along the second direction The two gates 405 are isolated from each other.
  • the side of the gate 405 away from the gate oxide layer 404 is flush with the sidewall of the second protection pillar 2212 away from the gate oxide layer.
  • longitudinal etching is performed by controlling plasma to remove part of the gate conductive material to form the gate 405 .
  • the side of the gate 405 in the second direction away from the gate oxide layer 404 and the second protection pillar 2212 are away from the gate oxide.
  • the sidewall of one side of the layer 404 is substantially flush along the extending direction of the second sub-active pillar 403 .
  • the first protective layer since the second protective pillar formed through the sidewall process can have a further reduced size based on the existing photolithography process, the first protective layer also has a further reduced size. size, using the first protective layer as a mask to form a smaller gate electrode and/or forming a smaller spacing between gate electrodes; at the same time, using the first protective layer as a mask can reduce One photolithography process step, thereby reducing process cost and difficulty; furthermore, due to the self-aligned second protective pillar formed through the sidewall process, the alignment accuracy and process window of the formed gate can be improved.
  • a first insulating material is filled at least between two adjacent gate electrodes 405 through processes such as PVD and CVD to form the gate isolation structure 406 .
  • a first insulating material may also be filled in the gap between the first protective layers 221.
  • the top surface of the first insulating material is flush with the top surface of the second sub-active pillar top 4031.
  • the gate isolation structure 406 is formed to space the gates 405 of two adjacent rows of transistors 400 arranged along the second direction from each other.
  • each second sub-active pillar 403 is still a whole, and the second sub-active pillar bottom 4033 and the second sub-active pillar in each second sub-active pillar 403
  • the pillar middle part 4032 and the second sub-active pillar top 4031 are only configured to regionally divide the second sub-active pillar 403 along the extension direction of the second sub-active pillar 403.
  • the middle part 4032 of the second sub-active pillar is configured to form the channel structure CH of the transistor 400;
  • the top part 4031 of the second sub-active pillar is configured to form the drain D or the source S of the transistor 400, so
  • the second sub-active pillar bottom 4033 is configured to form the source S or the drain D of the transistor.
  • the sidewall of the middle part 4032 of the second sub-active pillar is removed to form the second sub-active pillar 403 with a recess, and a recessed space R3 corresponding to the recessed portion; referring to the above-mentioned FIG. 29 , in the recessed space R3, at least a gate oxide layer 404 surrounding the recessed portion is formed.
  • the etching process used to form the second sub-active pillar 403 with the recessed portion may include a wet etching process, a dry etching process, and the like.
  • a wet etching process is used to remove the surface material of the middle part 4032 of the second sub-active pillar through isotropic removal to form the recessed space R3.
  • the diameter width of the second sub-active pillar middle part 4032 is smaller than the diameter width of the second sub-active pillar top 4031 and/or the diameter width of the second sub-active pillar bottom 4033.
  • more space can be reserved for the formation of a gate surrounding the middle of the second sub-active pillar in subsequent processes.
  • more space means that the gate has more gate material and has lower resistance, so that the gate has better electrical properties.
  • the transistor 400 is formed.
  • the transistor includes: a gate oxide layer 404 arranged around the second sub-active pillar, and a gate 405 arranged around the gate oxide layer 404.
  • the source electrode S and the drain electrode D respectively provided at two opposite ends of the second active pillar 403, the side of the gate electrode 405 away from the gate oxide layer 404 is connected to the second protection electrode 405.
  • the sidewall of the pillar 2212 away from the gate oxide layer 405 is flush.
  • the shape of the gate is different; for example, referring to Figure 31, in a columnar gate transistor, the gate is formed in a columnar form on one side of the channel region; in a semi-surround gate transistor , the gate half surrounds the channel area; in the all-around (GAA, Gate All Around) gate transistor, the gate completely surrounds the channel area.
  • GAA Gate All Around
  • the transistor types in the embodiments of the present disclosure may include the above-mentioned types, but are not limited thereto.
  • the type of the transistor is a full surround gate transistor 400.
  • the gate structure here includes a gate (G, Gate) and a gate oxide layer; among them, the gate oxide layer is located between the gate and the channel region and is configured as an electrically isolated trench. channel area and gate to reduce the hot carrier effect of the transistor.
  • G Gate
  • the gate oxide layer is located between the gate and the channel region and is configured as an electrically isolated trench. channel area and gate to reduce the hot carrier effect of the transistor.
  • the material of the gate may include metal and/or polysilicon (Poly), etc.
  • the material of the gate oxide layer may include, but is not limited to, silicon oxide.
  • gate formation methods include but are not limited to PVD, CVD, ALD, etc.
  • the formation method of the gate oxide layer includes but is not limited to in-situ oxidation.
  • a source electrode and a drain electrode are respectively formed at two opposite ends of the second sub-active pillar.
  • methods of forming the source electrode and the drain electrode include, but are not limited to, ion implantation processes, diffusion processes, and the like.
  • the positions of the source electrode and the drain electrode located at the opposite ends of the second sub-active pillar can be interchanged; the actual situation can be selected and set according to actual needs.
  • the memory in the above embodiment is a transistor on capacitor (TOC) structure, and the structure further includes: a plurality of bit lines located on the transistor and connected to the top electrode of the second part. touch.
  • TOC transistor on capacitor
  • the method further includes forming a bit line BL on the transistor.
  • the constituent material of the bit line BL includes at least one of cobalt, nickel, tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, aluminum-copper, silver, gold, etc. .
  • bit line BL is configured to perform a read or write operation on the transistor when the transistor is turned on.
  • bit line BL above the transistor and using the bit line BL as a metal bit line (Metal BL) can reduce resistance and process difficulty; it is more consistent with the circuit design scheme of the memory.
  • each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar.
  • Sub-active pillar a first element is added to the first sub-active pillar, and the resistivity of the first sub-active pillar containing the first element in the material is smaller than that of the first sub-active pillar in which the material does not contain the first element.
  • the resistivity of a sub-active pillar is used to form a storage structure on the sidewall of the first sub-active pillar; and a channel structure of the transistor located in the second sub-active pillar is formed.
  • a first element is added to the first sub-active pillar to reduce the resistivity of the first sub-active pillar, thereby reducing the resistance between the first sub-active pillar and the memory structure, and thereby reducing the resistance between the first sub-active pillar and the memory structure.
  • Reduce signal transmission delays ultimately improving the performance of semiconductor structures.
  • forming the memory structure and the transistor on the same active pillar can reduce the difficulty of aligning the memory cell and the transistor, thereby reducing the process difficulty.
  • embodiments of the present disclosure provide a semiconductor structure, including: a substrate, a plurality of active pillars located above the substrate, a memory structure, and a plurality of transistors;
  • the plurality of active pillars are arranged in an array along the first direction and the second direction; each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar.
  • Source pillar; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; the material of the first sub-active pillar contains a first element, and the material contains the first element
  • the resistivity of the first sub-active pillar is less than the resistivity of the first sub-active pillar whose material does not include the first element;
  • the storage structure covers the sidewall of the first sub-active column
  • the channel structure of each transistor is located in the second sub-active pillar, and the extending direction of the channel structure is the same as the extending direction of the second sub-active pillar.
  • the first element includes an N-type doping element or a P-type doping element
  • the material of the first sub-active pillar includes a semiconductor material; or the first element includes a metal element, so The material of the first sub-active pillar includes a compound of the metal element.
  • the substrate includes an isolation structure on which a plurality of the active pillars are located.
  • the storage structure includes:
  • the second electrode layer is located in the gap of the dielectric layer and covers the surface of the dielectric layer.
  • the semiconductor structure further includes: a first protective layer surrounding the top sidewall of the second sub-active pillar;
  • the first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars;
  • Each of the first protection pillars is located between the tops of two adjacent second sub-active pillars in the first direction, and covers two opposite side walls of the two adjacent second sub-active pillars;
  • Each second protection pillar extends along the first direction, covers the sidewall of the top of the second sub-active pillar that is not covered by the first protection pillar, and covers the sidewall of the first protection pillar.
  • the diameter width of the middle part of the second sub-active pillar is smaller than the diameter width of the top part of the second sub-active pillar and/or the diameter width of the bottom part of the second sub-active pillar;
  • the transistor includes: a gate oxide layer arranged around the second active sub-pillar, a gate electrode arranged around the gate oxide layer, and two opposite ends of the second active pillar respectively.
  • the side of the gate electrode away from the gate oxide layer is flush with the side wall of the second protection pillar away from the gate oxide layer.
  • the semiconductor structure further includes:
  • a plurality of bit lines are located on the transistor and are electrically connected to the top of the second sub-active pillar.
  • the semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the above-mentioned embodiments.
  • a memory including: one or more semiconductor structures as described in any one of the above embodiments of the present disclosure.
  • a first element is added to the first sub-active pillar to reduce the resistivity of the first sub-active pillar, thereby reducing the gap between the first sub-active pillar and the storage structure. resistance, thereby reducing the delay in signal transmission and ultimately improving the performance of the semiconductor structure.
  • forming the memory structure and the transistor on the same active pillar can reduce the difficulty of aligning the memory cell and the transistor, thereby reducing the process difficulty.
  • the memory includes DRAM.

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Abstract

本公开实施例公开了一种半导体结构及其制作方法、存储器，其中，所述半导体结构包括：衬底、位于所述衬底上方的多个有源柱、存储结构、多个晶体管；所述多个有源柱沿第一方向和第二方向呈阵列排布；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；所述第一子有源柱的材料包含第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；所述存储结构，覆盖所述第一子有源柱的侧壁；每一所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。

Description

半导体结构及其制作方法、存储器
相关申请的交叉引用
本申请基于申请号为202210707466.X、申请日为2022年06月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法、存储器。
背景技术
动态随机存取存储器(DRAM，Dynamic Random Access Memory)的存储阵列架构是由包括一个晶体管和一个电容器的存储单元(即1T1C的存储单元)组成的阵列。晶体管的栅极与字线相连，漏极与位线相连，源极与电容器相连。
随着动态随机存取存储器的尺寸不断缩小，存储单元的尺寸也随之缩小。如何保证动态随机存取存储器中存储单元的性能，成为亟待解决的问题。
发明内容
根据本公开的第一方面，提供了一种半导体结构，包括：衬底、位于所述衬底上方的多个有源柱、存储结构、多个晶体管；
所述多个有源柱沿第一方向和第二方向呈阵列排布；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；所述第一子有源柱的材料包含第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；
所述存储结构，覆盖所述第一子有源柱的侧壁；
每一所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。
上述方案中，所述第一元素包括N型掺杂元素或P型掺杂元素，所述第一子有源柱的材料包括半导体材料；或者，所述第一元素包括金属元素，所述第一子有源柱的材料包括所述金属元素的化合物。
上述方案中，所述衬底包括隔离结构，多个所述有源柱位于所述隔离结构上。
上述方案中，所述存储结构包括：
第一电极层，所述第一电极层覆盖所述第一子有源柱的侧壁；
介质层，至少覆盖所述第一电极层的侧壁；
第二电极层，位于所述介质层的间隙中，覆盖所述介质层的表面。
上述方案中，所述半导体结构还包括：围绕所述第二子有源柱顶部侧壁的第一保护层；
所述第一保护层包括多个第一保护柱和多个第二保护柱；
每个所述第一保护柱位于在第一方向相邻的两个第二子有源柱顶部之间，且覆盖相邻的两个第二子有源柱相对的两个侧壁；
每一所述第二保护柱沿第一方向延伸，覆盖所述第二子有源柱顶部未被所述第一保护柱覆盖的侧壁，并且覆盖所述第一保护柱的侧壁。
上述方案中，所述第二子有源柱中部的径宽小于所述第二子有源柱顶部的径宽和/或所述第二子有源柱底部的径宽；
所述晶体管包括：环绕所述第二子有源柱设置的栅极氧化层，环绕所述栅极氧化层设置的栅极，以及分别设置在所述第二有源柱相对的两个端部的源极和漏极，所述栅极远离所述栅极氧化层的一侧与所述第二保护柱远离所述栅极氧化层的一侧的侧壁齐平。
上述方案中，所述半导体结构还包括：
多条位线，位于所述晶体管上，与所述第二子有源柱顶部电连接。
根据本公开的第二方面，提供了一种存储器，包括：一个或多个如本公开上述方案中任一项所述的半导体结构。
根据本公开的第三方面，提供了一种半导体结构的制作方法，所述方法包括：
提供衬底，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个有源柱；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；
在所述第一子有源柱中增加第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；
至少在所述第一子有源柱的侧壁形成存储结构；
形成多个晶体管，所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。
上述方案中，
所述第一元素包括N型或P型掺杂元素，在所述第一子有源柱中增加第一元素，包括：通过扩散或者离子注入工艺在所述第一子有源柱中增加N型或P型掺杂元素；
或者，
所述第一元素包括金属元素，在所述第一子有源柱中增加第一元素，包括：形成覆盖所述第一子有源柱的侧壁的含有所述金属元素的金属层；采用退火工艺，使得所述金属层和所述第一子有源柱反应形成金属化合物。
上述方案中，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个有源柱，包括：
在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个半导体柱；每一所述半导体柱包括第一部分、位于所述第一部分上的第二部分、以及位于所述第二部分上的第三部分；
形成覆盖所述第三部分的顶面的支撑层；
形成至少覆盖所述第三部分的侧壁的第二保护层；
对所述半导体柱进行氧化处理，以使所述第一部分被完全氧化成氧化柱，且所述第二部分的表面被氧化成氧化层；
去除所述第二部分的表面的氧化层，得到所述第一子有源柱；
在形成所述存储结构之后，去除所述支撑层以及所述第二保护层，得到所述第二子有源柱。
上述方案中，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个半导体柱，包括：
提供半导体基底；
在所述基底中形成多条沿第一方向间隔排布的第一沟槽，以及多条沿第二方向间隔排布的第二沟槽；
对每一所述第一沟槽和/或所述第二沟槽底部进行扩大处理，形成所述多个半导体柱。
上述方案中，所述形成支撑层，包括：
在多个所述半导体柱之间填充满所述第一绝缘材料，得到第一绝缘层；
沉积第二绝缘材料，所述第二绝缘材料覆盖所述第一绝缘层和所述半导体柱的顶面，得到所述第二绝缘层；
沿所述第二方向去除部分所述第二绝缘层形成第一浅沟槽，所述第一浅沟槽的底面与所述半导体柱的顶面齐平，在所述第一浅沟槽内填充所述第一绝缘材料；
沿所述第一方向去除部分所述第二绝缘层形成第二浅沟槽，所述第二浅沟槽的底面与所述半导体柱的顶面齐平，且暴露出所述半导体柱的顶面；在所述第二浅沟槽内填充所述第二绝缘材料；
未被去除的所述第二绝缘层和所述第二浅沟槽内填充所述第二绝缘材料构成所述支撑层。
上述方案中，所述形成第二保护层，包括：
去除部分所述第一绝缘材料，形成第三浅沟槽；所述第三浅沟槽的底面与所述第三部分的底面齐平，暴露出所述第三部分的侧壁；
沉积牺牲材料，所述牺牲材料至少覆盖所述第三部分的侧壁，得到所述第二保护层。
上述方案中，所述至少在所述第一子有源柱的侧壁形成存储结构，包括：
形成覆盖所述第一子有源柱侧壁的第一导电层；
形成至少覆盖所述第一导电层的侧壁的介质层；
在所述介质层的间隙中形成第二导电层。
上述方案中，形成所述存储结构之后，所述方法还包括：形成围绕所述第二子有源柱顶部侧壁的第一保护层；
所述形成第一保护层，包括：
在所述第二子有源柱之间形成第一绝缘材料；
去除所述第二子有源柱顶部的部分第一绝缘材料，形成多个第一凹槽，每个所述第一凹槽暴露出在第一方向上相邻的两个所述第二子有源柱顶部相对的两个侧壁；
填充所述第一凹槽形成多个第一保护柱；
去除所述第二子有源柱顶部剩余的所述第一绝缘材料，形成多个沿所述第一方向延伸的第二凹槽；
在所述第二凹槽的侧壁形成多个第二保护柱，所述第一保护柱与所述第二保护柱共同构成所述第一保护层。
上述方案中，所述形成晶体管，包括：
在形成所述第一保护层之后，去除所述第二子有源柱中部对应的第一绝缘材料，暴露出所述第二子有源柱中部的侧壁；
形成覆盖所述第二子有源柱中部的侧壁的栅极氧化层；
形成覆盖所述栅极氧化层的栅极；
在所述第二子有源柱底部和顶部分别形成源极、漏极；
在所述第二保护柱之间以及所述栅极之间形成隔离结构。
上述方案中，所述形成覆盖栅极氧化层的栅极，包括：
在所述栅极氧化层的间隙中填充栅极导电材料；
以所述第一保护层为掩膜层，去除部分所述栅极导电材料，剩余的栅极导电材料形成所述栅极。
上述方案中，在形成所述栅极氧化层之前，去除所述第二子有源柱中部的侧壁，形成具有凹部的所述第二子有源柱，以及与所述凹部对应的凹陷空间；在所述凹陷空间中，至少形成环绕所述凹部的栅极氧化层。
附图说明
图1为本公开实施例中提供的一种DRAM晶体管的电路连接示意图；
图2为本公开实施例提供的半导体结构的制作方法的流程示意图；
图3至图31为本公开实施例提供的一种半导体结构的制作过程的立体结构示意图。
在上述附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本 公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、硅锗、锗、砷化嫁、磷化锢等。替代地，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本公开实施例涉及的半导体结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里，所述最终的器件可以包括存储器，所述存储器包括但不限于动态随机存取存储器，以下仅以动态随机存取存储器为例进行说明。
但需要说明的是，以下实施例关于动态随机存取存储器的描述仅用来说明本公开，并不用来限制本公开的范围。
随着动态随机存取存储器技术的发展，存储单元的尺寸越来越小，其阵列架构由8F 2到6F 2再到4F 2；另外，基于动态随机存取存储器中对离子和漏电流的需求，存储器的架构从平面阵列晶体管(Planar Array Transistor)到凹栅阵列晶体管(Recess Gate Array Transistor)，又从凹栅阵列晶体管到掩埋式沟道阵列晶体管(Buried Channel Array Transistor)，再从掩埋式沟道阵列晶体管到垂直沟道阵列晶体管(Vertical Channel Array Transistor)。
本公开的一些实施例中，不论是平面晶体管还是掩埋式晶体管，动态随机存取存储器均由多个存储单元结构构成，每一个存储单元结构主要是由一个晶体管与一个由晶体管所操控的存储单元(存储电容)构成，即动态随机存取存储器包括1个晶体管(T，Transistor)和1个电容(C，Capacitor)(1T1C)的架构；其主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特是l还是0。
图1为本公开实施例中提供的一种采用1T1C的架构的控制电路示意图；如图1所示，晶体管T的漏极与位线(BL，Bit Line)电连接，晶体管T的源区与电容C的其中一个电极板电连接，电容C的另外一个电极板可以连接参考电压，所述参考电压可以是地电压也可以是其他电压，晶体管T的栅极与字线(WL，Word Line)连接；通过字线WL施加电压控制晶体管T导通或截止，位线BL配置为在晶体管T导通时，对所述晶体管T执行读取或写入操作。
然而，为了实现存储器的小型化发展，动态随机存取存储器的尺寸在不断缩小，存储单元中电容与晶体管之间的电阻越来越大，影响存储单元的信号传输；同时，电容的尺寸也随之缩小，进而使得形成电容与晶体管对准的工艺难度越来越大。
基于此，为解决上述问题中的一个或多个，本公开实施例提供了一种半导体结构的制作方法。图2为本公开实施例提供的半导体结构的制作方法的流程示意图。如图2所示，本公开实施例提供的半导体结构的制作方法包括以下步骤：
S201、提供衬底，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个有源柱；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；
S202、在所述第一子有源柱中增加第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；
S203、至少在所述第一子有源柱的侧壁形成存储结构；
S204、形成多个晶体管，所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。
应当理解，图2中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图2中所示的各步骤可以根据实际需求进行顺序调整。
这里及下文中，第一方向和第二方向表示为与衬底的顶面平行的两个正交方向；第三方向为垂直于衬底的顶面的方向，也就是第三方向为所述有源柱的延伸方向；其中，所述衬底的顶面可以理解为与所述有源柱的延伸方向垂直的平面。
在一些实施例中，所述第一方向与所述第二方向之间的夹角范围为0-90度。在一些具体实施例中，所述第一方向可以垂直于所述第二方向。可以理解的是，所述第一方向与所述第二方向之间的夹角构建了所述半导体柱的沿所述第一方向与所述第二方向的阵列排布的位置关系。
示例性地，第一方向表示为附图中的X方向；第二方向表示为附图中的Y方向；第三方向表示为附图中的Z方向。
图3至图31为本公开实施例提供的一种半导体结构的制作过程的立体结构示意图。下面结合图2、图3至图31，对本公开实施例提供的半导体结构的制作方法进行详细地说明。
执行步骤S201，参考图3至图14，形成多个有源柱。
在一些实施例中，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个有源柱，包括以下步骤：
a、在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个半导体柱；每一所述半导体柱包括第一部分、位于所述第一部分上的第二部分、以及位于所述第二部分上的第三部分；
b、形成覆盖所述第三部分的顶面的支撑层；
c、形成至少覆盖所述第三部分的侧壁的第二保护层；
d、对所述半导体柱进行氧化处理，以使所述第一部分被完全氧化成氧化柱，且所述第二部分的表面被氧化成氧化层；
e、去除所述第二部分的表面的氧化层，得到所述第一子有源柱；
f、在形成所述存储结构之后，去除所述支撑层以及所述第二保护层，得到所述第二子有源柱。
执行步骤a，参考图3至图6，形成多个半导体柱。
在一些实施例中，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个半导体柱，包括：
提供半导体基底；
在所述基底中形成多条沿第一方向间隔排布的第一沟槽，以及多条沿第二方向间隔排布的第二沟槽；
对每一所述第一沟槽和/或所述第二沟槽底部进行扩大处理，形成所述多个半导体柱。
参考图3，所述半导体基底100的材料可以包括硅(Si)、锗(Ge)、锗化硅(SiGe)等。
参考图3，通过光刻-蚀刻工艺(LE，Lithography-Etch)对所述半导体基底100的顶面进行第一刻蚀，在所述半导体基底中形成多个沿第一方向间隔排布的第一沟槽T1；这里，每一所述第一沟槽T1沿第二方向延伸。所述第一沟槽T1将所述半导体基底100划分为多个半导体条102。
这里，所述第一沟槽T1位于半导体基底中，也就是说，第一沟槽T1沿第三方向上的深度小于所述半导体基底100沿第三方向上的厚度。
所述第一刻蚀包括但不限于干法等离子体刻蚀工艺。
在一些实施例中，所述第一沟槽T1包括但不限于浅槽隔离(STI，Shallow Trench Isolation)结构。
参考图4，在所述第一沟槽T1中形成第一绝缘材料201；其中，所述第一绝缘材料201的顶面与所述半导体基底100的顶面基本齐平；这里，所述第一绝缘材料201配置为起支撑作用。
在一些实施例中，所述第一绝缘材料201的组成材料包括但不限于氧化硅(SiO 2)。
形成所述第一绝缘材料201的方法包括但不限于物理气相沉积(PVD，Physical Vapor Deposition)工艺、化学气相沉积(CVD，Chemical Vapor Deposition)工艺、原子层沉积(ALD，Atomic Layer Deposition)等工艺。
在一些实施例中，所述第一沟槽T1包括但不限于浅槽隔离(STI，Shallow Trench Isolation)结构。
参考图5，通过光刻-蚀刻工艺，对所述半导体基底100的顶面进行第二刻蚀，在所述半导体基底100中形成多个沿第二方向间隔排布的第二沟槽T2；这里，每一所述第二沟槽T2沿第一方向延伸。所述第二沟槽T2将每个所述半导体条102分为多个半导体柱103。
这里，所述第二沟槽T2位于半导体基底中，也就是说，第二沟槽T2沿第三方向上的深度小于所述半导体基底100沿第三方向上的厚度。
所述第二刻蚀包括但不限于干法等离子体刻蚀工艺。
在一些实施例中，所述第二沟槽T2包括但不限于浅槽隔离结构。
继续参考图5，对每一所述第二沟槽T3底部进行扩大处理；这里，所述扩大处理可以理解为对对第二沟槽T2的底部进行沿第二方向的刻蚀，使得第二沟槽T2的底部沿所述第二方向的径宽大于相应沟槽的顶部沿所述第二方向的径宽。
这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性地，所述湿法刻蚀工艺中，将刻蚀剂通入第二沟槽T2的底部，通过刻蚀剂的各向异性刻蚀，增大第二沟槽T2的底部沿Y轴方向的径宽。
示例性地，所述干法刻蚀工艺中，通过控制等离子体进行横向刻蚀，以在第二沟槽T2的底部形成径宽扩大的沟槽结构。
实际应用中，也可以在形成第一沟槽T1的过程中对每一所述第一沟槽T1底部进行扩大处理；这里，以对每一所述第二沟槽T2底部进行扩大处理作为示例。
在一些实施例中，对每一所述第一沟槽和/或所述第二沟槽底部进行扩大处理采用包括但不限于BOSCH蚀刻工艺。
示例性地，继续参考图5，先用正常蚀刻工艺形成沿第三方向上的宽度一致的沟槽，例如采用浅槽隔离工艺形成第二沟槽(此时的沟槽形态可以参照图3中第一沟槽的形态进行理解)，再利用所述BOSCH蚀刻工艺对第二沟槽底部进行扩大处理，形成如图5所示的底部被扩大的第三沟槽。
实际应用中，所述第二沟槽T2沿第三方向上的深度与所述第一沟槽T1沿第三方向上的深度可以相同，也可以不同。示例性地，所述第二沟槽T2沿第三方向上的深度与所述第一沟槽T1沿第三方向上的深度基本相同。这样，可以减少制造过程中对工艺参数的调整，降低工艺难度。
本公开实施例中，在对每一所述第一沟槽T1和/或所述第二沟槽T2底部进行扩大处理的过程后，刻蚀工艺使得位于衬底101上的多个立方体柱的底部区域被刻蚀，立方体柱的底部区域尺寸减小，进而形成所述有源柱103，参考图5。
需要说明的是，这里，每一所述半导体柱103仍然为一个整体，包括第一部分1031、位于所述第一部分上的第二部分1032、以及位于所述第二部分上的第三部分1033。每一所述半导体柱103中的第一部分1031、第二部分1032、第三部分1033仅配置为沿所述半导体柱103延伸方向上对所述半导体柱103进行区域上的划分，而并不意味着第一部分1031、第二部分1032、第三部分1033可以分开或有明显堆叠界面的不同结构。
在一些实施例中，所述第一部分1031沿所述第一方向的最大径宽小于所述第二部分1032沿所述第一方向的最小径宽；和/或，所述第一部分1031沿所述第二方向的最大径宽小于所述第二部分1032沿所述第二方向的最小径宽。
示例性地，在对第二沟槽T2进行扩大处理时，所述半导体柱的第一部分1031沿Y轴方向的最大径宽小于所述半导体柱的第二部分1032沿Y轴方向的最小径宽。
本公开实施例中，通过形成底部径宽较小的所述半导体柱，利于后续工艺制程中将将所述多个半导体柱氧化形成有源柱，以在每一有源柱与衬底之间设置相应的氧化柱，使得在有源柱的部分侧壁上形成的存储结构(如，电容)能够被隔离，进而减少存储结构(如，电容)在使用的过程中漏电问题的存在。
参考图6，在所述第二沟槽中形成第一绝缘材料201；其中，所述第一绝缘材料201的顶面与所述半导体基底100的顶面基本齐平。
在一些实施例中，所述第一绝缘材料201的组成材料包括但不限于氧化硅(SiO 2)。
形成所述第一绝缘材料201的方法包括但不限于PVD、CVD等工艺。
以及，在所述第二沟槽T2中填充满第一绝缘材料201之后，对所述第一绝缘材料201和所述半导体柱103的顶面进行化学机械抛光(CMP，Chemical Mechanical Polishing)处理，使得所述第一绝缘材料201和所述半导体柱103的顶面平齐。
执行步骤b，参考图7至图11，形成支撑层。
在一些实施例中，所述形成支撑层，包括：
在多个所述半导体柱之间填充满所述第一绝缘材料，得到第一绝缘层；
沉积第二绝缘材料，所述第二绝缘材料覆盖所述第一绝缘层和所述半导体柱的顶面，得到所述第二绝缘层；
沿所述第二方向去除部分所述第二绝缘层形成第一浅沟槽，所述第一浅沟槽的底面与所述半导体柱的顶面齐平，在所述第一浅沟槽内填充所述第一绝缘材料；
沿所述第一方向去除部分所述第二绝缘层形成第二浅沟槽，所述第二浅沟槽的底面与所述半导体柱的顶面齐平，且暴露出所述半导体柱的顶面；在所述第二浅沟槽内填充所述第二绝缘材料；
未被去除的所述第二绝缘层和所述第二浅沟槽内填充所述第二绝缘材料构成所述支撑层。
参考图7，多个所述半导体柱103之间已填充满所述第一绝缘材料201(参考图6)，得到第一绝缘层211。
继续参考图7，沉积第二绝缘材料，所述第二绝缘材料覆盖所述第一绝缘层211和所述半导体柱103的顶面，得到所述第二绝缘层212。
这里，形成所述第二绝缘层212的方法包括但不限于PVD、CVD等工艺。
这里，所述第二绝缘层212的材料与第一绝缘层211的材料可以不同。示例性地，所述第二绝缘层212的组成材料包括但不限于氮化硅或碳；所述第一绝缘层211的组成材料包括但不限于氧化硅。
参考图8，通过光刻-蚀刻工艺沿所述第二方向去除部分所述第二绝缘层212形成第一浅沟槽ST1，所述第一浅沟槽ST1的底面与所述半导体柱103的顶面齐平。
这里，所述第一浅沟槽ST1并不暴露出所述半导体柱103的顶面。
参考图9，通过包括但不限于PVD、CVD等工艺在所述第一浅沟槽ST1内填充所述第一绝缘材料201。
这里，第一绝缘材料201与所述第一绝缘层211的材料相同。示例性地，第一绝缘材料201的组成材料包括但不限于氧化硅。
参考图10，通过光刻-蚀刻工艺沿所述第一方向去除部分所述第二绝缘层212、部分所述第一绝缘材料201，形成第二浅沟槽ST2，所述第二浅沟槽ST2的底面与所述半导体柱103的顶面齐平。
这里，所述第二浅沟槽ST2暴露出所述半导体柱103的顶面。
参考图11，通过包括但不限于PVD、CVD等工艺在所述第二浅沟槽ST2内填充所述第二绝缘材料202。未被去除的所述第二绝缘层212和所述第二浅沟槽内填充所述第二绝缘材料202构成所述支撑层2121。
这里，第二绝缘材料202与所述第二绝缘层212的材料相同，且与所述第一绝缘材料201的材料不相同。所述第二绝缘材料202的组成材料包括但不限于氮化硅或碳；所述第一绝缘材料201的组成材料包括但不限于氧化硅。
这样，所述支撑层2121配置为保护所述有源柱103的顶面；同时，覆盖所述有源柱103的 顶面的所述支撑层2121为一体的形成网状结构，利于对所述半导体柱103进行有效的支撑。也就是说，所述支撑层2121既保护所述有源柱103的顶面，又能支撑所述阵列排布的多个所述半导体柱103，以利于形成稳定的半导体结构。
执行步骤c，参考图12至图14，形成第二保护层。
在一些实施例中，所述形成第二保护层，包括：
去除部分所述第一绝缘材料，形成第三浅沟槽；所述第三浅沟槽的底面与所述第三部分的底面齐平，暴露出所述第三部分的侧壁；
沉积牺牲材料，所述牺牲材料至少覆盖所述第三部分的侧壁，得到所述第二保护层。
参考图12，采用蚀刻工艺去除部分所述第一绝缘材料201，形成第三浅沟槽ST3；所述第三浅沟槽ST3的底面与所述第三部分1033的底面齐平，暴露出所述第三部分1033的侧壁。
这里，所采用的刻蚀工艺可以包括干法刻蚀工艺等。
示例性地，所述干法刻蚀工艺中，以支撑层2121为掩膜，沿Z轴方向蚀刻所述支撑层2121的网格间的第一绝缘材料201(参考图11)，以及所述第三部分1033之间的第一绝缘材料201(参考图11)，形成第三浅沟槽ST3。
参考图13，通过包括但不限于PVD、CVD等工艺，在第三浅沟槽ST3中沉积牺牲材料203，所述牺牲材料203覆盖所述第三浅沟槽ST3的侧壁、底面以及所述支撑层2121暴露的底面。
这里，牺牲材料203的材料与第一绝缘材料201的材料不同。示例性地，所述牺牲材料203的组成材料包括但不限于氮化硅或碳；所述第一绝缘层211的组成材料包括但不限于氧化硅。
参考图14，采用蚀刻工艺去除覆盖所述第三浅沟槽ST3底面的牺牲材料203(参考图13)，保留至少覆盖所述第三部分1033的侧壁的牺牲材料，得到所述第二保护层213。
这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性地，所述干法刻蚀工艺中，通过控制等离子体进行纵向刻蚀，去除覆盖所述第三浅沟槽ST3底面的牺牲材料203，而至少保留覆盖所述第三部分1033的侧壁的牺牲材料203。
这样，所述第二保护层覆盖所述第三部分1033的侧壁，可以减少后续制造过程中对所述第三部分1033造成的不必要的污染。需要说明的是，所述第三部分1033在后续工艺中配置为形成晶体管的沟道结构，可以理解的是沟道结构对于半导体结构的性能的影响至关重要，通过所述第二保护层覆盖所述第三部分1033的侧壁，以及所述支撑层2121覆盖所述第三部分1033的顶面，避免对后续工艺所述第三部分1033的污染，避免晶体管的沟道结构造成不必要的缺陷。
执行步骤d和e，参考图15至图18，形成第一子有源柱。
参考图15，采用蚀刻工艺去除覆盖所述有源柱103之间剩余的第一绝缘材料201(参考图14)，暴露出所述一部分1031的侧壁、所述第二部分1032的侧壁、以及部分所述衬底101的顶面。
这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
参考图16，对所述半导体柱103(参考图15)进行氧化处理，以使所述第一部分1031(参考图15)被完全氧化成氧化柱104，且所述第二部分1032(参考图15)的表面被氧化成氧化层106。
示例性地，通过氧化工艺对所述半导体柱103进行氧化，使得第一部分1031全部被氧化成氧化柱104，以及暴露出的半导体柱的第二部分1032的表面被氧化成氧化层106，同时，衬底101的顶面也被氧化形成一层衬底氧化层105。
这里，氧化柱104和氧化层106的材料相同。示例性地，氧化柱104和所述氧化层106的组成材料包括但不限于氧化硅。
这里，需要说明的是，前述通过对第二沟槽T2进行扩大处理后，半导体柱103底部与衬底101之间的过渡部分也就是第一部分1031的尺寸较小，易于被完全氧化。与此同时，所述第二部分1032尺寸较小相对较大，仅表面被氧化。
对所述半导体柱103进行氧化处理后，所述第三部分1033(参考图15)和第二部分1032未被氧化的部分，也就是有源柱401与衬底101之间被所述氧化柱104电隔离；防止所述有源柱401与衬底101之间的漏电缺陷。
这里及以下，每一所述有源柱401仍然为一个整体，包括第一子有源柱402、位于所述第 一子有源柱402上第二子有源柱403；每一所述有源柱401中的第一子有源柱402、第二子有源柱403仅配置为沿所述有源柱401延伸方向上对所述有源柱401进行区域上的划分，而并不意味着第一子有源柱402、第二子有源柱403可以分开或有明显堆叠界面的不同结构。
可以理解的是，对所述半导体柱103进行氧化处理后形成有源柱401的时候，已经同步形成了所述第一子有源柱402和所述第二子有源柱403。
这里及以下，每一所述第二子有源柱403仍然为一个整体。所述第二子有源柱403包括第二子有源柱底部4033、位于所述第二子有源柱底部4033上的第二子有源柱中部4032、以及位于所述第二子有源柱中部4032上的第二子有源柱顶部4031；每一所述第二子有源柱403中的第二子有源柱底部4033、第二子有源柱中部4032、第二子有源柱顶部4031仅配置为沿所述第二子有源柱403延伸方向上对所述第二子有源柱403进行区域上的划分，而并不意味着第二子有源柱底部4033、第二子有源柱中部4032、第二子有源柱顶部4031可以分开或有明显堆叠界面的不同结构。
参考图17，在所述氧化层和所述氧化柱的间隙中填充所述第一绝缘材料201，以及在所述第二保护层213的间隙中和所述支撑层2121的网格状间隙中填充所述第一绝缘材料201。
这里，填充第一绝缘材料201的方法包括但不限于PVD、CVD等工艺。
第一绝缘材料201与氧化柱104(参考图16)、氧化层106(参考图16)的材料可以相同或者不同。示例性地，第一绝缘材料201的组成材料包括但不限于氧化硅。示例性地，第一绝缘材料201、氧化柱104、氧化层106的组成材料可以相同，这里，均以第一绝缘材料201示出。
实际应用中，可以在多个氧化柱104之间，在多个所述有源柱401之间，在所述支撑层2121的网格状间隙中，填充第一绝缘材料201，使得第一绝缘材料201与所述支撑层2121的顶面齐平。
参考图18，采用蚀刻工艺去除在所述支撑层2121的网格状间隙中、在所述第二保护层213的间隙的所述第一绝缘材料201，以及去除在所述第一子有源柱402之间的所述第一绝缘材料201，暴露出所述第一子有源柱402的侧壁；同时，保留在所述衬底101上未被去除的所述第一绝缘材料成为所述隔离结构107。
在一些具体的实施例中，所述第一子有源柱402可以深入所述隔离结构107中，且沿所述第一子有源柱402延伸方向并贯穿所述隔离结构107。所述第一子有源柱402的底部具有深入所述隔离结构107中的部分，所述隔离结构107可以为所述第一子有源柱402提供稳固的支撑。这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
结合图16和图18，在多个氧化柱104之间的第一绝缘材料201与加上氧化柱104、衬底氧化层105一起就构成了在衬底101上的隔离结构107。
示例性地，隔离结构107的组成材料包括但不限于氧化硅。隔离结构107可以改善隔离结构107之上的功能器件(例如所述第一子有源柱402、下文图21所述的存储结构315)与衬底101之间的漏电问题。
执行步骤f，参考图20至图21，形成第二子有源柱。
参考图20至图21，在形成所述存储结构315之后，去除所述支撑层2121以及所述第二保护层213，得到所述第二子有源柱403。
实际应用中，参考图20，在所述第二子有源柱403之间的间隙中填充介质层均需要被去除，仅保留所述第二子有源柱403。
示例性地，在所述第二子有源柱403之间的间隙中填充有所述支撑层2121，以及在形成所述存储结构315的过程中，填充于所述支撑层2121之间的部分第一电极层3151、介质层3152、第二电极层3153，均需要被去除。
这里，采用蚀刻工艺去除覆盖所述支撑层2121；去除填充于所述支撑层2121之间的部分第一电极层3151、介质层3152、第二电极层3153，保留至少覆盖所述第一子有源柱402的侧壁的存储结构315；去除覆盖在所述第二子有源柱403的侧壁的所述第二保护层213。
这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性地，所述干法刻蚀工艺中，通过控制等离子体进行纵向刻蚀，去除在所述第二子有源柱403之间的间隙中填充介质层，形成所述第二子有源柱403，且暴露出所述第二子有源柱 403的侧壁和顶面。
可以理解的是，在形成有源柱401(参考上述图16)的时候已经同步形成了第一子有源柱402和第二子有源柱403；这里，只是将所述第二子有源柱403之间的间隙中填充介质层均需要被去除(参考上述图20至图21)，暴露出所述第二子有源柱403的侧壁和顶面，以便于后续工艺制程的在所述第二子有源柱403内形成晶体管400的沟道结构CH、源极S、漏极D，以及围绕所述第二子有源柱403形成栅极405、栅极氧化层404(参考下述图31)。
本公开实施例中通过在衬底上形成多个有源柱，每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱。在后续工艺制程的在第一子有源柱侧壁形成存储单元，以及在所述第二子有源柱内形成晶体管的沟道结构、源极、漏极和围绕所述第二子有源柱形成栅极、栅极氧化层。也就是说，存储结构和晶体管在同一有源柱上形成可以降低存储单元与晶体管对准的难度，从而减少工艺难度。
执行步骤S202，继续参考图18，在所述第一子有源柱中增加第一元素。
在一些实施例中，
所述第一元素包括N型或P型掺杂元素，在所述第一子有源柱中增加第一元素，包括：通过扩散或者离子注入工艺在所述第一子有源柱中增加N型或P型掺杂元素；
或者，
所述第一元素包括金属元素，在所述第一子有源柱中增加第一元素，包括：形成覆盖所述第一子有源柱的侧壁的含有所述金属元素的金属层；采用快速热退火工艺，使得所述金属层和所述第一子有源柱反应形成金属化合物。
继续参考图18，在一些实施例中，所述第一元素可以包括N型或P型掺杂元素，采用气相扩散的工艺，将所述第一掺杂元素从所述第一子有源柱402的侧壁掺入所述第一子有源柱402中。
这里，所述N型掺杂元素可以包括氮(N)元素、磷(P)元素、砷(As)元素、锑(Sb)元素等中的至少之一；所述P型掺杂元素可以包括硼(B)元素、镓(Ga)元素、铟(In)元素等中的至少之一。
示例性地，所述第一元素包括磷元素，采用气相扩散的工艺，在800℃-1200℃温度下，通入含有磷元素的气体，所述气体与所述第一子有源柱402的侧壁接触，首先在所述第一子有源柱402的侧壁表面形成含有磷元素的薄层介质，在800℃-1200℃温度下，所述薄层介质中的磷元素扩散至所述第一子有源柱402的内部，在所述第一子有源柱402中增加磷元素；增加有磷元素所述第一子有源柱402相对于未具有磷元素所述第一子有源柱402具有较低的电阻率。
实际应用，还可以根据不同导电类型的晶体管(参考下文图31中的晶体管400)，确定所述第一元素包括N型或P型掺杂元素。示例性地，例如所述晶体管结构为N型晶体管时，则所述第一元素为N型掺杂元素，所述N型掺杂元素例如为磷元素、砷元素、锑元素；所述晶体管结构为P型晶体管时，则所述第一元素为P型掺杂元素，所述P型掺杂元素例如为硼元素、镓元素、铟元素。
继续参考图18，在另一些实施例中，所述第一元素可以包括金属元素，采用薄膜沉积工艺形成覆盖所述第一子有源柱402的侧壁的含有所述金属元素的金属层，采用退火工艺，如快速热退火工艺(RTP，Rapid Thermal Processing)，使得所述金属层和所述第一子有源柱402反应形成金属化合物。
这里，所述金属元素的组成材料包括钴(Co)、镍(Ni)、钨(W)、钛(Ti)、钽(Ta)、铜(Cu)、铝(Al)、银(Ag)和金(Au)等中的至少之一。
示例性地，所述第一元素包括钴元素，采用薄膜沉积工艺形成覆盖所述第一子有源柱402的侧壁的含有钴元素的金属层，采用快速热退火工艺，使得所述含有钴元素的金属层和所述第一子有源柱402反应形成钴的化物。在所述第一子有源柱402中增加钴元素，形成了钴的化物，增加有钴元素所述第一子有源柱402相对于未具有钴元素所述第一子有源柱402具有较低的电阻率。
实际应用中，可以根据实际需要，通过调整薄膜沉积工艺和/或快速热退火工艺参数，可以调控所述金属层与所述第一子有源柱的反应程度，可以控制形成的所述金属化合物的形态。例 如，所述金属层可以仅与所述第一子有源柱的表面反应，所述第一子有源柱的表面层形成为所述金属化合物；所述金属层还可以与所述第一子有源柱完全反应，整个所述第一子有源柱均形成为所述金属化合物。
本公开实施例中利用在所述第一子有源柱中增加第一元素来降低第一子有源柱的电阻率，从而减小第一子有源柱与存储结构之间的电阻，进而减少信号传输的延迟，最终提高半导体结构的性能。
执行步骤S203，参考图19至图20，形成存储结构。
在一些实施例中，所述至少在所述第一子有源柱的侧壁形成存储结构，包括：
形成覆盖所述第一子有源柱侧壁的第一导电层；
形成至少覆盖所述第一导电层的侧壁的介质层；
在所述介质层的间隙中形成第二导电层。
参考图19，形成覆盖所述第一子有源柱402侧壁的第一导电层3151；
这里，第一导电层配置为电容的下电极；介质层配置为电容的电介质；第二导电层配置为电容的上电极。
在一些具体实施例中，所述第一导电层3151的组成材料可以包括但不限于钌(Ru)、氧化钌(RuO)、氮化钛(TiN)。
本公开实施例中，可以通过选择性沉积工艺在所述第一子有源柱的侧壁形成第一导电层，还可以通过其他沉积工艺形成。
所述选择性沉积工艺是指有选择性地将第一导电层沉积在第一子有源柱的侧壁。这里，所述其他沉积工艺包括但不限于PVD、CVD、ALD等工艺。
在一些具体实施例中，所述形成覆盖所述第一子有源柱402侧壁的第一导电层3151，包括：
通过选择性沉积工艺，形成覆盖所述第一子有源柱402侧壁的第一导电层3151。
参考图20，形成至少覆盖所述第一导电层3151的侧壁的介质层3152；在所述介质层3152的间隙中形成第二导电层3153。
所述介质层的组成材料包括高介电常数(High-K)材料，高介电常数材料一般指介电常数高于3.9的材料，且通常显著高于该值。在一些具体示例中，所述介质层的材料可以包括但不限于氧化铝(Al 2O 3)、氧化锆(ZrO)、氧化铪(HfO 2)、钛酸锶(SrTiO 3)等。
在一些具体实施例中，所述第二导电层的组成材料可以包括但不限于钌、氧化钌、氮化钛。
这里，形成第二导电层的方法包括但不限于PVD、CVD等工艺。
需要说明的是，上述实施例中形成第一导电层和第二电极层的方法也可以理解为采用选择性沉积工艺形成导电层对导电层(CoC，Conductive on Conductive)；这里，选择性沉积工艺包括但不限于ALD工艺等。
本公开实施例中，通过选择性沉积工艺形成第一导电层的过程中，可以使得配置为形成第一导电层的材料仅在所述第一子有源柱的侧壁，或形成在其他被选择的材料上，而不形成在所述隔离结构的顶面。这样，一方面保证了第一电极层之间的相互隔离，避免了第一电极层之间的相互干扰；另一方面，还可以避免采用其他工艺形成第一导电层的过程中出现的空洞问题，进而提高了半导体结构的可靠性。
执行步骤S204，参考图22至图31，形成多个晶体管。
在一些实施例中，形成所述存储结构之后，所述方法还包括：形成围绕所述第二子有源柱顶部侧壁的第一保护层；
所述形成第一保护层，包括：
在所述第二子有源柱之间形成第一绝缘材料；
去除所述第二子有源柱顶部的部分第一绝缘材料，形成多个第一凹槽，每个所述第一凹槽暴露出在第一方向上相邻的两个所述第二子有源柱顶部相对的两个侧壁；
填充所述第一凹槽形成多个第一保护柱；
去除所述第二子有源柱顶部剩余的所述第一绝缘材料，形成多个沿所述第一方向延伸的第二凹槽；
在所述第二凹槽的侧壁形成多个第二保护柱，所述第一保护柱与所述第二保护柱共同构成 所述第一保护层。
参考图22，在所述第二子有源柱403之间形成第一绝缘材料201；其中，所述第一绝缘材料201的顶面与所述第二子有源柱403的顶面齐平。
以及，对所述第一绝缘材料201和所述第二子有源柱403的顶面进行抛光处理，使得所述第一绝缘材料201和所述半导体柱103的顶面平齐。
这里，所述第一绝缘材料201的组成材料包括但不限于氧化硅。
形成所述第一绝缘材料201的方法包括但不限于PVD、CVD、ALD等工艺。
参考图23，通过光刻-蚀刻工艺去除所述第二子有源柱顶部4031的部分第一绝缘材料，形成多个沿所述第一方向和所述第二方向阵列排布的第一凹槽R1，每个所述第一凹槽R1暴露出在第一方向上相邻的两个所述第二子有源柱顶部4031相对的两个侧壁，且每个所述第一凹槽R1的底面与所述第二子有源柱顶部4031的底面基本齐平。也就是说，所述第一凹槽R1沿第三方向上的深度与所述第二子有源柱顶部4031沿第三方向上的厚度基本相当。
所述第一刻蚀包括但不限于干法等离子体刻蚀工艺。
参考图24，在所述第一凹槽R1中填充第二绝缘材料，形成多个第一保护柱2211；其中，所述第一保护柱2211的顶面与所述第二子有源柱顶部4031的顶面基本齐平；这里，所述第一保护柱2211配置为保护所述第二子有源柱顶部4031的侧壁。
这里，形成所述第一保护柱2211的材料的方法包括但不限于PVD、CVD等工艺。
这里，所述第一保护柱2211的组成材料与所述第一绝缘材料201的组成材料可以不同。示例性地，所述第一保护柱2211的组成材料包括但不限于氮化硅或碳；所述第一绝缘材料201的组成材料包括但不限于氧化硅。
在一些实施例中，形成所述第一保护柱2211采用包括但不限于浅槽隔离工艺。
参考图25，通过蚀刻工艺去除所述第二子有源柱顶部4031剩余的所述第一绝缘材料201，形成多个沿所述第一方向延伸的第二凹槽R2，每个所述第二凹槽R2至少暴露出未被所述第一保护柱2211覆盖的所述第二子有源柱顶部4031的其他侧壁(可以理解为在第二方向上相邻的两个所述第二子有源柱顶部4031相对的两个侧壁)，且每个所述第二凹槽R2的底面与所述第二子有源柱顶部4031的底面基本齐平。也就是说，所述第二凹槽R2沿第三方向上的深度与所述第二子有源柱顶部4031沿第三方向上的厚度基本相当。
所述第一刻蚀包括但不限于干法等离子体刻蚀工艺。
参考图26，通过侧墙(spacer)工艺形成的所述第二保护柱2212。
通过包括但不限于PVD、CVD等工艺在所述第二凹槽R2的侧壁和底面沉积第二绝缘材料，同时在所述第一保护柱2211顶面、所述第二子有源柱顶部4031的顶面沉积第二绝缘材料。
采用蚀刻工艺去除在所述第二凹槽R2的底面的第二绝缘材料，同时去除在所述第一保护柱2211顶面、所述第二子有源柱顶部4031的顶面的第二绝缘材料，保留在所述第二凹槽的侧壁的第二绝缘材料，形成多个第二保护柱2212。每个所述第二保护柱2212沿第一方向延伸，配置为保护所述第二子有源柱顶部4031的侧壁。这里，所述第一保护柱2211与所述第二保护柱2212共同构成所述第一保护层221，所述第一保护层221环绕于所述第二子有源柱顶部4031，保护所述第二子有源柱顶部4031的所有侧壁。
这里，所述第二保护柱2212的组成材料与所述第一绝缘材料201的组成材料可以不同。示例性地，所述第二保护柱2212的组成材料包括但不限于氮化硅或碳；所述第一绝缘材料201的组成材料包括但不限于氧化硅。
在一些实施例中，形成所述第二保护柱2212采用包括干法刻蚀工艺等。
示例性地，所述干法刻蚀工艺中，通过控制等离子体进行纵向刻蚀，去除在所述第二凹槽R2的底面的第二绝缘材料，同时去除在所述第一保护柱2211顶面、所述第二子有源柱顶部4031的顶面的第二绝缘材料，保留在所述第二凹槽的侧壁的第二绝缘材料，形成所述第二保护柱2212。
本公开实施例中，通过侧墙工艺形成的所述第二保护柱2212，保护所述第二子有源柱顶部4031的侧壁的同时，还可以作为掩膜配置为形成栅极405(参考下文图30)。通过侧墙工艺形成的所述第二保护柱2212作为掩膜，可以在现有的光刻工艺的基础上，具有进一步微缩掩膜的 尺寸，用以形成更小尺寸的半导体结构。以所述第一保护层为掩膜，能够减少一个光刻工艺步骤，从而减少工艺成本、难度。由于通过侧墙工艺形成的所述第二保护柱，是基于所述第二子有源柱而自对准形成的，能提高后续工艺制程中形成的栅极(参考下文图30)的对准的精度、工艺窗口。
在一些实施例中，所述形成晶体管，包括：
在形成所述第一保护层之后，去除所述第二子有源柱中部对应的第一绝缘材料，暴露出所述第二子有源柱中部的侧壁；
形成覆盖所述第二子有源柱中部的侧壁的栅极氧化层；
形成覆盖所述栅极氧化层的栅极；
在所述第二子有源柱底部和顶部分别形成源极、漏极；
在所述第二保护柱之间以及所述栅极之间形成隔离结构。
参考图27，在形成所述第一保护层221之后，在所述第一保护层221保护所述第二子有源柱顶部4031的所有侧壁的情况下，去除所述第二子有源柱中部4032对应的第一绝缘材料201，暴露出所述第二子有源柱中部4032的侧壁；且这里未被去除的第一绝缘材料201的顶面与所述第二子有源柱中部4032的底面基本齐平，也就是说，未被去除的第一绝缘材料201沿第三方向上的深度与所述第二子有源柱底部4033沿第三方向上的厚度基本相当。
这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性地，采用湿法刻蚀工艺，各向同性的去除去除所述第二子有源柱中部4032之间的第一绝缘材料，暴露出所述第二子有源柱中部4032的侧壁；且未被去除的第一绝缘材料201覆盖所述第二子有源柱底部4033的侧壁。
参考图29，形成覆盖所述第二子有源柱中部4032的侧壁的栅极氧化层404。
可以通过原位氧化所述第二子有源柱中部4032的侧壁方式，环绕每一所述第二子有源柱中部4032的侧壁形成所述栅极氧化层404。
还可以通过ALD工艺在环绕每一所述第二子有源柱中部4032的侧壁沉积栅极氧化层404。
这里，所述栅极氧化层404的材料包括但不限于氧化硅。
参考图30，形成覆盖所述栅极氧化层的栅极405。
在一些实施例中，所述形成覆盖栅极氧化层404的栅极405，包括：
在所述栅极氧化层404的间隙中填充栅极导电材料；
以所述第一保护层221为掩膜层，去除部分所述栅极导电材料，剩余的栅极导电材料形成所述栅极405。
通过电化学电镀(ECP，Electro-Chemical Plating)、PVD、CVD等工艺在所述栅极氧化层404的间隙中填充栅极导电材料。实际应用中，所述栅极导电材料还可以填充于所述第一保护层221之间的间隙，所述栅极导电材料的顶面与所述第二子有源柱顶部4031的顶面齐平。
这里，所述栅极导电材料的组成材料包括钴、镍、钨、氮化钨、钛、氮化钛、钽、氮化钽、铜、铝、铝铜、银和金等中的至少其中之一。
以所述第一保护层221为掩膜层，采用包括湿法蚀刻工艺、干法刻蚀工艺等，去除部分所述栅极导电材料，剩余的栅极导电材料形成多个沿第二方向排布的所述栅极405。每个所述栅极405沿第一方向延伸，将沿所述第二方向排布的每一排晶体管中每个晶体管的栅极相互物理连接；且沿所述第二方向排布的相邻的两个所述栅极405之间相互隔离。
在一些实施例中，所述栅极405远离所述栅极氧化层404的一侧与所述第二保护柱2212远离所述栅极氧化层的一侧的侧壁齐平。
示例性地，所述干法刻蚀工艺中，通过控制等离子体进行纵向刻蚀，去除部分所述栅极导电材料，形成所述栅极405。
由于以所述第一保护层221为掩膜层，沿第二方向上的所述栅极405远离所述栅极氧化层404的一侧与所述第二保护柱2212远离所述栅极氧化层404的一侧的侧壁在沿所述第二子有源柱403的延伸方向基本齐平。
本公开实施例中，由于通过侧墙工艺形成的所述第二保护柱，能在现有的光刻工艺的基础上，具有进一步微缩的尺寸，因而所述第一保护层也具有进一步微缩的尺寸，以所述第一保护 层为掩膜，形成的更小尺寸栅极和/或形成的更小的栅极之间的间距；同时，以所述第一保护层为掩膜，能够减少一个光刻工艺步骤，从而减少工艺成本、难度；再者，由于通过侧墙工艺形成的自对准的所述第二保护柱，能提高形成的栅极的对准的精度、工艺窗口。
参考图31，通过PVD、CVD等工艺至少在相邻的两个所述栅极405之间填充第一绝缘材料，形成所述栅极隔离结构406。实际应用中，还可以在所述第一保护层221之间的间隙中填充第一绝缘材料所述第一绝缘材料的顶面与所述第二子有源柱顶部4031的顶面齐平。形成的所述栅极隔离结构406将沿所述第二方向排布的相邻两排晶体管400的栅极405相互间隔。
可以理解的是，这里，每一所述第二子有源柱403仍然为一个整体，每一所述第二子有源柱403中的第二子有源柱底部4033、第二子有源柱中部4032、第二子有源柱顶部4031仅配置为沿所述第二子有源柱403延伸方向上对所述第二子有源柱403进行区域上的划分。所述第二子有源柱中部4032配置为形成所述晶体管400的沟道结构CH；所述第二子有源柱顶部4031配置为形成所述晶体管400的漏极D或源极S，所述第二子有源柱底部4033配置为形成所述晶体管的源极S或漏极D。
在一些实施例中，参考上述图28，在形成所述栅极氧化层之前，去除所述第二子有源柱中部4032的侧壁，形成具有凹部的所述第二子有源柱403，以及与所述凹部对应的凹陷空间R3；参考上述图29，在所述凹陷空间R3中，至少形成环绕所述凹部的栅极氧化层404。
这里，形成具有凹部的所述第二子有源柱403所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性地，采用湿法刻蚀工艺，各向同性的去除去除所述第二子有源柱中部4032的表层材料，形成所述凹陷空间R3。
这里，所述第二子有源柱中部4032的径宽小于所述第二子有源柱顶部4031的径宽和/或所述第二子有源柱底部4033的径宽。
本公开实施例中，通过在所述第二子有源柱中部形成具有凹部的结构，可以为后续工艺制程中环绕所述第二子有源柱中部的栅极的形成预留更多的空间，更多的空间意味着所述栅极具有更多的栅极材料而具有更低的电阻，使得栅极具有更好的电性能。
接着继续参考图30至图31，形成所述晶体管400，所述晶体管包括：环绕所述第二子有源柱设置的栅极氧化层404，环绕所述栅极氧化层404设置的栅极405，以及分别设置在所述第二有源柱403相对的两个端部的源极S和漏极D，所述栅极405远离所述栅极氧化层404的一侧与所述第二保护柱2212远离所述栅极氧化层405的一侧的侧壁齐平。
这里，不同类型的晶体管中，栅极的形状不同；示例性的，参考图31，柱型栅极晶体管中，栅极以柱状形式形成在沟道区的一侧；半环绕型栅极晶体管中，栅极半包围沟道区；全环绕型(GAA，Gate All Around)栅极晶体管中，栅极全包围沟道区。
本公开实施例中的晶体管类型可以包括上述多种类型，但不限于此。优选地，参考图31，所述晶体管的类型为全环绕型栅极晶体管400。
需要说明的是，这里的栅极结构包括栅极(G，Gate)和栅极氧化层(Gate oxide layer)；其中，栅极氧化层位于栅极与沟道区之间，配置为电隔离沟道区和栅极，减小晶体管的热载流子效应。
这里，栅极的材料可以包括金属和/或多晶硅(Poly)等。栅极氧化层的材料可以包括但不限于氧化硅。
在一些实施例中，栅极的形成方法包括但不限于PVD、CVD、ALD等。栅极氧化层的形成方法包括但不限于原位氧化。
在所述第二子有源柱相对的两端分别形成源极、漏极。
在一些具体实施例中，形成源极、漏极的方法包括但不限于离子注入工艺和扩散工艺等。
需要说明的是，位于第二子有源柱相对的两端的源极和漏极的位置可以互换；实际情况可以根据实际需求进行选择设置。
可以理解的是，上述实施例中的存储器为晶体管-电容(TOC，Transistor on Capacitor)结构，所述结构还包括：多条位线，位于所述晶体管上，与所述第二部分的顶部电接触。
因此，在一些实施例中，所述方法还包括：在晶体管上形成位线BL。
这里，所述位线BL的组成材料包括钴、镍、钨、氮化钨、钛、氮化钛、钽、氮化钽、铜、铝、铝铜、银和金等中的至少其中之一。
可以理解的是，位线BL配置为在晶体管导通时，对所述晶体管执行读取或写入操作。
这里，将位线BL设置在晶体管的上方，并将位线BL作为金属位线(Metal BL)，可以减少电阻，降低工艺难度；与存储器的电路设计方案更匹配。
本公开提出的上述各个实施例中，通过在衬底上形成多个有源柱，每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱，在所述第一子有源柱中增加第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率，再在所述第一子有源柱的侧壁的形成存储结构；以及形成位于所述第二子有源柱内的所述晶体管的沟道结构。本公开实施例中利用在所述第一子有源柱中增加第一元素来降低第一子有源柱的电阻率，从而减小第一子有源柱与存储结构之间的电阻，进而减少信号传输的延迟，最终提高半导体结构的性能。此外，存储结构和晶体管在同一有源柱上形成可以降低存储单元与晶体管对准的难度，从而减少工艺难度。
根据本公开的又一方面，本公开实施例提供的半导体结构，包括：衬底、位于所述衬底上方的多个有源柱、存储结构、多个晶体管；
所述多个有源柱沿第一方向和第二方向呈阵列排布；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；所述第一子有源柱的材料包含第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；
所述存储结构，覆盖所述第一子有源柱的侧壁；
每一所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。
在一些实施例中，所述第一元素包括N型掺杂元素或P型掺杂元素，所述第一子有源柱的材料包括半导体材料；或者，所述第一元素包括金属元素，所述第一子有源柱的材料包括所述金属元素的化合物。
在一些实施例中，所述衬底包括隔离结构，多个所述有源柱位于所述隔离结构上。
在一些实施例中，所述存储结构包括：
第一电极层，所述第一电极层覆盖所述第一子有源柱的侧壁；
介质层，至少覆盖所述第一电极层的侧壁；
第二电极层，位于所述介质层的间隙中，覆盖所述介质层的表面。
在一些实施例中，所述半导体结构还包括：围绕所述第二子有源柱顶部侧壁的第一保护层；
所述第一保护层包括多个第一保护柱和多个第二保护柱；
每个所述第一保护柱位于在第一方向相邻的两个第二子有源柱顶部之间，且覆盖相邻的两个第二子有源柱相对的两个侧壁；
每一所述第二保护柱沿第一方向延伸，覆盖所述第二子有源柱顶部未被所述第一保护柱覆盖的侧壁，并且覆盖所述第一保护柱的侧壁。
在一些实施例中，所述第二子有源柱中部的径宽小于所述第二子有源柱顶部的径宽和/或所述第二子有源柱底部的径宽；
所述晶体管包括：环绕所述第二子有源柱设置的栅极氧化层，环绕所述栅极氧化层设置的栅极，以及分别设置在所述第二有源柱相对的两个端部的源极和漏极，所述栅极远离所述栅极氧化层的一侧与所述第二保护柱远离所述栅极氧化层的一侧的侧壁齐平。
在一些实施例中，所述半导体结构还包括：
多条位线，位于所述晶体管上，与所述第二子有源柱顶部电连接。
本公开实施例提供的半导体结构与上述实施例中半导体结构的制造方法制造得到的半导体结构类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
根据本公开的再一方面，提供了一种存储器，包括：一个或多个如本公开上述实施例中中任一项所述的半导体结构。
基于此，本公开实施例中，利用在所述第一子有源柱中增加第一元素来降低第一子有源柱的电阻率，从而减小第一子有源柱与存储结构之间的电阻，进而减少信号传输的延迟，最终提高半导体结构的性能。此外，存储结构和晶体管在同一有源柱上形成可以降低存储单元与晶体管对准的难度，从而减少工艺难度。
在一些实施例中，所述存储器包括DRAM。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种半导体结构，包括：衬底、位于所述衬底上方的多个有源柱、存储结构、多个晶体管；
    所述多个有源柱沿第一方向和第二方向呈阵列排布；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；所述第一子有源柱的材料包含第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；
    所述存储结构，覆盖所述第一子有源柱的侧壁；
    每一所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。
  2. 根据权利要求1所述的半导体结构，其中，所述第一元素包括N型掺杂元素或P型掺杂元素，所述第一子有源柱的材料包括半导体材料；或者，所述第一元素包括金属元素，所述第一子有源柱的材料包括所述金属元素的化合物。
  3. 根据权利要求1所述的半导体结构，其中，所述衬底包括隔离结构，多个所述有源柱位于所述隔离结构上。
  4. 根据权利要求1所述的半导体结构，其中，所述存储结构包括：
    第一电极层，所述第一电极层覆盖所述第一子有源柱的侧壁；
    介质层，至少覆盖所述第一电极层的侧壁；
    第二电极层，位于所述介质层的间隙中，覆盖所述介质层的表面。
  5. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：围绕所述第二子有源柱顶部侧壁的第一保护层；
    所述第一保护层包括多个第一保护柱和多个第二保护柱；
    每个所述第一保护柱位于在第一方向相邻的两个第二子有源柱顶部之间，且覆盖相邻的两个第二子有源柱相对的两个侧壁；
    每一所述第二保护柱沿第一方向延伸，覆盖所述第二子有源柱顶部未被所述第一保护柱覆盖的侧壁，并且覆盖所述第一保护柱的侧壁。
  6. 根据权利要求5所述的半导体结构，其中，所述第二子有源柱中部的径宽小于所述第二子有源柱顶部的径宽和/或所述第二子有源柱底部的径宽；
    所述晶体管包括：环绕所述第二子有源柱设置的栅极氧化层，环绕所述栅极氧化层设置的栅极，以及分别设置在所述第二子有源柱相对的两个端部的源极和漏极，所述栅极远离所述栅极氧化层的一侧与所述第二保护柱远离所述栅极氧化层的一侧的侧壁齐平。
  7. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：
    多条位线，位于所述晶体管上，与所述第二子有源柱顶部电连接。
  8. 一种存储器，包括：一个或多个如权利要求1至7中任一项所述的半导体结构。
  9. 一种半导体结构的制作方法，所述方法包括：
    提供衬底，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个有源柱；每一所述有源柱包括第一子有源柱和位于所述第一子有源柱上的第二子有源柱；所述第一方向和所述第二方向相交且均与所述衬底的顶面平行；
    在所述第一子有源柱中增加第一元素，材料中包含所述第一元素的第一子有源柱的电阻率小于材料中未包含所述第一元素的第一子有源柱的电阻率；
    至少在所述第一子有源柱的侧壁形成存储结构；
    形成多个晶体管，所述晶体管的沟道结构位于所述第二子有源柱内，所述沟道结构的延伸方向与所述第二子有源柱的延伸方向相同。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，
    所述第一元素包括N型或P型掺杂元素，在所述第一子有源柱中增加第一元素，包括：通过扩散或者离子注入工艺在所述第一子有源柱中增加N型或P型掺杂元素；
    或者，
    所述第一元素包括金属元素，在所述第一子有源柱中增加第一元素，包括：形成覆盖所述第一子有源柱的侧壁的含有所述金属元素的金属层；采用退火工艺，使得所述金属层和所述第一子有源柱反应形成金属化合物。
  11. 根据权利要求9所述的半导体结构的制作方法，其中，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个有源柱，包括：
    在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个半导体柱；每一所述半导体柱包括第一部分、位于所述第一部分上的第二部分、以及位于所述第二部分上的第三部分；
    形成覆盖所述第三部分的顶面的支撑层；
    形成至少覆盖所述第三部分的侧壁的第二保护层；
    对所述半导体柱进行氧化处理，以使所述第一部分被完全氧化成氧化柱，且所述第二部分的表面被氧化成氧化层；
    去除所述第二部分的表面的氧化层，得到所述第一子有源柱；
    在形成所述存储结构之后，去除所述支撑层以及所述第二保护层，得到所述第二子有源柱。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，在所述衬底上形成沿第一方向和第二方向呈阵列排布的多个半导体柱，包括：
    提供半导体基底；
    在所述基底中形成多条沿第一方向间隔排布的第一沟槽，以及多条沿第二方向间隔排布的第二沟槽；
    对每一所述第一沟槽和/或所述第二沟槽底部进行扩大处理，形成所述多个半导体柱。
  13. 根据权利要求11所述的半导体结构的制作方法，其中，所述形成支撑层，包括：
    在多个所述半导体柱之间填充满第一绝缘材料，得到第一绝缘层；
    沉积第二绝缘材料，所述第二绝缘材料覆盖所述第一绝缘层和所述半导体柱的顶面，得到所述第二绝缘层；
    沿所述第二方向去除部分所述第二绝缘层形成第一浅沟槽，所述第一浅沟槽的底面与所述半导体柱的顶面齐平，在所述第一浅沟槽内填充所述第一绝缘材料；
    沿所述第一方向去除部分所述第二绝缘层形成第二浅沟槽，所述第二浅沟槽的底面与所述半导体柱的顶面齐平，且暴露出所述半导体柱的顶面；在所述第二浅沟槽内填充所述第二绝缘材料；
    未被去除的所述第二绝缘层和所述第二浅沟槽内填充所述第二绝缘材料构成所述支撑层。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述形成第二保护层，包括：
    去除部分所述第一绝缘材料，形成第三浅沟槽；所述第三浅沟槽的底面与所述第三部分的底面齐平，暴露出所述第三部分的侧壁；
    沉积牺牲材料，所述牺牲材料至少覆盖所述第三部分的侧壁，得到所述第二保护层。
  15. 根据权利要求9所述的半导体结构的制作方法，其中，所述至少在所述第一子有源柱的侧壁形成存储结构，包括：
    形成覆盖所述第一子有源柱侧壁的第一导电层；
    形成至少覆盖所述第一导电层的侧壁的介质层；
    在所述介质层的间隙中形成第二导电层。
  16. 根据权利要求9所述的半导体结构的制作方法，其中，形成所述存储结构之后，所述方法还包括：形成围绕所述第二子有源柱顶部侧壁的第一保护层；
    所述形成第一保护层，包括：
    在所述第二子有源柱之间形成第一绝缘材料；
    去除所述第二子有源柱顶部的部分第一绝缘材料，形成多个第一凹槽，每个所述第一凹槽暴露出在第一方向上相邻的两个所述第二子有源柱顶部相对的两个侧壁；
    填充所述第一凹槽形成多个第一保护柱；
    去除所述第二子有源柱顶部剩余的所述第一绝缘材料，形成多个沿所述第一方向延伸的第二凹槽；
    在所述第二凹槽的侧壁形成多个第二保护柱，所述第一保护柱与所述第二保护柱共同构成 所述第一保护层。
  17. 根据权利要求16所述的半导体结构的制作方法，其中，所述形成晶体管，包括：
    在形成所述第一保护层之后，去除所述第二子有源柱中部对应的第一绝缘材料，暴露出所述第二子有源柱中部的侧壁；
    形成覆盖所述第二子有源柱中部的侧壁的栅极氧化层；
    形成覆盖所述栅极氧化层的栅极；
    在所述第二子有源柱底部和顶部分别形成源极、漏极；
    在所述第二保护柱之间以及所述栅极之间形成隔离结构。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，所述形成覆盖栅极氧化层的栅极，包括：
    在所述栅极氧化层的间隙中填充栅极导电材料；
    以所述第一保护层为掩膜层，去除部分所述栅极导电材料，剩余的栅极导电材料形成所述栅极。
  19. 根据权利要求17所述的半导体结构的制作方法，其中，
    在形成所述栅极氧化层之前，去除所述第二子有源柱中部的侧壁，形成具有凹部的所述第二子有源柱，以及与所述凹部对应的凹陷空间；在所述凹陷空间中，至少形成环绕所述凹部的栅极氧化层。
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