WO2024012104A1 - 一种半导体结构的制作方法及其结构 - Google Patents

一种半导体结构的制作方法及其结构 Download PDF

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Publication number
WO2024012104A1
WO2024012104A1 PCT/CN2023/098988 CN2023098988W WO2024012104A1 WO 2024012104 A1 WO2024012104 A1 WO 2024012104A1 CN 2023098988 W CN2023098988 W CN 2023098988W WO 2024012104 A1 WO2024012104 A1 WO 2024012104A1
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word line
dielectric layer
region
capacitor
active
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PCT/CN2023/098988
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Publication of WO2024012104A1 publication Critical patent/WO2024012104A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure and its structure.
  • the memory cells are arranged in the horizontal direction. Therefore, the integration density of the two-dimensional or planar semiconductor device can be determined by the area occupied by the unit memory unit.
  • the integration density of the two-dimensional or planar semiconductor device is extremely high.
  • the earth is affected by the technology of forming fine patterns, so that there is a limit to the continued increase in the integration density of two-dimensional or planar semiconductor devices. Therefore, there is an urgent need to design a semiconductor structure that can stack memory cells in three dimensions.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and its structure, which can at least provide a semiconductor structure stacked in a three-dimensional direction, which is beneficial to improving the space utilization of the semiconductor structure.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming active regions, the active regions being spaced along a first direction, a second direction, and a third direction.
  • the active region includes a first doping region, a channel region and a second doping region arranged along the second direction; forming a word line, the word line extending along the first direction , the word line includes a first word line and a second word line, the first word line is located on the top surface of the channel area, and the second word line is located on the bottom surface of the channel area; forming a bit line , the bit line is located between the adjacent active regions arranged along the second direction, the bit line extends along the third direction, and the bit line covers the second doped region Far from the sidewall of the channel region; forming a capacitor, the capacitor extends along the second direction, is stacked along the third direction, and the capacitor covers the first doped region away from the trench The side wall of the road area.
  • the method of forming an active area includes: forming a first stacked structure on the surface of the substrate, the first stacked structure including a first interlayer dielectric layer, an initial The active area, the first interlayer dielectric layer, and the first isolation layer are etched into the initial active area to form the active area.
  • the step of etching the initial active region includes: a first etching process, the first etching process includes: etching the first stack structure to form a layer along the The first stacked structures are arranged at intervals in a first direction; forming a second stacked structure, the second stacked structure is located between the adjacent first stacked structures, the second stacked structure includes a structure along the first stacked structure; A second interlayer dielectric layer and a second isolation layer are arranged sequentially in three directions. The second interlayer dielectric layer is in contact with the first interlayer dielectric layer. The second isolation layer is in contact with the initial active layer. area or the first isolation layer contact connection; a second etching process, the second etching process includes: etching The first stacked structure and the second stacked structure are etched to form the active regions spaced apart along the second direction.
  • the first interlayer dielectric layer is made of the same material as the second interlayer dielectric layer.
  • forming the word line includes etching the first interlayer dielectric layer along the second direction to form a first groove, the first groove exposing the active the surface of the channel region; forming an initial word line, the initial word line is located on the surface of the channel region and the second doped region; patterning the initial word line to expose the third On the surface of the second doped region, the remaining initial word line serves as the word line, wherein the word line located on the top surface of the channel region serves as the first word line, and the word line located on the bottom surface of the channel region serves as the first word line.
  • the word line serves as the second word line.
  • the step of forming the bit line includes: forming a third isolation layer, the third isolation layer is located between the active areas spaced along the second direction and covers the the surface of the second doped region; patterning the third isolation layer to form a second groove, the second groove exposing the sidewall of the second doped region away from the channel region; forming the The bit line fills the second groove.
  • the step of forming the capacitor includes: etching the active region to form a third groove; forming a lower plate covering the sidewalls of the third groove; A capacitive dielectric layer is formed, and the capacitive dielectric layer covers the surface of the lower electrode plate; an upper electrode plate is formed, and the upper electrode plate covers the surface of the capacitive dielectric layer and fills the third groove.
  • etching the active region includes: patterning the first stack structure to expose a side surface of the active region away from the word line; etching the active region to The third groove is formed.
  • embodiments of the present disclosure further provide a semiconductor structure, including: a substrate; and active regions, the active regions are spaced apart along the first direction, the second direction, and the third direction, And the active region includes a first doped region, a channel region and a second doped region arranged along the second direction; a word line, the word line extends along the first direction, and along the They are stacked in a third direction, and the word lines include: a first word line and a second word line. The first word line is located on the top surface of the channel area, and the second word line is located on the trench.
  • bit line the bit line is located between the adjacent active areas arranged along the second direction, and the same bit line is connected to the two adjacent active areas.
  • contact connection the bit line extends along the third direction, and the bit line covers the sidewall of the second doped region away from the channel region;
  • a capacitor the capacitor extends along the second direction, The stacks are arranged along the third direction, and the capacitor covers the sidewall of the first doped region away from the channel region.
  • the width of the bit line is smaller than the spacing between adjacent word lines.
  • the active areas spaced apart along the third direction share the same bit line.
  • the active areas spaced apart along the first direction share the same word line.
  • a first interlayer dielectric layer is further included, and the first interlayer dielectric layer is located on the top and bottom surfaces of the capacitor and the active area.
  • it further includes: a first isolation layer, the capacitor, the active area electrically connected to the capacitor, and a first layer located on the top and bottom surfaces of the capacitor and the active area.
  • the interlayer dielectric layer forms a repeating unit, and the repeating unit and the first isolation layer are alternately arranged in the third direction.
  • the capacitor includes: a lower plate, the lower plate includes a bottom surface in contact with the first doped region, and side surfaces surrounding an edge of the bottom surface and extending along the second direction, The bottom surface and the side surface enclose an accommodation space; a capacitive dielectric layer covers the inner wall of the accommodation space; an upper plate covers the inner wall of the capacitive dielectric layer, and the upper plate covers the inner wall of the capacitive dielectric layer.
  • the upper electrode plate fills the accommodation space.
  • the capacitors arranged along the third direction share the capacitor dielectric layer and the upper plate.
  • 1 to 10 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 11 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • the present disclosure provides a method for manufacturing a semiconductor structure, which consists of forming a first word line located on the top surface of the channel area of the active area and a second word line located on the bottom surface of the channel area to form a word line.
  • the bit line in the impurity region far away from the sidewall of the channel region forms a capacitor located in the first doping region far away from the sidewall of the channel region to realize the function of the semiconductor structure, and by forming the capacitor along the first direction, the second direction and the third direction.
  • Active regions are arranged at intervals, and corresponding capacitors, word lines and bit lines are respectively formed in the first doped region, channel region and second doped region of the active region to form a semiconductor structure stacked in a three-dimensional direction. , thereby improving the space utilization of the semiconductor structure and thereby increasing the stacking density of the semiconductor structure.
  • FIGS. 1 to 10 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view along the dotted line direction of FIG. 6 .
  • FIG. 8 to FIG. 10 is a schematic structural diagram corresponding to the subsequent manufacturing method based on FIG. 7 .
  • the manufacturing method of a semiconductor structure includes: providing a substrate 100 ; forming active regions 110 , which are arranged at intervals along the first direction X, the second direction Y, and the third direction Z, and the active areas 110 are
  • the region 110 includes a first doped region 111, a channel region 112 and a second doped region 113 arranged along the second direction X;
  • a word line 120 is formed, the word line 120 extends along the first direction X, and the word line 120 includes a A word line 121 and a second word line 122, the first word line 121 is located on the top surface of the channel area 112, and the second word line 122 is located on the bottom surface of the channel area 112;
  • a bit line 130 is formed, and the bit line 130 is located along the second Between the adjacent active regions 110 arranged in the direction Y, the bit line 130 extends along the third direction Z, and the bit line 130 covers the sidewall of the second doped region 113 away from the channel region 112;
  • the word line 120 is positioned on the surface of the channel region 112 of the active region 110 , the capacitor 140 is positioned on the sidewall of the first doped region 111 away from the channel region 112 , and the bit line 130 is positioned on the second doped region 113 far away from the channel.
  • the sidewalls of the track area 112 realize the storage of the semiconductor structure, and the active areas are arranged at intervals along the first direction X, the second direction Y and the third direction Z, and the bit lines 130 are arranged to extend along the third direction Z.
  • the word line 120 extends along the first direction X, thereby realizing stacking of semiconductor structures and improving space utilization of the semiconductor structures.
  • the method of forming the active region 110 includes: forming a first stacked structure 150 on the surface of the substrate 100 .
  • the first stacked structure 150 includes first interlayer dielectric layers 160 sequentially arranged along the third direction Z. , the initial active region 114, the first interlayer dielectric layer 160, and the first isolation layer 180; etching the initial active region 114 to form the active region 110.
  • the first interlayer dielectric layer 160 By forming the first interlayer dielectric layer 160, it can be used to subsequently form a support structure for the capacitor, thereby preventing the capacitor 140 from being partially suspended in the semiconductor structure. By supporting the capacitor through the first interlayer dielectric layer 160, the capacitor can be prevented from being broken or deformed. , thereby improving the reliability of the semiconductor structure, and by forming the first interlayer The dielectric layer 160 can guide the flow of the etching liquid during the subsequent etching process, and fix the flow path of the etching liquid when the subsequent etching liquid flows, thereby fixing the etching direction and avoiding over-etching or etching deviation. Case. As a result, the reliability of the semiconductor structure can be improved.
  • the substrate 100 may include a substrate 101 and an isolation layer 102 stacked in sequence.
  • the isolation layer 102 is used to realize the substrate 101 and the first stacked structure 150 The insulation between them prevents leakage between the active region 110 and the substrate 101 in the first stacked structure 150, which is beneficial to improving the electrical performance of the semiconductor structure.
  • the material of the substrate 101 may be silicon material
  • the material of the isolation layer 102 may be an insulating material such as silicon oxide or silicon nitride.
  • the step of etching the initial active region 114 includes: a first etching process.
  • the first etching process includes: etching the first stack structure 150 to form a first stacked structure 150 spaced apart along the first direction X.
  • the initial active regions 114 arranged along the first direction X may be formed by etching to form the first stack structures 150 arranged at intervals along the first direction X.
  • a second stacked structure 210 is formed.
  • the second stacked structure 210 is located between adjacent first stacked structures 150 .
  • the second stacked structure 210 includes second interlayer dielectric layers arranged sequentially along the third direction Z. 190, the second isolation layer 200, the second interlayer dielectric layer 190 is in contact with the first interlayer dielectric layer 160, and the second isolation layer 200 is in contact with the initial active region 114 or the first isolation layer 180.
  • the gap formed by etching the first stacked structure 150 can be filled, and the second stacked structure 210 can be used as a support structure for the subsequent formation of word lines, thereby avoiding deformation of the formed word lines, thereby improving the quality of the semiconductor structure. reliability.
  • the material of the second interlayer dielectric layer 190 may be the same as the material of the first interlayer dielectric layer 160
  • the material of the second isolation layer 200 may be the same as the material of the first isolation layer 180 , so that subsequent steps can be performed.
  • the first interlayer dielectric layer 160 and the second interlayer dielectric layer 190 are simultaneously etched in the same step
  • the second isolation layer 200 and the first isolation layer 180 are simultaneously etched in the same step, thereby reducing the semiconductor structure.
  • the second isolation layer 200 and the first isolation layer 180 use the same filling for illustration.
  • the thickness of the second interlayer dielectric layer 190 is equal to the thickness of the first interlayer dielectric layer 160 , that is to say, the top surface of the second interlayer dielectric layer 190 is equal to the thickness of the first interlayer dielectric layer 160 .
  • the top surface of the interlayer dielectric layer 160 is flush; the thickness of the second isolation layer 200 is equal to the thickness of the first isolation layer 180 , that is, the top surface of the second isolation layer 200 is equal to the top surface of the first isolation layer 180 Flush, allowing the formation of regular-shaped semiconductor structures.
  • the thickness of the second interlayer dielectric layer may also be different from the thickness of the first interlayer dielectric layer, and the thickness of the second isolation layer may also be different from the thickness of the first isolation layer.
  • the thickness may be determined according to actual requirements. Production needs are adjusted.
  • the thicknesses between adjacent first interlayer dielectric layers 160 are equal, so that in the process of forming the first stacked structure, only the same deposition speed and the same thickness can be controlled. deposition time, so that the first interlayer dielectric layer 160 with equal thickness can be formed, and the same process parameters can be used in the process of forming the second interlayer dielectric layer 190 of the second stacked structure 210, so that the first interlayer dielectric layer 160 can be formed.
  • the formation parameters of the interlayer dielectric layer 160 and the second interlayer dielectric layer 190 are not adjusted to facilitate the entire production process; in other embodiments, the thickness between adjacent first interlayer dielectric layers 160 can also be The thickness of the adjacent second interlayer dielectric layer 190 may also be unequal, and may be adjusted according to actual production requirements.
  • the thickness of the initial active region 114 may be greater than the thickness of the first interlayer dielectric layer 160 . In other embodiments, the thickness of the initial active region may also be equal to the thickness of the first interlayer dielectric layer 160 . The thickness of the interlayer dielectric layer; in some embodiments, the thickness of the initial active region may also be smaller than the thickness of the first interlayer dielectric layer. It can be adjusted according to the actual production situation.
  • the thickness of the initial active region 114 By controlling the thickness of the initial active region 114 to be greater than the thickness of the first interlayer dielectric layer 160 , there can be more carriers in the initial active region 114 and the transmission rate of the initial active region 114 can be improved; by forming the initial active region 114 The thickness is equal to the thickness of the first interlayer dielectric layer, which can reduce the process complexity of the semiconductor structure in the production process; by forming the initial active region with a thickness smaller than the thickness of the first interlayer dielectric layer, the adjacent initial active region can be improved insulation between.
  • the thickness of the initial active region 114 is greater than the thickness of the first isolation layer 180 , that is, That is to say, in the subsequent process of forming the second isolation layer 200, the thickness of the second isolation layer 200 that is in contact with the initial active region 114 is greater than the thickness of the second isolation layer 200 that is connected with the first isolation layer 180.
  • the thickness of the initial active region 114 being greater than the thickness of the first isolation layer 180 can increase the number of carriers in the initial active region 114, thereby increasing the transmission rate of the initial active region 114; in other embodiments, the initial active region 114 has The thickness of the source region 114 is equal to the thickness of the first isolation layer 180, so that in the subsequent process of forming the second isolation layer 200, there is no need to change the formation parameters of the second isolation layer 200; in some embodiments, the initial active The thickness of the region can also be smaller than the thickness of the first isolation layer, and can be adjusted according to actual conditions. This disclosure does not limit the thickness of the initial active region 114 and the first isolation layer 180 .
  • the thickness of the initial active region 114, the thickness of the first interlayer dielectric layer 160 and the first isolation layer can be equal or different, and can be adjusted according to the actual situation.
  • the thickness of the illustrated part of the disclosure is The difference is only for the convenience of distinguishing different film layers, and does not limit the thickness relationship between the film layers.
  • the step of etching the initial active region 114 may further include: a second etching process.
  • the second etching process includes: etching the first stack structure 150 and the second stack structure 210 to form a layer along the first stack structure 150 and the second stack structure 210 .
  • the active areas 110 arranged at intervals in the two directions Y can be formed by the second etching.
  • the active areas 110 arranged at intervals along the second direction Y can also provide a process basis for the subsequent formation of word lines. It can be understood that the active regions 110 arranged at intervals along the second direction Y are formed by etching the same initial active region 114, so the formed active regions 110 are symmetrically distributed.
  • adjacent active regions 110 are formed by etching the same initial active region 114.
  • one of the active regions 110 includes a first doped region 111, a channel region 112 and a second doped region 113 arranged along the second direction, and the other active region 110 includes: along the second direction
  • the second doped region 113, the channel region 112 and the first doped region 111 are arranged in Y.
  • the step of forming the word line 120 may include: etching the first interlayer dielectric layer 160 along the second direction Y to form a first groove 220 , and the first groove 220 exposes the active region 110 The surface of the channel region 112; forming an initial word line, which is located on the surface of the channel region 112 and the second doped region 113; patterning the initial word line to expose the surface of the second doped region 113, leaving the initial words
  • the word line 120 located on the top surface of the channel region 112 serves as the first word line 121
  • the word line 120 located on the bottom surface of the channel region 112 serves as the second word line 122 .
  • the process of etching the first interlayer dielectric layer 160 also includes etching the second interlayer dielectric layer 190 that is in contact with the first interlayer dielectric layer 160. That is to say, before forming the first recess During the process of forming the groove 220, the first groove 220 also exposes the top surface of the second isolation layer 200 that is in contact with the active area 110. In this way, during the subsequent process of forming the word line 120, a continuous word line along the second direction is formed. 120, that is to say, the active areas 110 arranged along the second direction share the word line 120.
  • the first interlayer dielectric layer 160 located above the active region 110 and the first interlayer dielectric layer 160 located below the active region 110 are made of the same material, when etching the first interlayer dielectric layer 160 The top surface and bottom surface of the channel area 112 of the active area 110 are exposed at the same time.
  • the formed word line 120 simultaneously covers the top surface and the bottom surface of the channel area 112 and is located in the channel.
  • the word line 120 on the top surface of the region 112 serves as the first word line 121
  • the word line 120 on the bottom surface of the channel region 112 serves as the second word line 122.
  • the facing area between the line 120 and the active region 110 can thereby improve the ability of the word line 120 to control the channel region 112 and improve the performance of the semiconductor structure.
  • the method further includes: forming a gate dielectric layer (not shown in the figure).
  • the gate dielectric layer covers the surface of the active area 110, so that the word line 120 can be avoided. Direct contact connection with the active area 110 .
  • the material of the gate dielectric layer may be an insulating material such as silicon oxide or silicon nitride.
  • the step of forming the bit line 130 includes: forming a third isolation layer 230 , the third isolation layer 230 is located between the active regions 110 spaced apart along the second direction, and covers the second doped region. 113; pattern the third isolation layer 230 to form a second groove 240, the second groove 240 exposes the sidewall of the second doped region 113 away from the channel region 112; form a bit line 130, and the bit line 130 fills The second groove 240 is filled.
  • a third isolation layer 230 is formed.
  • the third isolation layer 230 also covers the top surface of the semiconductor structure. By forming the third isolation layer 230 on the top surface of the semiconductor structure, it can also be removed later.
  • the mask layer located on the top surface of the third isolation layer 230 plays a role in protecting the semiconductor structure, and can also prevent the removal of the mask layer from contacting the internal structure of the semiconductor structure, thereby improving the reliability of the semiconductor structure.
  • the material of the third isolation layer 230 may be an insulating material, such as silicon oxide or silicon nitride.
  • a mask layer is formed on the top surface of the semiconductor structure.
  • the pattern of the mask layer exposes part of the top surface of the third isolation layer 230 .
  • the third isolation layer 230 is etched using the mask layer as a mask to form the second isolation layer 230 .
  • forming the second groove 240 further includes removing the mask layer.
  • a portion of the third isolation layer 230 located on the top surface of the first isolation layer 180 may be etched first to expose the first isolation layer 230 .
  • the sidewalls of the layer 180 are then etched using the first isolation layer 180 as a mask to continue etching the third isolation layer 230. That is to say, in the second direction Y, the width of the pattern opening of the mask layer can be larger than that of the adjacent ones. The gap between the source areas 110.
  • the second groove 240 By first forming the second groove 240 with a larger opening on the part of the third isolation layer 230 located on the top surface of the first isolation layer 180, it is easy to position the spaced first isolation layers 180, and then use the first isolation layer 180 as the Mask etching of the third isolation layer 230 can avoid etching offset during the etching process and prevent part of the bit line 130 from not being in contact with the second doping region 113 of the active region 110 during the subsequent formation of the bit line 130 , thereby improving the reliability of the manufacturing process of the semiconductor structure.
  • the second groove 240 is formed before the second groove 240 is formed.
  • the formed second groove 240 exposes the sidewall of the adjacent active area 110, thereby ensuring the electrical connection between the bit line and the active area 110 when the bit line is subsequently formed.
  • bit line 130 is formed. It can be understood that the adjacent active areas 110 along the second direction Y and the active areas 110 spaced apart along the third direction Z share the same bit line 130 .
  • a portion of the third isolation layer 230 that is in contact with the sidewalls of the word lines 120 is still retained, so that this portion of the retained third isolation layer 230 can be
  • the word line 120 and the bit line 130 are isolated to avoid contact between the word line 120 and the bit line 130, avoid abnormalities in the semiconductor structure, and improve the reliability of the semiconductor structure.
  • the steps of forming the capacitor 140 include: etching the active region 110 to form a third groove 250 ; forming a lower plate 141 covering the sidewalls of the third groove 250 ; forming The capacitive dielectric layer 142 covers the surface of the lower plate 141; an upper plate 143 is formed, the upper plate 143 covers the surface of the capacitive dielectric layer 142 and fills the third groove 250.
  • the first stacked structure 150 is patterned to expose the side surface of the active area 110 away from the word line 120 ; by patterning the first stacked structure 150 to form the fourth groove 260 , by forming the fourth The groove 260 can etch the active region 110 through the surface of the active region 110 exposed by the fourth groove 260, thereby providing a process basis for subsequent formation of the capacitor 140.
  • the fourth groove 260 can be formed by mask etching. That is to say, a mask can be formed on the surface of the third isolation layer 230 first, and the pattern of the fourth groove 260 can be defined through the mask. , the fourth groove 260 is formed by mask etching, and after the fourth groove 260 is formed, the mask on the top surface of the third isolation layer 230 is also removed.
  • the active area is etched to form a third groove 250 .
  • the formation of the third groove 250 can provide a process basis for subsequent formation of a capacitor.
  • a capacitor 140 is formed.
  • the capacitor 140 shares the capacitive dielectric layer 142 and the upper plate 143.
  • the capacitance of the shared capacitive dielectric layer 142 and the upper plate 143 passes through a non-shared capacitor.
  • the lower plate 141 determines the capacitance of the capacitor 140, and the production process can be facilitated by arranging the capacitor 140 that shares the capacitive dielectric layer 142 and the upper plate 143.
  • the material of the lower plate 141 may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper or tungsten; the material of the capacitor dielectric layer 142 may include: ZrO, AlO, ZrNbO, Any one or any combination of ZrHfO, ZrAlO; the material of the upper plate 143 includes compounds formed by one or two of metal nitride and metal silicide, such as titanium nitride, titanium silicide, and nickel silicide. , titanium silicon nitride or other conductive materials, or the material of the upper plate 143 can also be a conductive semiconductor material, such as polysilicon, silicon germanium, etc.
  • the relative area between the lower plate 141 and the upper plate 143 of the capacitor 140, the distance between the lower plate 141 and the upper plate 143, and the material of the capacitor dielectric layer 142 may all affect the capacity of the capacitor 140.
  • the relative area between the lower plate 141 and the upper plate 143 of the capacitor 140, the distance between the lower plate 141 and the upper plate 143, and the material of the capacitor dielectric layer 142 can be set according to actual needs.
  • the capacitor dielectric layer and the upper electrode plate located only in the third groove can also be formed. That is to say, the capacitor dielectric layer and the upper electrode plate can also be formed not in the third direction.
  • the capacitor sharing the upper capacitor dielectric layer and the upper electrode plate can be formed by first forming the capacitor dielectric layer and the upper electrode plate that fill the third groove and the fourth groove, and then etching to expose the fourth groove. The capacitance of the capacitance dielectric layer and the upper plate is not shared in the third direction.
  • the capacitive dielectric layer 142 after forming the capacitive dielectric layer 142 and before forming the upper plate 143, it further includes: forming a diffusion barrier layer (not shown in the figure), the diffusion barrier layer covering the surface of the capacitive dielectric layer 142 away from the lower plate 141, That is to say, the upper electrode plate 143 covers the surface of the diffusion barrier layer away from the capacitive dielectric layer 142, and the diffusion barrier layer blocks the conductive elements in the upper electrode plate 143 from diffusing into the capacitive dielectric layer 142 to avoid reducing the conductive performance of the upper electrode plate 143. , and can prevent the upper plate 143 from affecting the insulation performance of the capacitor dielectric layer 142 .
  • the material of the diffusion barrier layer may be a metal compound such as titanium nitride.
  • the word line 120 is formed on the surface of the channel region 112 of the active region 110
  • the capacitor 140 is formed on the sidewall of the first doped region 111 away from the channel region 112
  • the capacitor 140 is formed on the sidewall of the first doped region 111 away from the channel region 112
  • the capacitor 140 is formed on the sidewall of the second doped region 113 away from the channel region 112 of the active region 110.
  • the bit lines 130 on the sidewalls of the channel region 112 realize the storage of the semiconductor structure, and the active regions are arranged at intervals along the first direction X, the second direction Y and the third direction Z, and the bit lines 130 are arranged along the third direction Extending in the direction Z, the word line 120 is arranged to extend along the first direction X, thereby forming a stack of semiconductor structures, which can improve the space utilization of the semiconductor structures.
  • Another embodiment of the present disclosure also provides a semiconductor structure, which can be formed through some or all of the above process steps.
  • the semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that it is the same as the previous embodiment. or corresponding parts, please refer to the corresponding descriptions of the foregoing embodiments, which will not be described in detail below.
  • Figure 11 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 12 is a schematic diagram of the internal structure of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 100; an active region 110, the active regions 110 are arranged at intervals along the first direction X, the second direction Y and the third direction Z, and the active region 110 It includes a first doped region 111, a channel region 112 and a second doped region 113 arranged along the second direction Y; a word line 120, which extends along the first direction X and is stacked and arranged along the third direction Z , and the word line 120 includes: a first word line 121 and a second word line 122.
  • the first word line 121 is located on the top surface of the channel area 112, and the second word line 122 is located on the bottom surface of the channel area 112; the bit line 130, The line 130 is located between adjacent active areas 110 arranged along the second direction Y, and the same bit line 130 is in contact with the two adjacent active areas 110.
  • the bit line 130 extends along the third direction Z.
  • the line 130 covers the sidewall of the second doped region 113 away from the channel region 112; the capacitor 140 extends along the second direction Y and is stacked along the third direction Z, and the capacitor 140 covers the first doped region 111 away from sidewalls of channel region 112 .
  • the active areas 110 spaced apart along the first direction X share the same word line 120.
  • the required space can thereby improve the space utilization of the semiconductor structure, thereby increasing the stacking density of the semiconductor structure.
  • the contact area between the word line 120 and the active area 110 can be increased, thereby increasing the size of the word line 120.
  • the ability to control the channel region 112 improves the performance of the semiconductor structure.
  • the active areas 110 spaced apart along the third direction Z share the same bit line 130 .
  • the space required for laying out the bit lines 130 can be reduced, thereby improving the space utilization of the semiconductor structure and thereby increasing the stacking density of the semiconductor structure.
  • adjacent active areas 110 along the second direction Y share the same bit line 130. As shown in FIG. 12, six active areas 110 share the same bit line 130.
  • Sharing the same bit line 130 between adjacent active areas can reduce the space required for laying out the bit line 130, thereby improving the space utilization of the semiconductor structure, thereby increasing the stacking density of the semiconductor structure, and correspondingly increasing the area of the bit line 130. , thereby reducing the resistance of the bit line 130 itself, thereby increasing the transmission rate of the bit line 130 .
  • the active regions 110 adjacent along the second direction Y are axially symmetrically distributed along the bit lines 130 located between the adjacent active regions 110 . That is, the active regions 110 located on one side of the bit lines 130 are symmetrically distributed.
  • the region 110 includes a first doped region 111, a channel region 112 and a second doped region 113 arranged along the second direction.
  • the active region 110 located on the other side of the bit line 130 includes a first doped region 111 arranged along the second direction Y.
  • the second doped region 113, the channel region 112 and the first doped region 111 are axially symmetrically distributed along the bit lines 130 located between the adjacent active regions 110 . That is, the active regions 110 located on one side of the bit lines 130 are symmetrically distributed.
  • the region 110 includes a first doped region 111, a channel region 112 and a second doped region 113 arranged along the second direction.
  • the second doped region 113, the channel region 112 and the first doped region 111 are
  • the width of the bit line 130 is smaller than the spacing between adjacent word lines 120 .
  • the width of the bit line 130 is smaller than the distance between adjacent word lines 120.
  • a third isolation layer 230 is further included between the bit line 130 and the word line 120.
  • the third isolation layer 230 is used to isolate the word line 120 and the bit line 130, thereby preventing the word line 120 from being separated from the bit line 130.
  • Contact connection avoids abnormalities in the semiconductor structure, thereby improving the reliability of the semiconductor structure.
  • the capacitor 140 includes: a lower plate 141.
  • the lower plate 141 includes a bottom surface in contact with the first doped region 111, and side surfaces surrounding the edge of the bottom surface and extending along the second direction Y.
  • the bottom surface and the side surfaces form a There is an accommodation space; a capacitive dielectric layer 142, which covers the inner wall of the accommodation space; and an upper plate 143, which covers the inner wall of the capacitive dielectric layer 142, and the upper plate 143 fills the accommodation space.
  • the lower plate 141 covers the active area 110 and the sidewalls of the space surrounded by the first interlayer dielectric layer 160 located on the top and bottom surfaces of the active area 110 , and the capacitive dielectric layer 142 covers the inner wall of the lower plate 141 , the upper plate 143 covers the inner wall of the capacitive dielectric layer 142 .
  • the capacitors 140 arranged along the third direction Z share the capacitor dielectric layer 142 and the upper plate 143 .
  • the capacitance of the common capacitance dielectric layer 142 and the upper plate 143 determines the capacity of the capacitor 140 through the unshared lower plate 141.
  • the capacitors 140 distributed along the first direction X, the second direction and the third direction Z share the upper plate 143, and the capacitors 140 distributed along the first direction X and the third direction Z share the upper plate 143.
  • the capacitor dielectric layer 142 is shared.
  • the capacitor dielectric layer 142 and the upper plate 143 are shared, that is to say, the 18 capacitors 140 arranged along the second direction Y share the same upper plate 143, and the nine capacitors 140 arranged along the second direction Y share the same capacitive medium.
  • Layer 142 The capacitor dielectric layer 142 and the upper plate 143 are shared, that is to say, the 18 capacitors 140 arranged along the second direction Y share the same upper plate 143, and the nine capacitors 140 arranged along the second direction Y share the same capacitive medium.
  • the upper plate and the capacitor dielectric layer can also be arranged to be spaced apart along the first direction. That is to say, the six capacitors arranged along the second direction share the same upper plate.
  • the three arranged capacitors share the same capacitor dielectric layer; in some embodiments, the upper plate and the capacitor dielectric layer can also be arranged to be evenly spaced along the first direction and the third direction, that is to say, the capacitors are parallel to each other.
  • the upper plate and capacitor dielectric layer are not shared.
  • the number of capacitors 140 that share the upper plate 143 and the capacitive dielectric layer 142 is determined by the number of capacitors 140 arranged along the first direction X, the second direction Y, and the third direction Z. In other words, the number of capacitors sharing the upper plate 143 and the capacitive dielectric layer 142 can be controlled by controlling the number of capacitors 140 arranged in different directions.
  • the embodiment of the present disclosure does not limit the number and arrangement of the capacitors 140. needs to be adjusted.
  • a diffusion barrier layer (not shown in the figure) is also included between the upper plate 143 and the capacitive dielectric layer 142 , and the diffusion barrier layer blocks the conductive elements in the upper plate 143 from diffusing into the capacitive dielectric layer 142 , to avoid reducing the conductive performance of the upper plate 143, and to prevent the upper plate 143 from affecting the insulation performance of the capacitive dielectric layer 142.
  • a first interlayer dielectric layer 160 is also included.
  • the first interlayer dielectric layer 160 is located on the top and bottom surfaces of the capacitor 140 and the active region 110 . By forming the first interlayer dielectric layer 160, it can play a role in supporting the capacitor 140 and the active region 110, and can prevent the capacitor 140 and the active region 110 from being suspended, thereby preventing the capacitor 140 and the active region 110 from being deformed, and improving the semiconductor quality. Structural reliability.
  • it also includes: a first isolation layer 180, a capacitor 140, an active area 110 electrically connected to the capacitor 140, and a first interlayer dielectric layer 160 located on the top and bottom surfaces of the capacitor 140 and the active area 110.
  • a repeating unit is formed.
  • the repeating units and the first isolation layer 180 are alternately arranged.
  • the insulation between adjacent active regions 110 can be improved, and different repeating units can be spaced apart, thereby facilitating process production.
  • a second stacked structure 210 is also included.
  • the second stacked structure 210 includes a second interlayer dielectric layer 190 and a second isolation layer 200 stacked sequentially in the third direction Z, and the second interlayer dielectric layer 190 is stacked sequentially in the third direction Z.
  • the dielectric layer 190 is in contact with the first interlayer dielectric layer 160
  • the second isolation layer 200 is in contact with the initial active region 114 or the first isolation layer 180 .
  • the material of the second interlayer dielectric layer 190 may be the same as the material of the first interlayer dielectric layer 160
  • the material of the second isolation layer 200 may be the same as the material of the first isolation layer 180 .
  • the embodiment of the present disclosure can improve the ability of the word line 120 to control the channel region 112 by arranging the word line 120 on the top and bottom surfaces of the active area 110, and by arranging the bit line 130 on the Y row along two directions. between the adjacent active areas 110 of the cloth, and the same bit line 130 is in contact with the two adjacent active areas 110 , so that the adjacent active areas 110 along the second direction Y share the same bit line 130 , by arranging the capacitor 140 to extend along the second direction Y and the capacitor 140 covering the sidewall of the first doped region 111 away from the channel region 112, thereby realizing the stacking of semiconductor structures, which can improve the space utilization of the semiconductor structure and improve the efficiency of the semiconductor structure. Stacking density, increasing the number of capacitors 140.

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Abstract

本公开实施例提供一种半导体结构的制作方法及其结构，其中，半导体结构的制作方法包括：提供基底；形成有源区、字线、位线及电容，有源区包括沿第二方向排布的第一掺杂区、沟道区及第二掺杂区；字线包括第一字线及第二字线，第一字线位于沟道区的顶面，第二字线位于沟道区的底面；位线位于沿第二方向排布的相邻的有源区之间，位线覆盖第二掺杂区远离沟道区的侧壁；电容覆盖第一掺杂区远离沟道区的侧壁。

Description

一种半导体结构的制作方法及其结构
交叉引用
本公开要求于2022年07月13日递交的名称为“一种半导体结构的制作方法及其结构”、申请号为202210827394.2的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构的制作方法及其结构。
背景技术
随着半导体结构的不断发展，其关键尺寸不断减小，但由于光刻机的限制，其关键尺寸的缩小存在极限，因此如何在一片晶圆上做出更高存储密度的芯片，是众多科研工作者和半导体从业人员的研究方向。
二维或平面半导体器件中，存储单元均是水平方向上排列，因此，二维或平面半导体器件的集成密度可以由单位存储单元所占据的面积决定，则二维或平面半导体器件的集成密度极大地受到形成精细图案的技术影响，使得二维或平面半导体器件的集成密度的持续增大存在极限。因而，急需设计一种可以三维方向上堆叠设置存储单元的半导体结构。
发明内容
本公开实施例提供一种半导体结构的制作方法及其结构，至少可以提供一种在三维方向上堆叠的半导体结构，有利于提高半导体结构的空间利用率。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制作方法，包括：提供基底；形成有源区，所述有源区沿第一方向、第二方向及第三方向间隔排布，且所述有源区包括沿所述第二方向排布的第一掺杂区、沟道区及第二掺杂区；形成字线，所述字线沿所述第一方向延伸，所述字线包括第一字线及第二字线，所述第一字线位于所述沟道区的顶面，所述第二字线位于所述沟道区的底面；形成位线，所述位线位于沿所述第二方向排布的相邻的所述有源区之间，所述位线沿所述第三方向延伸，所述位线覆盖所述第二掺杂区远离所述沟道区的侧壁；形成电容，所述电容沿所述第二方向延伸，沿所述第三方向堆叠排布，且所述电容覆盖所述第一掺杂区远离所述沟道区的侧壁。
在一些实施例中，形成有源区的方法包括：在所述基底表面形成第一堆叠结构，所述第一堆叠结构包括沿所述第三方向上依次排布的第一层间介质层、初始有源区、第一层间介质层、第一隔离层；刻蚀所述初始有源区，以形成所述有源区。
在一些实施例中，刻蚀所述初始有源区的步骤包括：第一次刻蚀处理，所述第一次刻蚀处理，包括：刻蚀所述第一堆叠结构，以形成沿所述第一方向间隔排布的所述第一堆叠结构；形成第二堆叠结构，所述第二堆叠结构位于相邻的所述第一堆叠结构之间，所述第二堆叠结构包括沿所述第三方向上依次排布的第二层间介质层，第二隔离层，所述第二层间介质层与所述第一层间介质层接触连接，所述第二隔离层与所述初始有源区或者所述第一隔离层接触连接；第二次刻蚀处理，所述第二次刻蚀处理包括：刻 蚀所述第一堆叠结构及所述第二堆叠结构，以形成沿第二方向间隔排布的所述有源区。
在一些实施例中，所述第一层间介质层的材料与所述第二层间介质层的材料相同。
在一些实施例中，形成所述字线的步骤包括：沿所述第二方向刻蚀所述第一层间介质层，以形成第一凹槽，所述第一凹槽暴露所述有源区的所述沟道区的表面；形成初始字线，所述初始字线位于所述沟道区及所述第二掺杂区的表面；图形化所述初始字线，以暴露所述第二掺杂区的表面，剩余所述初始字线作为所述字线，其中，位于所述沟道区顶面的所述字线作为所述第一字线，位于所述沟道区底面的所述字线作为所述第二字线。
在一些实施例中，形成所述位线的步骤包括：形成第三隔离层，所述第三隔离层位于沿所述第二方向间隔排布的所述有源区之间，且覆盖所述第二掺杂区的表面；图形化所述第三隔离层，以形成第二凹槽，所述第二凹槽暴露所述第二掺杂区远离所述沟道区的侧壁；形成所述位线，所述位线填充满所述第二凹槽。
在一些实施例中，形成所述电容的步骤包括：刻蚀所述有源区，以形成第三凹槽；形成下极板，所述下极板覆盖所述第三凹槽的侧壁；形成电容介质层，所述电容介质层覆盖所述下极板的表面；形成上极板，所述上极板覆盖所述电容介质层的表面，且填充满所述第三凹槽。
在一些实施例中，刻蚀所述有源区包括：图形化所述第一堆叠结构，以暴露所述有源区远离所述字线的一侧表面；刻蚀所述有源区，以形成所述第三凹槽。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：基底；有源区，所述有源区沿第一方向、第二方向及第三方向间隔排布，且所述有源区包括沿所述第二方向排布的第一掺杂区、沟道区及第二掺杂区；字线，所述字线沿所述第一方向延伸，沿所述第三方向堆叠排布，且所述字线包括：第一字线及第二字线，所述第一字线位于所述沟道区的顶面，所述第二字线位于所述沟道区底面；位线，所述位线位于沿所述第二方向排布的相邻的所述有源区之间，，且同一所述位线与相邻的两个所述有源区接触连接，所述位线沿所述第三方向延伸，所述位线覆盖所述第二掺杂区远离所述沟道区的侧壁；电容，所述电容沿所述第二方向延伸，沿所述第三方向堆叠排布，且所述电容覆盖所述第一掺杂区远离所述沟道区的侧壁。
在一些实施例中，在所述第二方向上，所述位线的宽度小于相邻所述字线之间的间距。
在一些实施例中，沿所述第三方向间隔排布的所述有源区共用同一所述位线。
在一些实施例中，沿所述第一方向间隔排布的所述有源区共用同一所述字线。
在一些实施例中，还包括：第一层间介质层，所述第一层间介质层位于所述电容及所述有源区的顶面及底面。
在一些实施例中，还包括：第一隔离层，所述电容、与所述电容电连接的所述有源区及位于所述电容及所述有源区的顶面和底面的第一层间介质层构成一重复单元，在所述第三方向上，所述重复单元与所述第一隔离层交替排布。
在一些实施例中，所述电容包括：下极板，所述下极板包括与所述第一掺杂区接触的底面，及环绕所述底面边缘并沿所述第二方向延伸的侧面，所述底面与所述侧面围成有容纳空间；电容介质层，所述电容介质层覆盖所述容纳空间的内壁；上极板，所述上极板覆盖所述电容介质层的内壁，且所述上极板填充满所述容纳空间。
在一些实施例中，沿所述第三方向上排布的所述电容共用所述电容介质层及所述上极板。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例 性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图10为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图；
图11为本公开一实施例提供的一种半导体结构的结构示意图；
图12为本公开一实施例提供的另一种半导体结构的结构示意图。
具体实施方式
由背景技术可知，半导体结构中存储单元的集成密度有待提高。
本公开实施提供一种半导体结构的制作方法，通过形成位于有源区的沟道区顶面的第一字线及位于沟道区底面的第二字线以构成字线，形成位于第二掺杂区远离沟道区侧壁的位线，形成位于第一掺杂区远离沟道区侧壁的电容，以实现半导体结构的功能，且通过形成沿第一方向、第二方向及第三方向间隔排布的有源区，并分别在有源区的第一掺杂区、沟道区及第二掺杂区形成对应的电容、字线及位线从而形成在三维方向上堆叠设置半导体结构，从而可以提高半导体结构的空间利用率，进而提高半导体结构的堆叠密度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图1至图10，图1至图10为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图，其中图7为图6沿虚线方向的剖视图，图8至图10为在图7的基础上进行的后续的制作方法对应的结构示意图。
参考图1至图10，半导体结构的制作方法包括：提供基底100；形成有源区110，有源区110沿第一方向X、第二方向Y及第三方向Z间隔排布，且有源区110包括沿第二方向X排布的第一掺杂区111、沟道区112及第二掺杂区113；形成字线120，字线120沿第一方向X延伸，字线120包括第一字线121及第二字线122，第一字线121位于沟道区112的顶面，第二字线122位于沟道区112的底面；形成位线130，位线130位于沿第二方向Y排布的相邻的有源区110之间，位线130沿第三方向Z延伸，位线130覆盖第二掺杂区113远离沟道区112的侧壁；形成电容140，电容140沿第二方向Y延伸，沿第三方向Z堆叠排布，且电容140覆盖第一掺杂区111远离沟道区112的侧壁。通过设置字线120位于有源区110的沟道区112的表面，设置电容140位于第一掺杂区111远离沟道区112的侧壁，设置位线130位于第二掺杂区113远离沟道区112的侧壁从而实现半导体结构的存储，并通过设置有源区沿第一方向X、第二方向Y及第三方向Z间隔排布，设置位线130沿第三方向Z延伸，设置字线120沿第一方向X延伸，从而实现了半导体结构的堆叠，可以提高半导体结构的空间利用率。
参考图1至图4，形成有源区110的方法包括：在基底100表面形成第一堆叠结构150，第一堆叠结构150包括沿第三方向Z上依次排布的第一层间介质层160、初始有源区114、第一层间介质层160、第一隔离层180；刻蚀初始有源区114，以形成有源区110。
通过形成第一层间介质层160可以用于后续形成电容的支撑结构，从而可以避免电容140在半导体结构内有部分悬空，通过第一层间介质层160支撑电容从而可以避免电容出现断裂或者变形，从而可以提高半导体结构的可靠性，且通过形成第一层间 介质层160可以在后续刻蚀的过程中引导刻蚀液的流动，在后续刻蚀液流动时固定刻蚀液的流动路径，从而可以固定刻蚀方向，避免出现过刻蚀或者刻蚀偏移的情况。从而可以提高半导体结构的可靠性。
具体的，参考图1，在一些实施例中，沿第二方向Y上，基底100可以包括依次堆叠的衬底101和隔离层102，隔离层102用于实现衬底101与第一堆叠结构150之间的绝缘，避免第一堆叠结构150中的有源区110与衬底101之间产生漏电，有利于提高半导体结构的电学性能。
在一些实施例中，衬底101的材料可以是硅材料，隔离层102的材料可以是氧化硅或者氮化硅等绝缘材料。
参考图2，刻蚀初始有源区114的步骤包括：第一次刻蚀处理，第一次刻蚀处理包括：刻蚀第一堆叠结构150，以形成沿第一方向X间隔排布的第一堆叠结构150。通过刻蚀形成沿第一方向X间隔排布的第一堆叠结构150可以形成沿第一方向X排布的初始有源区114。
参考图3，形成第二堆叠结构210，第二堆叠结构210位于相邻的第一堆叠结构150之间，第二堆叠结构210包括沿第三方向Z上依次排布的第二层间介质层190，第二隔离层200，第二层间介质层190与第一层间介质层160接触连接，第二隔离层200与初始有源区114或者第一隔离层180接触连接。通过形成第二堆叠结构210可以填充刻蚀第一堆叠结构150形成的间隙，且通过第二堆叠结构210作为后续形成字线的支撑结构，从而可以避免形成字线出现变形，进而提高半导体结构的可靠性。
在一些实施例中，第二层间介质层190的材料可以与第一层间介质层160的材料相同，第二隔离层200的材料可以与第一隔离层180的材料相同，从而可以在后续刻蚀的过程在同一步中同时刻蚀第一层间介质层160及第二层间介质层190，在同一步中同时刻蚀第二隔离层200及第一隔离层180，从而减少半导体结构的形成方法的工艺步骤。本公开实施例中，第二隔离层200与第一隔离层180使用相同的填充进行示意。
在一些实施例中，在沿第三方向Z上，第二层间介质层190的厚度与第一层间介质层160的厚度相等，也就是说第二层间介质层190的顶面与第一层间介质层160的顶面齐平；第二隔离层200的厚度与第一隔离层180的厚度相等，也就是说，第二隔离层200的顶面与第一隔离层180的顶面齐平，从而可以形成形状规则的半导体结构。在一些实施例中，第二层间介质层的厚度也可以与第一层间介质层的厚度不相等，第二隔离层的厚度也可以与第一隔离层的厚度不相等，可以根据实际的生产需求进行调整。
在一些实施例中，在沿第三方向Z上，相邻的第一层间介质层160之间的厚度相等，如此可以在形成第一堆叠结构的过程中仅需控制相同的沉积速度及相同的沉积时间，从而可以形成厚度相等的第一层间介质层160，且在形成第二堆叠结构210的第二层间介质层190的过程中可以采用相同的工艺参数，从而可以在形成第一层间介质层160及第二层间介质层190的过程中不调整形成的参数，便于整个生产过程；在另一些实施例中，相邻的第一层间介质层160之间的厚度也可以不相等，相邻的第二层间介质层190的厚度也可以不相等，可以根据实际的生产需求进行调整。
在一些实施例中，在沿第三方向Z上，初始有源区114的厚度可以大于第一层间介质层160的厚度，在另一些实施例中，初始有源区的厚度也可以等于第一层间介质层的厚度；在又一些实施例中，初始有源区的厚度也可以小于第一层间介质层的厚度。可以根据实际的生产情况进行调整。通过控制初始有源区114的厚度大于第一层间介质层160的厚度可以使初始有源区114内具有较多的载流子可以提高初始有源区114的传输速率；通过形成初始有源的厚度等于第一层间介质层的厚度，可以在生产工艺中降低半导体结构的工艺复杂程度；通过形成初始有源区的厚度小于第一层间介质层的厚度可以提高相邻初始有源区之间的绝缘性。
在一些实施例中，初始有源区114的厚度大于第一隔离层180的厚度，也就 是说，后续在形成第二隔离层200的过程中，与初始有源区114接触连接的第二隔离层200的厚度大于与第一隔离层180连接的第二隔离层200的厚度，通过形成初始有源区114的厚度大于第一隔离层180的厚度可以提高初始有源区114内的载流子的数量，从而可以提高初始有源区114传输速率；在另一些实施例中，初始有源区114的厚度等于第一隔离层180的厚度，如此后续在形成第二隔离层200的过程中，可以不需要改变第二隔离层200的形成参数；在又一些实施例中，初始有源区的厚度还可以小于第一隔离层的厚度，可以根据实际情况进行调整，本公开不对初始有源区114及第一隔离层180的厚度进行限制。
可以理解的是，初始有源区114的厚度、第一层间介质层160及第一隔离层之间的厚度可以相等，也可以不同，可以根据实际情况进行调整，本公开图示部分的厚度不同仅是为了便于区分不同的膜层，并非对膜层之间的厚度关系进行限定。
参考图4，刻蚀初始有源区114的步骤还可以包括：第二次刻蚀处理，第二次刻蚀处理包括：刻蚀第一堆叠结构150及第二堆叠结构210，以形成沿第二方向Y间隔排布的有源区110，通过第二次刻蚀即可以形成沿第二方向Y间隔排布的有源区110，还可以为后续形成字线提供工艺基础。可以理解的是，沿第二方向Y间隔排布的有源区110是通过刻蚀同一初始有源区114形成的，故形成的有源区110呈对称分布，也就是说，相邻的有源区110中，其中一有源区110包括沿第二方向排布的第一掺杂区111、沟道区112及第二掺杂区113，另一有源区110包括：沿第二方向Y排布的第二掺杂区113、沟道区112及第一掺杂区111。
参考图4及图5，形成字线120的步骤可以包括：沿第二方向Y刻蚀第一层间介质层160，以形成第一凹槽220，第一凹槽220暴露有源区110的沟道区112的表面；形成初始字线，初始字线位于沟道区112及第二掺杂区113的表面；图形化初始字线，以暴露第二掺杂区113的表面，剩余初始字线作为字线120，其中，位于沟道区112顶面的字线120作为第一字线121，位于沟道区112底面的字线120作为第二字线122。
可以理解的是，在刻蚀第一层间介质层160的过程中还包括将与第一层间介质层160接触的第二层间介质层190一起刻蚀，也就是说在形成第一凹槽220的过程中，第一凹槽220还暴露与有源区110接触的第二隔离层200的顶面，如此，后续在形成字线120的过程中，形成沿第二方向连续的字线120，也就是说沿第二方向排布的有源区110共用字线120。
可以理解的是，由于位于有源区110上方的第一层间介质层160与位于有源区110下方的第一层间介质层160的材料相同，在刻蚀第一层间介质层160的时候同时暴露有源区110的沟道区112的顶面和底面，在沉积字线120的导电材料的过程中，形成的字线120同时覆盖沟道区112的顶面和底面，位于沟道区112顶面的字线120作为第一字线121，位于沟道区112底面的字线120作为第二字线122，通过形成第一字线121和第二字线122的方式可以增加字线120与有源区110之间的正对面积，从而可以提高字线120控制沟道区112的能力，提高半导体结构的性能。
在一些实施例中，形成第一凹槽220之后，形成字线120之前还包括：形成栅介质层(图中未示出)栅介质层覆盖有源区110的表面，从而可以避免字线120与有源区110直接接触连接。
在一些实施例中，栅介质层的材料可以是氧化硅或者氮化硅等绝缘材料。
参考图5至图7，形成位线130的步骤包括：形成第三隔离层230，第三隔离层230位于沿第二方向间隔排布的有源区110之间，且覆盖第二掺杂区113的表面；图形化第三隔离层230，以形成第二凹槽240，第二凹槽240暴露第二掺杂区113远离沟道区112的侧壁；形成位线130，位线130填充满第二凹槽240。
参考图5，形成第三隔离层230，在一些实施例中，第三隔离层230还覆盖在半导体结构的顶面，通过形成位于半导体结构顶面的第三隔离层230还可以在后续去除 位于第三隔离层230顶面的掩膜层的时候起到保护半导体结构的作用，还可以避免去除掩膜层试剂与半导体结构内部结构接触，可以提高半导体结构的可靠性。
第三隔离层230的材料可以是绝缘材料，例如氧化硅或者氮化硅等。
参考图6，在半导体结构的顶面形成掩膜层，掩膜层的图案暴露第三隔离层230的部分顶面，通过以掩膜层为掩膜刻蚀第三隔离层230以形成第二凹槽240，通过先形成掩膜层并通过掩膜刻蚀的方式形成第二凹槽240可以提高形成的第二凹槽240的图案精确性，从而可以提高半导体结构的可靠性，在一些实施例中，形成第二凹槽240之后还包括去除掩膜层。
参考图7，在一些实施例中，在形成第二凹槽240(参考图6)的过程中，可以先刻蚀位于第一隔离层180顶面的部分第三隔离层230，以暴露第一隔离层180的侧壁，然后再以第一隔离层180为掩膜继续刻蚀第三隔离层230，也就是说，在第二方向Y上，掩膜层的图案开口的宽度可以大于相邻有源区110之间的间隙。通过先在位于第一隔离层180顶面的部分第三隔离层230上形成较大开口的第二凹槽240，可以便于定位间隔的第一隔离层180，然后再以第一隔离层180为掩膜刻蚀第三隔离层230可以避免在刻蚀过程中刻蚀偏移，避免后续在形成位线130的过程中部分位线130未与有源区110的第二掺杂区113接触连接，从而可以提高半导体结构的制作工艺的可靠性。换句话说，通过先刻蚀位于第一隔离层180顶面的部分第三隔离层230，再以第一隔离层180为掩膜继续刻蚀第三隔离层230可以确保在形成第二凹槽240的过程中，形成的第二凹槽240暴露相邻有源区110的侧壁，从而可以在后续形成位线的时候确保位线与有源区110的电连接。
继续参考图7，形成位线130，可以理解的是，沿第二方向Y相邻的有源区110及沿第三方向Z上间隔排布的有源区110共用同一位线130。
在一些实施例中，在上述刻蚀第三隔离层230的过程中还保留部分与字线120侧壁接触的部分第三隔离层230，从而可以通过这部分被保留的第三隔离层230可以将字线120及位线130隔离，从而避免字线120与位线130接触，避免半导体结构出现异常，提高半导体结构的可靠性。
参考图8至图10，形成电容140的步骤包括：刻蚀有源区110，以形成第三凹槽250；形成下极板141，下极板141覆盖第三凹槽250的侧壁；形成电容介质层142，电容介质层142覆盖下极板141的表面；形成上极板143，上极板143覆盖电容介质层142的表面，且填充满第三凹槽250。
具体的，参考图8，图形化第一堆叠结构150，以暴露有源区110远离字线120的一侧表面；通过图形化第一堆叠结构150以形成第四凹槽260，通过形成第四凹槽260可以通过第四凹槽260暴露的有源区110表面进而刻蚀有源区110，从而为后续形成电容140提供工艺基础。
在一些实施例中，可以通过掩膜刻蚀的方式形成第四凹槽260，也就是说，可以先在第三隔离层230的表面形成掩膜，通过掩膜定义第四凹槽260的图案，在通过掩膜刻蚀的方式形成第四凹槽260，在形成第四凹槽260之后还包括去除第三隔离层230顶面的掩膜。
参考图9，刻蚀有源区，以形成第三凹槽250，通过形成第三凹槽250可以为后续形成电容提供工艺基础。
参考图10，形成电容140，在一些实施例中，沿第三方向Z上，电容140共用电容介质层142及上极板143，共用电容介质层142及上极板143的电容通过不共用的下极板141决定电容140的电容量，通过设置共用电容介质层142及上极板143的电容140可以便于生产工艺。
在一些实施例中，下极板141的材料可以包括氮化钛、氮化钽、铜或钨等金属材料中的任一种或任意组合；电容介质层142的材料可以包括：ZrO，AlO，ZrNbO， ZrHfO，ZrAlO中的任一种或其任一组合；上极板143的材料包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛、硅化钛、硅化镍、硅氮化钛或者其他导电材料，或者，上极板143的材料也可以为导电的半导体材料，如多晶硅，锗硅等。
可以理解的是，电容140的下极板141与上极板143之间的相对面积、下极板141及上极板143之间的距离及电容介质层142的材料都可能影响电容140的容量的大小，故可以根据实际的需求设置电容140的下极板141与上极板143之间的相对面积、下极板141及上极板143之间的距离及电容介质层142的材料。
在另一些实施例中，在形成电容介质层及上极板的过程中，还可以形成仅位于第三凹槽内的电容介质层及上极板，也就是说也可以形成在第三方向上不共用上电容介质层及上极板的电容，可以通过先形成填充满第三凹槽及第四凹槽的电容介质层及上极板，然后再刻蚀以暴露第四凹槽的方式形成在第三方向上不共用电容介质层及上极板的电容。
在一些实施例中，在形成电容介质层142后形成上极板143之前还包括：形成扩散阻挡层(图中未示出)，扩散阻挡层覆盖电容介质层142远离下极板141的表面，也就是说，上极板143覆盖扩散阻挡层远离电容介质层142的表面，通过扩散阻挡层阻挡上极板143中的导电元素向电容介质层142中扩散，避免降低上极板143的导电性能，且可以避免上极板143影响电容介质层142的绝缘性能。
在一些实施例中，扩散阻挡层的材料可以是氮化钛等金属化合物。
本公开实施例通过形成位于有源区110的沟道区112表面的字线120，形成位于第一掺杂区111远离沟道区112侧壁的电容140，形成位于第二掺杂区113远离沟道区112的侧壁的位线130从而实现半导体结构的存储，并通过设置有源区沿第一方向X、第二方向Y及第三方向Z间隔排布，设置位线130沿第三方向Z延伸，设置字线120沿第一方向X延伸，从而形成了半导体结构的堆叠，可以提高半导体结构的空间利用率。
本公开另一实施例还提供一种半导体结构，可以通过上述部分或者全部工艺步骤形成，以下将结合附图对本公开另一实施例提供的半导体结构进行说明，需要说明的是与前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图11、图12及图10，其中图11为本公开一实施例提供的一种半导体结构的示意图，图12为本公开一实施例提供的一种半导体结构的内部结构示意图。
参考图11、图12及图10，半导体结构包括：基底100；有源区110，有源区110沿第一方向X、第二方向Y及第三方向Z间隔排布，且有源区110包括沿第二方向Y排布的第一掺杂区111、沟道区112及第二掺杂区113；字线120，字线120沿第一方向X延伸，沿第三方向Z堆叠排布，且字线120包括：第一字线121及第二字线122，第一字线121位于沟道区112的顶面，第二字线122位于沟道区112底面；位线130，位线130位于沿第二方向Y排布的相邻的有源区110之间，且同一位线130与相邻的两个有源区110接触连接，位线130沿第三方向Z延伸，位线130覆盖第二掺杂区113远离沟道区112的侧壁；电容140，电容140沿第二方向Y延伸，沿第三方向Z堆叠排布，且电容140覆盖第一掺杂区111远离沟道区112的侧壁。
在一些实施例中，沿第一方向X间隔排布的有源区110共用同一字线120，通过设置第一方向X间隔排布的有源区110共用同一字线120可以减少布局字线120所需的空间，从而可以提高半导体结构的空间利用率，从而提高半导体结构的堆叠密度。
通过设置第一字线121位于沟道区112的顶面，第二字线122位于沟道区112底面，可以增加字线120与有源区110之间的接触面积，从而可以提高字线120控制沟道区112的能力，提高半导体结构的性能。
在一些实施例中，沿第三方向Z间隔排布的有源区110共用同一位线130。通过设置沿第三方向Z间隔排布的有源区110共用同一位线130可以减少布局位线130所需的空间，从而可以提高半导体结构的空间利用率，从而提高半导体结构的堆叠密度。
在一些实施例中，沿第二方向Y相邻的有源区110共用同一位线130，如图12所述，6个有源区110共用同一位线130，通过设置沿第二方向Y相邻的有源区共用同一位线130可以减少布局位线130所需的空间，从而可以提高半导体结构的空间利用率，从而提高半导体结构的堆叠密度，且相应的还可以提高位线130的面积，从而可以降低位线130自身的电阻，从而提高位线130的传输速率。
在一些实施例中，沿第二方向Y相邻的有源区110沿位于相邻有源区110之间的位线130成轴对称分布，也就是说，位于位线130一侧的有源区110包括沿第二方向排布的第一掺杂区111、沟道区112及第二掺杂区113，位于位线130另一侧的有源区110包括沿第二方向Y排布的第二掺杂区113、沟道区112及第一掺杂区111。
在一些实施例中，在第二方向Y上，位线130的宽度小于相邻字线120之间的间距。通过设置位线130的宽度小于相邻字线120之间的间距，从而可以将位线130与字线120进行隔离。
在一些实施例中，位线130与字线120之间还包括第三隔离层230，通过第三隔离层230将字线120与位线130进行隔离，从而可以避免字线120与位线130接触连接，避免半导体结构出现异常，从而可以提高半导体结构的可靠性。
在一些实施例中，电容140包括：下极板141，下极板141包括与第一掺杂区111接触的底面，及环绕底面边缘并沿第二方向Y延伸的侧面，底面与侧面围成有容纳空间；电容介质层142，电容介质层142覆盖容纳空间的内壁；上极板143，上极板143覆盖电容介质层142的内壁，且上极板143填充满容纳空间。换句话说，下极板141覆盖有源区110及位于有源区110顶面及底面的第一层间介质层160围成的空间的侧壁，电容介质层142覆盖下极板141的内壁，上极板143覆盖电容介质层142的内壁。
在一些实施例中，沿第三方向Z上排布的电容140共用电容介质层142及上极板143。共用电容介质层142及上极板143的电容通过不共用的下极板141决定电容140的容量，通过设置共用电容介质层142及上极板143的电容140可以便于生产工艺，且可以增加电容140的数量。
在一些实施例中，参考图12，沿第一方向X、第二方向及第三方向Z上分布的电容140共用上极板143，沿第一方向X及第三方向Z上分布的电容140共用电容介质层142，沿第一方向X排布的三个电容140共用电容介质层142及上极板143，沿第二方向Y上排布的两个电容140共用上极板143并不共用电容介质层142，(其中一个电容140与有源区110的连接示意出，另一个电容140与有源区110的连接并未示意出)及沿第三方向Z上排布的三个电容140共用电容介质层142及上极板143，也就是说沿第二方向Y排布的18个电容140共用同一上极板143，沿第二方向Y上排布的九个电容140共用同一电容介质层142。
在另一些实施例中，还可以将上极板及电容介质层设置为沿第一方向上间隔，也就是说沿第二方向排布的六个电容共用同一上极板，沿第二方向上排布的三个电容共用同一电容介质层；在又一些实施例中，还可以将上极板及电容介质层设置为沿第一方向上及第三方向上均间隔，也就是说电容之间并不共用上极板及电容介质层。
需要说明的是，上述共用上极板143及电容介质层142的电容140的数量是取决于沿第一方向X、第二方向Y及第三方向Z上排布的电容140的数量，换句话说，可以通过控制在不同方向排布的电容140的数量以控制共用上极板143及电容介质层142的电容数量，本公开实施例不对电容140的数量及排布方式进行限制，可以根据实际的需求进行调整。
在一些实施例中，上极板143和电容介质层142之间还包括扩散阻挡层(图中未示出)，通过扩散阻挡层阻挡上极板143中的导电元素向电容介质层142中扩散，避免降低上极板143的导电性能，且可以避免上极板143影响电容介质层142的绝缘性能。
在一些实施例中，还包括第一层间介质层160，第一层间介质层160位于电容140及有源区110的顶面及底面。通过形成第一层间介质层160可以起到支撑电容140及有源区110的作用，可以避免电容140及有源区110处于悬空，从而避免电容140及有源区110出现变形，可以提高半导体结构的可靠性。
在一些实施例中，还包括：第一隔离层180，电容140、与电容140电连接的有源区110及位于电容140及有源区110的顶面及底面的第一层间介质层160构成一重复单元，在第三方向Z上，重复单元与第一隔离层180交替排布。在第三方向Z上，通过设置第一隔离层180可以提高相邻有源区110之间的绝缘性，且可以将不同的重复单元间隔开，从而便于工艺生产。
在一些实施例中，还包括：第二堆叠结构210，第二堆叠结构210包括，在第三方向Z上依次堆叠的第二层间介质层190及第二隔离层200，且第二层间介质层190与第一层间介质层160接触连接，第二隔离层200与初始有源区114或者第一隔离层180接触连接，通过形成第二堆叠结构210可以在形成有源区110的过程中对半导体结构进行填充。
第二层间介质层190的材料可以与第一层间介质层160的材料相同，第二隔离层200的材料可以与第一隔离层180的材料相同。通过设置第二层间介质层190的材料与第一层间介质层160的材料相同，第二隔离层200的材料与第一隔离层180的材料相同可以在生产工艺中减少刻蚀试剂的种类。
本公开实施例通过提供一种半导体结构，通过设置字线120位于有源区110的顶面及底面可以提高字线120控制沟道区112的能力，通过设置位线130位于沿二方向Y排布的相邻的有源区110之间，且同一位线130与相邻的两个有源区110接触连接，从而使沿第二方向Y上相邻的有源区110共用同一位线130，通过设置电容140沿第二方向Y延伸且电容140覆盖第一掺杂区111远离沟道区112的侧壁，从而实现半导体结构的堆叠，可以提高半导体结构的空间利用率，提高半导体结构的堆叠密度，增加电容140的数量。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (16)

  1. 一种半导体结构的制作方法，包括：
    提供基底(100)；
    形成有源区(110)，所述有源区(110)沿第一方向(X)、第二方向(Y)及第三方向(Z)间隔排布，且所述有源区(110)包括沿所述第二方向(Y)排布的第一掺杂区(111)、沟道区(112)及第二掺杂区(113)；
    形成字线(120)，所述字线(120)沿所述第一方向(X)延伸，所述字线(120)包括第一字线(121)及第二字线(122)，所述第一字线(121)位于所述沟道区(112)的顶面，所述第二字线(122)位于所述沟道区(112)的底面；
    形成位线(130)，所述位线(130)位于沿所述第二方向(Y)排布的相邻的所述有源区(110)之间，所述位线(130)沿所述第三方向(Z)延伸，所述位线(130)覆盖所述第二掺杂区(113)远离所述沟道区(112)的侧壁；
    形成电容(140)，所述电容(140)沿所述第二方向(Y)延伸，沿所述第三方向(Z)堆叠排布，且所述电容(140)覆盖所述第一掺杂区(111)远离所述沟道区(112)的侧壁。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述有源区(110)的方法包括：
    在所述基底(100)表面形成第一堆叠结构(150)，所述第一堆叠结构(150)包括沿所述第三方向(Z)上依次排布的第一层间介质层(160)、初始有源区(114)、第一层间介质层(160)、第一隔离层(180)；
    刻蚀所述初始有源区(114)，以形成所述有源区(110)。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，刻蚀所述初始有源区(114)的步骤包括：第一次刻蚀处理，所述第一次刻蚀处理，包括：刻蚀所述第一堆叠结构(150)，以形成沿所述第一方向(X)间隔排布的所述第一堆叠结构(150)；
    形成第二堆叠结构(210)，所述第二堆叠结构(210)位于相邻的所述第一堆叠结构(150)之间，所述第二堆叠结构(210)包括沿所述第三方向(Z)上依次排布的第二层间介质层(190)，第二隔离层(200)，所述第二层间介质层(190)与所述第一层间介质层(160)接触连接，所述第二隔离层(200)与所述初始有源区(114)或者所述第一隔离层(180)接触连接；
    第二次刻蚀处理，所述第二次刻蚀处理包括：刻蚀所述第一堆叠结构(150)及所述第二堆叠结构(210)，以形成沿所述第二方向(Y)间隔排布的所述有源区(110)。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，所述第一层间介质层(160)的材料与所述第二层间介质层(190)的材料相同。
  5. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述字线(120)的步骤包括：
    沿所述第二方向(Y)刻蚀所述第一层间介质层(160)，以形成第一凹槽(220)，所述第一凹槽(220)暴露所述有源区(110)的所述沟道区(112)的表面；
    形成初始字线，所述初始字线位于所述沟道区(112)及所述第二掺杂区(113)的表面；
    图形化所述初始字线，以暴露所述第二掺杂区(113)的表面，剩余所述初始字线作为所述字线(120)，其中，位于所述沟道区(112)顶面的所述字线(120)作为所述第一字线(121)，位于所述沟道区(112)底面的所述字线(120)作为所述第二字线(122)。
  6. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述位线(130)的步骤包括：
    形成第三隔离层(230)，所述第三隔离层(230)位于沿所述第二方向(Y)间隔排布的所述有源区(110)之间，且覆盖所述第二掺杂区(113)的表面；
    图形化所述第三隔离层(230)，以形成第二凹槽(240)，所述第二凹槽(240)暴露所述第二掺杂区(113)远离所述沟道区(112)的侧壁；
    形成所述位线(130)，所述位线(130)填充满所述第二凹槽(240)。
  7. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述电容(140)的步骤包括：
    刻蚀所述有源区(110)，以形成第三凹槽(250)；
    形成下极板(141)，所述下极板(141)覆盖所述第三凹槽(250)的侧壁；
    形成电容介质层(142)，所述电容介质层(142)覆盖所述下极板(141)的表面；
    形成上极板(143)，所述上极板(143)覆盖所述电容介质层(142)的表面，且填充满所述第三凹槽(250)。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，刻蚀所述有源区(110)包括：图形化所述第一堆叠结构(150)，以暴露所述有源区(110)远离所述字线(120)的一侧表面；
    刻蚀所述有源区(110)，以形成所述第三凹槽(250)。
  9. 一种半导体结构，包括：
    基底(100)；
    有源区(110)，所述有源区(110)沿第一方向(X)、第二方向(Y)及第三方向(Z)间隔排布，且所述有源区(110)包括沿所述第二方向(Y)排布的第一掺杂区(111)、沟道区(112)及第二掺杂区(113)；
    字线(120)，所述字线(120)沿所述第一方向(X)延伸，沿所述第三方向(Z)堆叠排布，且所述字线(120)包括：第一字线(121)及第二字线(122)，所述第一字线(121)位于所述沟道区(112)的顶面，所述第二字线(122)位于所述沟道区(112)底面；
    位线(130)，所述位线(130)位于沿所述第二方向(Y)排布的相邻的所述有源区(110)之间，且同一所述位线(130)与相邻的两个所述有源区(110)接触连接，所述位线(130)沿所述第三方向(Z)延伸，所述位线(130)覆盖所述第二掺杂区(113)远离所述沟道区(112)的侧壁；
    电容(140)，所述电容(140)沿所述第二方向(Y)延伸，沿所述第三方向(Z)堆叠排布，且所述电容(140)覆盖所述第一掺杂区(111)远离所述沟道区(112)的侧壁。
  10. 根据权利要求9所述的半导体结构，其中，在所述第二方向(Y)上，所述位线(130)的宽度小于相邻所述字线(120)之间的间距。
  11. 根据权利要求9所述的半导体结构，其中，沿所述第三方向(Z)间隔排布的所述有源区(110)共用同一所述位线(130)。
  12. 根据权利要求9所述的半导体结构，其中，沿所述第一方向(X)间隔排布的所述有源区(110)共用同一所述字线(120)。
  13. 根据权利要求9所述的半导体结构，其中，还包括：第一层间介质层(160)，所述第一层间介质层(160)位于所述电容(140)及所述有源区(110)的顶面及底面。
  14. 根据权利要求13所述的半导体结构，其中，还包括：第一隔离层(180)，所述电容(140)、与所述电容(140)电连接的所述有源区(110)及位于所述电容(140)和所述有源区(110)的顶面及底面的所述第一层间介质层(160)构成一重复单元，在所述第三方向(Z)上，所述重复单元与所述第一隔离层(180)交替排布。
  15. 根据权利要求9所述的半导体结构，其中，所述电容(140)包括：
    下极板(141)，所述下极板(141)包括与所述第一掺杂区(111)接触的底面，及环绕所述底面边缘并沿所述第二方向(Y)延伸的侧面，所述底面与所述侧面围成有容纳空间；
    电容介质层(142)，所述电容介质层(142)覆盖所述容纳空间的内壁；
    上极板(143)，所述上极板(143)覆盖所述电容介质层(142)的内壁，且所述上极板 (143)填充满所述容纳空间。
  16. 根据权利要求15所述的半导体结构，其中，沿所述第三方向(Z)上排布的所述电容(140)共用所述电容介质层(142)及所述上极板(143)。
PCT/CN2023/098988 2022-07-13 2023-06-07 一种半导体结构的制作方法及其结构 WO2024012104A1 (zh)

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CN114373759A (zh) * 2020-10-15 2022-04-19 爱思开海力士有限公司 存储单元和具有该存储单元的半导体器件
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