WO2024082840A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
WO2024082840A1
WO2024082840A1 PCT/CN2023/116750 CN2023116750W WO2024082840A1 WO 2024082840 A1 WO2024082840 A1 WO 2024082840A1 CN 2023116750 W CN2023116750 W CN 2023116750W WO 2024082840 A1 WO2024082840 A1 WO 2024082840A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
channel
layer
along
grooves
Prior art date
Application number
PCT/CN2023/116750
Other languages
English (en)
French (fr)
Inventor
冯道欢
赵文礼
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024082840A1 publication Critical patent/WO2024082840A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for manufacturing the same.
  • the gate structure can surround the channel region of the transistor so that the transistor can maximize the control of the current therein.
  • the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the gate control capability of transistors and reducing power consumption.
  • an embodiment of the present disclosure provides a semiconductor structure, including: providing a substrate; forming a plurality of semiconductor columns extending along a first direction on the substrate, the semiconductor columns being arranged at intervals along a second direction and a third direction, the semiconductor columns including a first doping region, a channel region and a second doping region, the first doping region and the second doping region being located on opposite sides of the channel region, wherein the channel region includes a plurality of channel layers parallel to the planes where the third direction and the first direction are located; forming a plurality of word lines extending along the third direction, each word line connecting the channel regions of a plurality of semiconductor columns along the third direction, the word line covering at least a portion of the surface of the channel layer; the third direction is perpendicular to the surface of the substrate, the first direction intersects with the second direction and both are parallel to the surface of the substrate.
  • the word line after forming the word line, it also includes: forming multiple bit lines extending along the second direction, each bit line along the second direction connecting the first doped regions of multiple semiconductor columns; and/or forming a memory cell, the memory cell extending along the first direction and connected to the second doped region of the semiconductor column.
  • a plurality of semiconductor pillars extending along a first direction are formed on a substrate, including: forming a stacking structure on the substrate, the stacking structure including a sacrificial layer and a semiconductor layer alternately stacked along a third direction; etching the stacking structure to form a plurality of first grooves spaced apart along a second direction, the first grooves being located in the sacrificial layer and the semiconductor layer and extending along the first direction; filling an insulating layer in the first grooves; etching the semiconductor layer between the first grooves along the third direction to form a plurality of second grooves spaced apart along the second direction, the remaining semiconductor layer serving as semiconductor pillars, the second grooves being located at least between adjacent first grooves, and having a plurality of second grooves between adjacent first grooves, the semiconductor pillars located between the second grooves serving as channel layers, and the channel layers located between adjacent first grooves constituting channel regions.
  • a plurality of word lines extending along a third direction are formed, including: forming a gate dielectric layer, the gate dielectric layer covering the surface of the channel layer of the semiconductor column; filling a conductive layer in the second groove, the conductive layer covering the surface of the gate dielectric layer; patterning the conductive layer to form word lines and a plurality of third grooves extending along the first direction, the third grooves being located between adjacent word lines; and filling the third grooves with insulating material.
  • the method further includes: removing the sacrificial layer between the first grooves to form a second groove along the third groove.
  • the method further comprises: filling a conductive layer in the gap between adjacent semiconductor pillars in the direction; filling a conductive layer in the second groove; and filling the conductive layer in the gap.
  • the first groove after forming the first groove, it also includes: removing the sacrificial layer between the first grooves; filling the insulating layer in the first groove also includes: filling the gap between the first grooves with the insulating layer; after forming the second groove, it also includes: removing the insulating layer between the first grooves to form a gap between adjacent semiconductor pillars along a third direction; filling the conductive layer in the second groove, it also includes: filling the conductive layer in the gap.
  • the process of forming the first groove includes a dry etching process
  • the process of forming the second groove includes a dry etching process
  • a plurality of semiconductor pillars extending along a first direction and a plurality of word lines extending along a third direction are formed on a substrate, including: forming a stacking structure on the substrate, the stacking structure including sacrificial layers and semiconductor layers alternately stacked along the third direction; etching the stacking structure to form a plurality of channel trench groups spaced apart in a second direction, the channel trench groups being located within the stacking structure, the channel trench groups including a plurality of channel trenches, the semiconductor layers between adjacent channel trenches serving as channel layers, and the channel layers corresponding to the same channel trench group serving as channel regions; forming word lines within the channel trenches; etching the stacking structure to form a plurality of isolation trenches extending along the first direction, the isolation trenches being located between the channel trench groups, and the remaining semiconductor layers being semiconductor pillars; and filling the isolation trenches with isolation layers.
  • the method further includes: removing the sacrificial layer between the channel trenches in the channel trench group to form a gap; forming a word line in the channel trench, and further includes: filling the word line in the gap.
  • word lines are formed, including: forming a gate dielectric layer, the gate dielectric layer covers the surface of the channel layer of the semiconductor column; forming a conductive layer, the conductive layer covers the surface of the gate dielectric layer and fills the channel groove, the upper surface of the conductive layer is higher than the upper surface of the stacked structure; patterning the conductive layer to form word lines, the word lines correspond to the channel groove groups one by one and are arranged at intervals along the second direction.
  • the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate, and semiconductor columns located on the substrate and extending along a first direction, the semiconductor columns are arranged at intervals along a second direction and a third direction, the semiconductor column includes a first doping region, a channel region and a second doping region, the first doping region and the second doping region are located on opposite sides of the channel region, wherein the channel region includes a plurality of channel layers parallel to the planes where the third direction and the first direction are located; a plurality of word lines extending along the third direction, each word line connecting the channel regions of a plurality of semiconductor columns along the third direction, the word line covering at least a portion of the surface of the channel layer; the third direction is perpendicular to the surface of the substrate, the first direction intersects with the second direction and are both parallel to the surface of the substrate.
  • the semiconductor structure further includes: a plurality of bit lines extending along a second direction, each bit line along the second direction connecting a first doped region of a plurality of semiconductor columns; and/or a memory cell extending along the first direction and connected to a second doped region of the semiconductor column.
  • semiconductor columns, word lines, bit lines and memory cells constitute a memory array structure, and the memory array structure is arranged along a first direction on a substrate. In the first direction, two adjacent memory array structures are symmetrically arranged along the bit lines, and semiconductor columns located in the same layer in the two adjacent memory array structures are connected to the same bit line.
  • the word line surrounds the channel layer of the semiconductor pillar, or the word line is located on both sides of the channel layer along the second direction.
  • two sides of the channel layer along the third direction are insulating layers or sacrificial layers.
  • a ratio of a width of the channel layer to a width of the channel region is in a range of 0.2-0.6.
  • 1 to 16 are schematic structural diagrams corresponding to various steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of a semiconductor structure provided according to another embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is at least beneficial for improving the gate control capability of transistors and reducing power consumption.
  • FIG. 1 to FIG. 16 are schematic structural diagrams corresponding to various steps of the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure
  • FIG. 6 to FIG. 9 are schematic cross-sectional structural diagrams of FIG. 5 along the AA1 direction
  • FIG. 11 and FIG. 12 are schematic cross-sectional structural diagrams of FIG. 10 along the BB1 direction
  • FIG. 13 to FIG. 16 are schematic cross-sectional structural diagrams of FIG. 4 along the CC1 direction.
  • a method for manufacturing a semiconductor structure comprising:
  • a substrate 100 is provided.
  • the substrate 100 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.
  • a plurality of semiconductor pillars 101 extending along a first direction X are formed on a substrate (not shown in the figures), the semiconductor pillars 101 are arranged at intervals along a second direction Y and a third direction Z, the semiconductor pillars 101 include a first doped region I, a channel region II and a second doped region III, the first doped region I and the second doped region III are located on opposite sides of the channel region II, wherein the channel region II includes a plurality of channel layers 102 parallel to the plane where the third direction Z and the first direction X are located; a plurality of word lines 103 extending along the third direction Z are formed, each word line 103 along the third direction Z connects the channel region II of a plurality of semiconductor pillars 101, and the word line 103 covers at least a portion of the surface of the channel layer 102; the third direction Z is perpendicular to the substrate surface, the first direction X intersects with the second direction Y and is parallel to the substrate surface.
  • the angle between the first direction X and the second direction Y is 90°; in other embodiments, the angle between the first direction and the second direction may be 30°, 45° or 60°, and this embodiment does not constitute a limitation on the angle between the first direction and the second direction.
  • the material forming the semiconductor pillar 101 includes an elemental semiconductor material or a chemical Compound semiconductor materials. Elemental semiconductor materials may be germanium, silicon, selenium, boron, tellurium or antimony; compound semiconductor materials may be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide or gallium arsenic silicon. In other embodiments, the material forming the semiconductor pillar 101 may also include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide).
  • IGZO Indium Gallium Zinc Oxide
  • IWO Indium Tungsten Oxide
  • ITO Indium Tin Oxide
  • the first doping region I and the second doping region III are located on opposite sides of the channel region II.
  • the first doping region I and the second doping region III may both have P-type doping ions; in other embodiments, the first doping region I and the second doping region III may both have N-type doping ions.
  • the N-type ions may be phosphorus ions, arsenic ions, or antimony ions; and the P-type ions may be boron ions, indium ions, or boron fluoride ions.
  • a material forming the word line 103 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, molybdenum, titanium, or tungsten.
  • the method for manufacturing a semiconductor structure further includes: forming a plurality of bit lines 104 extending along a second direction Y, each bit line 104 connected to a first doping region I of a plurality of semiconductor pillars 101 along the second direction Y; and forming a storage unit 105, the storage unit 105 extending along a first direction X and connected to a second doping region III of the semiconductor pillar 101.
  • the control capability of the bit line 104 can be improved;
  • the formed storage unit 105 (for example, a columnar capacitor or a cup-shaped capacitor) extending along the first direction X and connected to the second doping region III of the semiconductor pillar 101 can extend the storage unit 105 in a direction parallel to the surface of the substrate 100, thereby facilitating an increase in the length of the storage unit 105 along the first direction X, so as to improve the charge storage capability of the storage unit 105, and compared with a storage unit perpendicular to the surface of the substrate 100, it can prevent the storage unit from being overly high and tipping over.
  • a plurality of semiconductor pillars 101 extending along a first direction X are formed on a substrate 100 , including:
  • a stacked structure 113 is formed on a substrate 100, and the stacked structure 113 includes sacrificial layers 111 and semiconductor layers 112 alternately stacked along a third direction Z; referring to Figure 5, the stacked structure 113 is etched to form a plurality of first grooves 124 spaced apart along a second direction Y, and the first grooves 124 are located in the sacrificial layers 111 and the semiconductor layers 112 and extend along the first direction X; and an insulating layer 114 is filled in the first grooves 124.
  • the stacking structure 113 includes 6 layers of alternatingly stacked sacrificial layers 111 and semiconductor layers 112, that is, the number of layers of the sacrificial layer 111 is 3 layers, and the number of layers of the semiconductor layer 112 is 3 layers; in other embodiments, the stacking structure may include 4 layers, 8 layers, 10 layers or 12 layers, or other numbers of alternatingly stacked sacrificial layers and semiconductor layers, that is, the number of layers of the sacrificial layers and the semiconductor layers are both 2 layers, 4 layers, 5 layers or 6 layers, etc. This embodiment does not constitute a limitation on the number of stacked layers of the sacrificial layers and the semiconductor layers in the stacking structure.
  • the material forming the sacrificial layer 111 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and the like.
  • the material forming the semiconductor layer 112 includes an elemental semiconductor material or a compound semiconductor material.
  • the elemental semiconductor material may be germanium, silicon, selenium, boron, tellurium or antimony; the compound semiconductor material may be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide or gallium arsenic silicon, etc.
  • the material forming the semiconductor layer 112 may also include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide) or ITO (Indium Tin Oxide).
  • the material forming the semiconductor layer 112 is the same as the material forming the substrate 100 ; in other embodiments, the material forming the semiconductor layer is different from the material forming the substrate.
  • the processes for forming the sacrificial layer 111 and the semiconductor layer 112 may be deposition processes, and the deposition processes may be chemical vapor deposition processes, physical vapor deposition processes, or atomic layer deposition processes, etc.
  • the processes for forming the sacrificial layer 111 and the semiconductor layer 112 may be epitaxial growth processes, and the epitaxial growth processes may be molecular beam epitaxial growth processes, atmospheric and reduced pressure epitaxial growth processes, or ultra-high vacuum chemical vapor deposition processes, etc.
  • the process of forming the first groove 124 includes a dry etching process. Since dry etching is anisotropic, the stacked structure 113 can be etched along the third direction Z by dry etching to form the first groove 124, and the first groove 124 penetrates the stacked structure 113 along the third direction Z, so that the formed semiconductor pillars 101 extend along the first direction X and are arranged along the third direction Z.
  • the material forming the insulating layer 114 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the semiconductor layer 112 and the sacrificial layer 111 between the first grooves 124 are etched along the third direction Z to form a plurality of second grooves 123 spaced apart along the second direction Y, the second grooves 123 being located at least between adjacent first grooves 124, and a plurality of second grooves 123 being provided between adjacent first grooves 124, the remaining semiconductor layer 112 serving as semiconductor columns 101, the semiconductor columns 101 located between the second grooves 123 serving as the channel layer 102, and the channel layer 102 located between adjacent first grooves 124 constituting the channel region II.
  • the process of forming the second groove 123 includes a dry etching process, and the second groove 123 penetrates the stack structure 113 along the third direction Z.
  • the etching direction of the second groove 123 and the first groove 124 can be the same, so that the formed channel layer 102 can be parallel to the plane where the first direction X and the third direction Z are located, which is conducive to the subsequent formation of the word line 103 extending along the third direction Z, and the channel regions II of multiple semiconductor pillars 101 along the third direction Z can be connected to the same word line 103.
  • part of the second groove 123 may also be located in the first groove 124.
  • the second groove 123 can expose two opposite surfaces of all the channel layers 102 along the second direction Y, and then when forming a word line, the contact area between the word line and the channel layer 102 is further increased, thereby increasing the contact area between the channel region of the transistor structure and the word line, and improving the gate control capability of the transistor.
  • a word line may be directly formed in the second groove, that is, along the third direction, both sides of the channel layer are sacrificial layers, thereby improving the manufacturing efficiency of the semiconductor structure.
  • the method further includes: removing the sacrificial layer 111 between the first grooves 124 to form a gap 115 between adjacent semiconductor pillars 101 along the third direction Z.
  • the word line can surround the surface of the channel layer 102, and the contact area between the word line and the channel layer 102 is further increased, thereby increasing the contact area between the channel region of the transistor structure and the word line, and thereby improving the gate control capability of the transistor.
  • the width of the second groove is equal to the width of the channel region, so that the word line formed after filling the conductive material in the second groove can pass through the channel layers in the channel region and cover the surface of the channel layer; therefore, in the first direction, the sacrificial layer and the semiconductor layer at both ends of the second groove are retained, and after the second groove is formed, when the sacrificial layer between the first grooves is removed, the remaining channel layer uses the semiconductor layer as a support structure to avoid collapse of the channel layer.
  • a plurality of word lines 103 extending along a third direction Z are formed, including: forming a gate dielectric layer 116, the gate dielectric layer 116 covers the surface of the channel layer 102 of the semiconductor pillar 101; filling a conductive layer 117 in the second groove 123, the conductive layer 117 is formed in the second groove 123, and the conductive layer 117 is formed in the second groove 123;
  • the conductive layer 117 covers the surface of the gate dielectric layer 116, and the upper surface of the conductive layer 117 is higher than the upper surface of the channel layer 102;
  • the conductive layer 117 is patterned to form a word line 103 and a plurality of third grooves 125 extending along the first direction X, and the third grooves 125 are located between adjacent word lines 103; and an insulating material is filled in the third grooves 125.
  • the gate dielectric layer 116 is formed to cover the surface of the semiconductor layer 112 and the conductive layer 117 covers the surface of the gate dielectric layer 116 to form a gate structure of the transistor; the conductive layer 117 is formed to fill the second groove 123 and then the conductive layer 117 is patterned, so that adjacent word lines 103 are separated, thereby avoiding the interconnection between adjacent word lines 103 along the second direction Y to cause a short circuit, and the word line 103 extends along the third direction Z, and the same word line 103 can control the transistors formed by multiple semiconductor pillars 101 along the third direction Z, thereby improving the control ability of the word line 103.
  • filling the second groove 123 with a conductive layer 117 also includes: filling the gap 115 with a conductive layer 117 .
  • the sacrificial layer 111 between the first grooves 124 may not be removed, and the word line 103 may be directly formed to improve the manufacturing efficiency of the semiconductor structure. Then, along the third direction, both sides of the channel layer are sacrificial layers, and the word line is located on two opposite sides of the channel layer along the second direction and two opposite sides of the sacrificial layer along the second direction.
  • the material forming the gate dielectric layer 116 includes silicon oxide, metal oxide, high-K material, etc.
  • the gate dielectric layer 116 is at least one of silicon dioxide, hafnium dioxide, aluminum oxide, zirconium dioxide, aluminum oxynitride, hafnium oxynitride, hafnium oxysilicate, or hafnium oxysilicon nitride.
  • the material forming the conductive layer 117 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, molybdenum, titanium, or tungsten.
  • the insulating material may be silicon oxide, silicon nitride or silicon oxynitride, etc.
  • the insulating material is the same as the material of the insulating layer and is represented by the same features. In other embodiments, the insulating material may be different from the material of the insulating layer.
  • removing the sacrificial layer 111 between the first grooves 124; and filling the insulating layer 114 in the first grooves 124 further includes: filling the gaps between the first grooves 124 with the insulating layer 114.
  • drawings provided in this embodiment are only partial structural schematic diagrams of the semiconductor structure, and other structures or material layers may be provided around the stacked structure 113. Therefore, when the sacrificial layer 111 between the first grooves 124 is removed, the other structures or material layers may serve as support structures for the remaining semiconductor layer 112 to avoid collapse of the semiconductor layer 112 after the sacrificial layer 111 is removed.
  • the semiconductor layer 112 and the insulating layer 114 between the first grooves 124 are etched along the third direction Z to form a plurality of second grooves 123 spaced apart along the second direction Y, the second grooves 123 are at least located between adjacent first grooves 124, and there are a plurality of second grooves 123 between adjacent first grooves 124, the semiconductor layer 112 located between the second grooves 123 serves as the channel layer 102, the channel layer 102 located between adjacent first grooves 124 constitutes the channel region II, and the remaining semiconductor layer 112 serves as the semiconductor column 101.
  • a plurality of word lines 103 extending along a third direction Z are formed, including: forming a gate dielectric layer 116, the gate dielectric layer 116 covers the surface of the channel layer 102 of the semiconductor column 101; filling a conductive layer 117 in the second groove 123, the conductive layer 117 covers the gate dielectric layer 116 surface, and the upper surface of the conductive layer 117 is higher than the upper surface of the stacked structure 113; the conductive layer 117 is patterned to form a word line 103 and a plurality of third grooves 125 extending along the first direction X, the third grooves 125 are located between adjacent word lines 103; and the third grooves 125 are filled with insulating material.
  • the two sides of the channel layer 102 are insulating layers 114, and the formed word line 103 only covers the two opposite surfaces of the channel layer 102 along the second direction Y, thereby reducing the manufacturing process of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure while satisfying the requirement of increasing the contact area between the word line 103 and the channel region II.
  • the following steps may be performed: removing the insulating layer 114 between the first grooves 124 to form a gap 115 between the semiconductor pillars 101 adjacent to each other along the third direction Z; filling the second groove 123 with a conductive layer, and further comprising: filling the gap 115 with a conductive layer.
  • a word line structure as shown in FIG. 9 is formed, so that the word line 103 formed by the conductive layer 117 surrounds the channel layer 102 of the semiconductor pillar 101, thereby increasing the contact area between the channel region II of the semiconductor pillar 101 and the word line 103, and improving the gate control capability of the transistor.
  • the method for forming a semiconductor column and a word line provided in the above embodiment may first form a semiconductor column extending in a first direction and in a second direction and a third direction, and then form a channel layer in a channel region of the semiconductor column and fill it with a conductive material to form a word line.
  • a channel layer and a word line covering a surface of the channel layer and extending in a third direction may be formed first, and then an isolation trench may be formed in the first direction to separate the word line and the semiconductor layer to form a plurality of semiconductor columns.
  • a plurality of semiconductor pillars 101 extending along a first direction X and a plurality of word lines 103 extending along a third direction Z are formed on the substrate 100, including: returning to Figure 4, a stacking structure 113 is formed on the substrate 100, the stacking structure 113 includes sacrificial layers 111 and semiconductor layers 112 alternately stacked along the third direction Z; referring to Figure 13, the stacking structure 113 is etched to form a plurality of channel groove groups 129 spaced apart in a second direction Y, the channel groove group 129 is located in the stacking structure 113, the channel groove group 129 includes a plurality of channel grooves 119, the semiconductor layer 112 between adjacent channel grooves 119 in the channel groove group 129 serves as a channel layer 102, and the channel layer 102 corresponding to the same channel groove group 129 serves as a channel region II.
  • the process of forming the channel grooves 119 includes a dry etching process.
  • the spacing between adjacent channel grooves 119 in the channel groove group 129 is smaller than the spacing between adjacent channel groove groups 129. It can be understood that dry etching is anisotropic, and by forming the channel grooves 119 by dry etching, all the channel grooves 119 in the channel groove group 129 can be formed along the third direction Z, so that the remaining semiconductor layer 112 between the remaining channel grooves 119 can be parallel to the plane where the first direction X and the third direction Z are located.
  • the method further includes: removing the sacrificial layer 111 between the channel trenches 119 in the channel trench group 129 to form a gap 115.
  • the method further includes: removing the sacrificial layer 111 between the channel trenches 119 in the channel trench group 129 to form a gap 115.
  • a word line 103 is formed in the channel groove 119.
  • forming the word line 103 may include: forming a gate dielectric layer 116, the gate dielectric layer 116 covers the surface of the channel layer 102 of the semiconductor pillar 101; forming a conductive layer 117, the conductive layer 117 covers the surface of the gate dielectric layer 116; and patterning the conductive layer 117 to form the word line 103, the word line 103 corresponds to the channel groove group 129 one by one and is arranged at intervals along the second direction Y.
  • Forming the conductive layer 117 to cover the surface of the gate dielectric layer 116 and patterning the conductive layer 117 can make the word line 103 and the channel groove group 129 have a certain shape.
  • the trench groups 129 correspond one to one, so that the word lines 103 extend along the third direction Z and are arranged at intervals in the second direction Y. Then, the same word line 103 can control transistors formed by multiple semiconductor pillars 101 along the third direction Z, thereby improving the control capability of the word line 103.
  • removing the sacrificial layer 111 between the channel trenches 119 in the channel trench group 129 to form the gap 115 is taken as an example. Then, forming the word line 103 in the channel trench 119 further includes: filling the gap 115 with a conductive layer 117 .
  • the sacrificial layer between the channel grooves 119 in the channel groove group 129 may not be removed, and the word line 103 may be directly formed, thereby improving the manufacturing efficiency of the semiconductor structure. Then, along the third direction, both sides of the channel layer are sacrificial layers, and the word line is located on two opposite sides of the channel layer along the second direction and two opposite sides of the sacrificial layer along the second direction.
  • the stacked structure 113 is etched to form a plurality of isolation trenches 135 extending along the first direction X.
  • the isolation trenches 135 are located between the channel trench groups 129 .
  • An isolation layer is filled in the isolation trenches 135 , and the remaining semiconductor layer 112 is a semiconductor column 101 .
  • the process of forming the isolation trench 135 includes a dry etching process. It is understood that dry etching is anisotropic, and by forming the isolation trench 135 by dry etching, the etching direction of the isolation trench 135 and the channel trench 119 can be the same, thereby separating the adjacent channel trench groups 129, and etching the stacked structure 113 to form the semiconductor pillar 101.
  • the material forming the isolation layer includes silicon oxide, silicon nitride or silicon oxynitride.
  • the number of channel layers in the channel region of the same semiconductor column is 4 layers, and the number of channel layers in the channel regions of different semiconductor columns is the same.
  • the number of channel layers in the channel region of the same semiconductor column can also be 2 layers, 3 layers, 5 layers or 8 layers, and the number of channel layers in the channel regions of different semiconductor columns can be different.
  • This embodiment does not constitute a limitation on the number of channel layers in the channel region of the same semiconductor column, nor does it constitute a limitation on the relationship between the number of channel layers in the channel regions of different semiconductor columns.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure can improve the arrangement density of the transistor structure formed by the semiconductor pillars 101 and improve the integration density of the semiconductor structure by forming a plurality of semiconductor pillars 101 extending along the first direction X, and the semiconductor pillars 101 are arranged along the second direction Y and the third direction Z.
  • the channel region II of the semiconductor pillar 101 includes a plurality of channel layers 102 parallel to the plane where the third direction Z and the first direction X are located, which can increase the surface area of the channel region II, thereby increasing the contact area between the word line 103 and the channel region II of the semiconductor pillar 101, improving the gate control capability of the transistor structure and reducing power consumption.
  • the word line 103 extends along the third direction Z, and each word line 103 along the third direction Z connects the channel region II of a plurality of semiconductor pillars 101, which can increase the control capability of the word line 103.
  • another embodiment of the present disclosure provides a semiconductor structure, which is at least conducive to improving the gate control capability of the transistor structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.
  • the semiconductor structure includes: a substrate (not shown in the figure), and a semiconductor column 101 located on the substrate and extending along a first direction X, the semiconductor column 101 is arranged at intervals along a second direction Y and a third direction Z, the semiconductor column 101 includes a first doping region I, a channel region II and a second doping region III, the first doping region I and the second doping region III are located on opposite sides of the channel region II, wherein the channel region II includes a plurality of channel layers 102 parallel to the plane where the third direction Z and the first direction X are located; a plurality of channels along the third direction
  • the word lines 103 extending from the third direction Z are connected to the channel regions II of the semiconductor pillars 101 , and the word lines 103 cover at least a portion of the surface of the channel layer 102 .
  • the third direction Z is perpendicular to the substrate surface, and the first direction X and the second direction Y intersect and are parallel to the substrate surface.
  • the semiconductor structure further includes: a plurality of bit lines 104 extending along the second direction Y, each bit line 104 connected to the first doping region I of the plurality of semiconductor pillars 101 along the second direction Y; and a memory cell 105, the memory cell 105 extending along the first direction X and connected to the second doping region III of the semiconductor pillar 101.
  • the bit line 104 extends along the second direction Y, and the same bit line 104 connects the first doping region I of the plurality of semiconductor pillars 101 along the second direction Y, which can improve the control capability of the bit line 104.
  • the memory cell 105 extends along the first direction X and is connected to the second doping region III of the semiconductor pillar 101, which can make the memory cell 105 extend in a direction parallel to the substrate surface, thereby facilitating the increase of the length of the memory cell 105 along the first direction X, so as to improve the charge storage capability of the memory cell 105, and compared with the memory cell perpendicular to the substrate surface, it can prevent the memory cell from being overly high and tipping over.
  • FIG. 17 is a schematic diagram of a semiconductor structure provided according to another embodiment of the present disclosure.
  • semiconductor pillars 101, word lines 103, bit lines 104, and memory cells 105 constitute a memory array structure (as shown in FIG. 2 ), and the memory array structure is arranged along a first direction X on a substrate (not shown in the figure), and in the first direction X, two adjacent memory array structures are symmetrically arranged along the bit lines 104, and semiconductor pillars 101 located in the same layer in two adjacent memory array structures are connected to the same bit line 104.
  • semiconductor pillars 101 located in the same layer in two adjacent memory array structures can be connected to the same bit line 104, thereby further enhancing the control capability of the bit line 104, and the corresponding control end of the bit line 104 can be reduced, thereby improving the space utilization of the semiconductor structure, and facilitating improving the integration density of the semiconductor structure.
  • the word line 103 may surround the channel layer 102 of the semiconductor pillar 101.
  • the word line 103 surrounding the channel layer 102 of the semiconductor pillar 101 may further increase the contact area between the word line 103 and the channel region II, thereby improving the gate control capability of the transistor structure.
  • the gate dielectric layer 116 surrounds the outer circumference of the channel layer 102 of the semiconductor pillar 101 .
  • the word line 103 includes a first portion contacting at least two sides of the channel layer 102 of the semiconductor column 112, and a second portion connected to multiple first portions connected to multiple channel layers 102 of the same semiconductor column 112, the second portion is located above the stacked structure, and the second portions of adjacent word lines 103 are separated by third grooves 125 filled with insulating material.
  • the word line 103 covers two opposite side surfaces of the channel layer 102 of the semiconductor pillar 112 along the second direction Y, and covers two opposite side surfaces of the filling insulating layer 114 between the channel layers 102 in the third direction Z along the second direction Y.
  • both sides of the channel layer along the third direction are insulating layers or sacrificial layers, and the insulating layers and sacrificial layers can serve as supports between the channel layers in the third direction to improve the stability of the semiconductor structure.
  • the ratio of the width of the channel layer 102 to the width of the channel region II is in the range of 0.2-0.6, for example, 0.2, 0.3, 0.4, 0.5 or 0.6, etc. It can be understood that multiple channel layers 102 of the same semiconductor column 101 constitute the channel region II, and the smaller the width of the channel layer 102 along the second direction Y, the greater the number of corresponding channel layers 102, and the larger the surface area of the channel layer 102 constituting the channel region II. However, if the channel layer 102 is too thin, it will result in that the first doped region I and the second doped region III along the first direction X cannot be electrically connected through the channel region II.
  • the width of the channel layer 102 is larger, it may be impossible to form multiple channel layers 102 in the same channel region II. Therefore, along the second direction Y, the ratio of the width of the channel layer 102 to the width of the channel region II needs to be within a certain range.
  • the row is adjusted to increase the contact area between the channel region II and the word line 103 while avoiding affecting the performance of the semiconductor structure.
  • the semiconductor structure provided by the embodiment of the present disclosure has a plurality of semiconductor pillars 101 extending along a first direction X, and the semiconductor pillars 101 are arranged along a second direction Y and a third direction Z, which can improve the arrangement density of the transistor structure formed by the semiconductor pillars 101 and improve the integration density of the semiconductor structure.
  • the channel region II of the semiconductor pillar 101 includes a plurality of channel layers 102 parallel to the plane where the third direction Z and the first direction X are located, which can increase the surface area of the channel region II, thereby increasing the contact area between the word line 103 and the channel region II of the semiconductor pillar 101, improving the gate control capability of the transistor structure and reducing power consumption.
  • the word line 103 extends along the third direction Z, and each word line 103 along the third direction Z connects the channel region II of a plurality of semiconductor pillars 101, which can increase the control capability of the word line 103.

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

公开了一种半导体结构及其制造方法，方法包括：在基底上形成沿第一方向延伸且沿第二方向和第三方向间隔排列的多个半导体柱，半导体柱包括第一掺杂区、沟道区和第二掺杂区，沟道区包括与第三方向和第一方向所在平面平行的多个沟道层。形成沿第三方向延伸的多条字线，沿第三方向上每一字线连接多个半导体柱的沟道区，字线覆盖沟道层至少部分表面。

Description

半导体结构及其制造方法
交叉引用
本公开要求于2022年10月21日递交的名称为“半导体结构及其制造方法”、申请号为202211296176.7的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制造方法。
背景技术
随着半导体器件的不断微缩，为了满足开启电压和饱和电流等需求，三维器件结构(例如，鳍式场效应晶体管FinFET和纳米线等)正在成为行业发展方向。三维器件结构中栅极结构可以包围晶体管的沟道区，以便晶体管对其中的电流进行最大化的控制。
在3D DRAM的研究过程中，也需要进一步探索提升栅控能力和降低功耗的方法。
发明内容
本公开实施例提供一种半导体结构及其制造方法，至少有利于提高晶体管的栅控能力和降低功耗。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：提供基底；于基底上形成多个沿第一方向延伸的半导体柱，半导体柱沿第二方向和第三方向间隔排列，半导体柱包括第一掺杂区、沟道区和第二掺杂区，第一掺杂区和第二掺杂区位于沟道区的相对两侧，其中，沟道区包括与第三方向和第一方向所在平面平行的多个沟道层；形成多条沿第三方向延伸的字线，沿第三方向上每一字线连接多个半导体柱的沟道区，字线覆盖沟道层至少部分表面；第三方向垂直于基底表面，第一方向与第二方向相交且均平行于基底表面。
在一些实施例中，在形成字线之后，还包括：形成多条沿第二方向延伸的位线，沿第二方向上每一位线连接多个半导体柱的第一掺杂区；和/或形成存储单元，存储单元沿第一方向延伸，且与半导体柱的第二掺杂区连接。
在一些实施例中，于基底上形成多个沿第一方向延伸的半导体柱，包括：于基底上形成堆叠结构，堆叠结构包括沿第三方向交替层叠的牺牲层和半导体层；刻蚀堆叠结构以形成多个沿第二方向相间隔的第一凹槽，第一凹槽位于牺牲层和半导体层内且沿第一方向延伸；于第一凹槽内填充绝缘层；沿第三方向刻蚀第一凹槽之间的半导体层，以形成多个沿第二方向相间隔的第二凹槽，剩余的半导体层作为半导体柱，第二凹槽至少位于相邻第一凹槽之间，且相邻的第一凹槽之间具有多个第二凹槽，位于第二凹槽之间的半导柱作为沟道层，位于相邻第一凹槽之间的沟道层构成沟道区。
在一些实施例中，形成多条沿第三方向延伸的字线，包括：形成栅介质层，栅介质层覆盖半导体柱的沟道层表面；于第二凹槽内填充导电层，导电层覆盖栅介质层表面；图形化导电层，以形成字线和多个沿第一方向延伸的第三凹槽，第三凹槽位于相邻的字线之间；于第三凹槽内填充绝缘材料。
在一些实施例中，在形成第二凹槽后，还包括：去除第一凹槽之间的牺牲层，以形成沿第三 方向相邻半导体柱之间的间隙；于第二凹槽内填充导电层，还包括：于间隙内填充导电层。
在一些实施例中，在形成第一凹槽之后还包括：去除第一凹槽之间的牺牲层；于第一凹槽内填充绝缘层还包括：于第一凹槽之间的间隙填充绝缘层；在形成第二凹槽后，还包括：去除第一凹槽之间的绝缘层以形成沿第三方向相邻半导体柱之间的间隙；于第二凹槽内填充导电层，还包括：于间隙内填充导电层。
在一些实施例中，形成第一凹槽的工艺包括干法刻蚀工艺，形成第二凹槽的工艺包括干法刻蚀工艺。
在一些实施例中，于基底上形成多个沿第一方向延伸的半导体柱以及形成多条沿第三方向延伸的字线，包括：于基底上形成堆叠结构，堆叠结构包括沿第三方向交替层叠的牺牲层和半导体层；刻蚀堆叠结构以形成多个在第二方向上相间隔的沟道沟槽组，沟道沟槽组位于堆叠结构内，沟道沟槽组包括多个沟道沟槽，相邻沟道沟槽之间的半导体层作为沟道层，对应同一沟道沟槽组的沟道层作为沟道区；于沟道沟槽内形成字线；刻蚀堆叠结构以形成多个沿第一方向延伸的隔离沟槽，隔离沟槽位于沟道沟槽组之间，剩余半导体层为半导体柱；于隔离沟槽内填充隔离层。
在一些实施例中，在形成沟道沟槽组后，还包括：去除沟道沟槽组内沟道沟槽之间的牺牲层以形成间隙；于沟道沟槽内形成字线，还包括：于间隙内填充字线。
在一些实施例中，形成字线，包括：形成栅介质层，栅介质层覆盖半导体柱的沟道层表面；形成导电层，导电层覆盖栅介质层的表面且填充于沟道沟槽内，导电层的上表面高于堆叠结构上表面；图形化导电层以形成字线，字线与沟道沟槽组一一对应且沿第二方向间隔排布。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：基底，以及位于基底上沿第一方向延伸的半导体柱，半导体柱沿第二方向和第三方向间隔排列，半导体柱包括第一掺杂区、沟道区和第二掺杂区，第一掺杂区和第二掺杂区位于沟道区的相对两侧，其中，沟道区包括与第三方向和第一方向所在平面平行的多个沟道层；多条沿第三方向延伸的字线，沿第三方向上每一字线连接多个半导体柱的沟道区，字线覆盖沟道层至少部分表面；第三方向垂直于基底表面，第一方向与第二方向相交且均平行于基底表面。
在一些实施例中，半导体结构还包括：多条沿第二方向延伸的位线，沿第二方向上每一位线连接多个半导体柱的第一掺杂区；和/或存储单元，存储单元沿第一方向延伸，且与半导体柱的第二掺杂区连接。
在一些实施例中，半导体柱、字线、位线和存储单元构成存储阵列结构，存储阵列结构在基底上沿第一方向排列，在第一方向上，相邻两个存储阵列结构沿位线对称设置，且相邻两个存储阵列结构中位于同一层的半导体柱连接同一位线。
在一些实施例中，字线环绕半导体柱的沟道层，或所述字线位于所述沟道层的沿所述第二方向的两侧。
在一些实施例中，沟道层沿第三方向上的两侧为绝缘层或牺牲层。
在一些实施例中，在第二方向上，沟道层的宽度与沟道区的宽度之比范围为0.2-0.6。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动新的前提下，还可以根据这些附图获得其他的附图。
图1至图16为本公开一实施例提供的半导体结构的制造方法各个步骤对应的结构示意图；
图17为本公开另一实施例提供的一种半导体结构的示意图。
具体实施方式
由背景技术可知，在3D DRAM的研究过程中也需要进一步探索提升栅控能力和降低功耗的方法。
根据本公开一些实施例，本公开一实施例提供一种半导体结构的制造方法，至少有利于提高晶体管的栅控能力和降低功耗。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1至图16为本公开实施例提供的半导体结构的制造方法各个步骤对应的结构示意图，图6至图9为图5沿AA1方向的剖面结构示意图，图11和图12为图10沿BB1方向的剖面结构示意图，图13至图16为图4沿CC1方向的剖面结构示意图，以下将结合附图对本实施例提供的半导体结构的制造方法进行详细说明，具体如下：
半导体结构的制造方法，包括：
参考图1，提供基底100。
对于基底100，形成基底100的材料可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
参考图2及图3，于基底(图中未示出)上形成多个沿第一方向X延伸的半导体柱101，半导体柱101沿第二方向Y和第三方向Z间隔排列，半导体柱101包括第一掺杂区I、沟道区II和第二掺杂区III，第一掺杂区I和第二掺杂区III位于沟道区II的相对两侧，其中，沟道区II包括与第三方向Z和第一方向X所在平面平行的多个沟道层102；形成多条沿第三方向Z延伸的字线103，沿第三方向Z上每一字线103连接多个半导体柱101的沟道区II，字线103覆盖沟道层102至少部分表面；第三方向Z垂直于基底表面，第一方向X与第二方向Y相交且均平行于基底表面。
需要说明的是，在本实施例中，第一方向X与第二方向Y的夹角为90°；在其他实施例中，第一方向与第二方向的夹角可以为30°、45°或者60°，本实施例并不构成对第一方向和第二方向之间的夹角的限定。
对于半导体柱101，在一些实施例中，形成半导体柱101的材料包括元素半导体材料或者化 合物半导体材料。元素半导体材料可以锗、硅、硒、硼、碲或者锑；化合物半导体材料可以为砷化镓、磷化锢、锑化锢、碳化硅、硫化镉或者镓砷硅等。在另一些实施例中，形成半导体柱101的材料还可以包括IGZO(铟镓锌氧化物，Indium Gallium Zinc Oxide)、IWO(掺钨氧化铟，Indium Tungsten Oxide)或者ITO(氧化铟锡，Indium Tin Oxide)的至少一种。
对于第一掺杂区I和第二掺杂区III，第一掺杂区I和第二掺杂区III位于沟道区II的相对两侧，在一些实施例中，第一掺杂区I和第二掺杂区III可以均具有P型掺杂离子；在另一些实施例中，第一掺杂区I和第二掺杂区III可以均具有N型掺杂离子。其中，N型离子具体可以为磷离子、砷离子或者锑离子；P型离子具体可以为硼离子、铟离子或者氟化硼离子。
对于字线103，形成字线103的材料包括多晶硅、氮化钛、铝化钛、氮化钽、硅化镍、硅化钴、钽、铜、铝、钼、钛或者钨中的至少一种。
在一些实施例中，半导体结构的制造方法还包括：形成多条沿第二方向Y延伸的位线104，沿第二方向Y上每一位线104连接多个半导体柱101的第一掺杂区I；形成存储单元105，存储单元105沿第一方向X延伸，且与半导体柱101的第二掺杂区III连接。通过形成沿第二方向Y延伸的位线104，且同一位线104连接第二方向Y上多个半导体柱101的第一掺杂区I，可以提高位线104的控制能力；形成的存储单元105(例如柱状电容器、杯状电容器)沿第一方向X延伸，且与半导体柱101的第二掺杂区III连接，可以使存储单元105沿与基底100表面平行的方向延伸，从而有利于增加存储单元105沿第一方向X上的长度，以提高存储单元105的电荷存储能力，相较于垂直于基底100表面的存储单元，可以避免存储单元的高度过高发生倾倒。
参考图4至图7，在一些实施例中，于基底100上形成多个沿第一方向X延伸的半导体柱101，包括：
参考图4，于基底100上形成堆叠结构113，堆叠结构113包括沿第三方向Z交替层叠的牺牲层111和半导体层112；参考图5，刻蚀堆叠结构113以形成多个沿第二方向Y相间隔的第一凹槽124，第一凹槽124位于牺牲层111和半导体层112内且沿第一方向X延伸；于第一凹槽124内填充绝缘层114。
对于堆叠结构113，在本实施例提供的附图中，堆叠结构113包括6层交替层叠的牺牲层111和半导体层112，即牺牲层111的层数为3层，半导体层112的层数为3层；在其他实施例中，堆叠结构可以包括4层、8层、10层或者12层等其他数量交替层叠的牺牲层和半导体层，即牺牲层和半导体层的层数均为2层、4层、5层或者6层等，本实施例不构成对堆叠结构中牺牲层和半导体层堆叠层数的限定。
对于牺牲层111，形成牺牲层111的材料包括硅、锗、锗化硅、碳化硅和砷化镓等。
对于半导体层112，形成半导体层112的材料包括元素半导体材料或者化合物半导体材料。元素半导体材料可以锗、硅、硒、硼、碲或者锑；化合物半导体材料可以为砷化镓、磷化锢、锑化锢、碳化硅、硫化镉或者镓砷硅等。在另一些实施例中，形成半导体层112的材料还可以包括IGZO(铟镓锌氧化物，Indium Gallium Zinc Oxide)、IWO(掺钨氧化铟，Indium Tungsten Oxide)或者ITO(氧化铟锡，Indium Tin Oxide)的至少一种。
在一些实施例中，形成半导体层112的材料与形成基底100的材料相同；在另一些实施例中，形成半导体层的材料与形成基底的材料不同。
在一些实施例中，形成牺牲层111和半导体层112的工艺均可以是沉积工艺，沉积工艺可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺等。在另一些实施例中，形成牺牲层111和半导体层112的工艺均可以是外延生长工艺，外延生长工艺可以是分子束外延生长工艺、常压及减压外延生长工艺或者超高真空化学气相沉积工艺等。
对于第一凹槽124，形成第一凹槽124的工艺包括干法刻蚀工艺。由于干法刻蚀为各向异性，通过干法刻蚀可以沿第三方向Z刻蚀堆叠结构113而形成第一凹槽124，第一凹槽124沿第三方向Z贯穿堆叠结构113，从而使形成的半导体柱101沿第一方向X延伸且沿第三方向Z排列。
对于绝缘层114，形成绝缘层114的材料包括氧化硅、氮化硅或者氮氧化硅等。
参考图6，沿第三方向Z刻蚀第一凹槽124之间的半导体层112和牺牲层111，以形成多个沿第二方向Y相间隔的第二凹槽123，第二凹槽123至少位于相邻第一凹槽124之间，且相邻的第一凹槽124之间具有多个第二凹槽123，剩余的半导体层112作为半导体柱101，位于第二凹槽123之间的半导体柱101作为沟道层102，位于相邻第一凹槽124之间的沟道层102构成沟道区II。
对于第二凹槽123，形成第二凹槽123的工艺包括干法刻蚀工艺，第二凹槽123沿第三方向Z贯穿堆叠结构113。通过干法刻蚀可以使第二凹槽123与第一凹槽124的刻蚀方向相同，从而使形成的沟道层102可以与第一方向X和第三方向Z所在的平面平行，进而以后利于后续形成沿第三方向Z延伸的字线103，且沿第三方向Z上多个半导体柱101的沟道区II可以连接同一字线103。
参考图7，在另一些实施例中，部分第二凹槽123还可以位于第一凹槽124内。通过形成部分第二凹槽123位于第一凹槽124内，可以使第二凹槽123暴露出所有沟道层102沿第二方向Y上相对的两个表面，进而在形成字线时，字线与沟道层102的接触面积进一步增加，提高晶体管结构的沟道区与字线的接触面积，提高晶体管的栅控能力。
在一些实施例中，在形成第二凹槽之后，可以直接在第二凹槽内形成字线，即沿第三方向上，沟道层的两侧为牺牲层，从而提高半导体结构的制造效率。
在一些实施例中，参考图8，在形成第二凹槽123后，还包括：去除第一凹槽124之间的牺牲层111，以形成沿第三方向Z相邻半导体柱101之间的间隙115。去除第一凹槽124之间的牺牲层111，可以暴露出沟道层102沿第三方向Z的相对两个表面，进而在形成字线的过程中，字线可以环绕沟道层102的表面，字线与沟道层102的接触面积进一步增加，提高晶体管结构的沟道区与字线的接触面积，进而提高晶体管的栅控能力。
可以理解的是，在第一方向上，第二凹槽的宽度与沟道区的宽度相等，以便于在第二凹槽内填充导电材料后形成的字线能够穿过沟道区内的沟道层之间，并覆盖沟道层的表面；因此，在第一方向上，第二凹槽两端的牺牲层和半导体层保留，在形成第二凹槽后，去除第一凹槽之间的牺牲层时，剩余的沟道层以半导体层作为支撑结构，避免沟道层发生坍塌。
参考图9，在一些实施例中，形成多条沿第三方向Z延伸的字线103，包括：形成栅介质层116，栅介质层116覆盖半导体柱101的沟道层102表面；于第二凹槽123内填充导电层117，导电 层117覆盖栅介质层116表面，且导电层117的上表面高于沟道层102的上表面；图形化导电层117，以形成字线103和多个沿第一方向X延伸的第三凹槽125，第三凹槽125位于相邻的字线103之间；于第三凹槽125内填充绝缘材料。形成栅介质层116覆盖半导体层112的表面且导电层117覆盖栅介质层116表面，以形成晶体管的栅极结构；形成导电层117填充第二凹槽123后再图形化导电层117，可以使相邻的字线103之间分隔开，从而避免沿第二方向Y上相邻的字线103之间相互连通导致短路，且字线103沿第三方向Z延伸，同一字线103可以沿第三方向Z控制多个半导体柱101形成的晶体管，提高字线103的控制能力。
在图9中，以在形成第二凹槽123后，去除第凹槽12之间的牺牲层111，以形成沿第三方向Z相邻半导体柱101之间的间隙115为例，则在第二凹槽123内填充导电层117，还包括：于间隙115内填充导电层117。
在一些实施例中，在形成第二凹槽123之后，可以不去除第凹槽124之间的牺牲层111，直接形成字线103以提高半导体结构的制造效率，则在沿第三方向上，沟道层的两侧为牺牲层，字线位于沟道层沿第二方向上相对的两个侧面以及牺牲层沿第二方向上相对的两个侧面。
对于栅介质层116，形成栅介质层116的材料包括硅氧化物、金属氧化物、高K材料等。例如，栅介质层116为二氧化硅、二氧化铪、氧化铝、二氧化锆、氮氧化铝、氮氧化铪、矽酸铪氧化合物或者氮氧矽铪化合物的至少其中一种。
对于导电层117，形成导电层117的材料包括多晶硅、氮化钛、铝化钛、氮化钽、硅化镍、硅化钴、钽、铜、铝、钼、钛或者钨中的至少一种。
对于绝缘材料，绝缘材料可以是氧化硅、氮化硅或者氮氧化硅等。在本实施例中，绝缘材料与绝缘层的材料相同，并以相同的特征表示。在其他实施例中，绝缘材料可以与绝缘层的材料不同。
参考图10至图12，在另一些实施例中，在形成第一凹槽124之后还包括：参考图10，去除第一凹槽124之间的牺牲层111；于第一凹槽124内填充绝缘层114还包括：于第一凹槽124之间的间隙填充绝缘层114。去除第一凹槽124之间的牺牲层111，并在第一凹槽124之间的间隙内填充绝缘层114，如此，可以使后续形成的半导体柱101之间通过绝缘层114分隔开，从而避免相邻的半导体柱101之间相互影响，提高半导体结构的稳定性。
可以理解的是，本实施例提供的附图仅为半导体结构中的部分结构示意图，在堆叠结构113的周围还可以具有其他的结构或者材料层，进而在去除第一凹槽124之间的牺牲层111时，其他的结构或者材料层可以作为剩余半导体层112的支撑结构，避免去除牺牲层111之后半导体层112发生坍塌。
参考图11，沿第三方向Z刻蚀第一凹槽124之间的半导体层112和绝缘层114，以形成多个沿第二方向Y相间隔的第二凹槽123，第二凹槽123至少位于相邻第一凹槽124之间，且相邻的第一凹槽124之间具有多个第二凹槽123，位于第二凹槽123之间的半导体层112作为沟道层102，位于相邻第一凹槽124之间的沟道层102构成沟道区II，剩余的半导体层112作为半导体柱101。
参考图12，形成多条沿第三方向Z延伸的字线103，包括：形成栅介质层116，栅介质层116覆盖半导体柱101的沟道层102表面；于第二凹槽123内填充导电层117，导电层117覆盖栅介质层 116表面，且导电层117的上表面高于堆叠结构113的上表面；图形化导电层117，以形成字线103和多个沿第一方向X延伸的第三凹槽125，第三凹槽125位于相邻的字线103之间；于第三凹槽125内填充绝缘材料。
通过图10至图12所示的半导体柱以及字线的形成方法，在沿第三方向Z上，沟道层102的两侧为绝缘层114，形成的字线103仅覆盖于沟道层102沿第二方向Y上的相对两个表面，从而在满足提高字线103与沟道区II接触面积的情况下，减少半导体结构的制作工艺过程，提高半导体结构的制作效率。
在一些实施例中，在形成第二凹槽123后，还可以包括：去除第一凹槽124之间的绝缘层114以形成沿第三方向Z相邻半导体柱101之间的间隙115；于第二凹槽123内填充导电层，还包括：于间隙115内填充导电层。从而形成如图9所示的字线结构，使导电层117形成的字线103环绕半导体柱101的沟道层102，从而提高半导体柱101沟道区II与字线103的接触面积，提高晶体管的栅控能力。
上述实施例中提供的形成半导体柱以及字线的方法，可以先形成沿第一方向延伸，且沿第二方向和第三方向的半导体柱，再在半导体柱的沟道区形成沟道层并填充导电材料以形成字线。在另一些实施例中，可以先形成沟道层以及覆盖沟道层表面且沿第三方向延伸的字线，再沿第一方向形成隔离槽将字线和半导体层分隔开，以形成多个半导体柱。
例如，参考图4以及图13至图16，于所述基底100上形成多个沿第一方向X延伸的半导体柱101以及形成多条沿第三方向Z延伸的字线103，包括：返回参考图4，于基底100上形成堆叠结构113，堆叠结构113包括沿第三方向Z交替层叠的牺牲层111和半导体层112；参考图13，刻蚀堆叠结构113以形成多个在第二方向Y上相间隔的沟道沟槽组129，沟道沟槽组129位于堆叠结构113内，沟道沟槽组129包括多个沟道沟槽119，沟道沟槽组129内相邻沟道沟槽119之间的半导体层112作为沟道层102，对应同一沟道沟槽组129的沟道层102作为沟道区II。
在一些实施例中，形成沟道沟槽119的工艺包括干法刻蚀工艺。沟道沟槽组129内相邻沟道沟槽119之间的间距小于相邻沟道沟槽组129之间的间距。可以理解的是，干法刻蚀为各向异性，通过干法刻蚀形成沟道沟槽119，可以使沟道沟槽组129内的所有沟道沟槽119均沿第三方向Z形成，从而剩余沟道沟槽119之间剩余的半导体层112可以均与第一方向X和第三方向Z所在的平面平行。
参考图14，在一些实施例中，在形成沟道沟槽组129后，还包括：去除沟道沟槽组129内沟道沟槽119之间的牺牲层111以形成间隙115。通过去除沟道沟槽组129内沟道沟槽119之间的牺牲层111形成间隙115，可以暴露出沟道层102沿第三方向Z的相对两个表面，进而在间隙115内填充导电层形成的字线时，字线可以环绕沟道层102的表面，提高晶体管结构的沟道区II与字线的接触面积，进而提高晶体管的栅控能力。
参考图15，于沟道沟槽119内形成字线103。例如，形成字线103可以包括：形成栅介质层116，栅介质层116覆盖半导体柱101的沟道层102表面；形成导电层117，导电层117覆盖栅介质层116的表面；图形化导电层117以形成字线103，字线103与沟道沟槽组129一一对应且沿第二方向Y间隔排布。形成导电层117覆盖栅介质层116表面并图形化导电层117，可以使字线103与沟道 沟槽组129一一对应，使字线103沿第三方向Z延伸，且在第二方向Y间隔排布，则同一字线103可以沿第三方向Z控制多个半导体柱101形成的晶体管，提高字线103的控制能力。
在图15中，以在形成沟道沟槽组129后，去除沟道沟槽组129内沟道沟槽119之间的牺牲层111以形成间隙115为例，则在沟道沟槽119内形成字线103，还包括：于间隙115内填充导电层117。
在一些实施例中，在形成沟道沟槽组129后，可以不去除沟道沟槽组129内沟道沟槽119之间的牺牲层，直接形成字线103，从而提高半导体结构的制造效率，则在沿第三方向上，沟道层的两侧为牺牲层，字线位于沟道层沿第二方向上相对的两个侧面以及牺牲层沿第二方向上相对的两个侧面。
参考图16，刻蚀堆叠结构113以形成多个沿第一方向X延伸的隔离沟槽135，隔离沟槽135位于沟道沟槽组129之间；于隔离沟槽135内填充隔离层，剩余半导体层112为半导体柱101。
在一些实施例中，形成隔离沟槽135的工艺包括干法刻蚀工艺。可以理解的是，干法刻蚀为各向异性，通过干法刻蚀形成隔离沟槽135，可以使隔离沟槽135与沟道沟槽119的刻蚀形成方向相同，从而将相邻的沟道沟槽组129分隔开，同时刻蚀堆叠结构113以形成半导体柱101。
对于隔离层，形成隔离层的材料包括氧化硅、氮化硅或者氮氧化硅等。
需要说明的是，在本公开实施例中，同一半导体柱的沟道区中沟道层的层数为4层，且不同半导体柱的沟道区中沟道层的数量相同。在其他实施例中，同一半导体柱的沟道区中沟道层的数量还可以是2层、3层、5层或者8层，不同半导体柱的沟道区中沟道层的数量可以不同，本实施例不构成对同一半导体柱的沟道区中沟道层的数量的限定，也不构成对不同半导体柱的沟道区中沟道层数量关系的限定。
本公开实施例提供的半导体结构的制造方法，通过形成沿第一方向X延伸的多个半导体柱101，且半导体柱101沿第二方向Y和第三方向Z排列，可以提高半导体柱101形成的晶体管结构的排列密度，提高半导体结构的集成密度。半导体柱101的沟道区II包括与第三方向Z和第一方向X所在平面平行的多个沟道层102，可以使沟道区II的表面积增加，从而字线103与半导体柱101的沟道区II接触面积增加，提高了晶体管结构的栅控能力并降低功耗。字线103沿第三方向Z延伸，且沿第三方向Z上每一字线103连接多个半导体柱101的沟道区II，可以使字线103的控制能力增加。
根据本公开一些实施例，本公开另一实施例提供一种半导体结构，至少有利于提高晶体管结构的栅控能力。需要说明的是，与上述实施例相同或者相应的部分，可参考前述实施例的相应说明，以下将不做详细赘述。
以下将结合附图对本实施例提供的半导体结构进行详细说明，具体如下：
继续参考图2和图3，半导体结构，包括：基底(图中未示出)，以及位于基底上沿第一方向X延伸的半导体柱101，半导体柱101沿第二方向Y和第三方向Z间隔排列，半导体柱101包括第一掺杂区I、沟道区II和第二掺杂区III，第一掺杂区I和第二掺杂区III位于沟道区II的相对两侧，其中，沟道区II包括与第三方向Z和第一方向X所在平面平行的多个沟道层102；多条沿第三方向 Z延伸的字线103，沿第三方向Z上每一字线103连接多个半导体柱101的沟道区II，字线103覆盖沟道层102至少部分表面；第三方向Z垂直于基底表面，第一方向X与第二方向Y相交且均平行于基底表面。
在一些实施例中，半导体结构还包括：多条沿第二方向Y延伸的位线104，沿第二方向Y上每一位线104连接多个半导体柱101的第一掺杂区I；存储单元105，存储单元105沿第一方向X延伸，且与半导体柱101的第二掺杂区III连接。位线104沿第二方向Y延伸，且同一位线104连接第二方向Y上多个半导体柱101的第一掺杂区I，可以提高位线104的控制能力。存储单元105沿第一方向X延伸，且与半导体柱101的第二掺杂区III连接，可以使存储单元105沿与基底表面平行的方向延伸，从而有利于增加存储单元105沿第一方向X上的长度，以提高存储单元105的电荷存储能力，相较于垂直于基底表面的存储单元，可以避免存储单元的高度过高发生倾倒。
图17为本公开另一实施例提供的一种半导体结构的示意图。
参考图17，在一些实施例中，半导体柱101、字线103、位线104和存储单元105构成存储阵列结构(如图2所示)，存储阵列结构在基底(图中未示出)上沿第一方向X排列，在第一方向X上，相邻两个存储阵列结构沿位线104对称设置，且相邻两个存储阵列结构中位于同一层的半导体柱101连接同一位线104。通过将存储阵列结构沿第一方向X上排列，且相邻的两个存储阵列结构沿位线104对称设置，可以使相邻的两个存储阵列结构中位于同一层的半导体柱101连接同一位线104，进而使位线104的控制能力进一步增强，相应的位线104的控制端可以减少，提高了半导体结构的空间利用率，有利于提高半导体结构的集成密度。
在一些实施例中，参考图9，字线103可以环绕半导体柱101的沟道层102。字线103环绕半导体柱101的沟道层102可以使字线103与沟道区II的接触面积进一步增加，进而提高晶体管结构的栅控能力。
在一些实施例中，参考图9，栅介质层116环绕半导体柱101的沟道层102的外周面。
在一些实施例中，参考图12，字线103包括与半导体柱112的沟道层102的至少两面接触的第一部分，和与同一半导体柱112的多个沟道层102连接的多个第一部分连接的第二部分，第二部分位于堆叠结构的上方，且相邻字线103的第二部分之间间隔有填充了绝缘材料的第三凹槽125。
在一些实施例中，参考图12，字线103覆盖半导体柱112的沟道层102沿第二方向Y相对的两侧面，以及覆盖第三方向Z上沟道层102之间的填充绝缘层114沿第二方向Y相对的两侧面。
在一些实施例中，沟道层沿第三方向上的两侧为绝缘层或牺牲层，绝缘层和牺牲层可以作为第三方向上沟道层之间的支撑，以提高半导体结构的稳定性。
在一些实施例中，在第二方向Y上，沟道层102的宽度与沟道区II的宽度之比范围为0.2-0.6，例如0.2、0.3、0.4、0.5或者0.6等。可以理解的是，同一半导体柱101的多个沟道层102构成沟道区II，沿第二方向Y上沟道层102的宽度越小，相应的沟道层102的数量可以越多，则沟道层102构成沟道区II的表面积越大，但是沟道层102过薄会导致沿第一方向X上第一掺杂区I和第二掺杂区III无法通过沟道区II电连接。沟道层102的宽度越大时，可能无法在同一沟道区II中形成多个沟道层102，因此，沿第二方向Y上，沟道层102的宽度与沟道区II的宽度之比需要在一定范围内进 行调整，以满足提高沟道区II与字线103的接触面积，同时避免对半导体结构的使用性能造成影响。
本公开实施例提供的半导体结构，具有沿第一方向X延伸的多个半导体柱101，且半导体柱101沿第二方向Y和第三方向Z排列，可以提高半导体柱101形成的晶体管结构的排列密度，提高半导体结构的集成密度。半导体柱101的沟道区II包括与第三方向Z和第一方向X所在平面平行的多个沟道层102，可以使沟道区II的表面积增加，从而字线103与半导体柱101的沟道区II接触面积增加，提高了晶体管结构的栅控能力并降低功耗。字线103沿第三方向Z延伸，且沿第三方向Z上每一字线103连接多个半导体柱101的沟道区II，可以使字线103的控制能力增加。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (20)

  1. 一种半导体结构的制造方法，其特征在于，包括：
    提供基底(100)；
    于所述基底(100)上形成多个沿第一方向(X)延伸的半导体柱(101)，所述半导体柱(101)沿第二方向(Y)和第三方向(Z)间隔排列，所述半导体柱(101)包括第一掺杂区(I)、沟道区(II)和第二掺杂区(III)，所述第一掺杂区(I)和所述第二掺杂区(III)位于所述沟道区(II)的相对两侧，其中，所述沟道区(II)包括与所述第三方向(Z)和所述第一方向(X)所在平面平行的多个沟道层(102)；
    形成多条沿所述第三方向(Z)延伸的字线(103)，沿所述第三方向(Z)上每一所述字线(103)连接多个所述半导体柱(101)的所述沟道区(II)，所述字线(103)覆盖所述沟道层(102)至少部分表面；
    所述第三方向(Z)垂直于所述基底(100)表面，所述第一方向(X)与所述第二方向(Y)相交且均平行于所述基底(100)表面。
  2. 根据权利要求1所述的半导体结构的制造方法，其特征在于，在形成所述字线(103)之后，还包括：
    形成多条沿所述第二方向(Y)延伸的位线(104)，沿所述第二方向(Y)上每一所述位线(104)连接多个所述半导体柱(101)的所述第一掺杂区(I)；和/或
    形成存储单元(105)，所述存储单元(105)沿所述第一方向(X)延伸，且与所述半导体柱(101)的第二掺杂区(III)连接。
  3. 根据权利要求1所述的半导体结构的制造方法，其特征在于，于所述基底(100)上形成多个沿所述第一方向(X)延伸的所述半导体柱(101)，包括：
    于所述基底(100)上形成堆叠结构(113)，所述堆叠结构(113)包括沿所述第三方向(Z)交替层叠的牺牲层(111)和半导体层(112)；
    刻蚀所述堆叠结构(113)以形成多个沿所述第二方向(Y)相间隔的第一凹槽(124)，所述第一凹槽(124)位于所述牺牲层(111)和所述半导体层(112)内且沿所述第一方向(X)延伸；
    于所述第一凹槽(124)内填充绝缘层(114)；
    沿所述第三方向(Z)刻蚀所述第一凹槽(124)之间的所述半导体层(112)，以形成多个沿所述第二方向(Y)相间隔的第二凹槽(123)，剩余所述半导体层(112)作为所述半导体柱(101)，所述第二凹槽(123)至少位于相邻所述第一凹槽(124)之间，且相邻的所述第一凹槽(124)之间具有多个所述第二凹槽(123)，位于所述第二凹槽(123)之间的所述半导体柱(101)作为所述沟道层(102)，位于相邻所述第一凹槽(124)之间的所述沟道层(102)构成所述沟道区(II)。
  4. 根据权利要求3所述的半导体结构的制造方法，其特征在于，形成多条沿所述第三方向(Z)延伸的所述字线(103)，包括：
    形成栅介质层(116)，所述栅介质层(116)覆盖所述半导体柱(101)的所述沟道层(102)表面；
    于所述第二凹槽(123)内填充导电层(117)，所述导电层(117)覆盖所述栅介质层(116)表面；
    图形化所述导电层(117)，以形成所述字线(103)和多个沿所述第一方向(X)延伸的第三凹槽(125)，所述第三凹槽(125)位于相邻的所述字线(103)之间；
    于所述第三凹槽(125)内填充绝缘材料。
  5. 根据权利要求4所述的半导体结构的制造方法，其特征在于，在形成所述第二凹槽(123)后，还包括：去除所述第一凹槽(124)之间的所述牺牲层(111)，以形成沿第三方向(Z)相邻所述半导体柱(101)之间的间隙(115)；于所述第二凹槽(123)内填充所述导电层(117)，还包括：于所述间隙(115)内填充导电层(117)。
  6. 根据权利要求4所述的半导体结构的制造方法，其特征在于，在形成所述第一凹槽(124)之后还包括：去除所述第一凹槽(124)之间的所述牺牲层(111)；
    于所述第一凹槽(124)内填充所述绝缘层(114)，还包括：于所述第一凹槽(124)之间的间隙填充所述绝缘层(114)；
    在形成所述第二凹槽(123)后，还包括：去除所述第一凹槽(124)之间的所述绝缘层(114)以形成沿第三方向(Z)相邻半导体柱(101)之间的间隙(115)；
    于所述第二凹槽(123)内填充所述导电层(117)，还包括：于所述间隙(115)内填充导电层(117)。
  7. 根据权利要求4所述的半导体结构的制造方法，其特征在于，形成所述第一凹槽(124)的工艺包括干法刻蚀工艺，形成所述第二凹槽(123)的工艺包括干法刻蚀工艺。
  8. 根据权利要求1所述的半导体结构的制造方法，其特征在于，于所述基底(100)上形成多个沿所述第一方向(X)延伸的所述半导体柱(101)以及形成多条沿所述第三方向(Z)延伸的所述字线(103)，包括：
    于所述基底(100)上形成堆叠结构(113)，所述堆叠结构(113)包括沿所述第三方向(Z)交替层叠的牺牲层(111)和半导体层(112)；
    刻蚀所述堆叠结构(113)以形成多个在所述第二方向(Y)上相间隔的沟道沟槽组(129)，所述沟道沟槽组(129)位于所述堆叠结构(113)内，所述沟道沟槽组(129)包括多个沟道沟槽(119)，相邻所述沟道沟槽(119)之间的所述半导体层(112)作为所述沟道层(102)，对应同一所述沟道沟槽组(129)的所述沟道层(102)作为所述沟道区(II)；
    于所述沟道沟槽(119)内形成所述字线(103)；
    刻蚀所述堆叠结构(113)以形成多个沿所述第一方向(X)延伸的隔离沟槽(135)，所述隔离沟槽(135)位于所述沟道沟槽组(129)之间，剩余的所述半导体层(112)作为所述半导体柱(101)；
    于所述隔离沟槽(135)内填充隔离层。
  9. 根据权利要求8所述的半导体结构的制造方法，其特征在于，在形成所述沟道沟槽组(129)后，还包括：去除所述沟道沟槽组(129)内所述沟道沟槽(119)之间的所述牺牲层(111)以形成间隙(115)；于所述沟道沟槽(119)内形成所述字线(103)，还包括：于所述间隙(115)内填 充所述字线(103)。
  10. 根据权利要求8所述的半导体结构的制造方法，其特征在于，形成所述字线(103)，包括：
    形成栅介质层(116)，所述栅介质层(116)覆盖所述半导体柱(101)的所述沟道层(102)表面；
    形成导电层(117)，所述导电层(117)覆盖所述栅介质层(116)的表面且填充于所述沟道沟槽(119)内，所述导电层(117)的上表面高于所述堆叠结构(113)上表面；
    图形化所述导电层(117)以形成所述字线(103)，所述字线(103)与所述沟道沟槽组(129)一一对应且沿所述第二方向(Y)间隔排布。
  11. 一种半导体结构，其特征在于，包括：
    基底(100)，以及位于所述基底(100)上沿第一方向(X)延伸的半导体柱(101)，所述半导体柱(101)沿第二方向(Y)和第三方向(Z)间隔排列，所述半导体柱(101)包括第一掺杂区(I)、沟道区(II)和第二掺杂区(III)，所述第一掺杂区(I)和所述第二掺杂区(III)位于所述沟道区(II)的相对两侧，其中，所述沟道区(II)包括与所述第三方向(Z)和所述第一方向(X)所在平面平行的多个沟道层(102)；
    多条沿所述第三方向(Z)延伸的字线(103)，沿所述第三方向(Z)上每一所述字线(103)连接多个所述半导体柱(101)的所述沟道区(II)，所述字线(103)覆盖所述沟道层(102)至少部分表面；
    所述第三方向(Z)垂直于所述基底(100)表面，所述第一方向(X)与所述第二方向(Y)相交且均平行于所述基底(100)表面。
  12. 根据权利要求11所述的半导体结构，其特征在于，所述半导体结构还包括：
    多条沿所述第二方向(Y)延伸的位线(104)，沿所述第二方向(Y)上每一所述位线(104)连接多个所述半导体柱(101)的所述第一掺杂区(I)；和/或
    存储单元(105)，所述存储单元(105)沿所述第一方向(X)延伸，且与所述半导体柱(101)的第二掺杂区(III)连接。
  13. 根据权利要求12所述的半导体结构，其特征在于，所述半导体柱(101)、所述字线(103)、所述位线(104)和所述存储单元(105)构成存储阵列结构，所述存储阵列结构在所述基底(100)上沿所述第一方向(X)排列，在所述第一方向(X)上，相邻两个所述存储阵列结构沿所述位线(104)对称设置，且相邻两个所述存储阵列结构中位于同一层的所述半导体柱(101)连接同一所述位线(104)。
  14. 根据权利要求11所述的半导体结构，其特征在于，所述字线(103)环绕所述半导体柱(101)的所述沟道层(102)，或所述字线(103)位于所述沟道层(102)的沿所述第二方向(Y)的两侧。
  15. 根据权利要求11所述的半导体结构，其特征在于，所述沟道层(102)沿所述第三方向(Z)的两侧为绝缘层(114)或牺牲层(111)。
  16. 根据权利要求11所述的半导体结构，其特征在于，在所述第二方向(Y)上，所述沟道层(102) 的宽度与所述沟道区(II)的宽度之比范围为0.2-0.6。
  17. 根据权利要求11所述的半导体结构，其特征在于，所述字线(103)还位于所述沟道层(102)沿所述第三方向(Z)的两侧。
  18. 根据权利要求11所述的半导体结构，其特征在于，沿所述第二方向(Y)相邻的所述半导体柱(101)之间形成有绝缘层(114)。
  19. 根据权利要求18所述的半导体结构，其特征在于，沿所述第三方向(Z)上，所述字线(103)顶面高于所述绝缘层(114)顶面。
  20. 根据权利要求18所述的半导体结构，其特征在于，所述字线(103)与所述绝缘层(114)顶面平齐。
PCT/CN2023/116750 2022-10-21 2023-09-04 半导体结构及其制造方法 WO2024082840A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211296176.7A CN115605022A (zh) 2022-10-21 2022-10-21 半导体结构及其制造方法
CN202211296176.7 2022-10-21

Publications (1)

Publication Number Publication Date
WO2024082840A1 true WO2024082840A1 (zh) 2024-04-25

Family

ID=84847990

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/116750 WO2024082840A1 (zh) 2022-10-21 2023-09-04 半导体结构及其制造方法

Country Status (2)

Country Link
CN (1) CN115605022A (zh)
WO (1) WO2024082840A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115605022A (zh) * 2022-10-21 2023-01-13 长鑫存储技术有限公司（Cn） 半导体结构及其制造方法
CN118574408A (zh) * 2023-02-23 2024-08-30 长鑫存储技术有限公司 半导体结构及其制备方法
CN118632518A (zh) * 2023-03-09 2024-09-10 北京超弦存储器研究院 3d堆叠的半导体器件及其制造方法、电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114725106A (zh) * 2022-03-29 2022-07-08 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法、存储器
CN115050744A (zh) * 2022-05-09 2022-09-13 长鑫存储技术有限公司 半导体结构及制备方法
CN115064538A (zh) * 2022-06-06 2022-09-16 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法
CN115605022A (zh) * 2022-10-21 2023-01-13 长鑫存储技术有限公司（Cn） 半导体结构及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114725106A (zh) * 2022-03-29 2022-07-08 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法、存储器
CN115050744A (zh) * 2022-05-09 2022-09-13 长鑫存储技术有限公司 半导体结构及制备方法
CN115064538A (zh) * 2022-06-06 2022-09-16 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法
CN115605022A (zh) * 2022-10-21 2023-01-13 长鑫存储技术有限公司（Cn） 半导体结构及其制造方法

Also Published As

Publication number Publication date
CN115605022A (zh) 2023-01-13

Similar Documents

Publication Publication Date Title
CN109285836B (zh) 半导体存储设备及其制造方法及包括存储设备的电子设备
CN109285838B (zh) 半导体存储设备及其制造方法及包括存储设备的电子设备
WO2024082840A1 (zh) 半导体结构及其制造方法
US9324727B2 (en) Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same
TWI707461B (zh) 三維記憶裝置及其製造方法
WO2018058812A1 (zh) 存储器件及其制造方法及包括该存储器件的电子设备
US20220285506A1 (en) Nor-type storage device, method of manufacturing the same, and electronic apparatus including storage device
WO2023216402A1 (zh) 半导体结构及制备方法
US11895845B2 (en) Memory device and method for manufacturing the same, and electronic apparatus including the memory device
CN111276490B (zh) 一种三维存储器及其制作方法
WO2024046019A1 (zh) 半导体结构的制作方法及其结构
US20200381311A1 (en) Semiconductor device and method of fabricating the same
WO2022188623A1 (zh) Nor型存储器件及其制造方法及包括存储器件的电子设备
CN115064494A (zh) 半导体结构及制备方法
WO2023011084A1 (zh) Nor型存储器件及其制造方法及包括存储器件的电子设备
CN114725106A (zh) 半导体结构及半导体结构的制备方法、存储器
US20230397399A1 (en) Semiconductor structure and manufacturing method thereof
CN115411040A (zh) 半导体结构
CN108962905B (zh) 存储器件及其制造方法及包括该存储器件的电子设备
TW202137507A (zh) 三維記憶體元件以及其製作方法
WO2023221301A1 (zh) 一种半导体结构的制作方法及其结构
WO2024045266A1 (zh) 半导体结构的制作方法及其结构
US20240334684A1 (en) Semiconductor memory device
WO2024045265A1 (zh) 一种半导体结构的制作方法及其结构
US20240040766A1 (en) Method for fabricating semiconductor structure and semiconductor structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23878835

Country of ref document: EP

Kind code of ref document: A1