WO2024037164A1 - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

Info

Publication number
WO2024037164A1
WO2024037164A1 PCT/CN2023/100139 CN2023100139W WO2024037164A1 WO 2024037164 A1 WO2024037164 A1 WO 2024037164A1 CN 2023100139 W CN2023100139 W CN 2023100139W WO 2024037164 A1 WO2024037164 A1 WO 2024037164A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
regions
layer
opening
channel
Prior art date
Application number
PCT/CN2023/100139
Other languages
English (en)
French (fr)
Inventor
李晓杰
林超
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024037164A1 publication Critical patent/WO2024037164A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of memory, and in particular, to a semiconductor device and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then passes through the bit line. Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • transistors in the existing 3D DRAM manufacturing process usually adopt a multi-layer stacked lateral transistor structure.
  • the channel areas of the lateral transistors are floating, charges are easily accumulated in the channel area and cause a floating body effect.
  • the floating body effect will bring many adverse consequences (such as causing leakage current, resulting in Storage data loss, etc.), seriously affecting the performance of the device and even causing the device to fail.
  • Some embodiments of the present disclosure provide a method for forming a semiconductor device, including:
  • Line-shaped semiconductor patterns extending along the first direction and arranged in an array in the second direction and the vertical direction are formed on the semiconductor substrate.
  • a first insulating layer is formed between the line-shaped semiconductor patterns.
  • the linear semiconductor pattern includes a channel region arranged along the first direction and a drain region connected to the channel region;
  • Part of the first insulating layer is removed to form a first opening, and sidewalls perpendicular to the second direction of a plurality of drain regions distributed in a vertical direction are exposed on both sides of the first opening, and the first opening is exposed on both sides of the first opening.
  • the bottom of an opening exposes part of the surface of the semiconductor substrate;
  • Conductive material is filled in the first opening to form a grounded conductive plug.
  • Two sides of the grounded conductive plug perpendicular to the second direction are respectively connected to a plurality of the ground doped regions, and the grounded conductive plug The bottom of the conductive plug is connected to the semiconductor substrate.
  • the process of forming a linear semiconductor pattern extending along a first direction and arranged in an array in a second direction and a vertical direction on the semiconductor substrate includes:
  • the stacked structure including sacrificial layers and semiconductor layers alternately stacked in the vertical direction;
  • the first insulating layer is filled between the linear semiconductor patterns.
  • the first opening is located in the first groove, and one first groove is spaced between adjacent first openings along the second direction.
  • the method further includes: removing the first insulating layer in the first trench between adjacent channel regions to form a second opening, with two sides of the second opening respectively exposed along the vertical direction. Sidewalls perpendicular to the second direction of a plurality of channel regions distributed on A channel region is correspondingly formed in the channel region, the doping type of the channel region and the ground doping region is the same and the channel region is adjacent to the ground doping region; a channel region is formed that fills the second Open first isolation layer.
  • the linear semiconductor pattern further includes a source region connected to the channel region along the first direction, and the source region and the drain region are respectively located at both ends of the channel region
  • the method further includes: etching and removing the remaining first insulating layer in the first trench between adjacent source regions and between adjacent drain regions to form a third opening. Partial side walls perpendicular to the second direction of the plurality of drain regions distributed along the vertical direction are exposed, and sides of the plurality of source regions distributed along the vertical direction perpendicular to the second direction are exposed.
  • a source region is formed in the doping region, and the doping type of the drain region and the source region is opposite to the doping type of the ground doping region; after forming the source region and the drain region, a second isolation is formed in the third opening. layer.
  • a plurality of discrete bit lines are formed, each of the bit lines is connected to a plurality of the drain regions in a vertical direction, and the bit lines are arranged along the second direction.
  • the linear semiconductor pattern includes two drain regions connected along the first direction, two channel regions respectively connected to the two drain regions, and two channel regions respectively connected to the two drain regions.
  • Two source regions connected to two channel regions, the two channel regions are respectively located on opposite sides of the two drain regions, and the two source regions are respectively located on opposite sides of the corresponding channel regions.
  • the method includes: forming two corresponding drain regions in the two drain regions, and the bit line is connected to the two drain regions. drain connection.
  • the method further includes: removing the first insulating layer and the first isolation layer between the adjacent channel regions so that the channel regions are suspended; A word line dielectric layer is formed on the surface of the channel region; a metal word line extending along the second direction is formed on the word line dielectric layer in the channel region of each layer.
  • the method further includes: removing the sacrificial layer between adjacent drain regions along the first trench to form a first cavity; and the first insulating layer further filling the first cavity. cavity.
  • the method further includes: removing the first insulating layer and the second isolation layer between the source regions, and forming a capacitor connected to the source region in the area where the sacrificial layer and the second isolation layer are removed.
  • Some embodiments of the present disclosure also provide a semiconductor device, including:
  • a stacked structure located on the semiconductor substrate includes linear semiconductor pattern layers arranged at intervals along the vertical direction, each layer of the linear semiconductor pattern layer includes a layer extending along a first direction and along a first direction.
  • a grounded conductive plug is located between adjacent linear semiconductor patterns in the second direction, the grounded conductive plug penetrates the stacked structure in a vertical direction and is connected to the semiconductor substrate, and the grounded conductive plug The plug is connected to the ground doped regions on both sides in the second direction, and the bottom of the ground conductive plug connected to the semiconductor substrate.
  • two rows of linear semiconductor patterns arranged at intervals are included between adjacent ground conductive plugs.
  • the linear semiconductor pattern further includes a source region and a drain region connected to the channel region, and the source region and the drain region are respectively located on both sides of the channel region along the first direction. terminal, and the doping type of the source region and the drain region is opposite to that of the channel region, and the ground doping region is located on one side of the drain region along the second direction.
  • the method further includes: a plurality of discrete bit lines, each of which is connected to a plurality of drain regions in a vertical direction.
  • the linear semiconductor pattern includes two drain regions arranged along the first direction and electrically connected, respectively for a channel region located on one side of the two drain regions and connected to the corresponding drain region and located on one side of the two drain regions and connected to the corresponding drain region.
  • a source region connected to one side of the corresponding channel region.
  • one of the bit lines connects the two drain regions of the electrical connection.
  • the method further includes: a word line dielectric layer located on the surface of the channel region; and a word line dielectric layer located on the channel region of the linear semiconductor layer of each layer extending along the second direction. metal word lines.
  • the method further includes: a capacitor connected to the source region.
  • linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction are formed on a semiconductor substrate, and the linear semiconductor patterns are A first insulating layer is formed between the patterns, and the linear semiconductor pattern includes a channel region arranged along the first direction and a drain region connected to the channel region; part of the first insulating layer is removed To form a first opening, both sides of the first opening expose the sidewalls of a plurality of drain regions distributed in the vertical direction perpendicular to the second direction, and the bottom of the first opening exposes the semiconductor A portion of the surface of the substrate; along the first opening, perform ion doping on a plurality of exposed drain regions to form ground doping regions in a plurality of the drain regions, the ground doping regions being connected to the
  • the channel region is connected and has the same doping type as the channel region; the first opening is filled with conductive material to form a grounded conductive plug, the grounded
  • two sides of the grounded conductive plug perpendicular to the second direction are respectively connected to a plurality of the ground doping regions, and the bottom of the grounded conductive plug It is connected to the semiconductor substrate, so that multiple channel regions in multiple linear semiconductor patterns on both sides of the ground conductive plug can be grounded simultaneously through the ground conductive plug and the ground doped region, thereby connecting the multiple channel regions to the ground simultaneously.
  • the charges accumulated in the channel region are released through the ground doped region and the grounded conductive plug, preventing the floating body effect and improving the performance of the device, and the ground doped region is formed in the drain region, and the grounded conductive plug
  • the plug is formed in the first trench and does not occupy additional area, ensuring the integration of the formed 3D DRAM device.
  • 1-22 is a schematic structural diagram of the formation process of a semiconductor device in some embodiments of the present disclosure.
  • Some embodiments of the present disclosure first provide a method for forming a semiconductor device. The formation method will be described in detail below with reference to the accompanying drawings.
  • Figure 2 is a schematic cross-sectional structural diagram along the cutting line AA1 in Figure 1, providing a semiconductor substrate 200;
  • the linear semiconductor patterns 203 are arranged in an array.
  • a first insulating layer 202 is formed between the linear semiconductor patterns 203.
  • the linear semiconductor patterns 203 include channel regions 22 arranged along the first direction and are connected to the channel regions 22. drain region 21.
  • the material of the semiconductor substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC); it may also be silicon on insulator (SOI) or germanium on insulator (GOI). ); or it can also be other materials, such as gallium arsenide and other Group III-V compounds.
  • the material of the semiconductor substrate 200 is single crystal silicon (Si).
  • the linear semiconductor pattern 203 is subsequently used to form the channel region, source region and drain region of the lateral transistor.
  • the linear semiconductor patterns 203 extend along the first direction and are arranged in an array in the second direction and the vertical direction. Specifically, this means: both ends of each linear semiconductor pattern 203 extend along the first direction, and several linear semiconductor patterns 203 It is divided into multiple layers along the vertical direction, and each layer has a plurality of linear semiconductor patterns 203 arranged in parallel along the second direction.
  • the linear semiconductor pattern 203 includes a channel region 22 arranged along a first direction and a drain region 21 connected to the channel region 22.
  • the linear semiconductor pattern 203 also includes a source region connected to the channel region 22 along the first direction.
  • the electrode region 23, the source region 23 and the drain region 21 are respectively located at both ends of the channel region 22.
  • the linear semiconductor pattern 203 includes two connected drain regions 21 along the first direction, two channel regions 22 respectively connected to the two drain regions 21, and two channel regions 22 respectively connected to the two drain regions 21.
  • the two source regions 23 connected by the region 22 have two channel regions 22 located on opposite sides of the two drain regions 21 respectively, and the two source regions 23 are located on opposite sides of the corresponding channel regions 22 respectively. Therefore, two lateral transistors that can be subsequently formed on the linear semiconductor pattern 203 can share a bit line, thereby improving the integration of the device.
  • the numbers of drain regions 21 , channel regions 22 and source regions 23 on the linear semiconductor pattern 203 can be set according to actual needs.
  • the process of forming the linear semiconductor patterns 203 extending along the first direction and arranged in an array in the second direction and the vertical direction on the semiconductor substrate 200 includes: forming a stack on the semiconductor substrate 200 Structure 201, the stacked structure 201 includes sacrificial layers and semiconductor layers stacked alternately in the vertical direction; the stacked structure is etched to form a plurality of first trenches 204 penetrating the stacked structure in the first direction and the vertical direction, adjacent The remaining semiconductor layer between the first trenches 204 is a linear semiconductor pattern 203, the vertical direction is perpendicular to the upper surface of the semiconductor substrate 200, the first direction and the second direction are perpendicular and parallel to the upper surface of the semiconductor substrate 200; The first insulating layer 202 is filled between the linear semiconductor patterns 203 .
  • the material of the sacrificial layer is different from the material of the semiconductor layer, so that when the sacrificial layer is subsequently removed, the sacrificial layer has a high etching selectivity ratio (the etching selectivity ratio is greater than 2:1) relative to the semiconductor layer (or linear semiconductor pattern) , so that when the sacrificial layer is removed, the semiconductor layer (or linear semiconductor pattern) will not be etched or the amount of etching will be small.
  • the material of the semiconductor layer is silicon or silicon germanium
  • the material of the sacrificial layer is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbide, amorphous silicon, amorphous carbon, polycrystalline silicon, or silicon germanium.
  • the material of the semiconductor layer is silicon
  • the material of the sacrificial layer is silicon germanium.
  • the sacrificial layer and the semiconductor layer are respectively formed through a deposition process, and the deposition process includes an epitaxial process.
  • the semiconductor layer is not doped with impurity ions.
  • the first insulating layer 202 is used for electrical isolation between subsequently formed devices.
  • the material of the first insulating layer 202 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide). Silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), one or more of low dielectric constant (K less than 2.5) materials.
  • the material of the first insulating layer 202 is silicon oxide
  • the process of forming the first insulating layer 202 is a chemical vapor deposition process.
  • the sacrificial layer is a non-electrically isolating material such as amorphous silicon, amorphous carbon, polysilicon or silicon germanium
  • the remaining sacrificial layer between the linear semiconductor patterns 203 needs to be removed along the first trench. , forming a first cavity at a corresponding position, and when filling the first trench with the first insulating layer 202, the first cavity is also filled with the first insulating layer 202.
  • the material of the sacrificial layer is silicon oxide, silicon nitride, silicon oxynitride or silicon nitride carbide
  • the remaining sacrificial layer between adjacent linear semiconductor patterns 203 is not removed.
  • the remaining sacrificial layer between adjacent linear semiconductor patterns 203 is directly used as a part of the first insulating layer 202.
  • the stacked structure includes alternately stacked sacrificial layers and semiconductor layers.
  • the alternate stacking of sacrificial layers and semiconductor layers means: after forming a sacrificial layer, a layer of semiconductor layer is formed on the surface of the sacrificial layer, and then the sacrificial layer and the semiconductor layer are formed sequentially in cycles.
  • the number of sacrificial layers and semiconductor layers can be determined according to actual needs. In this embodiment, four sacrificial layers and four semiconductor layers are used as an example for description.
  • the bottom layer of the stacked structure is a sacrificial layer and the top layer is a semiconductor layer. In other embodiments, both the topmost and bottommost layers of the stack are sacrificial layers. In other embodiments, the number of sacrificial layers and semiconductor layers may be other numbers or set according to actual needs.
  • Figure 4 is a schematic cross-sectional structural diagram along the cutting line AA1 in Figure 3.
  • Part of the first insulating layer 202 is removed to form the first opening 205. Both sides of the first opening 205 are exposed and distributed in the vertical direction.
  • the sidewalls of the plurality of drain regions 21 that are perpendicular to the second direction, and the bottom of the first opening 205 exposes a portion of the surface of the semiconductor substrate 200 .
  • the purpose of forming the first opening 205 is to subsequently use the first opening 205 as a window for ion implantation to perform ion doping on the multiple exposed drain regions to form ground doped regions in the multiple drain regions, and in After the ground doped region is formed, conductive material is filled in the first opening 205 to form a grounded conductive plug.
  • the two sides of the grounded conductive plug perpendicular to the second direction are respectively connected to the plurality of ground doped regions, and the grounded conductive plug The bottom of the plug is connected to the semiconductor substrate 200 .
  • Part of the first insulating layer 202 is removed to form the first opening 205 using an anisotropic dry etching process, including a plasma etching process.
  • a patterned mask layer (not shown in the figure) is formed on the surface of the stacked structure. The patterned mask layer exposes the portions that need to be etched. The surface of the first insulating layer 202 is etched using the patterned mask layer as a mask to remove part of the first insulating layer 202 to form the first opening 205 .
  • Each formed first opening 205 exposes (part of) sidewalls perpendicular to the second direction of a plurality of drain regions 21 distributed in the vertical direction.
  • the position of the first opening 205 is close to the junction of the drain region 21 and the channel region 22, so that the ground doped region formed in the drain region 21 is easily connected to the channel region, so that the ground is formed in the drain region later.
  • the doped region and the grounded conductive plug formed in the first opening allow the channel region 22 to be grounded, thereby releasing the accumulated charges in the channel region 22 through the grounded doped region and the grounded conductive plug to prevent the floating body effect. , improves the performance of the device, and the ground doping region is formed in the drain region, and the ground conductive plug is formed in the first trench, which does not occupy additional area and ensures the integration of the formed 3D DRAM device. .
  • the first opening 205 is located in the first groove 204, and there is a first groove 204 spaced between adjacent first openings 205 along the second direction. Since one first opening 205 can be exposed The sidewalls of the drain regions 21 of the two adjacent linear semiconductor patterns 203 in the second direction are exposed. Subsequently, after a ground conductive plug is formed in the first opening 205, a ground conductive plug is used to connect the ground conductive plugs to the plurality of ground doped holes on both sides. By connecting the hybrid regions, the channel areas 22 of two adjacent linear semiconductor patterns 203 can be grounded through a grounded conductive plug. That is, only a small number of grounded conductive plugs need to be formed to realize all linear semiconductor patterns. The drain region 21 of 203 is grounded. Similarly, only a small number of first The opening 205 enables the formation of a ground doped region in the drain region 21 of all linear semiconductor patterns 203, thereby reducing the difficulty of the process.
  • FIG. 5 is a schematic cross-sectional structural diagram along the cutting line AA1 in FIG. 6 .
  • the multiple exposed drain regions 21 are ion-doped, so that in the multiple drain regions 21
  • a ground doped region 206 is formed in the substrate.
  • the ground doped region 206 is connected to the channel region 22 and has the same doping type as the channel region 22 .
  • the ground doped region 206 is only formed in a part of the drain region (a part close to the first opening 205 ), and the other part of the drain region 21 is subsequently used to form the drain region.
  • Ion doping uses an ion implantation process, such as plasma sidewall doping.
  • the impurity ions doped in the ground doped region 206 (drain region 21) may be N-type impurity ions or P-type impurity ions.
  • the P-type impurity ions are one or more of boron, gallium, and indium
  • the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.
  • the impurity ions doped in the ground doped region 206 (drain region 21) are P-type impurity ions.
  • the formed ground doped region 206 is connected to the channel region 22 and has the same doping type as the channel region 22.
  • the channel region 22 will be doped subsequently, that is, the ground doped region 206 and the channel region 22 have the same doping type.
  • the doping type enables the ground doped region 206 and the channel region 22 to be conductive.
  • Figure 8 is a schematic cross-sectional structural view along the cutting line AA1 in Figure 7.
  • the first opening is filled with conductive material to form a grounded conductive plug 207.
  • the grounded conductive plug 207 is perpendicular to both sides of the second direction.
  • Each side surface is connected to a plurality of ground doped regions 206 respectively, and the bottom of the ground conductive plug 207 is connected to the semiconductor substrate 200 .
  • the material of the ground conductive plug 207 is metal and its compounds or doped polysilicon.
  • the metal and its compounds can be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, One or more of WN and Wsi.
  • the impurity ions doped in the doped polysilicon are the same type as the impurity ions doped in the ground doping region 206 .
  • the formation process of the grounded conductive plug 207 is: forming a conductive material layer in the first opening and on the surface of the stacked structure, filling the first opening with the conductive material layer; using a chemical mechanical polishing process to planarize and remove the stacked structure.
  • the conductive material layer on the surface and the remaining conductive material layer in the first opening serve as ground conductive plugs 207 .
  • the grounded conductive plug 207 By forming the grounded conductive plug 207 in the first opening, two sides of the grounded conductive plug 207 perpendicular to the second direction are connected to the plurality of grounded doping regions 206 respectively, and the bottom of the grounded conductive plug 207 is connected to the semiconductor substrate. 200 connection, therefore through the ground conductive plug 207 and the ground doped region 206, multiple channel regions 22 in the multiple linear semiconductor patterns 203 on both sides of the ground conductive plug 207 can be grounded simultaneously, thereby connecting multiple trenches. The charge accumulated in the channel region 22 is released through the ground doped region and the grounded conductive plug to prevent the floating body effect and improve the performance of the device.
  • the ground doped region 206 is formed in the drain region 21 and the grounded conductive plug 207 is formed in the first trench, does not occupy additional area, and can ensure the integration of the formed 3D DRAM device.
  • Figure 10 is a schematic cross-sectional structural diagram along the cutting line AA1 direction of Figure 9.
  • the first insulating layer 202 in the first trench between adjacent channel regions 209 is removed to form a second opening 208. Both sides of the second opening 208 respectively expose sidewalls of a plurality of channel regions 22 distributed in the vertical direction and perpendicular to the second direction.
  • the purpose of forming the second opening 208 is to subsequently use the second opening 208 as a window for ion implantation to ion-dope the multiple exposed channel regions to form channel regions in the multiple channel regions.
  • the formed second opening 208 is located in the first trench between adjacent channel regions 22 , and both sides of the second opening 208 respectively expose a plurality of channel regions distributed in the vertical direction and perpendicular to the second direction. 22 side walls.
  • the length of the first opening 208 (the size of the first opening 208 in the first direction) is the same as the length of the channel region 22 (the size of the channel region 22 in the first direction).
  • An anisotropic dry etching process including a plasma etching process, is used to remove the first insulating layer 202 in the first trench between adjacent channel regions 209 .
  • a patterned mask layer (not shown in the figure) is formed on the surface of the stacked structure. The patterned mask layer exposes a portion of the surface of the first insulating layer 202 that needs to be etched; using the patterned mask layer as a mask, a portion of the first insulating layer 202 is etched away to form the second opening 208 .
  • FIG. 12 is a schematic cross-sectional structural view along the cutting line AA1 in FIG. 11 .
  • the multiple channel regions exposed by the second opening 208 are ion doped.
  • a channel region 209 is correspondingly formed in the region.
  • the channel region 209 and the ground doping region 206 have the same doping type, and the channel region 209 is adjacent to the ground doping region 206 .
  • the plurality of channel regions exposed by the second opening 208 are ion doped using an ion implantation process, such as plasma sidewall doping.
  • the channel region 209 (channel region) has the same doping type as the ground doped region 206, and the impurity ions doped in the channel region 209 (channel region) may be N-type impurity ions or P-type impurity ions.
  • the P-type impurity ions are one or more of boron, gallium, and indium
  • the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.
  • the impurity ions doped in the channel region 209 (channel region) are P-type impurity ions.
  • channel region 209 may be formed before or after ground doped region 206 .
  • FIG. 14 is a schematic cross-sectional structural view along the cutting line AA1 in FIG. 13 , forming a first isolation layer 210 that fills the second opening.
  • the material of the first isolation layer 210 may be different from the material of the first insulating layer 202. Subsequently, when the remaining first insulating layer 202 in the first trench is removed to form the third opening, the first insulating layer 202 is relative to the first insulating layer 202.
  • the isolation layer 210 has a high etching selectivity ratio (greater than 2:1), so the first isolation layer 210 will not be etched or a very small amount will be etched; and, the remaining third portion of the first trench in the first trench will be subsequently removed.
  • an insulating layer 202 forms the third opening, there is no need to form an additional patterned mask layer, and maskless etching can be performed directly to save process steps.
  • the material of the first isolation layer 210 can also be the same as the material of the first insulating layer 202 , and a patterned mask layer is formed in other areas before the remaining first insulating layer 202 is subsequently removed.
  • the material of the first isolation layer 210 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide). Silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), one or more of low dielectric constant (K less than 2.5) materials.
  • the material of the first isolation layer 210 is silicon nitride, and the process of forming the first isolation layer 210 is a chemical vapor deposition process and a chemical mechanical polishing process.
  • FIG. 16 is a schematic cross-sectional structural diagram along the cutting line AA1 in FIG.
  • the first insulating layer forms a third opening 218. Both sides of the third opening 218 expose part of the sidewalls perpendicular to the second direction of the plurality of drain regions 21 distributed in the vertical direction and the side walls of the drain regions 21 distributed in the vertical direction. Sidewalls of the plurality of source regions 23 perpendicular to the second direction.
  • the purpose of forming the third opening 218 is to subsequently use the third opening 218 as a window for ion implantation, and perform ion doping on the multiple exposed drain regions and multiple source regions along the third opening.
  • a drain region is formed in a plurality of source regions and a source region is formed in a plurality of source regions.
  • the formed third opening 218 is located in the first trench between the adjacent drain region 21 and the adjacent source region 23. Both sides of the third opening 218 are exposed to a plurality of holes distributed in the vertical direction. A portion of the sidewall of the drain region 21 that is perpendicular to the second direction and a plurality of source regions distributed along the vertical direction. 23 is a side wall perpendicular to the second direction.
  • FIG. 18 is a schematic cross-sectional structural diagram along the cutting line AA1 in FIG. 17 .
  • the multiple exposed drain regions and multiple source regions are ion doped along the third opening 218 .
  • a drain region 211 is formed in the electrode region, and source regions 212 are formed in a plurality of source regions.
  • the doping type of the drain region 211 and the source region 212 is opposite to the doping type of the ground doped region 206 .
  • the exposed plurality of drain regions and the plurality of source regions along the third opening 218 are ion doped using an ion implantation process, such as plasma sidewall doping.
  • the doping type of the drain region 211 and the source region 212 is opposite to the doping type of the ground doping region 206 and the channel region 209.
  • the impurity ions doped in the channel region, the drain region 211 and the source region 212 may be N-type impurity ions. Or P-type impurity ions.
  • the P-type impurity ions are one or more of boron, gallium, and indium
  • the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.
  • the impurity ions doped in the channel region, drain region 211 and source region 212 are N-type impurity ions.
  • two corresponding drain regions 211 are formed in the two drain regions 21 respectively.
  • drain region 211 and source region 212 may be formed before or after channel region 209 .
  • the drain region 211 and the source region 212 may also be formed before or after the ground doping region 206 .
  • FIG. 20 is a schematic cross-sectional structural diagram along the cutting line AA1 in FIG. 19 .
  • a second isolation layer 213 is formed in the third opening.
  • the material of the second isolation layer 213 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide). Silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), one or more of low dielectric constant (K less than 2.5) materials.
  • the material of the second isolation layer 213 is silicon oxide
  • the process of forming the first isolation layer 210 is a chemical vapor deposition process and a chemical mechanical polishing process.
  • Figure 22 is a schematic cross-sectional structural diagram along the cutting line AA1 in Figure 21, forming multiple discrete bit lines 214, each bit line 214 connected to multiple drain regions 211 in the vertical direction, and The bit lines 211 are arranged along the second direction.
  • the bit line 214 runs through the plurality of drain regions 211 in the vertical direction and is connected to the plurality of drain regions 211 .
  • the material of the bit line 214 is metal, and the metal can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.
  • one bit line 211 is connected to two drain regions 211 of the two connected drain regions.
  • the method further includes: removing the first insulation layer and the first isolation layer between adjacent channel regions 209 to make the channel region suspended; forming a word line dielectric layer on the surface of the suspended channel region ( (not shown in the figure); form metal word lines 217 extending in the second direction on the word line dielectric layer in the channel region of each layer; fill the third isolation layer 220 between the metal word lines 217.
  • the metal word lines 217 are horizontal word lines (the horizontal word lines are arranged horizontally and parallel to the surface of the semiconductor substrate 200) and extend along the second direction.
  • the metal word lines 210 of adjacent layers are discrete or separated.
  • the metal word lines 210 have a surrounding gate structure, and each metal word line 210 surrounds the surface of a plurality of channel regions 209 arranged along the second direction in a certain layer.
  • the metal word line may have a double-layer gate structure, and the double-layer gates in each metal word line are respectively located on the upper and lower surfaces of a plurality of channel regions 209 arranged along the second direction in a certain layer.
  • the material of the word line dielectric layer may be silicon oxide or a high-K (K greater than 2.5) dielectric material
  • the material of the metal word line may be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN , TaN, Ta, TaC, TaSiN, one or more of W, WN, Wsi.
  • the wordline dielectric layer and metal wordline 217 may be located between the bitline and ground conductor plugs. before or after formation.
  • the method further includes: removing the first insulating layer and the second isolation layer between the source regions 212, and forming a capacitor 215 connected to the source region 212 in the area where the sacrificial layer and the second isolation layer are removed; A fourth isolation layer 221 is formed between 215 .
  • Some embodiments of the present disclosure also provide a semiconductor device, with reference to Figures 21 and 22, including:
  • the stacked structure 201 is located on the semiconductor substrate 200.
  • the stacked structure 201 includes linear semiconductor pattern layers arranged at intervals along the vertical direction.
  • Each linear semiconductor pattern layer includes a linear semiconductor pattern layer extending along a first direction and arranged along a second direction.
  • a plurality of parallel linear semiconductor patterns 203 are laid out.
  • the semiconductor pattern 203 includes a channel region 209 and a ground doped region 206 connected to the channel region 209; and the ground doped region 206 and the channel region 209 have the same doping. type;
  • the grounded conductive plug 207 is located between adjacent linear semiconductor patterns 203 in the second direction.
  • the grounded conductive plug 207 penetrates the stacked structure 201 in the vertical direction and connects to the semiconductor substrate 200 , and the grounded conductive plug 207 is connected to the grounded conductive plug 207 in the second direction.
  • the two directions are connected to the ground doped regions 206 on both sides.
  • two rows of spaced apart linear semiconductor patterns 203 are included between adjacent ground conductive plugs 207 .
  • the linear semiconductor pattern 203 further includes a source region 212 and a drain region 211 connected to the channel region 209.
  • the source region 212 and the drain region 211 are respectively located at both ends of the channel region 209 along the first direction, and
  • the doping type of the source region 212 and the drain region 211 is opposite to that of the channel region 209, and the ground doped region 206 is located on one side of the drain region 211 along the second direction.
  • a plurality of discrete bit lines 214 are also included, each bit line 214 being connected to a plurality of drain regions 211 in the vertical direction.
  • the linear semiconductor pattern 203 includes two drain regions 211 arranged along the first direction and electrically connected, respectively for a channel region located on one side of the two drain regions 211 and connected to the corresponding drain region 211 209 and a source region 212 located on one side of the corresponding channel region 209 and connected to the corresponding channel region 209 .
  • One bit line 214 connects two electrically connected drain regions 211 .
  • the two drain regions 211 arranged along the first direction are in contact connection, and the bit line 214 surrounds the contact connection position of the two drain regions 211; it can also be that the two drain regions 211 arranged in the first direction are spaced apart, The bit line 214 is located between the two drain regions 211 and is in contact with the two drain regions 211 respectively.
  • it also includes: a word line dielectric layer located on the surface of the channel region 209; a metal word extending along the second direction on the word line dielectric layer of the channel region of the linear semiconductor layer of each layer. Line 217.
  • a capacitor 215 connected to the source region 215 is also included.
  • an isolation layer or an insulating layer (202, 213, 220, 221) for isolation between adjacent linear semiconductor patterns 203

Abstract

一种半导体器件及其形成方法，形成方法，在半导体衬底上形成呈阵列排布的线状半导体图形，线状半导体图形之间形成有第一绝缘层，线状半导体图形包括沿第一方向排布的沟道区域和漏极区域；去除部分第一绝缘层以形成第一开口，第一开口两侧暴露出多个漏极区域的侧壁，底部暴露出半导体衬底的部分表面；沿第一开口，在多个漏极区域中形成接地掺杂区，接地掺杂区与沟道区域连接，且与沟道区域具有相同的掺杂类型；在第一开口形成接地导电插塞。

Description

半导体器件及其形成方法
相关申请引用说明
本公开要求于2022年09月19日递交的中国专利申请号202210997527.0，申请名为“半导体器件及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及存储器领域，尤其涉及一种半导体器件及其形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
为了提高集成度，现有3D DRAM制作过程中晶体管通常会采用多层堆叠的横向晶体管结构。而多层堆叠的横向晶体管结构中由于横向晶体管的沟道区域都是浮空的，电荷容易在沟道区域积累带来浮体效应，浮体效应会带来很多不良后果(比如会引起漏电流，导致存储数据丢失等)，严重影响器件的性能，甚至使器件失效。
发明内容
本公开一些实施例提供了一种半导体器件的形成方法，包括：
提供半导体衬底；
在所述半导体衬底上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形，所述线状半导体图形之间形成有第一绝缘层，所述线状半导体图形包括沿所述第一方向排布的沟道区域和与所述沟道区域连接的漏极区域；
去除部分所述第一绝缘层以形成第一开口，所述第一开口两侧暴露出沿竖直方向上分布的多个漏极区域的垂直于所述第二方向的侧壁，所述第一开口底部暴露出所述半导体衬底的部分表面；
沿所述第一开口，对暴露的多个漏极区域进行离子掺杂，以在多个所述漏极区域中形成接地掺杂区，所述接地掺杂区与所述沟道区域连接，且与所述沟道区域具有相同的掺杂类型；
在所述第一开口中填充导电材料，形成接地导电插塞，所述接地导电插塞垂直于所述第二方向的两个侧面分别与多个所述接地掺杂区连接，且所述接地导电插塞的底部与所述半导体衬底连接。
在一些实施例中，在所述半导体衬底上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形的过程包括：
在所述半导体衬底上形成堆叠结构，所述堆叠结构包括在所述竖直方向上交替层叠的牺牲层和半导体层；
刻蚀所述堆叠结构，以形成在所述第一方向和竖直方向贯穿所述堆叠结构的多个第一沟槽，相邻所述第一沟槽之间剩余的半导体层为线状半导体图形，所述竖直方向垂直于所述半导体衬底上表面，所述第一方向与所述第二方向垂直且均平行于所述半导体衬底上表面；
在所述线状半导体图形之间填充所述第一绝缘层。
在一些实施例中，所述第一开口位于所述第一沟槽中，且沿所述第二方向上，相邻所述第一开口之间间隔有一个所述第一沟槽。
在一些实施例中，还包括：去除相邻所述沟道区域之间的第一沟槽中的第一绝缘层，形成第二开口，所述第二开口两侧分别暴露出沿竖直方向上分布的多个沟道区域的垂直于所述第二方向的侧壁；沿所述第二开口，对所述第二开口暴露的多个沟道区域进行离子掺杂，在多个所述沟道区域中相应的形成沟道区，所述沟道区与所述接地掺杂区的掺杂类型相同且所述沟道区与所述接地掺杂区邻接；形成填充满所述第二开口的第一隔离层。
在一些实施例中，所述线状半导体图形沿第一方向上还包括与所述沟道区域连接的源极区域，所述源极区域和漏极区域分别位于所述沟道区域两端，所述方法还包括：刻蚀去除相邻源极区域之间和相邻漏极区域之间的第一沟槽中剩余的所述第一绝缘层，形成第三开口，所述第三开口两侧暴露出沿竖直方向上分布的多个漏极区域的垂直于所述第二方向的部分侧壁以及沿竖直方向上分布的多个源极区域的垂直于所述第二方向的侧壁；沿所述第三开口对所述暴露的多个漏极区域和多个源极区域进行离子掺杂，在多个所述漏极区域中形成漏区，在多个所述源极区域中形成源区，所述漏区和源区的掺杂类型与所述接地掺杂区的掺杂类型相反；形成所述源区和漏区后，在所述第三开口中形成第二隔离层。
在一些实施例中，形成多个分立的位线，每一个所述位线与竖直方向上的多个所述漏区连接，且所述位线沿所述第二方向排布。
在一些实施例中，所述线状半导体图形沿所述第一方向上包括相连接的两个漏极区域、分别与两个所述漏极区域连接的两个沟道区域、及分别与两个所述沟道区域连接的两个源极区域，所述两个沟道区域分别位于两个漏极区域的相反侧，所述两个源极区域分别位于相应的沟道区域的相反侧。
在一些实施例中，所述方法包括：在所述两个漏极区域中分别形成相应的两个漏区，所述位线与相连接的所述两个漏极区域中的所述两个漏区连接。
在一些实施例中，所述方法还包括：去除所述相邻沟道区域之间的所述第一绝缘层和所述第一隔离层，使所述沟道区域悬空；在所述悬空的沟道区域的表面形成字线介质层；在每一层的所述沟道区域的字线介质层上形成沿第二方向延伸的金属字线。
在一些实施例中，还包括：沿所述第一沟槽去除相邻所述漏极区域之间的牺牲层，形成第一空腔；所述第一绝缘层还填充满所述第一空腔。
在一些实施例中，还包括：去除所述源区之间的第一绝缘层和第二隔离层，在去除所述牺牲层和第二隔离层的区域形成与所述源区连接的电容器。
本公开一些实施例还提供了一种半导体器件，包括：
半导体衬底；
位于所述半导体衬底上的堆叠结构，所述堆叠结构包括沿竖直方向上间隔排布的线状半导体图形层，每一层所述线状半导体图形层包括沿第一方向延伸且沿第二方向排布的多个平行的线状半导体图形，所述半导体图形包括沟道区和与所述沟道区连接的接地掺杂区；且所述接地掺杂区与所述沟道区具有相同的掺杂类型；
位于所述第二方向上相邻线状半导体图形之间的接地导电插塞，所述接地导电插塞沿竖直方向贯穿所述堆叠结构且连接所述半导体衬底，且所述接地导电插塞与在第二方向两侧的所述接地掺杂区连接，且所述接地导电插塞的底部 与所述半导体衬底连接。
在一些实施例中，沿所述第二方向上，相邻所述接地导电插塞之间包括两列间隔排布的线状半导体图形。
在一些实施例中，所述线状半导体图形还包括与所述沟道区连接的源区和漏区，所述源区和漏区分别位于所述沟道区沿所述第一方向的两端，且所述源区和漏区与所述沟道区的掺杂类型相反，且所述接地掺杂区位于所述漏区沿第二方向上的一侧。
在一些实施例中，还包括：多个分立的位线，每一个所述位线与竖直方向上的多个所述漏区连接。
在一些实施例中，所述线状半导体图形包括沿第一方向上排布且电连接的两个漏区，分别对于位于两个漏区一侧与对应的漏区连接的沟道区以及位于相应的沟道区一侧与相应的沟道区连接的源区。
在一些实施例中，一所述位线将所述电连接的两个漏区连接。
在一些实施例中，还包括：位于所述沟道区的表面的字线介质层；位于每一层的所述线状半导体层的沟道区的字线介质层上的沿第二方向延伸的金属字线。
在一些实施例中，还包括：与所述源区连接的电容器。
本公开前述一些实施例中的半导体器件的形成方法，在半导体衬底上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形，所述线状半导体图形之间形成有第一绝缘层，所述线状半导体图形包括沿所述第一方向排布的沟道区域和与所述沟道区域连接的漏极区域；去除部分所述第一绝缘层以形成第一开口，所述第一开口两侧暴露出沿竖直方向上分布的多个漏极区域的垂直于所述第二方向的侧壁，所述第一开口底部暴露出所述半导体衬底的部分表面；沿所述第一开口，对暴露的多个漏极区域进行离子掺杂，以在多个所述漏极区域中形成接地掺杂区，所述接地掺杂区与所述沟道区域连接，且与所述沟道区域具有相同的掺杂类型；在所述第一开口中填充导电材料，形成接地导电插塞，所述接地导电插塞垂直于所述第二方向的两个侧面分别与多个所述接地掺杂区连接，且所述接地导电插塞的底部与所述半导体衬底连接。通过在第一开口中形成接地导电插塞，所述接地导电插塞垂直于所述第二方向的两个侧面分别与多个所述接地掺杂区连接，且所述接地导电插塞的底部与所述半导体衬底连接，因而通过接地导电插塞和接地掺杂区可以使得地导电插塞两侧的多个线状半导体图形中的多个沟道区域可以同时接地，从而将所述多个沟道区域积累的电荷通过接地掺杂区和接地导电插塞释放掉，防止浮体效应的产生，提高了器件的性能，并且所述接地掺杂区是形成在漏极区域中，接地导电插塞是形成在第一沟槽中，不会占据额外的面积，能保证形成的3D DRAM器件的集成度。
附图说明
图1-22为本公开一些实施例中半导体器件的形成过程的结构示意图。
具体实施方式
下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且示意图只是示例，其在此不应限制本公开的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
本公开一些实施例首先提供了一种半导体器件的形成方法，下面结合附图对形成方法进行详细的描述。
参考图1和图2，图2为图1沿切割线AA1方向的剖面结构示意图，提供半导体衬底200；在半导体衬底200上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形203，线状半导体图形203之间形成有第一绝缘层202，线状半导体图形203包括沿第一方向排布的沟道区域22和与沟道区域22连接的漏极区域21。
半导体衬底200的材料可以为单晶硅(Si)、单晶锗(Ge)、或硅锗(SiGe)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，半导体衬底200的材料为单晶硅(Si)。
线状半导体图形203中后续用于形成横向晶体管的沟道区、源区和漏区。线状半导体图形203沿第一方向延伸、且在第二方向和竖直方向呈阵列排布具体指：每一个线状半导体图形203的两端沿第一方向延伸，若干个线状半导体图形203沿垂直方向上分成多层，每一层都有沿第二方向平行排布的多个线状半导体图形203。
线状半导体图形203包括沿第一方向排布的沟道区域22和与沟道区域22连接的漏极区域21，线状半导体图形203沿第一方向上还包括与沟道区域22连接的源极区域23，源极区域23和漏极区域21分别位于沟道区域22两端。
本实施例中，线状半导体图形203沿第一方向上包括相连接的两个漏极区域21、分别与两个漏极区域21连接的两个沟道区域22、及分别与两个沟道区域22连接的两个源极区域23，两个沟道区域22分别位于两个漏极区域21的相反侧，两个源极区域23分别位于相应的沟道区域22的相反侧。因而后续可以线状半导体图形203上形成的两个横向晶体管可以共用一个位线，提高器件的集成度。需要说明的是，在其他实施例中，线状半导体图形203上的漏极区域21、沟道区域22和源极区域23的数量可以根据实际需要进行设置。
在一些实施例中，在半导体衬底200上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形203的过程包括：在半导体衬底200上形成堆叠结构201，堆叠结构201包括在竖直方向上交替层叠的牺牲层和半导体层；刻蚀堆叠结构，以形成在第一方向和竖直方向贯穿堆叠结构的多个第一沟槽204，相邻第一沟槽204之间剩余的半导体层为线状半导体图形203，竖直方向垂直于半导体衬底200的上表面，第一方向与第二方向垂直且均平行于半导体衬底200上表面；在线状半导体图形203之间填充第一绝缘层202。
牺牲层的材料与半导体层的材料不相同，以在后续去除牺牲层时，牺牲层相对于半导体层(或线状半导体图形)具有高的刻蚀选择比(刻蚀选择比大于2:1)，从而使得牺牲层被去除的同时，半导体层(或线状半导体图形)不会被刻蚀或者被刻蚀的量较小。在一些实施例中，半导体层的材料为硅或锗硅，牺牲层的材料为氧化硅、氮化硅、氮氧化硅、氮碳化硅、无定型硅、无定形碳、多晶硅、锗硅中的一种。本实施例中，半导体层的材料为硅，牺牲层的材料为锗硅，牺牲层和半导体层分别通过沉积工艺形成，沉积工艺包括外延工艺。在一些实施例中，在形成半导体层时，半导体层中未掺杂杂质离子。
第一绝缘层202用于后续形成的器件之间的电学隔离。
在一些实施例中，第一绝缘层202的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)、低介电常数(K小于2.5)材料中的一种或几种。本实施例中，第一绝缘层202的材料为氧化硅，形成第一绝缘层202的工艺为化学气相沉积工艺。
需要说明的是，在一些实施例中。当牺牲层为无定型硅、无定形碳、多晶硅或锗硅等非电学隔离材料时，在形成第一沟槽后，还需要沿第一沟槽去除线状半导体图形203之间剩余的牺牲层，在对应位置形成第一空腔，在第一沟槽中填充第一绝缘层202时，在第一空腔中也填充第一绝缘层202。在其他实施例中，当牺牲层的材料为氧化硅、氮化硅、氮氧化硅或氮碳化硅时，形成第一沟槽后，不去除相邻线状半导体图形203之间剩余的牺牲层，在第一沟槽中填充第一绝缘层202后，直接将相邻线状半导体图形203之间剩余的牺牲层也作为第一绝缘层202的一部分。
堆叠结构包括交替层叠的牺牲层和半导体层，牺牲层和半导体层交替层叠是指：在形成一层牺牲层后，在该牺牲层的表面形成一层半导体层，然后依次循环进行形成牺牲层和位于牺牲层上的半导体层的步骤。牺牲层和半导体层的层数可以根据实际需要进行确定。本实施例中，以牺牲层为四层，半导体层为四层作为示例进行说明，堆叠结构的最底层为一层牺牲层和最顶层为一层半导体层。在其他实施例中，堆叠结构的最顶层和最底层都是一层牺牲层。在其他实施例中，牺牲层和半导体层的层数可以为其他数量或者根据实际需要进行设置。
参考图3和图4，图4为图3沿切割线AA1方向的剖面结构示意图，去除部分第一绝缘层202以形成第一开口205，第一开口205两侧暴露出沿竖直方向上分布的多个漏极区域21的垂直于第二方向的侧壁，第一开口205底部暴露出半导体衬底200的部分表面。
形成第一开口205的目的是：后续以第一开口205作为离子注入的窗口，对暴露的多个漏极区域进行离子掺杂，以在多个漏极区域中形成接地掺杂区，并且在形成接地掺杂区后，在第一开口205中填充导电材料，形成接地导电插塞，接地导电插塞垂直于第二方向的两个侧面分别与多个接地掺杂区连接，且接地导电插塞的底部与半导体衬底200连接。
去除部分第一绝缘层202以形成第一开口205采用各向异性的干法刻蚀工艺，包括等离子刻蚀工艺。在一实施例中，刻蚀去除部分第一绝缘层202之前，在堆叠结构表面上形成图形化的掩膜层(图中未示出)，图形化的掩膜层暴露出需要刻蚀的部分第一绝缘层202的表面；以图形化的掩膜层为掩膜，刻蚀去除部分第一绝缘层202以形成第一开口205。
每一个形成的第一开口205暴露出沿竖直方向上分布的多个漏极区域21的垂直于第二方向的(部分)侧壁。第一开口205的位置靠近漏极区域21和沟道区域22的交界处，以使得漏极区域21中形成的接地掺杂区容易与沟道区域连接，因而通过后续在漏极区域中形成接地掺杂区和以及第一开口中形成的接地导电插塞使得沟道区域22可以接地，从而将沟道区域22积累的电荷通过接地掺杂区和接地导电插塞释放掉，防止浮体效应的产生，提高了器件的性能，并且接地掺杂区是形成在漏极区域中，接地导电插塞是形成在第一沟槽中，不会占据额外的面积，能保证形成的3D DRAM器件的集成度。
本实施例中，第一开口205位于第一沟槽204中，且沿第二方向上，相邻第一开口205之间间隔有一个第一沟槽204，由于一个第一开口205就可以暴露出第二方向上两相邻的线状半导体图形203的漏极区域21的侧壁，后续在第一开口205形成接地导电插塞后，通过一个接地导电插塞与两侧的多个接地掺杂区连接，就可以使得两相邻的线状半导体图形203的沟道区域22通过一个接地导电插塞接地，即只需要形成较少数量的接地导电插塞就可以实现所有的线状半导体图形203的漏极区域21接地，同理只需要形成较少数量的第一 开口205，就可以使得实现所有的线状半导体图形203的漏极区域21中形成接地掺杂区，从而减小工艺的难度。
参考图5和图6，图5为图6沿切割线AA1方向的剖面结构示意图，沿第一开口205，对暴露的多个漏极区域21进行离子掺杂，以在多个漏极区域21中形成接地掺杂区206，接地掺杂区206与沟道区域22连接，且与沟道区域22具有相同的掺杂类型。
接地掺杂区206仅会形成在漏极区域的一部分区域中(靠近第一开口205的部分区域)中，漏极区域21另一部分区域后续用于形成漏区。
进行离子掺杂采用离子注入工艺，例如等离子侧壁掺杂工艺(plasmasidewall doping)。接地掺杂区206(漏极区域21)中掺杂的杂质离子可以为N型杂质离子或P型杂质离子。在一些实施例中，P型杂质离子为硼、镓、铟其中的一种或几种，N型杂质离子包括磷、砷、锑其中的一种或几种。本实施例中，接地掺杂区206(漏极区域21)中掺杂的杂质离子为P型杂质离子。
形成的接地掺杂区206与沟道区域22连接，且与沟道区域22具有相同的掺杂类型，沟道区域22后续会进行掺杂，即接地掺杂区206和沟道区域22具有相同的掺杂类型，使得接地掺杂区206和沟道区域22能导通。
参考图7和图8，图8为图7沿切割线AA1方向的剖面结构示意图，在第一开口中填充导电材料，形成接地导电插塞207，接地导电插塞207垂直于第二方向的两个侧面分别与多个接地掺杂区206连接，且接地导电插塞207的底部与半导体衬底200连接。
接地导电插塞207的材料为金属及其化合物或掺杂的多晶硅，金属及其化合物可以为Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、Wsi中的一种或几种。接地导电插塞217为掺杂的多晶硅时，掺杂的多晶硅中掺杂的杂质离子与接地掺杂区206中掺杂的杂质离子的类型相同。
在一实施例中，接地导电插塞207的形成过程为：在第一开口中以及堆叠结构表面上形成导电材料层，导电材料层填充满第一开口；采用化学机械研磨工艺平坦化去除堆叠结构表面上的导电材料层，将第一开口中剩余的导电材料层作为接地导电插塞207。
通过在第一开口中形成接地导电插塞207，接地导电插塞207垂直于第二方向的两个侧面分别与多个接地掺杂区206连接，且接地导电插塞207的底部与半导体衬底200连接，因而通过接地导电插塞207和接地掺杂区206可以使得地导电插塞207两侧的多个线状半导体图形203中的多个沟道区域22可以同时接地，从而将多个沟道区域22积累的电荷通过接地掺杂区和接地导电插塞释放掉，防止浮体效应的产生，提高了器件的性能，并且接地掺杂区206是形成在漏极区域21中，接地导电插塞207是形成在第一沟槽中，不会占据额外的面积，能保证形成的3D DRAM器件的集成度。
参考图9和图10，图10为图9沿切割线AA1方向的剖面结构示意图，去除相邻沟道区域209之间的第一沟槽中的第一绝缘层202，形成第二开口208，第二开口208两侧分别暴露出沿竖直方向上分布的垂直于第二方向的多个沟道区域22的侧壁。
形成第二开口208的目的是：后续以第二开口208作为离子注入的窗口，对暴露的多个沟道区域进行离子掺杂，以在多个沟道区域中形成沟道区。
形成的第二开口208位于相邻的沟道区域22之间的第一沟槽中，第二开口208两侧分别暴露出沿竖直方向上分布的垂直于第二方向的多个沟道区域 22的侧壁。第一开口208的长度(第一开口208在第一方向上的尺寸)与沟道区域22的长度(沟道区域22在第一方向上的尺寸)相同。
去除相邻沟道区域209之间的第一沟槽中的第一绝缘层202采用各向异性的干法刻蚀工艺，包括等离子刻蚀工艺。在一实施例中，去除相邻沟道区域209之间的第一沟槽中的第一绝缘层202之前，在堆叠结构表面上形成图形化的掩膜层(图中未示出)，图形化的掩膜层暴露出需要刻蚀的部分第一绝缘层202的表面；以图形化的掩膜层为掩膜，刻蚀去除部分第一绝缘层202以形成第二开口208。
参考图11和图12，图12为图11沿切割线AA1方向的剖面结构示意图，沿第二开口208，对第二开口208暴露的多个沟道区域进行离子掺杂，在多个沟道区域中相应的形成沟道区209，沟道区209与接地掺杂区206的掺杂类型相同且沟道区209与接地掺杂区206邻接。
对第二开口208暴露的多个沟道区域进行离子掺杂采用离子注入工艺，例如等离子侧壁掺杂工艺(plasmasidewall doping)。沟道区209(沟道区域)与接地掺杂区206的掺杂类型相同，沟道区209(沟道区域)中掺杂的杂质离子可以为N型杂质离子或P型杂质离子。在一些实施例中，P型杂质离子为硼、镓、铟其中的一种或几种，N型杂质离子包括磷、砷、锑其中的一种或几种。本实施例中，沟道区209(沟道区域)中掺杂的杂质离子为P型杂质离子。
在一些实施例中，沟道区209可以在接地掺杂区206之前或之后形成。
参考图13和图14，图14为图13沿切割线AA1方向的剖面结构示意图，形成填充满第二开口的第一隔离层210。
第一隔离层210的材料可以与第一绝缘层202的材料不相同，后续在去除第一沟槽中剩余的第一绝缘层202形成第三开口时，使得第一绝缘层202相对于第一隔离层210具有高的刻蚀选择比(大于2:1)，因而第一隔离层210不会被刻蚀或者被刻蚀的量很少；并且，后续在去除第一沟槽中剩余的第一绝缘层202形成第三开口时，也无需额外形成图形化的掩膜层，可以直接进行无掩膜刻蚀，以节省工艺步骤。在其他实施例中，第一隔离层210的材料也可以与第一绝缘层202的材料相同，后续去除剩余的第一绝缘层202之前，在其他区域形成图形化的掩膜层。
在一实施例中，第一隔离层210的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)、低介电常数(K小于2.5)材料中的一种或几种。本实施例中，第一隔离层210的材料为氮化硅，形成第一隔离层210的工艺为化学气相沉积工艺和化学机械研磨工艺。
参考图16和图15，图16为图15沿切割线AA1方向的剖面结构示意图，刻蚀去除相邻源极区域23之间和相邻漏极区域21之间的第一沟槽中剩余的第一绝缘层，形成第三开口218，第三开口218两侧暴露出沿竖直方向上分布的多个漏极区域21的垂直于第二方向的部分侧壁以及沿竖直方向上分布的多个源极区域23的垂直于第二方向的侧壁。
形成第三开口218的目的是：后续以第三开口218作为离子注入的窗口，沿第三开口对暴露的多个漏极区域和多个源极区域进行离子掺杂，在多个漏极区域中形成漏区，在多个源极区域中形成源区。
形成的第三开口218位于相邻的漏极区域21以及相邻源极区域23之间的第一沟槽中，第三开口218两侧分别两侧暴露出沿竖直方向上分布的多个漏极区域21的垂直于第二方向的部分侧壁以及沿竖直方向上分布的多个源极区域 23的垂直于第二方向的侧壁。
参考图17和图18，图18为图17沿切割线AA1方向的剖面结构示意图，沿第三开口218对暴露的多个漏极区域和多个源极区域进行离子掺杂，在多个漏极区域中形成漏区211，在多个源极区域中形成源区212，漏区211和源区212的掺杂类型与接地掺杂区206的掺杂类型相反。
沿第三开口218对暴露的多个漏极区域和多个源极区域进行离子掺杂采用离子注入工艺，例如等离子侧壁掺杂工艺(plasmasidewall doping)。漏区211和源区212的掺杂类型与接地掺杂区206和沟道区209的掺杂类型相反，沟道区漏区211和源区212中掺杂的杂质离子可以为N型杂质离子或P型杂质离子。在一些实施例中，P型杂质离子为硼、镓、铟其中的一种或几种，N型杂质离子包括磷、砷、锑其中的一种或几种。本实施例中，沟道区漏区211和源区212中掺杂的杂质离子为N型杂质离子。
本实施例中，在两个漏极区域21中分别形成相应的两个漏区211。
在一些实施例中，漏区211和源区212可以在沟道区209之前或之后形成。
在其他一些实施例中，漏区211和源区212也可以在接地掺杂区206之前或之后形成。
参考图19和图20，图20为图19沿切割线AA1方向的剖面结构示意图，形成源区212和漏区211后，在第三开口中形成第二隔离层213。
在一实施例中，第二隔离层213的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)、低介电常数(K小于2.5)材料中的一种或几种。本实施例中，第二隔离层213的材料为氧化硅，形成第一隔离层210的工艺为化学气相沉积工艺和化学机械研磨工艺。
参考图21和图22，图22为图21沿切割线AA1方向的剖面结构示意图，形成多个分立的位线214，每一个位线214与竖直方向上的多个漏区211连接，且位线211沿第二方向排布。
位线214沿垂直方向贯穿多个漏区211，并与多个漏区211连接。
位线214的材料为金属，金属可以为Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、Wsi中的一种或几种。
本实施例中，一个位线211与相连接的两个漏极区域中的两个漏区211连接。
在一些实施例中，方法还包括：去除相邻沟道区域209之间的第一绝缘层和第一隔离层，使沟道区域悬空；在悬空的沟道区域的表面形成字线介质层(图中未示出)；在每一层的沟道区域的字线介质层上形成沿第二方向延伸的金属字线217；在金属字线217之间填充第三隔离层220。
金属字线217为水平字线(水平字线呈水平设置，平行于半导体衬底200表面)，且沿第二方向延伸，相邻层的金属字线210是分立或分开的。
在一些实施例中，金属字线210为环绕栅结构，每一个金属字线210环绕某一层中沿第二方向排布的多个沟道区209表面上。
在其他实施例中，金属字线可以为双层栅结构，每一个金属字线中的双层栅分别位于某一层中沿第二方向排布的多个沟道区209的上下表面上。
在一实施例中，字线介质层的材料可以为氧化硅或高K(K大于2.5)介电材料，金属字线的材料可以为Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、Wsi中的一种或几种。
在一些实施例中，字线介质层和金属字线217可以在位线和接地导线插塞 形成之前或之后形成。
在一些实施例中，方法还包括：去除源区212之间的第一绝缘层和第二隔离层，在去除牺牲层和第二隔离层的区域形成与源区212连接的电容器215；在电容器215之间形成第四隔离层221。
本公开一些实施例还提供了一种半导体器件，参考图21和图22，包括：
半导体衬底200；
位于半导体衬底200上的堆叠结构201，堆叠结构201包括沿竖直方向上间隔排布的线状半导体图形层，每一层线状半导体图形层包括沿第一方向延伸且沿第二方向排布的多个平行的线状半导体图形203，半导体图形203包括沟道区209和与沟道区209连接的接地掺杂区206；且接地掺杂区206与沟道区209具有相同的掺杂类型；
位于第二方向上相邻线状半导体图形203之间的接地导电插塞207，接地导电插塞207沿竖直方向贯穿堆叠结构201且连接半导体衬底200，且接地导电插塞207与在第二方向两侧的接地掺杂区206连接。
在一些实施例中，且沿第二方向上，相邻接地导电插塞207之间包括两列间隔排布的线状半导体图形203。
在一些实施例中，线状半导体图形203还包括与沟道区209连接的源区212和漏区211，源区212和漏区211分别位于沟道区209沿第一方向的两端，且源区212和漏区211与沟道区209的掺杂类型相反，且接地掺杂区206位于漏区211沿第二方向上的一侧。
在一些实施例中，还包括：多个分立的位线214，每一个位线214与竖直方向上的多个漏区211连接。
在一些实施例中，线状半导体图形203包括沿第一方向上排布且电连接的两个漏区211，分别对于位于两个漏区211一侧与对应的漏区211连接的沟道区209以及位于相应的沟道区209一侧与相应的沟道区209连接的源区212。一个位线214将电连接的两个漏区211连接。可以是沿第一方向上排布的两个漏区211接触连接，位线214环绕两个漏区211的接触连接位置；也可以是沿第一方向上排布的两个漏区211间隔，位线214位于两个漏区211之间且分别与两个漏区211接触连接。
在一些实施例中，还包括：位于沟道区209的表面的字线介质层；位于每一层的线状半导体层的沟道区的字线介质层上的沿第二方向延伸的金属字线217。
在一些实施例中，还包括：与源区215连接的电容器215。
在一些实施例中，用于相邻线状半导体图形203之间隔离的隔离层或绝缘层(202、213、220、221)
需要说明的是，前述半导体器件的一些实施例中与前述半导体器件形成方法的一些实施例中相同或相似部分的限定或描述在此不再赘述，具体请参考前述半导体器件形成方法的一些实施例中相应部分的限定或描述。
本公开虽然已以较佳实施例公开如上，但其并不是用来限定本公开，任何本领域技术人员在不脱离本公开的精神和范围内，都可以利用上述揭示的方法和技术内容对本公开技术方案做出可能的变动和修改，因此，凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本公开技术方案的保护范围。

Claims (19)

  1. 一种半导体器件的形成方法，其中，包括：
    提供半导体衬底(200)；
    在所述半导体衬底(200)上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形(203)，所述线状半导体图形(203)之间形成有第一绝缘层(202)，所述线状半导体图形(203)包括沿所述第一方向排布的沟道区域(22)和与所述沟道区域(22)连接的漏极区域(21)；去除部分所述第一绝缘层(202)以形成第一开口(205)，所述第一开口(205)两侧暴露出沿竖直方向上分布的多个漏极区域(21)的垂直于所述第二方向的侧壁，所述第一开口(205)底部暴露出所述半导体衬底(200)的部分表面；
    沿所述第一开口(205)，对暴露的多个漏极区域(21)进行离子掺杂，以在多个所述漏极区域(21)中形成接地掺杂区(206)，所述接地掺杂区(206)与所述沟道区域(22)连接，且与所述沟道区域(22)具有相同的掺杂类型；
    在所述第一开口(205)中填充导电材料，形成接地导电插塞(207)，所述接地导电插塞(207)垂直于所述第二方向的两个侧面分别与多个所述接地掺杂区(206)连接，且所述接地导电插塞(207)的底部与所述半导体衬底(200)连接。
  2. 如权利要求1所述的半导体器件的形成方法，其中，在所述半导体衬底(200)上形成沿第一方向延伸、且在第二方向和竖直方向呈阵列排布的线状半导体图形(203)的过程包括：
    在所述半导体衬底(200)上形成堆叠结构(201)，所述堆叠结构(201)包括在所述竖直方向上交替层叠的牺牲层和半导体层；
    刻蚀所述堆叠结构(201)，以形成在所述第一方向和竖直方向贯穿所述堆叠结构(201)的多个第一沟槽(204)，相邻所述第一沟槽(204)之间剩余的半导体层为线状半导体图形(203)，所述竖直方向垂直于所述半导体衬底(200)上表面，所述第一方向与所述第二方向垂直且均平行于所述半导体衬底(200)上表面；
    在所述线状半导体图形(203)之间填充所述第一绝缘层(202)。
  3. 如权利要求2所述的半导体器件的形成方法，其中，所述第一开口(205)位于所述第一沟槽(204)中，且沿所述第二方向上，相邻所述第一开口(205)之间间隔有一个所述第一沟槽(204)。
  4. 如权利要求2所述的半导体器件的形成方法，其中，还包括：去除相邻所述沟道区域(22)之间的第一沟槽(204)中的第一绝缘层(202)，形成第二开口(208)，所述第二开口(208)两侧分别暴露出沿竖直方向上分布的多个沟道区域(22)的垂直于所述第二方向的侧壁；沿所述第二开口(208)，对所述第二开口(208)暴露的多个沟道区域(22)进行离子掺杂，在多个所述沟道区域(22)中相应的形成沟道区(209)，所述沟道区(209)与所述接地掺杂区(206)的掺杂类型相同且所述沟道区(209)与所述接地掺杂区(206)邻接；形成填充满所述第二开口(208)的第一隔离层(210)。
  5. 如权利要求2所述的半导体器件的形成方法，其中，所述线状半导体图形(203)沿第一方向上还包括与所述沟道区域(22)连接的源极区域(23)，所述源极区域(23)和漏极区域(21)分别位于所述沟道区域(22)两端，所述方法还包括：刻蚀去除相邻源极区域(23)之间和相邻漏极区域(21)之间的第一沟槽(204)中剩余的所述第一绝缘层(202)，形成第三开口(218)， 所述第三开口(218)两侧暴露出沿竖直方向上分布的多个漏极区域(21)的垂直于所述第二方向的部分侧壁以及沿竖直方向上分布的多个源极区域(23)的垂直于所述第二方向的侧壁；沿所述第三开口(218)对所述暴露的多个漏极区域(21)和多个源极区域(23)进行离子掺杂，在多个所述漏极区域(21)中形成漏区(211)，在多个所述源极区域(23)中形成源区(212)，所述漏区(211)和源区(212)的掺杂类型与所述接地掺杂区(206)的掺杂类型相反；形成所述源区(212)和漏区(211)后，在所述第三开口(218)中形成第二隔离层(213)。
  6. 如权利要求5所述的半导体器件的形成方法，其中，形成多个分立的位线(214)，每一个所述位线(214)与竖直方向上的多个所述漏区(211)连接，且所述位线(214)沿所述第二方向排布。
  7. 如权利要求6所述的半导体器件的形成方法，其中，所述线状半导体图形(203)沿所述第一方向上包括相连接的两个漏极区域(21)、分别与两个所述漏极区域(21)连接的两个沟道区域(22)、及分别与两个所述沟道区域(22)连接的两个源极区域(23)，所述两个沟道区域(22)分别位于两个漏极区域(21)的相反侧，所述两个源极区域(23)分别位于相应的沟道区域(22)的相反侧。
  8. 如权利要求7所述的半导体器件的形成方法，其中，所述方法包括：在所述两个漏极区域(21)中分别形成相应的两个漏区(211)，所述位线(214)与相连接的所述两个漏极区域(21)中的所述两个漏区(211)连接。
  9. 如权利要求4所述的半导体器件的形成方法，其中，所述方法还包括：去除所述相邻沟道区域(22)之间的所述第一绝缘层(202)和所述第一隔离层(210)，使所述沟道区域(22)悬空；在所述悬空的沟道区域(22)的表面形成字线介质层；在每一层的所述沟道区域(22)的字线介质层上形成沿第二方向延伸的金属字线(217)。
  10. 如权利要求2所述的半导体器件的形成方法，其中，还包括：沿所述第一沟槽(204)去除相邻所述漏极区域(21)之间的牺牲层，形成第一空腔；所述第一绝缘层(202)还填充满所述第一空腔。
  11. 如权利要求7所述的半导体器件的形成方法，其中，还包括：去除所述源区(212)之间的第一绝缘层(202)和第二隔离层(213)，在去除所述牺牲层和第二隔离层(213)的区域形成与所述源区(212)连接的电容器(215)。
  12. 一种半导体器件，其中，包括：
    半导体衬底(200)；
    位于所述半导体衬底(200)上的堆叠结构(201)，所述堆叠结构(201)包括沿竖直方向上间隔排布的线状半导体图形(203)层，每一层所述线状半导体图形(203)层包括沿第一方向延伸且沿第二方向排布的多个平行的线状半导体图形(203)，所述半导体图形包括沟道区(209)和与所述沟道区(209)连接的接地掺杂区(206)；且所述接地掺杂区(206)与所述沟道区(209)具有相同的掺杂类型；
    位于所述第二方向上相邻线状半导体图形(203)之间的接地导电插塞(207)，所述接地导电插塞(207)沿竖直方向贯穿所述堆叠结构(201)且连接所述半导体衬底(200)，且所述接地导电插塞(207)与在第二方向两侧的所述接地掺杂区(206)连接，且所述接地导电插塞(207)的底部与所述半导体衬底(200)连接。
  13. 如权利要求12所述的半导体器件，其中，沿所述第二方向上，相邻所述接 地导电插塞(207)之间包括两列间隔排布的线状半导体图形(203)。
  14. 如权利要求12所述的半导体器件，其中，所述线状半导体图形(203)还包括与所述沟道区(209)连接的源区(212)和漏区(211)，所述源区(212)和漏区(211)分别位于所述沟道区(209)沿所述第一方向的两端，且所述源区(212)和漏区(211)与所述沟道区(209)的掺杂类型相反，且所述接地掺杂区(206)位于所述漏区(211)沿第二方向上的一侧。
  15. 如权利要求14所述的半导体器件，其中，还包括：多个分立的位线(214)，每一个所述位线(214)与竖直方向上的多个所述漏区(211)连接。
  16. 如权利要求15所述的半导体器件，其中，所述线状半导体图形(203)包括沿第一方向上排布且电连接的两个漏区(211)，分别对于位于两个漏区(211)一侧与对应的漏区(211)连接的沟道区(209)以及位于相应的沟道区(209)一侧与相应的沟道区(209)连接的源区(212)。
  17. 如权利要求16所述的半导体器件，其中，一个所述位线(214)将所述电连接的两个漏区(211)连接。
  18. 如权利要求12所述的半导体器件，其中，还包括：位于所述沟道区(209)的表面的字线介质层；位于每一层的所述线状半导体层的沟道区(209)的字线介质层上的沿第二方向延伸的金属字线(217)。
  19. 如权利要求16所述的半导体器件，其中，还包括：与所述源区(212)连接的电容器(215)。
PCT/CN2023/100139 2022-08-19 2023-06-14 半导体器件及其形成方法 WO2024037164A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210997527.0 2022-08-19
CN202210997527.0A CN117672957A (zh) 2022-08-19 2022-08-19 半导体器件及其形成方法

Publications (1)

Publication Number Publication Date
WO2024037164A1 true WO2024037164A1 (zh) 2024-02-22

Family

ID=89940583

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/100139 WO2024037164A1 (zh) 2022-08-19 2023-06-14 半导体器件及其形成方法

Country Status (2)

Country Link
CN (1) CN117672957A (zh)
WO (1) WO2024037164A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170250224A1 (en) * 2016-02-26 2017-08-31 Sandisk Technologies Llc Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof
CN113196484A (zh) * 2019-11-25 2021-07-30 桑迪士克科技有限责任公司 包括集成栅极选择器的三维铁电存储器阵列及其形成方法
CN113284898A (zh) * 2020-01-31 2021-08-20 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN114512487A (zh) * 2020-11-16 2022-05-17 三星电子株式会社 半导体存储器装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170250224A1 (en) * 2016-02-26 2017-08-31 Sandisk Technologies Llc Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof
CN113196484A (zh) * 2019-11-25 2021-07-30 桑迪士克科技有限责任公司 包括集成栅极选择器的三维铁电存储器阵列及其形成方法
CN113284898A (zh) * 2020-01-31 2021-08-20 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN114512487A (zh) * 2020-11-16 2022-05-17 三星电子株式会社 半导体存储器装置

Also Published As

Publication number Publication date
CN117672957A (zh) 2024-03-08

Similar Documents

Publication Publication Date Title
US10453859B2 (en) Methods of manufacturing vertical memory devices
CN112103291B (zh) 具有埋置交叉耦接互连的结构及sram位单元
US10748923B2 (en) Vertical memory devices and methods of manufacturing the same
CN111668219B (zh) 集成互补场效应晶体管的结构及sram位单元
US20200043943A1 (en) Vertical memory devices and methods of manufacturing the same
US10515979B2 (en) Three-dimensional semiconductor devices with inclined gate electrodes
US11864383B2 (en) Vertical-type memory device
US11765886B2 (en) Semiconductor memory device
CN112736036A (zh) 半导体结构及其形成方法
KR20210000208A (ko) 반도체 장치 및 이의 제조 방법
WO2023103182A1 (zh) 存储单元、存储器及其制作方法
TWI802469B (zh) 記憶體裝置及其形成方法
US11587940B2 (en) Three-dimensional semiconductor memory devices
US20220406789A1 (en) Semiconductor device and method for fabricating the same
CN113707612B (zh) 存储器件及其形成方法
KR20130133559A (ko) 반도체 소자의 형성방법
US20230253318A1 (en) Semiconductor device
KR102640872B1 (ko) 3차원 반도체 장치
US7119390B2 (en) Dynamic random access memory and fabrication thereof
WO2024037164A1 (zh) 半导体器件及其形成方法
CN210837712U (zh) 半导体结构
CN114464621A (zh) 半导体器件
WO2024037347A1 (zh) 半导体结构及其形成方法
WO2024016753A1 (zh) 三维半导体结构及其形成方法
CN112736080A (zh) 半导体存储器及其形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23854069

Country of ref document: EP

Kind code of ref document: A1