WO2023103182A1 - 存储单元、存储器及其制作方法 - Google Patents

存储单元、存储器及其制作方法 Download PDF

Info

Publication number
WO2023103182A1
WO2023103182A1 PCT/CN2022/077310 CN2022077310W WO2023103182A1 WO 2023103182 A1 WO2023103182 A1 WO 2023103182A1 CN 2022077310 W CN2022077310 W CN 2022077310W WO 2023103182 A1 WO2023103182 A1 WO 2023103182A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
storage node
layer
sub
region
Prior art date
Application number
PCT/CN2022/077310
Other languages
English (en)
French (fr)
Inventor
吴公一
王晓玲
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/179,740 priority Critical patent/US20230209807A1/en
Publication of WO2023103182A1 publication Critical patent/WO2023103182A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a storage unit, a memory and a manufacturing method thereof.
  • a dynamic random access memory (DRAM) cell includes a capacitor to store charge and a transistor to access the capacitor.
  • DRAM stores data in the form of electric charge on a capacitor, so the capacitor needs to be recharged regularly every few milliseconds, and the larger the capacitance of the capacitor, the longer the data stored in the DRAM can be maintained.
  • DRAM mainly has a 6F2 structure.
  • the 4F2 structure will open a new era.
  • the capacitor structure has also undergone corresponding changes.
  • it is mainly stacked capacitors.
  • stacked capacitors In order to ensure high storage capacity, stacked capacitors often occupy a larger chip area and form a higher capacitor height. Not only will it hinder the improvement of integration, but it will also lead to bending and collapse.
  • it is very important to improve the current stacked capacitor structure and provide a new 3D columnar capacitor structure.
  • the main purpose of the present disclosure is to provide a storage unit, a memory and a manufacturing method thereof, so as to solve the problem in the prior art that the capacitor of a DRAM is limited in size and thus the integration level is difficult to increase.
  • a memory cell comprising: sequentially connected transistors, storage node contacts, and a capacitor, the capacitor includes a lower electrode, an upper electrode, and a dielectric layer, and the dielectric layer is located between the lower electrode and the upper electrode.
  • the lower electrode includes: a first electrode layer having a first sub-electrode region and a plurality of second sub-electrode regions connected to the first sub-electrode region, the first sub-electrode region is in contact with the surface of the storage node, each The second sub-electrode regions extend along a direction away from the contact of the storage node, and each second sub-electrode region has a first end surface and a second end surface opposite to each other in the extending direction, and the first end surface is in contact with the surface contacting the storage node; the second electrode layer covering at least part of the surface of the first electrode layer.
  • a memory including: a plurality of memory cells as described above, the memory cells are arranged in an array; a plurality of bit line structures arranged at intervals along the first direction, the bit line structure and the memory cells The transistors are electrically connected; a plurality of word line structures arranged at intervals along the second direction, the word line structures are electrically connected to the transistors, and the second direction intersects the first direction.
  • a method for fabricating a memory including the following steps: providing a substrate, and forming a plurality of bit line structures in the substrate, and each bit line structure is arranged at intervals along a first direction; A plurality of transistors are respectively formed on each bit line structure, and the bit line structure is electrically connected to the transistor; a plurality of word line structures are formed, and each word line structure is arranged at intervals along the second direction, and the word line structure is electrically connected to the transistor, and the second The direction intersects the first direction; forming a storage node contact on the transistor; forming a capacitor on the storage node contact such that the capacitor includes a lower electrode, an upper electrode, and a dielectric layer, the dielectric layer being located between the lower electrode and the upper electrode, the lower electrode comprising: The first electrode layer has a first sub-electrode region and a plurality of second sub-electrode regions connected to the first sub-electrode region.
  • the first sub-electrode region is in contact with the surface of the storage node.
  • the direction of node contact extends, and each second sub-electrode region has a first end surface and a second end surface opposite to each other in the extension direction, and the first end surface is in contact with the surface in contact with the storage node; the second electrode layer covers the first electrode layer at least part of the surface.
  • a storage unit including capacitors connected in sequence, storage node contacts and transistors, the capacitor has a lower electrode, an upper electrode and a dielectric layer, the dielectric layer is located between the lower electrode and the upper electrode, and the lower electrode Including a first electrode layer and a second electrode layer, the first electrode layer has a first sub-electrode region and a plurality of second sub-electrode regions connected to the first sub-electrode region, the first sub-electrode region is in contact with the surface of the storage node , each second sub-electrode region extends along a direction away from the storage node contact, and each second sub-electrode region has a first end face and a second end face opposite to each other in the extending direction, the first end face is in contact with the surface contacting the storage node, and the second end face is in contact with the storage node contact surface.
  • the two electrode layers cover at least part of the surface of the first electrode layer.
  • the structure of the lower electrode, the dielectric layer and the upper electrode constitute a double-sided capacitor structure, thereby increasing the capacitance area.
  • the capacitor structure can be used without increasing the capacitance size. In the case of increasing the storage capacity of the capacitor, it is beneficial to the integration of the capacitor.
  • FIG. 1 shows a schematic cross-sectional structure diagram of a memory cell provided in an embodiment of the present disclosure in the A-A' direction;
  • Fig. 2 shows a schematic cross-sectional structure diagram of a memory cell provided in an embodiment of the present disclosure in the B-B' direction, wherein the A-A' direction is perpendicular to the B-B' direction;
  • Fig. 3 shows a schematic cross-sectional structure diagram of an upper electrode, a lower electrode and a dielectric layer shown in Fig. 1 and Fig. 2;
  • FIG. 4 shows a schematic top view of the first sub-electrode region in the lower electrode shown in FIG. 3;
  • FIG. 5 shows a schematic top view of a DRAM memory with the memory cells shown in FIG. 1 and FIG. 2;
  • FIG. 6 shows a schematic flow diagram of a method for manufacturing a DRAM memory provided in an embodiment of the present disclosure
  • FIG. 7 shows a schematic cross-sectional structure diagram of a base after a bit line structure is formed in a substrate in a method for manufacturing a DRAM memory provided by an embodiment of the present disclosure
  • FIG. 8 shows a schematic top view of the substrate shown in FIG. 7;
  • FIG. 9 shows a schematic cross-sectional structure diagram of the base after forming a first doped region in contact with the bit line structure in the substrate shown in FIG. 7;
  • FIG. 10 shows a schematic cross-sectional structure diagram of the substrate after removing the first mask layer shown in FIG. 9 and sequentially forming an etching stop layer, a first insulating layer and a second mask layer on the substrate;
  • FIG. 11 shows a schematic top view of the substrate shown in FIG. 10;
  • FIG. 12 shows a schematic cross-sectional structure of the substrate after forming a channel region and a second doped region in the through hole shown in FIG. 11;
  • FIG. 13 shows a schematic cross-sectional structure of the substrate after removing the first insulating layer and the first oxide interlayer shown in FIG. 12;
  • FIG. 14 shows a schematic cross-sectional structure of the active region structure shown in FIG. 13 covering the gate dielectric layer, the material of the barrier layer and the rear substrate of the gate metal;
  • FIG. 15 shows a schematic cross-sectional structure diagram of the substrate after etching the gate metal and barrier layer material shown in FIG. 14 to form a gate and a gate barrier layer;
  • FIG. 16 shows a schematic cross-sectional structure of the substrate after covering the etching buffer layer and the second insulating layer on the gate and the gate barrier layer shown in FIG. 15;
  • FIG. 17 shows a schematic top view of the substrate after sequentially forming a third mask layer and a patterned photoresist layer on the second insulating layer shown in FIG. 16;
  • Figure 18(a) shows a schematic cross-sectional structure diagram of the substrate shown in Figure 22 in the A-A' direction;
  • Figure 18(b) shows a schematic cross-sectional structure diagram of the substrate shown in Figure 22 in the B-B' direction;
  • Figure 19(a)-(b) respectively show the cross-section of the substrate after forming a plurality of isolation grooves through the gate structure on the substrate through the third mask layer shown in Figure 18(a)-(b) Schematic;
  • Figure 20(a)-(b) respectively show the formation of the second oxide interlayer and the third insulating layer in the isolation groove shown in Figure 19(a)-(b) and on the second insulating layer.
  • Figure 21(a)-(b) respectively show the schematic cross-sectional structure of the substrate after forming the fourth mask layer on the third insulating layer shown in Figure 20(a)-(b);
  • FIG. 22(a)-(b) respectively show the schematic cross-sectional structure of the substrate after the fourth mask layer etching shown in FIG. 21(a)-(b) forms the groove through to/drain;
  • FIG. 23(a)-(b) respectively show the schematic cross-sectional structure diagrams of the substrate after the storage node contacts are formed in the grooves shown in FIG. 22(a)-(b);
  • FIG. 24(a)-(b) respectively show the schematic cross-sectional structure diagrams of the substrate after covering the capacitor material layer on the storage node contacts shown in FIG. 23(a)-(b);
  • 25(a)-(b) respectively show a schematic cross-sectional structure diagram of the substrate after etching the capacitive material layer shown in FIG. 24(a)-(b) to form a capacitive column in contact with the storage node;
  • Figure 26(a)-(b) respectively show the schematic cross-sectional structure of the substrate after forming the fourth insulating layer covering the capacitance column shown in Figure 25(a)-(b);
  • Figure 27(a)-(b) respectively shows a schematic cross-sectional structure diagram of the substrate after etching the fourth insulating layer and the capacitor column shown in Figure 26(a)-(b) to form the first electrode layer;
  • Figure 28(a)-(b) respectively show the formation of the second electrode material layer covering the first electrode layer shown in Figure 27(a)-(b) and etching the second electrode material layer to form the second electrode Schematic diagram of the cross-sectional structure of the substrate after the layer;
  • Figure 29(a)-(b) respectively show the schematic cross-sectional structure of the substrate after forming the dielectric layer covering the second electrode layer and part of the first electrode layer shown in Figure 28(a)-(b);
  • Figure 30(a)-(b) respectively show the schematic cross-sectional structure of the substrate after covering the third electrode layer on the dielectric layer shown in Figure 29(a)-(b);
  • FIG. 31(a)-(b) respectively show the schematic cross-sectional structure of the substrate after the fourth electrode layer is covered on the third electrode layer shown in FIG. 30(a)-(b).
  • the present disclosure proposes a memory cell, as shown in FIG. 1 to FIG. 5 , including sequentially connected transistors, storage node contacts 210, and capacitors.
  • the capacitor includes a lower electrode 310, an upper electrode 330, and a dielectric layer 320.
  • the dielectric layer 320 is located on the lower Between the electrode 310 and the upper electrode 330, the lower electrode 310 includes:
  • the first electrode layer 311 has a first sub-electrode region 3111 and a plurality of second sub-electrode regions 3112 connected to the first sub-electrode region 3111, the first sub-electrode region 3111 is in contact with the surface of the storage node, each second sub-electrode region
  • the electrode region 3112 extends in a direction away from the storage node contact 210, and each second sub-electrode region 3112 has a first end surface and a second end surface opposite to each other in the extending direction, and the first end surface is in contact with the surface of the storage node contact 210;
  • the second electrode layer 313 covers at least part of the surface of the first electrode layer 311 .
  • the structure of the lower electrode 310, the dielectric layer 320 and the upper electrode 330 constitute a double-sided capacitor structure, thereby increasing the capacitance area, and the capacitor structure can be increased without increasing the capacitance size.
  • the storage capacity of large capacitors is beneficial to the integration of capacitors.
  • the above-mentioned second electrode layer 313 covers part of the surface of the first electrode layer 311, for example, the second electrode layer 313 covers the sidewall of the second sub-electrode region 3112, and the first sub-electrode region 3111 has a first electrode region far away from the storage node contact 210.
  • the dielectric layer 320 covers the second electrode layer 313 , the second end surface of the second sub-electrode region 3112 and the third end surface of the first sub-electrode region 3111 , as shown in FIG. 3 and FIG. 4 .
  • the above capacitor structure can increase the storage capacity of the capacitor without increasing the size of the capacitor, thereby improving the storage performance of the storage unit.
  • the upper electrode 330 may include a third electrode layer 331 and a fourth electrode layer 332 , the third electrode layer 331 covers the dielectric layer 320 ; the fourth electrode layer 332 covers the third electrode layer 331 .
  • the materials that form the upper electrode 330 and the lower electrode 310 can be the same.
  • the first electrode layer 311 and the fourth electrode layer 332 can be made of silicon germanium with a larger area
  • the second electrode layer 313 and the third electrode layer 331 may be composed of thin titanium nitride.
  • the dielectric layer 320 can be made of a dielectric material with a high dielectric constant, such as HfO 2 , Al 2 O 3 , or HfSiO z , HfON, HfAlO z , ZrO 2 , ZrSiO z , Ta 2 O 5 , La 2 O 3.
  • HfLaO z , LaAlO z , LaSiO z , and nitrides or oxynitrides of the above materials are not limited to the above types, and those skilled in the art can make reasonable choices according to the existing technology.
  • the present disclosure ensures good electrical conductivity through such a double-electrode layer design.
  • the storage node contact 210 has an opposite first surface and a second surface, and the first surface is in contact with the first electrode layer 311; Two surface contacts, the transistor includes an active region structure 120 in contact with the second surface, the active region structure 120 has a third contact surface that contacts the storage node contact 210, preferably, the area of the second surface is larger than the area of the third contact surface .
  • the above-mentioned transistor includes an active region structure 120 and a gate structure 150
  • the active region structure 120 includes a source and a drain region and a channel region 122
  • the source and drain regions include a first The doped region 121 and the second doped region 123
  • the channel region 122 is located between the source and drain regions
  • the gate structure 150 is arranged around the channel region 122
  • the storage node contact is located on the source/drain region, wherein , in a direction perpendicular to the extension of the channel region 122 , any cross-sectional area of the storage node contact is larger than any cross-sectional area of the channel region 122 .
  • any cross-sectional width of the storage node contact 210 is greater than 1.1 times the width of the gate structure 150, for example, any cross-sectional width of the storage node contact 210 is 1.5 times that of the gate structure 150. 1.5 times, 2 times, 3 times of the width, when the width ratio of the two is greater than 1.1 times, to maintain a low contact resistance.
  • any cross-sectional area of the storage node contact 210 is larger than any cross-sectional area of the active region structure 120 in a direction parallel to the second surface, as shown in FIGS. 1 and 2 .
  • the cross-sectional area of the storage node contact 210 parallel to the second surface increases gradually.
  • the active region structure 120 includes a first doped region 121, a channel region 122 and a second doped region 123 sequentially connected along a direction away from the bit line structure 110, and the first doped region 121 is a drain region, the above-mentioned second doped region 123 is a source region.
  • the source region of the transistor is in contact with the storage node contact 210, and the drain region is located on the side of the drain away from the storage node contact 210 for contacting the bit line structure 110, as shown in FIGS.
  • the first doped region 121 may be a source region
  • the second doped region 123 may be a drain region
  • the drain region in the transistor is in contact with the storage node Contact 210
  • the source region is located on the side of the source away from the storage node contact 210 , and is used to contact the bit line structure 110 , which is not limited here.
  • the above-mentioned source and drain regions can be P-type doped or N-type doped, and the above-mentioned N-type doped source and drain regions are formed by ion implantation of N-type dopants such as phosphorus, arsenic, nitrogen, and antimony.
  • the P-type doped source and drain regions are formed by ion implantation of P-type dopants such as boron, aluminum, gallium and indium.
  • the memory cell of the present disclosure may further include an insulating layer surrounding the outer side of the storage node contact 210 , for example, the insulating layer is a silicon nitride layer 203 , as shown in FIGS. 1 and 2 .
  • the material for forming the storage node contact 210 may be, for example, polysilicon, metal or metal compound, such as titanium nitride, and is not particularly limited.
  • a memory as shown in FIG. 1 to FIG. 5 , including:
  • a plurality of the above storage units, the storage units are arranged in an array;
  • bit line structures 110 are electrically connected to the transistor;
  • a plurality of word line structures 190 are arranged at intervals along the second direction, the word line structures 190 are electrically connected to the transistors, and the second direction intersects the first direction.
  • bit line structure 110 is a buried bit line structure. But not limited to the above types, those skilled in the art can make a reasonable selection according to possible structures.
  • the bit line structure 110 is disposed on the side of the active region structure 120 away from the storage node contact 210 in the memory cell, as shown in FIGS. 1 and 2 .
  • the above-mentioned bit line structure 110 may include a first conductive layer 111 and a second conductive layer 112, the first conductive layer 111 covers part of the inner surface of the channel, the second conductive layer 112 is located in the channel and is wrapped by the first conductive layer 111, so as to Diffusion of the second conductive layer 112 to the substrate 100 is blocked, as shown in FIGS. 1 and 2 .
  • the first conductive layer 111 may be a titanium nitride layer, and the second conductive layer 112 may be metal tungsten.
  • each bit line structure 110 is arranged at intervals along the first direction;
  • a plurality of transistors are respectively formed on each bit line structure 110, and the bit line structure 110 is electrically connected to the source/drain regions of the transistors;
  • each word line structure 190 is arranged at intervals along the second direction, and the word line structures 190 are electrically connected to the gate structure 150 in the transistor circuit;
  • a capacitor is formed on the storage node contact 210, so that the capacitor includes a lower electrode 310, an upper electrode 330, and a dielectric layer 320, the dielectric layer 320 is located between the lower electrode 310 and the upper electrode 330, and the lower electrode 310 includes:
  • the first electrode layer 311 has a first sub-electrode region 3111 and a plurality of second sub-electrode regions 3112 connected to the first sub-electrode region 3111, the first sub-electrode region 3111 is in contact with the surface of the storage node contact 210, and each second The sub-electrode regions 3112 extend in a direction away from the storage node contact 210, and each second sub-electrode region 3112 has a first end surface and a second end surface opposite to each other in the extending direction, and the first end surface is in contact with the surface of the storage node contact 210;
  • the second electrode layer 313 covers at least part of the surface of the first electrode layer 311 .
  • the structure of the above-mentioned lower electrode, the dielectric layer and the upper electrode constitute a double-sided capacitor structure, thereby increasing the capacitance area, and the above-mentioned capacitor structure can be increased without increasing the capacitance size.
  • the storage capacity of large capacitors is beneficial to the integration of capacitors.
  • a substrate 100 is provided, and a plurality of embedded bit line structures 110 are formed in the substrate 100, and each bit line structure 110 is arranged at intervals along the first direction, as shown in FIGS. 7 and 8 , wherein, The first direction is the dotted line direction in FIG. 7 .
  • the aforementioned substrate 100 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or by performing selective An epitaxial thin film substrate obtained by epitaxial growth (SEG), etc., the substrate 100 may be a lightly doped substrate, such as a P-type or N-type substrate.
  • the step of forming a plurality of bit line structures 110 in the substrate 100 includes: forming a patterned first mask layer 101 on the substrate 100 through a photolithography process, through which the first mask layer 101 The substrate 100 is etched to form a plurality of trenches arranged along a first direction, and the bit line structure 110 is formed in the trenches.
  • the above-mentioned first mask layer 101 may be a hard mask material such as silicon nitride.
  • the above-mentioned bit line structure 110 may include a first conductive layer 111 and a second conductive layer 112, the first conductive layer 111 covers part of the inner surface of the channel, the second conductive layer 112 is located in the channel and covered by the first conductive layer 111 to block the diffusion of the second conductive layer 112 to the substrate 100, as shown in FIG. 6 .
  • the first conductive layer 111 may be a titanium nitride layer
  • the second conductive layer 112 may be metal tungsten.
  • a transistor is formed on the bit line structure 110, the transistor includes an active region structure 120 and a gate structure, so that the active region structure 120 is connected to the bit line structure 110, and the gate structure constitutes a DRAM
  • the word line structures 190 of the memory are arranged at intervals along the second direction, and the second direction intersects the first direction, as shown in FIGS. 9 to 19 .
  • the step of forming a transistor on the bit line structure 110 includes: forming a source/drain region on the bit line structure 110; forming a channel region 122; forming a drain/source region, the channel region being located at Between the source and drain regions; a gate structure 150 is formed, the gate structure 150 surrounds the channel region 122, and the storage node contact is located on the source/drain region, wherein, in a direction perpendicular to the extension of the channel region 122 , any cross-sectional area of the storage node contact 210 is larger than any cross-sectional area of the channel region 122 .
  • the active region structure 120 is formed on the bit line structure 110, so that a part of the active region structure 120 protrudes from the substrate 100, and the active region structure 120 is sequentially stacked in a direction away from the bit line structure 110.
  • the first doped region 121, the channel region 122 and the second doped region 123, the part of the active region structure 120 protruding from the substrate 100 includes the channel region 122, as shown in FIGS. 9 to 13;
  • a gate dielectric layer 130 surrounding the channel region 122 is formed on the substrate 100, as shown in FIG. , as shown in Figure 15.
  • the step of forming the active region structure 120 on the bit line structure 110 may include: depositing, for example, polysilicon in the trench with the bit line structure 110, and performing ion implantation on the polysilicon through the first mask layer 101 to form The first doped region 121 in contact with the bit line structure 110 is shown in FIG. 9 .
  • the first insulating layer 103 and the etch stop layer 102 are sequentially etched through the above-mentioned second mask layer 104 to form a plurality of Through holes, a first oxide interlayer 105 is formed on the inside of the above-mentioned through holes, polysilicon is filled in the through holes and ion implantation is performed to form a second doped region 123, after annealing, the first doped region 121 and A channel region 122 is formed between the second doped regions 123, as shown in FIG. Bare, as shown in Figure 13.
  • the first oxide spacer 105 is used to prevent ion diffusion to the surrounding during the subsequent ion implantation to form the second doped region 123.
  • the above-mentioned first oxide interlayer 105 may be silicon oxide.
  • the step of forming the gate structure 150 surrounding the active region structure 120 on the substrate 100 may include: forming a gate dielectric layer 130 on the surface of the channel region 122; depositing a barrier layer material 141 on the surface of the gate dielectric layer 130; The gate metal 151 is filled in the isolation groove formed between the adjacent channel regions 122, and the gate metal 151 covers the surface of the barrier layer material 141; the gate metal 151 and the barrier layer material 141 are etched to expose the gate dielectric layer 130 , the remaining barrier layer material 141 forms the gate barrier layer 140; backfills the first isolation material; selectively etches the first isolation material, the gate metal, and the gate barrier layer, and fills the second isolation material.
  • a barrier layer material 141 and a gate metal 151 are sequentially formed, and the gate metal 151 and the barrier layer material 141 are sequentially etched to form a gate surrounding the gate dielectric layer 130 Structure 150, part of the gate barrier layer 140 is located between the gate structure 150 and the gate dielectric layer 130, as shown in FIG. 14 to FIG. .
  • the etch stop layer 102 is located between the gate structure 150 and the substrate 100 .
  • the first isolation material forms an etching buffer layer 106 covering the gate structure 150 and the gate barrier layer 140
  • the second isolation material forms a second insulating layer 160 covering the etching buffer layer 106 , as shown in FIG. 16 .
  • the gate barrier layer 140 can be used as a protective layer for the gate dielectric layer 130
  • the material of the barrier layer 141 can be titanium nitride
  • the gate metal 151 can be metal tungsten, both of which have a high etching selectivity (W/TIN >4:1)
  • the gate dielectric layer 130 can be used as the etch stop layer 102, and it also has a high etch selectivity ratio (TIN/OXI>10:1) with titanium nitride, so that the end of the active region structure 120 can be avoided damaged during etching.
  • the step of forming a transistor on the bit line structure 110 may further include: forming a plurality of isolation grooves penetrating through the gate structure on the substrate 100, each isolation groove being arranged at intervals along the second direction, To remove part of the gate structure located between adjacent channel regions 122, so that the gate structure 150 independently surrounds each channel region 122, and the gate structure between adjacent isolation trenches constitutes a word line structure 190, as shown in FIG. 17 to Figure 19.
  • the step of forming the isolation groove in the gate structure 150 between adjacent active region structures 120 includes: sequentially forming a third mask layer 107 on the second insulating layer 160 and patterning photolithography Adhesive layer 108, as shown in Figure 17 to Figure 18, patterned photoresist layer 108 has the patterned area corresponding to the pre-formed isolation groove; Etching the third mask layer 107, with patterned photoresist The patterned area in the layer 108 is transferred to the third mask layer 107 to form a patterned third mask layer 107, and the second insulating layer 160, the etching buffer layer 106 and the second insulating layer 160 are etched through the third mask layer 107.
  • the gate structure 150 located between the adjacent active region structures 120 is etched at the etch stop layer 102 to form the aforementioned isolation trench, as shown in FIG. 19 .
  • the etching buffer layer 106 can play the role of etching buffer in the process of etching to form the isolation trench, and the material forming the etching buffer layer 106 can be silicon nitride, but it is not limited to the above-mentioned types. Those skilled in the art can make reasonable selections based on the prior art.
  • a storage node contact 210 is formed on the transistor, as shown in FIGS. 20-23.
  • the above-mentioned storage node contact 210 may have an opposite first contact surface and a second surface, and the second surface is in contact with the active region structure 120 .
  • the step of forming the storage node contact 210 on the transistor includes: forming an interlayer dielectric layer covering the exposed surface of the transistor on the substrate 100, as shown in FIG. 20 ; forming a groove in the interlayer dielectric layer 202, the groove 202 exposes the surface of the source/drain region of the transistor, as shown in FIG. 21 to FIG. 22; a storage node contact 210 is formed in the groove 202, and the storage node contact 210 includes an opposite first surface and a second surface , in the direction away from the transistor, the cross-sectional area of the storage node contact 210 in the direction parallel to the second surface increases gradually, as shown in FIG. 23 .
  • the material for forming the storage node contact 210 may be a material, which will not be repeated here.
  • the step of forming the interlayer dielectric layer covering the exposed surface of the transistor may include: forming a second oxide interlayer 170 and a third insulating layer 180 in the isolation trench and on the second insulating layer 160, as shown in FIG. 20 shown.
  • the above-mentioned second oxide interlayer 170 can reduce the stress and parasitic capacitance of the device, and the material can be silicon oxide.
  • the step of forming the groove 202 penetrating to the active region structure 120 in the interlayer dielectric layer may include: forming a patterned fourth mask layer 201 on the interlayer dielectric layer, the fourth mask layer 201 has a patterned area corresponding to the pre-formed groove 202, as shown in FIG. 21; the interlayer dielectric layer is etched through the fourth mask layer 201 to form the above-mentioned groove 202 in the interlayer dielectric layer, As shown in Figure 22.
  • the manufacturing method of the present disclosure may further include the following step: forming an insulating layer in the groove 202 , and the insulating layer is located on the sidewall of the groove 202 .
  • a silicon nitride layer 203 covering the inner wall of the groove 202 is formed.
  • a capacitor is formed on the storage node contact 210 such that the lower electrode 310 of the capacitor is in contact with the first contact surface, as shown in FIGS. 24 to 31 .
  • the step of forming a capacitor on the storage node contact 210 includes: forming a capacitor column 302 on the storage node contact 210, and the capacitor column 302 may extend in a direction away from the storage node contact 210, as shown in FIG. 24 to FIG. 25; the first electrode layer 311 is formed by etching the capacitance column, and the first electrode layer 311 includes a first sub-electrode region 3111 and a plurality of second sub-electrode regions 3112, as shown in FIG. 26 and FIG.
  • the first electrode layer 311 is deposited on the surface of the layer 311; the initial second electrode layer is etched back, and the surfaces of the first sub-electrode region 3111 and the plurality of second sub-electrode regions 3112 are exposed to form the second electrode layer 313, the first electrode Layer 311 and the second electrode layer 313 constitute the lower electrode 310 of the capacitor, as shown in Figure 28; a dielectric layer 320 is formed on the surface of the lower electrode 310, as shown in Figure 29; an upper electrode 330 is formed on the dielectric layer 320, as shown in Figure 30 and Figure 31.
  • the above-mentioned first sub-electrode region 3111 covers the first contact surface of the storage node contact 210, and the first sub-electrode region 3111 has a third end surface far away from the first contact surface, and one end of the second sub-electrode region 3112 is connected to the first sub-electrode
  • the regions 3111 are connected, and each second sub-electrode region 3112 extends in a direction away from the storage node contact 210, and each second sub-electrode region 3112 has a first end surface and a second end surface opposite to each other in the extending direction, and the first end surface and the first end surface are opposite to each other. contact surfaces.
  • the manufacturing process of the capacitor in the above embodiment has good stability, and the capacitor is not easy to be bent or collapsed.
  • the step of forming the capacitor column 302 on the storage node contact 210 may include: covering the storage node contact 210 with a capacitor material layer 301, as shown in FIG. 24, the capacitor material layer 301 may be polysilicon; The etching process forms a capacitive pillar 302, as shown in FIG. 25 .
  • the step of etching the capacitor column 302 to form the first electrode layer 311 may include: forming a fourth insulating layer 303 covering the capacitor column 302 , as shown in FIG. 26 ; and the etching channel of the capacitor column 302, so as to etch the capacitor column 302 to form a first sub-electrode region 3111 and a plurality of second sub-electrode regions 3112.
  • the first sub-electrode region 3111 and the second sub-electrode region 3112 constitute a U-shaped cross section of the first electrode layer 311 , as shown in FIG. 27 .
  • the step of forming the second electrode layer 313 on the sidewall of the second sub-electrode region 3112 may include: forming a second electrode material layer covering the first electrode layer 311, and etching the second electrode material layer to form The second electrode layer 313 covering the sidewall of the second sub-electrode region 3112, the second sub-electrode region 3112 has an exposed second end face away from the storage node contact 210, and the first sub-electrode region 3111 has an exposed second end face far away from the storage node contact 210.
  • the third end surface is as shown in FIG. 28 . After the dielectric layer 320 is formed, the dielectric layer 320 simultaneously covers the second end surface and the third end surface.
  • the material for forming the second electrode layer 313 may be titanium nitride, but it is not limited to the above types, and those skilled in the art can make a reasonable selection according to possible materials.
  • the step of covering the upper electrode 330 on the dielectric layer 320 may include: covering the third electrode layer 331 on the dielectric layer 320, as shown in FIG. 30 ; covering the fourth electrode layer on the third electrode layer 331 332, as shown in Figure 31.
  • the third electrode layer 331 and the fourth electrode layer 332 together constitute the upper electrode 330
  • the material forming the third electrode layer 331 may be titanium nitride
  • the material forming the fourth electrode layer 332 may be silicon germanium, but It is not limited to the above-mentioned types, and those skilled in the art can make reasonable selections according to possible materials.
  • the above capacitor structure can increase the storage capacity of the capacitor without increasing the size of the capacitor, thereby facilitating the integration of the capacitor;
  • the present disclosure also provides a manufacturing method of the above-mentioned memory.
  • the manufacturing process of the capacitor in the above-mentioned manufacturing method has good stability, and the capacitor is not easy to bend or collapse.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开提供了一种存储单元、存储器及其制作方法。该存储单元包括顺序连接的晶体管、存储节点接触和电容器，电容器包括下电极、上电极和电介质层，电介质层位于下电极与上电极之间，下电极包括：第一电极层，具有第一子电极区域以及与第一子电极区域连接的多个第二子电极区域，第一子电极区域与存储节点接触的表面接触，各第二子电极区域沿远离存储节点接触的方向延伸，且各第二子电极区域在延伸方向上具有相对的第一端面和第二端面，第一端面与存储节点接触的表面接触；第二电极层，覆盖于第一电极层的至少部分表面上。上述双面电容器结构增大了电容面积，上述电容器结构可以在不增大电容尺寸的情况下增大电容的储电量，从而有利于电容器的集成。

Description

存储单元、存储器及其制作方法
本公开以2021年12月9日递交的、申请号为202111516468.2且名称为“存储单元、存储器及其制作方法”的专利文件为优先权文件，该文件的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种存储单元、存储器及其制作方法。
背景技术
动态随机存取存储器(DRAM)单元包括用于存储电荷的电容器和存取电容器的晶体管。DRAM以电容器上的电荷的形式存储数据，所以需要在每几个毫秒的间隔即将电容器作规则性的再充电，而电容器的电容越大，储存在DRAM中的数据也可被维持得越久。
为了在一片晶圆上做出更多的芯片(Chip)，一个方法是尺寸微缩，另外则是结构的变化。目前DRAM主要是6F2结构，当尺寸微缩到一定程度时，4F2结构将会开启新的时代。在4F2结构中，电容结构也发生了相应的变化，目前主要是堆叠式电容，而堆叠式电容为保证高的存储电容量，往往占用较大的芯片面积，以及形成较高的电容高度，这不仅会妨碍集成度的提高，而且会导致容易发生弯曲和倒塌，特别是随着现在4F2结构的发展，对现在的堆叠式电容结构进行改进，提供一种新的3D柱状电容结构十分重要。
发明内容
本公开的主要目的在于提供一种存储单元、存储器及其制作方法，以解决现有技术中DRAM的电容器受尺寸限制而导致集成度难以提高的问题。
为了实现上述目的，根据本公开的一个方面，提供了一种存储单元，包括：顺序连接的晶体管、存储节点接触和电容器，电容器包括下电极、上电极和电介质层，电介质层位于下电极与上电极之间，下电极包括：第一电极层，具有第一子电极区域以及与第一子电极区域连接的多个第二子电极区域，第一子电极区域与存储节点接触的表面接触，各第二子电极区域沿远离存储节点接触的方向延伸，且各第二子电极区域在延伸方向上具有相对的第一端面和第二端面，第一端面与存储节点接触的表面接触；第二电极层，覆盖于第一电极层的至少部分表面上。
根据本公开的另一方面，提供了一种存储器，包括：多个如上述的存储单元，存储单元呈阵列排布；沿第一方向间隔设置的多条位线结构，位线结构与存储单元中的晶体管电连接；沿第二方向间隔设置的多条字线结构，字线结构与晶体管电连接，第二方向与第一方向相交。
根据本公开的另一方面，还提供了一种存储器的制作方法，包括以下步骤：提供衬底，并在衬底中形成多条位线结构，各条位线结构沿第一方向间隔设置；在各条位线结构上分别 形成多个晶体管，位线结构与晶体管电连接；形成多条字线结构，各条字线结构沿第二方向间隔设置，字线结构与晶体管电连接，第二方向与第一方向相交；在晶体管上形成存储节点接触；在存储节点接触上形成电容器，使电容器包括下电极、上电极和电介质层，电介质层位于下电极与上电极之间，下电极包括：第一电极层，具有第一子电极区域以及与第一子电极区域连接的多个第二子电极区域，第一子电极区域与存储节点接触的表面接触，各第二子电极区域沿远离存储节点接触的方向延伸，且各第二子电极区域在延伸方向上具有相对的第一端面和第二端面，第一端面与存储节点接触的表面接触；第二电极层，覆盖于第一电极层的至少部分表面上。
应用本公开的技术方案，提供了一种存储单元，包括顺序连接的电容器、存储节点接触和晶体管，电容器具有下电极、上电极和电介质层，电介质层位于下电极与上电极之间，下电极包括第一电极层和第二电极层，第一电极层具有第一子电极区域以及与第一子电极区域连接的多个第二子电极区域，第一子电极区域与存储节点接触的表面接触，各第二子电极区域沿远离存储节点接触的方向延伸，且各第二子电极区域在延伸方向上具有相对的第一端面和第二端面，第一端面与存储节点接触的表面接触，第二电极层覆盖于第一电极层的至少部分表面上，上述下电极的结构与电介质层和上电极构成了双面电容器结构，从而增大了电容面积，上述电容器结构可以在不增大电容尺寸的情况下增大电容的储电量，从而有利于电容器的集成。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1示出了在本公开实施方式所提供的一种存储单元在A-A＇方向的剖面结构示意图；
图2示出了在本公开实施方式所提供的一种存储单元在B-B＇方向的剖面结构示意图，其中，A-A＇方向与B-B＇方向垂直；
图3示出了图1和图2中所示的上电极、下电极以及电介质层的剖面结构示意图；
图4示出了图3中所示的下电极中第一子电极区域的俯视结构示意图；
图5示出了一种具有图1和图2所示的存储单元的DRAM存储器的俯视结构示意图；
图6示出了在本公开实施方式所提供的一种DRAM存储器的制作方法的流程示意图；
图7示出了在本公开实施方式所提供的一种DRAM存储器的制作方法中，在衬底中形成位线结构后基体的剖面结构示意图；
图8示出了图7所示的基体的俯视结构示意图；
图9示出了在图7所示的衬底中形成与位线结构接触的第一掺杂区后基体的剖面结构示意图；
图10示出了将图9所示的第一掩膜层去除并在衬底上顺序形成刻蚀停止层、第一绝缘层以及第二掩膜层后基体的剖面结构示意图；
图11示出了图10所示的基体的俯视结构示意图；
图12示出了在图11所示的通孔中形成沟道区和第二掺杂区后基体的剖面结构示意图；
图13示出了去除图12所示的第一绝缘层和第一氧化物隔层后基体的剖面结构示意图；
图14示出了在图13所示的有源区结构上覆盖栅介质层、阻挡层材料和栅极金属后基体的剖面结构示意图；
图15示出了刻蚀图14所示的栅极金属和阻挡层材料以形成栅极和栅极阻挡层后基体的剖面结构示意图；
图16示出了在图15所示的栅极和栅极阻挡层上覆盖刻蚀缓冲层和第二绝缘层后基体的剖面结构示意图；
图17示出了在图16所示的第二绝缘层上顺序形成第三掩膜层和图形化光刻胶层后基体的俯视结构示意图；
图18(a)示出了图22所示的基体在A-A＇方向的剖面结构示意图；
图18(b)示出了图22所示的基体在B-B＇方向的剖面结构示意图；
图19(a)-(b)分别示出了通过图18(a)-(b)所示的第三掩膜层在在衬底上形成贯穿栅极结构的多条隔离槽后基体的剖面结构示意图；
图20(a)-(b)分别示出了在图19(a)-(b)所示的隔离槽中以及第二绝缘层上形成第二氧化物隔层和第三绝缘层后基体的剖面结构示意图；
图21(a)-(b)分别示出了在图20(a)-(b)所示的第三绝缘层上形成第四掩膜层后基体的剖面结构示意图；
图22(a)-(b)分别示出了通过图21(a)-(b)所示的第四掩膜层刻蚀形成贯穿至/漏极的凹槽后基体的剖面结构示意图；
图23(a)-(b)分别示出了在图22(a)-(b)所示的凹槽中形成存储节点接触后基体的剖面结构示意图；
图24(a)-(b)分别示出了在图23(a)-(b)所示的存储节点接触上覆盖电容材料层后基体的剖面结构示意图；
图25(a)-(b)分别示出了刻蚀图24(a)-(b)所示的电容材料层以形成与存储节点接触接触的电容柱后基体的剖面结构示意图；
图26(a)-(b)分别示出了形成覆盖图25(a)-(b)所示的电容柱的第四绝缘层后基体的剖面结构示意图；
图27(a)-(b)分别示出了刻蚀图26(a)-(b)所示的第四绝缘层和电容柱以形成第一电极层后基体的剖面结构示意图；
图28(a)-(b)分别示出了形成覆盖图27(a)-(b)所示的第一电极层的第二电极材料层并将第二电极材料层刻蚀形成第二电极层后基体的剖面结构示意图；
图29(a)-(b)分别示出了形成覆盖图28(a)-(b)所示的第二电极层和部分第一电极层的电介质层后基体的剖面结构示意图；
图30(a)-(b)分别示出了在图29(a)-(b)所示的电介质层上覆盖第三电极层后基体的剖面结构示意图；
图31(a)-(b)分别示出了在图30(a)-(b)所示的第三电极层上覆盖第四电极层后基体的剖面结构示意图。
其中，上述附图包括以下附图标记：
100、衬底；101、第一掩膜层；102、刻蚀停止层；103、第一绝缘层；104、第二掩膜层；105、第一氧化物隔层；106、刻蚀缓冲层；107、第三掩膜层；108、图形化光刻胶层；110、位线结构；111、第一导电层；112、第二导电层；120、有源区结构；121、第一掺杂区；122、沟道区；123、第二掺杂区；130、栅介质层；140、栅极阻挡层；141、阻挡层材料；150、栅极结构；151、栅极金属；160、第二绝缘层；170、第二氧化物隔层；180、第三绝缘层；190、字线结构；201、第四掩膜层；202、凹槽；203、氮化硅层；210、存储节点接触；301、电容材料层；302、电容柱；303、第四绝缘层；310、下电极；311、第一电极层；3111、第一子电极区域；3112、第二子电极区域；313、第二电极层；320、电介质层；330、上电极；331、第三电极层；332、第四电极层。
具体实施方式
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
为了使本技术领域的人员更好地理解本公开方案，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分的实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例。此外，术语“包括”和“具有” 以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本公开提出了一种存储单元，如图1至图5所示，包括顺序连接的晶体管、存储节点接触210和电容器，电容器包括下电极310、上电极330和电介质层320，电介质层320位于下电极310与上电极330之间，下电极310包括：
第一电极层311，具有第一子电极区域3111以及与第一子电极区域3111连接的多个第二子电极区域3112，第一子电极区域3111与存储节点接触的表面接触，各第二子电极区域3112沿远离存储节点接触210的方向延伸，且各第二子电极区域3112在延伸方向上具有相对的第一端面和第二端面，第一端面与存储节点接触210的表面接触；
第二电极层313，覆盖于第一电极层311的至少部分表面上。
采用本公开的上述存储单元，上述下电极310的结构与电介质层320和上电极330构成了双面电容器结构，从而增大了电容面积，上述电容器结构可以在不增大电容尺寸的情况下增大电容的储电量，从而有利于电容器的集成。
上述第二电极层313覆盖于第一电极层311的部分表面上，例如，第二电极层313覆盖第二子电极区域3112的侧壁，第一子电极区域3111具有远离存储节点接触210的第三端面，电介质层320覆盖第二电极层313、第二子电极区域3112的第二端面以及第一子电极区域3111的第三端面，如图3和图4所示。上述电容器结构可以在不增大电容尺寸的情况下增大电容的储电量，从而提高存储单元的存储性能。
在本公开的上述存储单元中，上电极330可以包括第三电极层331和第四电极层332，第三电极层331覆盖电介质层320；第四电极层332覆盖第三电极层331。
形成上电极330和下电极310的材料可以相同的，详细而言，第一电极层311和第四电极层332例如可以是由较大面积锗硅构成，第二电极层313和第三电极层331可以是由薄的氮化钛构成。电介质层320可以是由高介电常数的电介质材料，例如可以列举HfO 2、Al 2O 3，也可以是HfSiO z、HfON、HfAlO z、ZrO 2、ZrSiO z、Ta 2O 5、La 2O 3、HfLaO z、LaAlO z、LaSiO z以及上述材料的氮化物或氮氧化物，当然并不局限于上述种类，本领域技术人员可以根据现有技术进行合理选取。本公开通过这样的双电极层设计保证了良好的导电性能。
在本公开的上述存储单元中，存储节点接触210具有相对的第一表面和第二表面，第一表面与第一电极层311接触；晶体管设置于存储节点接触210远离电容器的一侧并与第二表面接触，晶体管包括有源区结构120与第二表面接触，有源区结构120具有与存储节点接触210接触的第三接触面，优选地，第二表面的面积大于第三接触面的面积。
在一种优选的实施方式中，上述晶体管包括有源区结构120和栅极结构150，有源区结构120包括源极和漏极区以及沟道区122，源极和漏极区包括第一掺杂区121和第二掺杂区123，沟道区122位于源极和漏极区之间，栅极结构150环绕沟道区122设置，存储节点接触位于 源极/漏极区上，其中，在垂直于沟道区122延伸的方向上，存储节点接触的任意截面面积大于沟道区122的任意截面面积。
示例性的，在垂直于沟道区122延伸的方向上，存储节点接触210的任意截面宽度大于栅极结构150的宽度1.1倍，例如所述存储节点接触210的任意截面宽度是栅极结构150宽度的1.5倍、2倍、3倍，当所述二者的宽度比例大于1.1倍时，以保持一个低的接触电阻。
在一些实施方式中，在平行于第二表面的方向上，存储节点接触210的任意截面面积大于有源区结构120的任意截面面积，如图1和图2所示。例如还可以，在远离晶体管的方向上，存储节点接触210的平行于第二表面的截面面积递增。
示例性的，有源区结构120包括沿远离位线结构110的方向顺序连接的第一掺杂区121、沟道区122和第二掺杂区123，上述第一掺杂区121为漏极区，上述第二掺杂区123为源极区。此时，晶体管中的源极区与存储节点接触210接触，漏极区位于漏极远离存储节点接触210的一侧，用于与位线结构110接触，如图1和图2所示，但有源区结构并不局限于上述形式，上述第一掺杂区121可以为源极区，上述第二掺杂区123可以为漏极区，此时，晶体管中的漏极区与存储节点接触210接触，源极区位于源极远离存储节点接触210的一侧，用于与位线结构110接触，在此不做限定。
上述源极和漏极区可以为P型掺杂或N型掺杂，上述N型掺杂的源极和漏极区采用磷、砷、氮、锑等N型掺杂剂离子注入形成，上述P型掺杂的源极和漏极区采用硼、铝、镓、铟等P型掺杂剂离子注入形成。
本公开的上述存储单元中还可以包括环绕存储节点接触210外侧的绝缘层，示例性的，上述绝缘层为氮化硅层203，如图1和图2所示。形成上述存储节点接触210的材料例如可以为多晶硅、金属以及金属化合物，例如氮化钛等材料，并没有特别的限定。
根据本公开的另一方面，还提供了一种存储器，如图1至图5所示，包括：
多个上述的存储单元，存储单元呈阵列排布；
沿第一方向间隔设置的多条位线结构110，位线结构110与晶体管电连接；
沿第二方向间隔设置的多条字线结构190，字线结构190与晶体管电连接，上述第二方向与上述第一方向相交。
示例性的，上述位线结构110为埋入式位线结构。但并不局限于上述种类，本领域技术人员可以根据可能的结构进行合理选取。
在本公开的上述存储器中，在一些实施例中，位线结构110设置于有源区结构120远离存储单元中存储节点接触210的一侧，如图1和图2所示。
上述位线结构110可以包括第一导电层111和第二导电层112，第一导电层111覆盖沟道的部分内表面，第二导电层112位于沟道中并被第一导电层111包裹，以阻挡第二导电层112 向衬底100的扩散，如图1和图2所示。上述第一导电层111可以为氮化钛层，上述第二导电层112可以为金属钨。
根据本公开的另一方面，还提供了一种上述的存储器的制作方法，如图6所示，包括以下步骤：
提供衬底100，并在衬底100中形成多条位线结构110，各条位线结构110沿第一方向间隔设置；
在各条位线结构110上分别形成多个晶体管，位线结构110与晶体管中的源极/漏极区域电连接；
形成多条字线结构190，各条字线结构190沿第二方向间隔设置，字线结构190与晶体管电中的栅极结构150电连接；
在晶体管上形成存储节点接触210；
在存储节点接触210上形成电容器，使电容器包括下电极310、上电极330和电介质层320，电介质层320位于下电极310与上电极330之间，下电极310包括：
第一电极层311，具有第一子电极区域3111以及与第一子电极区域3111连接的多个第二子电极区域3112，第一子电极区域3111与存储节点接触210的表面接触，各第二子电极区域3112沿远离存储节点接触210的方向延伸，且各第二子电极区域3112在延伸方向上具有相对的第一端面和第二端面，第一端面与存储节点接触210的表面接触；
第二电极层313，覆盖于第一电极层311的至少部分表面上。
采用本公开的上述DRAM存储器的制作方法，上述下电极的结构与电介质层和上电极构成了双面电容器结构，从而增大了电容面积，上述电容器结构可以在不增大电容尺寸的情况下增大电容的储电量，从而有利于电容器的集成。
下面将结合附图更详细地描述根据本公开提供的DRAM存储器的制作方法的示例性实施方式。然而，这些示例性实施方式可以由多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的实施方式。应当理解的是，提供这些实施方式是为了使得本公开的公开彻底且完整，并且将这些示例性实施方式的构思充分传达给本领域普通技术人员。
首先，提供衬底100，并在衬底100中形成多条例如埋入式的位线结构110，各条位线结构110沿第一方向间隔设置，如图7和图8所示，其中，第一方向为图7中的虚线方向。
上述衬底100可以是硅衬底、绝缘体上硅(SOI)衬底、锗衬底、绝缘体上锗(GOI)衬底、硅锗衬底、III-V族化合物半导体衬底或通过执行选择性外延生长(SEG)获得的外延薄膜衬底等，衬底100可以是轻掺杂型的衬底，例如P型或者N型。
在一些实施方式中，在衬底100中形成多条位线结构110的步骤包括：通过光刻工艺在衬底100上形成图形化的第一掩膜层101，通过该第一掩膜层101刻蚀衬底100，以形成沿第一 方向排列的多个沟槽，在上述沟槽中形成位线结构110。上述第一掩膜层101可以为氮化硅等硬掩膜材料。
示例性的，上述位线结构110可以包括第一导电层111和第二导电层112，第一导电层111覆盖沟道的部分内表面，第二导电层112位于沟道中并被第一导电层111包裹，以阻挡第二导电层112向衬底100的扩散，如图6所示。上述第一导电层111可以为氮化钛层，上述第二导电层112可以为金属钨。
在形成上述位线结构110的步骤之后，在位线结构110上形成晶体管，晶体管包括有源区结构120和栅极结构，使有源区结构120与位线结构110连接，栅极结构构成DRAM存储器的字线结构190，字线结构190沿第二方向间隔设置，且第二方向与第一方向相交，如图9至图19所示。
在一些实施方式中，在位线结构110上形成晶体管的步骤包括：在位线结构110上形成源极/漏极区；形成沟道区122；形成漏极/源极区，沟道区位于源极和漏极区之间；形成栅极结构150，栅极结构150环绕沟道区122，存储节点接触位于源极/漏极区上，其中，在垂直于沟道区122延伸的方向上，存储节点接触210的任意截面面积大于沟道区122的任意截面面积。
示例性的，在位线结构110上形成有源区结构120，使有源区结构120中的部分突出于衬底100设置，有源区结构120具有沿远离位线结构110的方向顺序层叠的第一掺杂区121、沟道区122和第二掺杂区123，有源区结构120中突出于衬底100的部分包括沟道区122，如图9至图13所示；在衬底100上形成环绕沟道区122的栅介质层130，如图14所示；在衬底100上形成环绕栅介质层130的栅极结构150，栅极结构包括栅极结构150和栅介质层130，如图15所示。
具体地，在位线结构110上形成有源区结构120的步骤可以包括：在具有位线结构110的沟道中沉积例如多晶硅，并通过第一掩膜层101进行对多晶硅进行离子注入，以形成与位线结构110接触的第一掺杂区121，如图9所示。去除上述第一掩膜层101，在衬底100上述顺序形成刻蚀停止层102、第一绝缘层103以及多个图形化的第二掩膜层104，，以使刻蚀停止层102环绕有源区结构120，如图10和图11所示；通过上述第二掩膜层104顺序刻蚀第一绝缘层103和刻蚀停止层102，以形成与第一掺杂区121连通的多个通孔，在上述通孔的内部上形成第一氧化物隔层105，在通孔内填充例如多晶硅并进行离子注入，以形成第二掺杂区123，退火后在第一掺杂区121与第二掺杂区123之间形成沟道区122，如图12所示；去除上述第一绝缘层103和上述第一氧化物隔层105，以使沟道区122和第二掺杂区123裸露，如图13所示。
上述示例中，第一氧化物隔层105用于后续离子注入形成第二掺杂区123的过程中防止离子向周围扩散，上述第一氧化物隔层105还可以在去除第一绝缘层103的湿法刻蚀(WET)工艺中降低负载效应(loading effect)。上述第一氧化物隔层105可以为氧化硅。
示例性的，在衬底100上形成环绕有源区结构120的栅极结构150的步骤可以包括：在沟道区122表面形成栅介质层130；在栅介质层130表面沉积阻挡层材料141；在相邻沟道区 122之间形成的隔离槽内填充栅极金属151，栅极金属151覆盖阻挡层材料141的表面；刻蚀栅极金属151和阻挡层材料141，至曝露栅介质层130，剩余的阻挡层材料141形成栅极阻挡层140；回填第一隔离材料；选择性刻蚀第一隔离材料、栅极金属，及栅极阻挡层，并填充第二隔离材料。在上述刻蚀停止层102和上述栅介质层130上顺序形成阻挡层材料141和栅极金属151，并顺序刻蚀栅极金属151和阻挡层材料141，以形成环绕栅介质层130的栅极结构150，栅极阻挡层140中的部分位于栅极结构150与栅介质层130之间，如图14至图15所示，此时，晶体管中的栅极结构还包括上述栅极阻挡层140。在形成上述栅极结构150的步骤之后，刻蚀停止层102位于栅极结构150与衬底100之间。
上述第一隔离材料形成覆盖栅极结构150和栅极阻挡层140的刻蚀缓冲层106，上述第二隔离材料形成覆盖刻蚀缓冲层106的第二绝缘层160，如图16所示。
上述示例中，栅极阻挡层140可以作为栅介质层130的保护层，阻挡层材料141可以为氮化钛，栅极金属151可以为金属钨，两者具有高刻蚀选择比(W/TIN>4:1)，栅介质层130可以作为刻蚀停止层102，与氮化钛也具有高刻蚀选择比(TIN/OXI>10:1)，从而能够避免有源区结构120端部在刻蚀过程中受损。
在形成栅极结构150的步骤之后，在位线结构110上形成晶体管的步骤还可以包括：在衬底100上形成贯穿栅极结构的多条隔离槽，各隔离槽沿第二方向间隔设置，以去除位于相邻沟道区122之间的部分栅极结构，使得栅极结构150独立地环绕各沟道区122，相邻隔离槽之间的栅极结构构成字线结构190，如图17至图19所示。
示例性的，在位于相邻有源区结构120之间的栅极结构150中形成上述隔离槽的步骤包括：在上述第二绝缘层160上顺序形成第三掩膜层107和图形化光刻胶层108，如图17至图18所示，图形化光刻胶层108中具有与预形成的隔离槽对应的图形化区域；刻蚀第三掩膜层107，以将图形化光刻胶层108中的图形化区域转移至第三掩膜层107中，形成图形化的第三掩膜层107，并通过第三掩膜层107刻蚀第二绝缘层160、刻蚀缓冲层106以及位于相邻有源区结构120之间的栅极结构150，刻蚀停止在刻蚀停止层102，以形成上述隔离槽，如图19所示。
上述示例中，刻蚀缓冲层106可以在刻蚀形成隔离槽的过程中起到刻蚀缓冲的作用，形成刻蚀缓冲层106的材料可以为氮化硅，但并不局限于上述种类，本领域技术人员可以根据现有技术进行合理选取。
在位线结构110上形成晶体管的步骤之后，在晶体管上形成存储节点接触210，如图20至图23所示。
上述存储节点接触210可以具有相对的第一接触面和第二表面，第二表面与有源区结构120接触。
在一些实施方式中，在晶体管上形成存储节点接触210的步骤包括：在衬底100上形成覆盖晶体管的裸露表面的层间介质层，如图20所示；在层间介质层中形成凹槽202，凹槽202 曝露晶体管的源极/漏极区表面，如图21至图22所示；在凹槽202中形成存储节点接触210，存储节点接触210包括相对的第一表面和第二表面，在远离晶体管的方向上，存储节点接触210在平行于第二表面方向的截面面积递增，如图23所示。形成上述存储节点接触210的材料可以材料，在此不再赘述。
示例性的，形成上述覆盖晶体管的裸露表面的层间介质层的步骤可以包括：在上述隔离槽中以及第二绝缘层160上形成第二氧化物隔层170和第三绝缘层180，如图20所示。上述第二氧化物隔层170可以降低器件的应力和寄生电容，材料可以为氧化硅。
示例性的，在层间介质层中形成贯穿至有源区结构120的凹槽202的步骤可以包括：在上述层间介质层上形成图形化的第四掩膜层201，第四掩膜层201中具有与预形成的凹槽202对应的图形化区域，如图21所示；通过该第四掩膜层201刻蚀层间介质层，以在层间介质层中形成上述凹槽202，如图22所示。
在凹槽202中形成存储节点接触210的步骤之前，本公开的上述制作方法还可以包括以下步骤：在凹槽202内形成绝缘层，绝缘层位于所述凹槽202侧壁。示例性的，形成覆盖凹槽202内壁的氮化硅层203。
在晶体管上形成存储节点接触210的步骤之后，在存储节点接触210上形成电容器，使电容器中的下电极310与第一接触面接触，如图24至图31所示。
在一种些实施方式中，在存储节点接触210上形成电容器的步骤包括：在存储节点接触210上形成电容柱302，电容柱302可以沿远离存储节点接触210的方向延伸，如图24至图25所示；刻蚀电容柱形成第一电极层311，第一电极层311包括第一子电极区域3111以及多个第二子电极区域3112，如图26和图27所示；在第一电极层311表面上沉积初始第二电极层；回刻初始第二电极层，并曝露第一子电极区域3111、多个第二子电极区域3112的表面，以形成第二电极层313，第一电极层311和第二电极层313构成电容器的下电极310，如图28所示；在下电极310的表面上形成电介质层320，如图29所示；在电介质层320上形成上电极330，如图30和图31所示。
上述第一子电极区域3111覆盖于存储节点接触210的第一接触面，且第一子电极区域3111具有远离第一接触面的第三端面，第二子电极区域3112的一端与第一子电极区域3111连接，且各第二子电极区域3112沿远离存储节点接触210的方向延伸，各第二子电极区域3112在延伸方向上具有相对的第一端面和第二端面，第一端面与第一接触面接触。
上述实施方式中的电容制作工艺稳定性好，不容易发生电容弯曲或倒塌。
示例性的，在存储节点接触210上形成电容柱302的步骤可以包括：在存储节点接触210上覆盖电容材料层301，如图24所示，上述电容材料层301可以为多晶硅；采用光刻和刻蚀工艺形成电容柱302，如图25所示。
示例性的，将电容柱302刻蚀形成上述第一电极层311的步骤可以包括：形成覆盖电容柱302的第四绝缘层303，如图26所示；刻蚀形成顺序贯穿第四绝缘层303和电容柱302的刻 蚀通道，以将电容柱302刻蚀形成第一子电极区域3111以及多个第二子电极区域3112，在A-A＇方向和B-B＇方向上，由上述第一子电极区域3111以及第二子电极区域3112构成的第一电极层311的任意截面为U型，如图27所示。
示例性的，在第二子电极区域3112的侧壁上形成第二电极层313的步骤可以包括：形成覆盖第一电极层311的第二电极材料层，刻蚀第二电极材料层，以形成覆盖第二子电极区域3112侧壁的第二电极层313，第二子电极区域3112具有远离存储节点接触210的裸露的第二端面，第一子电极区域3111具有远离存储节点接触210的裸露的第三端面，如图28所示。在形成电介质层320后，电介质层320同时覆盖上述第二端面和第三端面。
在上述示例中，形成第二电极层313的材料可以为氮化钛，但并不局限于上述种类，本领域技术人员可以根据可能的材料进行合理选取。
示例性的，在电介质层320上覆盖上电极330的步骤可以包括：在上述电介质层320上覆盖第三电极层331，如图30所示；在上述第三电极层331上覆盖第四电极层332，如图31所示。
在上述示例中，第三电极层331和第四电极层332共同构成上电极330，形成第三电极层331的材料可以为氮化钛，形成第四电极层332的材料可以为锗硅，但并不局限于上述种类，本领域技术人员可以根据可能的材料进行合理选取。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
1)上述电容器结构可以在不增大电容尺寸的情况下增大电容的储电量，从而有利于电容器的集成；
2)本公开还提供了一种上述的存储器的制作方法，上述制作方法中的电容制作工艺稳定性好，不容易发生电容弯曲或倒塌。
以上所述仅为本公开的实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种存储单元，包括：顺序连接的晶体管、存储节点接触和电容器，所述电容器包括下电极、上电极和电介质层，所述电介质层位于所述下电极与所述上电极之间，所述下电极包括：
    第一电极层，具有第一子电极区域以及与所述第一子电极区域连接的多个第二子电极区域，所述第一子电极区域与所述存储节点接触的表面接触，各所述第二子电极区域沿远离所述存储节点接触的方向延伸，且各所述第二子电极区域在延伸方向上具有相对的第一端面和第二端面，所述第一端面与所述存储节点接触的表面接触；
    第二电极层，覆盖于所述第一电极层的至少部分表面上。
  2. 根据权利要求1所述的存储单元，其中，所述第二电极层覆盖于所述第二子电极区域的侧壁，所述第一子电极区域具有远离所述存储节点接触的第三端面，所述电介质层覆盖所述第二电极层、所述第二端面和所述第三端面。
  3. 根据权利要求1所述的存储单元，其中，所述上电极包括：
    第三电极层，覆盖所述电介质层；
    第四电极层，覆盖所述第三电极层。
  4. 根据权利要求1所述的存储单元，其中，所述存储节点接触包括相对的第一表面和第二表面，所述第一表面接触所述第一电极层，所述第二表面接触所述晶体管；其中，在远离所述晶体管的方向上，所述存储节点接触在平行于所述第二表面方向的截面面积递增。
  5. 根据权利要求1中所述的存储单元，其中，所述晶体管包括：
    源极/漏极区；
    沟道区，位于所述源极/漏极区中的源极区和漏极区之间；
    栅极结构，所述栅极结构环绕所述沟道区设置，所述存储节点接触位于所述源极/漏极区上，其中，在垂直于所述沟道区延伸的方向上，所述存储节点接触的任意截面面积大于所述沟道区的任意截面面积。
  6. 根据权利要求5中所述的存储单元，其中，在垂直于所述沟道区延伸的方向上，所述存储节点接触的任意截面宽度大于所述栅极结构的宽度1.1倍。
  7. 一种存储器，包括：
    多个如权利要求1至6中任一项所述的存储单元，所述存储单元呈阵列排布；
    沿第一方向间隔设置的多条位线结构，所述位线结构与所述存储单元中的晶体管电连接；
    沿第二方向间隔设置的多条字线结构，所述字线结构与所述晶体管电连接，所述第二方向与所述第一方向相交。
  8. 根据权利要求7所述的存储器，其中，所述位线结构为埋入式位线结构。
  9. 一种存储器的制作方法，包括以下步骤：
    提供衬底，并在所述衬底中形成多条位线结构，各条所述位线结构沿第一方向间隔设置；
    在各条所述位线结构上分别形成多个晶体管，所述位线结构与所述晶体管电连接；
    形成多条字线结构，各条字线结构沿第二方向间隔设置，所述字线结构与所述晶体管电连接，所述第二方向与所述第一方向相交；
    在所述晶体管上形成存储节点接触；
    在所述存储节点接触上形成电容器，使所述电容器包括下电极、上电极和电介质层，所述电介质层位于所述下电极与所述上电极之间，所述下电极包括：
    第一电极层，具有第一子电极区域以及与所述第一子电极区域连接的多个第二子电极区域，所述第一子电极区域与所述存储节点接触的表面接触，各所述第二子电极区域沿远离所述存储节点接触的方向延伸，且各所述第二子电极区域在延伸方向上具有相对的第一端面和第二端面，所述第一端面与所述存储节点接触的表面接触；
    第二电极层，覆盖于所述第一电极层的至少部分表面上。
  10. 根据权利要求9所述的存储器的制作方法，其中，在各条所述位线结构上形成多个所述晶体管的步骤包括：
    在所述位线结构上形成源极/漏极区；
    形成沟道区；
    形成漏极/源极区，所述沟道区位于所述漏极/源极区中的源极和漏极区之间；
    形成栅极结构，所述栅极结构环绕所述沟道区，所述存储节点接触位于所述源极/漏极区上，其中，在垂直于所述沟道区延伸的方向上，所述存储节点接触的任意截面面积大于所述沟道区的任意截面面积。
  11. 根据权利要求10所述的制作方法，其中，形成所述栅极结构的步骤包括：
    在所述沟道区表面形成栅介质层；
    在所述栅介质层表面沉积栅极阻挡层；
    在相邻所述沟道区之间形成的隔离槽内填充栅极金属，所述栅极金属覆盖所述栅极阻挡层的表面；
    刻蚀所述栅极金属和所述栅极阻挡层，至曝露所述栅介质层；
    回填第一隔离材料；
    选择性刻蚀所述第一隔离材料、所述栅极金属，及所述栅极阻挡层，并填充第二隔离材料。
  12. 根据权利要求9中所述的存储器的制作方法，其中，在所述晶体管上形成所述存储节点接触的步骤包括：
    形成覆盖所述晶体管的裸露表面的层间介质层；
    在所述层间介质层中形成凹槽，所述凹槽曝露所述晶体管的源极/漏极区表面；
    在所述凹槽中形成所述存储节点接触，所述存储节点接触包括相对的第一表面和第二表面，在远离所述晶体管的方向上，所述存储节点接触在平行于所述第二表面方向的截面面积递增。
  13. 根据权利要求12中所述的存储器的制作方法，其中，在所述晶体管上形成所述存储节点接触的步骤还包括：
    在所述凹槽内形成绝缘层，所述绝缘层位于所述凹槽侧壁。
  14. 根据权利要求9至13中任一项所述的存储器的制作方法，其中，在所述存储节点接触上形成所述电容器的步骤包括：
    在所述存储节点接触上形成电容柱；
    刻蚀所述电容柱形成所述第一电极层，所述第一电极层包括所述第一子电极区域以及所述多个第二子电极区域；
    在所述第一电极层表面上沉积初始第二电极层；
    回刻所述初始第二电极层，并曝露所述第一子电极区域、多个第二子电极区域的表面，以形成所述第二电极层，所述第一电极层和所述第二电极层构成所述下电极；
    在所述下电极的表面上形成所述电介质层；
    在所述电介质层上形成所述上电极。
  15. 根据权利要求14中所述的存储器的制作方法，其中，形成上电极的步骤包括：
    形成第三电极层，所述第三电极层覆盖所述电介质层；
    形成第四电极层，所述第四电极层覆盖所述第三电极层。
PCT/CN2022/077310 2021-12-09 2022-02-22 存储单元、存储器及其制作方法 WO2023103182A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/179,740 US20230209807A1 (en) 2021-12-09 2023-03-07 Memory cell, memory and method for manufacturing memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111516468.2 2021-12-09
CN202111516468.2A CN114284270A (zh) 2021-12-09 2021-12-09 存储单元、存储器及其制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/179,740 Continuation US20230209807A1 (en) 2021-12-09 2023-03-07 Memory cell, memory and method for manufacturing memory

Publications (1)

Publication Number Publication Date
WO2023103182A1 true WO2023103182A1 (zh) 2023-06-15

Family

ID=80872276

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/077310 WO2023103182A1 (zh) 2021-12-09 2022-02-22 存储单元、存储器及其制作方法

Country Status (3)

Country Link
US (1) US20230209807A1 (zh)
CN (1) CN114284270A (zh)
WO (1) WO2023103182A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116997177A (zh) * 2022-04-22 2023-11-03 长鑫存储技术有限公司 一种半导体器件及其制造方法
CN115458483A (zh) * 2022-08-29 2022-12-09 长鑫存储技术有限公司 半导体结构的制作方法及其结构
CN117835694A (zh) * 2022-09-27 2024-04-05 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020003280A1 (en) * 2000-06-28 2002-01-10 Yusuke Kohyama Electric fuse whose dielectric breakdown resistance is controlled by injecting impurities into an insulating film of a capacitor structure, and a method for manufacturing the same
US20020179948A1 (en) * 2001-06-01 2002-12-05 Jae-Goo Lee Integrated circuit memory device and method of fabricating the same
US20030224571A1 (en) * 2002-05-28 2003-12-04 Shinpei Iijima Semiconductor integrated circuit device with capacitor of crown structure and method of manufacturing the same
US20110292717A1 (en) * 2010-05-28 2011-12-01 Elpida Memory, Inc. Semiconductor device
US20200395436A1 (en) * 2019-06-11 2020-12-17 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
CN113764417A (zh) * 2020-06-03 2021-12-07 三星电子株式会社 半导体器件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020003280A1 (en) * 2000-06-28 2002-01-10 Yusuke Kohyama Electric fuse whose dielectric breakdown resistance is controlled by injecting impurities into an insulating film of a capacitor structure, and a method for manufacturing the same
US20020179948A1 (en) * 2001-06-01 2002-12-05 Jae-Goo Lee Integrated circuit memory device and method of fabricating the same
US20030224571A1 (en) * 2002-05-28 2003-12-04 Shinpei Iijima Semiconductor integrated circuit device with capacitor of crown structure and method of manufacturing the same
US20110292717A1 (en) * 2010-05-28 2011-12-01 Elpida Memory, Inc. Semiconductor device
US20200395436A1 (en) * 2019-06-11 2020-12-17 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
CN113764417A (zh) * 2020-06-03 2021-12-07 三星电子株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
US20230209807A1 (en) 2023-06-29
CN114284270A (zh) 2022-04-05

Similar Documents

Publication Publication Date Title
US9768186B2 (en) Three dimensional memory device having well contact pillar and method of making thereof
US11784256B2 (en) Semiconductor devices
WO2023103182A1 (zh) 存储单元、存储器及其制作方法
WO2023130883A1 (zh) 半导体结构及其制造方法
KR20180019824A (ko) 반도체 장치 및 그 제조 방법
CN105390542B (zh) 具有旁路栅极的半导体器件及其制备方法
KR20180115158A (ko) 반도체 장치 및 그 제조 방법
CN110896074A (zh) 集成电路存储器及其制造方法
KR20180056031A (ko) 반도체 장치 및 그 제조 방법
KR102587153B1 (ko) 3차원 메모리 디바이스 및 그 제조 방법
CN110931558A (zh) 双垂直沟道晶体管、集成电路存储器及其制备方法
KR20200057289A (ko) 반도체 장치 및 그 제조 방법
US8581315B2 (en) Semiconductor device having cylindrical lower electrode of capacitor and manufacturing method thereof
CN111373538B (zh) 三维存储器件及其制造方法
WO2014126214A1 (ja) 半導体装置
CN111916399B (zh) 一种半导体器件的制备方法以及半导体器件
CN115621195A (zh) 半导体器件及其制造方法
CN110931557A (zh) 半导体器件及其制备方法
WO2024037164A1 (zh) 半导体器件及其形成方法
US20240130116A1 (en) Semiconductor device
US11785869B2 (en) Memory device and method of manufacturing the same
CN218941671U (zh) 半导体器件
TW202215642A (zh) 積體電路裝置
CN114597175A (zh) 半导体存储装置及其制作方法
KR20210063577A (ko) 반도체 장치 및 이의 제조 방법