WO2023206812A1 - 半导体结构及其制备方法、存储器 - Google Patents

半导体结构及其制备方法、存储器 Download PDF

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Publication number
WO2023206812A1
WO2023206812A1 PCT/CN2022/104019 CN2022104019W WO2023206812A1 WO 2023206812 A1 WO2023206812 A1 WO 2023206812A1 CN 2022104019 W CN2022104019 W CN 2022104019W WO 2023206812 A1 WO2023206812 A1 WO 2023206812A1
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Prior art keywords
layer
semiconductor structure
sacrificial layer
initial
trench
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PCT/CN2022/104019
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English (en)
French (fr)
Inventor
刘佑铭
肖德元
蒋懿
邵光速
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长鑫存储技术有限公司
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Priority to US18/157,073 priority Critical patent/US20230345706A1/en
Publication of WO2023206812A1 publication Critical patent/WO2023206812A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure, a manufacturing method thereof, and a memory.
  • Dynamic random access memory is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage equipment or devices. Dynamic random access memory is composed of multiple repeated storage cells. Each storage unit usually includes a capacitor and a transistor. The capacitor stores data information, and the transistor controls the reading of data information in the capacitor.
  • semiconductor structures In order to improve the storage capacity of semiconductor structures, semiconductor structures have developed from two-dimensional structures to three-dimensional structures. However, when forming a three-dimensional semiconductor structure, it is difficult to dope the active region of the semiconductor structure, which increases the difficulty of preparing the semiconductor structure. The yield of semiconductor structures is also reduced.
  • embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and a memory to reduce the difficulty of preparing the active layer.
  • a first aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which includes:
  • each column of the stacked structures including a plurality of first sacrificial layers and active layers that are alternately stacked;
  • Part of the first sacrificial layer is removed to form first trenches and second trenches spaced apart along the second direction, and a portion of the surface of each active layer is exposed to the first trench and the second trench.
  • the groove wherein the second direction intersects the first direction, and the first direction and the second direction are both parallel to the surface of the substrate;
  • the exposed active layers are ion doped to form first doped regions and second doped regions spaced apart in each of the active layers, located between the first doped region and the The active layer between the second doped regions forms a channel region.
  • the method for manufacturing a semiconductor structure provided by embodiments of the present disclosure has the following advantages:
  • a first trench and a second trench are formed, and a portion of the active layer is exposed through the first trench and the second trench. After that, the exposed portion can be modified through an ion doping process.
  • the active layer is doped to form the first doped region and the second doped region, which reduces the difficulty of preparing the semiconductor structure and also improves the yield of the semiconductor structure.
  • removing a portion of the first sacrificial layer includes:
  • the second sacrificial layer fills the area between any adjacent stacked structures and covers the top surface of the stacked structures;
  • Remove part of the second sacrificial layer form a plurality of etching holes in a direction perpendicular to the substrate, each etching hole is located between adjacent stack structures, and expose the stack On the side of the structure, remove part of the first sacrificial layer along the etching hole.
  • the etching hole includes a first etching hole and a second etching hole, the first etching hole corresponds to the first doping region, and the second etching hole corresponds to the second doped region.
  • the step of forming a plurality of columns of stacked structures spaced along the first direction on the substrate includes:
  • first initial sacrificial layers and initial active layers that are stacked and alternately arranged on the substrate
  • a groove bottom of the third trench is located within the substrate.
  • the preparation method further includes:
  • a third etching hole is formed in the second sacrificial layer between any two adjacent columns of stacked structures, the third etching hole corresponds to the channel region, and the third etching hole is located at the between the first etching hole and the second etching hole, without exposing the side of the stacked structure;
  • a first support structure is formed in the third etched hole, and a second support structure is formed in the first trench and the second trench.
  • the preparation method further includes:
  • a gate oxide layer and a conductive layer are sequentially formed on the surface of the channel region of the active layer.
  • the step of removing the remaining second sacrificial layer and the first sacrificial layer includes:
  • the second sacrificial layer located between any adjacent stacked structures is wet etched, and the first sacrificial layer in each column of the stacked structures is wet etched to form the filling region.
  • the preparation method further includes:
  • An insulating layer is formed, covering the dielectric layer and connected to the first support structure and the second support structure.
  • the insulation layer, the first support structure and the second support structure are made of the same material.
  • the first doping region, the second doping region and the channel region have the same type of doping ions, and the concentration of doping ions in the channel region is less than that of the third doping region. Concentrations of doping ions in a doped region and the second doped region.
  • the step of forming a stacked and alternately arranged first initial sacrificial layer and an initial doping layer on the substrate includes:
  • the first initial sacrificial layer includes silicon germanium, silicon phosphide or silicon nitride.
  • a second aspect of the embodiments of the present disclosure provides a semiconductor structure, which is manufactured by the method for preparing a semiconductor structure provided in the first aspect.
  • a third aspect of the embodiment of the present disclosure provides a memory.
  • the memory includes the semiconductor structure provided in the second aspect.
  • the memory further includes a storage structure and a bit line structure.
  • the storage structure is connected to the first doped region or One of the second doped regions is electrically connected, and the bit line structure is electrically connected to the other one of the first doped region or the second doped region.
  • the bit line structure includes a plurality of bit lines arranged in parallel and spaced apart, and the plurality of bit lines are arranged in a stepped manner in a direction perpendicular to the substrate.
  • Figure 1 is a process flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of forming a first initial sacrificial layer and an initial active layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a cross-sectional view along the direction A-A in Figure 2;
  • Figure 4 is a schematic structural diagram of forming a mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 5 is a cross-sectional view along the A-A direction in Figure 4.
  • Figure 6 is a schematic structural diagram of a stacked structure formed in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 7 is a cross-sectional view along the A-A direction in Figure 6;
  • FIG. 8 is a cross-sectional view in the A-A direction after forming the second sacrificial layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 9 is a cross-sectional view in the B-B direction after forming the second sacrificial layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 10 is a schematic structural diagram of forming a second photoresist layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 11 is a schematic structural diagram of forming an etching hole in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 12 is a cross-sectional view in the A-A direction after forming an etching hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 13 is a cross-sectional view in the B-B direction after forming an etching hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 14 is a schematic structural diagram of forming a first doped region and a second doped region in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 15 is a schematic structural diagram of forming a third etching hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 16 is a cross-sectional view of the support structure formed in the A-A direction in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 17 is a cross-sectional view of the support structure formed in the B-B direction in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 18 is a cross-sectional view in the A-A direction after removing the remaining second sacrificial layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 19 is a cross-sectional view in the B-B direction after removing the remaining second sacrificial layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 20 is a cross-sectional view in the A-A direction after removing the remaining first sacrificial layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 21 is a cross-sectional view in the B-B direction after removing the remaining first sacrificial layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 22 is a cross-sectional view in the A-A direction after forming a dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 23 is a cross-sectional view in the B-B direction after forming a dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 24 is a cross-sectional view in the A-A direction after removing part of the dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 25 is a cross-sectional view in the B-B direction after removing part of the dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 26 is a cross-sectional view in the A-A direction after forming a gate oxide layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 27 is a cross-sectional view in the B-B direction after forming a gate oxide layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 28 is a cross-sectional view in the A-A direction after forming a conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 29 is a cross-sectional view in the B-B direction after forming a conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 30 is a schematic diagram of a memory provided by an embodiment of the present disclosure.
  • Figure 31 is a second schematic diagram of a memory provided by an embodiment of the present disclosure.
  • a portion of the first sacrificial layer is removed to form a first trench and a second trench, and a portion of the active layer is exposed through the first trench and the second trench.
  • source layer, and then the exposed active layer can be doped through an ion doping process to form the first doped region and the second doped region. This reduces the difficulty of preparing the semiconductor structure and also improves the improve the yield of semiconductor structures.
  • the semiconductor structure is a dynamic random access memory (DRAM) as an example for introduction below.
  • DRAM dynamic random access memory
  • this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for preparing a semiconductor structure includes the following steps:
  • Step S100 Provide a substrate.
  • a substrate 10 provides a support for supporting a film layer thereon.
  • the substrate 10 may be a semiconductor substrate.
  • the substrate 10 may be a silicon substrate, a germanium substrate, a silicon carbide (SiC) substrate, a silicon germanium (SiGe) substrate, a germanium on insulator (Germanium on Insulator, GOI for short) substrate or a silicon on insulator (Silicon on Insulator).
  • SOI silicon on Insulator
  • Step S200 Form multiple columns of stacked structures spaced apart along the first direction on the substrate.
  • Each column of stacked structures includes a plurality of first sacrificial layers and active layers that are alternately stacked.
  • first initial sacrificial layers 23 and initial active layers 24 are formed on the substrate 10 , that is, multiple layers of initial active layers 24 and multiple layers of first initial sacrificial layers 23 are formed on the substrate 10 , multiple layers of initial active layers 24 and multiple layers of first initial sacrificial layers 23 are sequentially stacked and alternately arranged in a direction perpendicular to the substrate 10 , and the first initial sacrificial layers 23 are arranged on the substrate 10 .
  • the number of the initial active layer 24 and the first initial sacrificial layer 23 can be set according to actual needs.
  • the initial active layer 24 and the first initial sacrificial layer 23 may be formed through a deposition process, where the deposition process may include chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition (PVD for short) or Atomic Layer Deposition (ALD for short), etc.
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the first initial sacrificial layer 23 is formed through an epitaxial growth process (Epitaxy, EPI for short). In this way, the crystal lattice between the first initial sacrificial layer 23 and the initial active layer 24 and the substrate 10 can be avoided.
  • the mismatch problem reduces the stress generated between the interface between the first initial sacrificial layer 23 and the substrate 10 and the first initial sacrificial layer 23 and the initial active layer 24, thereby improving the stability of the subsequently formed semiconductor structure.
  • the material of the first initial sacrificial layer 23 includes silicon germanium or silicon phosphide. In this way, the first initial sacrificial layer 23 and the initial active layer 24 can have a larger etching selectivity ratio, so that the subsequent process can be selective. The first sacrificial layer is completely removed, the etching of the active layer is reduced, and the yield of the semiconductor structure is improved.
  • a silicon layer of a certain thickness can be formed on the first initial sacrificial layer through a deposition process, and then the silicon layer is ion-doped to form the initial active layer 24 .
  • N-type ions Group V element ions such as phosphorus P or arsenic As
  • P-type ions group III element ions such as boron B or gallium Ga
  • a mask layer 30 is formed on the initial active layer, and the mask layer 30 is patterned.
  • a plurality of openings 31 are formed at intervals along the first direction Y, wherein each opening 31 extends along the second direction.
  • the second direction is the X direction in Figure 4.
  • a first photoresist layer (not shown in the figure) can be formed on the mask layer 30 .
  • a coating process can be used to form the first photoresist layer on the mask layer 30 .
  • the first photoresist layer is then exposed, developed or etched to form a first mask pattern in the first photoresist layer.
  • the first mask pattern includes a plurality of first protrusions and a first opening area located between adjacent first protrusions, the plurality of first protrusions are spaced apart along the first direction, and each first protrusion
  • the second direction extends along a second direction, and the second direction and the first direction are perpendicular to each other.
  • the first direction is the Y direction in FIG. 4 .
  • the mask layer 30 exposed in the opening area is removed by dry etching or wet etching, so as to form a plurality of openings 31 spaced apart in the first direction in the mask layer 30 .
  • FIG. 6 and FIG. 7 continue to remove the first initial sacrificial layer 23 and the initial active layer 24 exposed in the opening 31 through dry etching or wet etching, and the first initial sacrificial layer 24 is retained.
  • the layer 23 and the initial active layer 24 form a multi-column stacked structure 20, and a third trench 25 extending in the second direction is formed between any two adjacent columns of the stacked structure 20.
  • Each column stack structure 20 includes a plurality of first sacrificial layers 21 and active layers 22 that are alternately stacked.
  • the first sacrificial layers 21 are disposed on the substrate 10 .
  • part of the thickness of the substrate 10 can also be continued to be removed, so that the bottom of the third trench 25 is located within the substrate 10. In this way, the first sacrificial layer 21 can be better removed later. The integrity of the formed active layer 22 is ensured.
  • the first direction is the Y direction in Figure 6, and the second direction is the X direction in Figure 6.
  • the extension direction of the active layer and the substrate are parallel to each other, and thus a three-dimensional stacked memory unit can be formed.
  • more memory cells can be arranged in an effective area, thereby increasing the storage capacity of the semiconductor structure.
  • the mask layer 30 may be a single film layer or may have a stacked structure.
  • the mask layer 30 may include a first mask layer and a second mask layer.
  • the first mask layer is disposed on the initial active layer 24 and the second mask layer is disposed on On the first mask layer, in this way, the mask pattern can be transferred from the first photoresist layer to the second mask layer, and then the second mask layer with the mask pattern is used as a mask to etch
  • the first mask layer is used to transfer the mask pattern to the first mask layer.
  • the first mask layer with the mask pattern is used as a mask to etch the multi-layer first initial sacrificial layer 23 and the initial Active layer 24. This can improve the accuracy in the transfer process of the mask pattern, improve the preparation accuracy of the semiconductor structure, and thereby improve the yield of the semiconductor structure.
  • the material of the first mask layer may include silicon oxide, but is not limited thereto.
  • the material of the second mask layer may include silicon nitride, but is not limited thereto.
  • Step S300 Remove part of the first sacrificial layer to form first trenches and second trenches spaced apart along the second direction, with part of the surface of each active layer exposed in the first trenches and second trenches; wherein , the second direction intersects the first direction, and both the first direction and the second direction are parallel to the surface of the substrate.
  • a second sacrificial layer 40 is formed.
  • the second sacrificial layer 40 fills the area between any adjacent stacked structures 20 and covers the top surface of the stacked structure 20 .
  • a second sacrificial layer 40 is deposited in the third trench using a physical vapor deposition process or a chemical vapor deposition process.
  • the second sacrificial layer 40 extends outside the third trench 25 and covers the top surface of the stacked structure 20 .
  • the material of the second sacrificial layer 40 includes silicon oxide, but is not limited thereto.
  • the second sacrificial layer 40 can be planarized using a chemical mechanical polishing process (CMP) to ensure that the top surface of the second sacrificial layer 40 is flat.
  • CMP chemical mechanical polishing process
  • the top surface of the second sacrificial layer 40 can be used to facilitate the subsequent preparation of other film layers on the second sacrificial layer 40, thereby improving the preparation accuracy of the semiconductor structure.
  • part of the second sacrificial layer 40 is removed, and a plurality of etching holes 50 are formed in a direction perpendicular to the substrate 10 .
  • Each etching hole 50 is located between adjacent stacked structures 20 and exposes the stacked structure 20 .
  • part of the first sacrificial layer 20 is removed along the etching hole 50 .
  • a coating process can be used to form the second photoresist layer 60 on the second sacrificial layer 40 , and then, exposure, development or etching is used to form the second photoresist layer 60 on the second sacrificial layer 40 .
  • a second mask pattern is formed inside.
  • the second mask pattern includes a plurality of second protrusions and second opening areas located between adjacent second protrusions, the plurality of second protrusions are spaced apart along the second direction X, and each second protrusion The protrusion extends along the first direction Y.
  • the second sacrificial layer 40 exposed in the second opening area is removed to form a plurality of etching holes 50 in the second sacrificial layer 40 , wherein, The depth direction of the etching hole 50 is perpendicular to the substrate 10 , and the etching hole 50 exposes the top surface of the substrate 10 .
  • each etching hole 50 In the first direction Y, the sidewalls of each etching hole 50 are opposite surfaces of adjacent rows of stacked structures 20. Taking the orientation shown in FIG. 11 as an example, each etching hole 50 exposes one of the stacked structures. 20 front and rear surfaces. In this way, each etching hole can expose part of the first sacrificial layer, so that part of the first sacrificial layer can be selectively removed later, ensuring the normal progress of the preparation process of the semiconductor structure.
  • the plurality of etching holes 50 can be arranged in multiple rows and two columns, and each row of etching holes 50 is located between adjacent stacked structures 20 .
  • the etching hole 50 may include a first etching hole 51 and a second etching hole 52.
  • the active layer 22 exposed by the first etching hole 51 is used to form the subsequent first doping region 221 and the second etching hole 52.
  • One of the doped regions 222 and the active layer 22 exposed by the second etching hole 52 are used to form the subsequent first doped region 221 and the other of the second doped region 222 .
  • the groove 211 and the second groove 212 have the same depth direction as the first direction Y, and penetrate the first sacrificial layer 21 in the first direction Y.
  • the lengths of the first groove 211 and the second groove 212 may be the same or different. In an example, when the lengths are the same, the areas of the first doped region 221 and the second doped region 222 formed subsequently are approximately the same. In another example, when the lengths of the first trench 211 and the second trench 212 are different, the areas of the first doped region 221 and the second doped region 222 that are subsequently formed are different. In this way, the areas of the first doped region 221 and the second doped region 222 can be adjusted in a targeted manner. The performance of the semiconductor structure is controlled, thereby improving the usability of the semiconductor structure.
  • Step S400 Perform ion doping on the exposed active layer to form a first doping region and a second doping region spaced apart in each active layer, located between the first doping region and the second doping region.
  • the active layer between the regions forms the channel region.
  • the first doping region 221 and the second doping region 222 can be formed through ion diffusion or plasma doping system (PALD for short).
  • PLD plasma doping system
  • the active layer 22 located between the first doping region 221 and the second doping region 222 is the channel region 223.
  • the type of doping ions in the first doping region 221 and the second doping region 222 may be the same, And the type of doping ions in the first doping region 221 and the type of doping ions in the channel region 223 may be the same or different.
  • the type of doping ions in the first doping region 221 and the doping ions in the channel region 223 may be the same.
  • the doping ions in the active layer 22 are N-type ions, they may be doped through a plasma doping process. Doping the active layer exposed in the first trench and the second trench with N-type ions increases the concentration of N-type ions in the active layer 22 exposed in the first trench 211 and the second trench 212, Therefore, the concentration of doping ions in the channel region 223 is smaller than the concentration of doping ions in the first doping region 221 and the second doping region 222 .
  • the doping ions of the active layer 22 are P-type ions, the formation of the first doping region 221 and the second doping region 222 is the same as the above description, and will not be described again in this embodiment.
  • the type of doping ions in the first doping region 221 and the type of doping ions in the channel region 223 may be different.
  • the doping ions of the active layer 22 are N-type ions, they may be formed by plasma.
  • the doping process dopes the active layer 22 exposed in the first trench 211 and the second trench 212 with P-type ions, so that the active layer 22 forms a PNP structure.
  • the doped ions of the active layer 22 are P-type ions
  • the active layer 22 exposed in the first trench 211 and the second trench 212 can be doped with N-type ions through a plasma doping process, so that there are
  • the source layer 22 forms an NPN structure.
  • a portion of the first sacrificial layer is removed to form a first trench and a second trench, and a portion of the active layer is exposed through the first trench and the second trench.
  • an ion doping process can be used to The exposed active layer is doped to form the first doped region and the second doped region, which reduces the difficulty of preparing the semiconductor structure and also improves the yield of the semiconductor structure.
  • a method of preparing the semiconductor structure includes:
  • a third etching hole 70 is formed in the second sacrificial layer 40 between any two adjacent columns of stacked structures 20 , that is, in the second sacrificial layer 40 located in the third trench 25
  • a third etching hole 70 is formed in the second etching hole 70 .
  • the third etching hole 70 is located between the first etching hole 51 and the second etching hole 52 and corresponds to the channel region 223 . That is to say, the projection of the third etching hole 70 on the stacked structure at least covers the channel region 223 .
  • the third etching hole 70 does not expose the side of the stacked structure 20 , that is, in the first direction Y, the width of the third etching hole 70 is smaller than the width of the third trench 25 , thus ensuring the subsequent formation of the first support. There is a gap between the structure and the active layer to facilitate the formation of other film layers of the transistor.
  • the third etching hole 70 After the third etching hole 70 is formed, please refer to FIGS. 16 and 17 to form the first support structure 80 in the third etching hole and the second support structure in the first trench 211 and the second trench 212 Structure 90.
  • the insulating material can be formed through a physical vapor deposition process or a chemical vapor deposition process.
  • the insulating material located in the third etching hole 70 constitutes the first support structure 80 and is located in the first trench 211 and the second trench 212
  • the insulating material constitutes the second supporting structure 90 .
  • the material of the first support structure 80 and the second support structure 90 includes silicon nitride, but is not limited thereto.
  • the second support structure 90 is used to support any two active layers 22 in the vertical direction to prevent the active layer 22 from tilting or collapsing, thereby improving the yield of the semiconductor structure.
  • the method of preparing the semiconductor structure further includes:
  • the remaining second sacrificial layer and the first sacrificial layer are removed, and the remaining second sacrificial layer and the remaining area of the first sacrificial layer constitute a filling area.
  • the second sacrificial layer 40 located between any adjacent stacked structures 20 may be wet-etched to expose the side surfaces of each column of stacked structures 20 .
  • the filling area 100 may include a first filling area 100a and a second filling area 100b that are connected to each other.
  • the first filling area 100a is the area where the remaining second sacrificial layer 40 is located
  • the second filling area 100b is the area where the remaining first sacrificial layer 40 is located.
  • FIGS. 22 and 23 After the filling region 100 is formed, please refer to FIGS. 22 and 23 to form a dielectric layer 110 in the filling region 100 and remove part of the dielectric layer 110 to expose the channel region 223 of the active layer 22 .
  • a deposition process may be used to form the dielectric layer 110 that fills the filling region 100.
  • a deposition process may be used to form the dielectric layer 110 that fills the filling region 100.
  • FIGS. 24 and 25 to pattern the dielectric layer 110 and remove part of the dielectric layer 110 to form a third layer in the dielectric layer 110.
  • the fourth trench 111 exposes the channel region 223 of the active layer 22.
  • a gate oxide layer 120 and a conductive layer 130 are sequentially formed on the surface of the channel region 223 of the active layer 22 .
  • the gate oxide layer 120 and the conductive layer 130 form a word line structure 190 .
  • the gate oxide layer 120 can be formed through a selective deposition process.
  • the gate oxide layer can be selectively formed only on the surface of the channel region 223 of each active layer 22 through an ALD process. 120.
  • the material forming the gate oxide layer 120 can be avoided from filling the fourth trench, and the etching process can be avoided to remove part of the material forming the gate oxide layer 120, thereby simplifying the preparation process of the gate oxide layer 120, thereby reducing the semiconductor cost. Production costs of the fabrication process of the structure.
  • the gate oxide layer 120 has a high dielectric constant, which can increase the charge storage capacity of the gate oxide layer and prevent electrons or a small amount of carrier fluid generated by the conductive layer from entering the drain through the gate oxide layer. Reducing gate-induced drain leakage current improves the performance of semiconductor structures.
  • materials with high k dielectric constant may include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 2 ), lanthanum oxide (LaO), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), barium strontium titanium oxide (BaSrTiO 3 ), barium titanium oxide (BaTiO 3 ), strontium titanium oxide (SrTiO 3 ), lithium oxide (Li 2 O), aluminum oxide ( Al 2 O 3 ), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO 3 ) or combinations thereof.
  • hafnium oxide HfO 2
  • hafnium silicon oxide HfSiO 2
  • LaO zirconium oxide
  • ZrSiO 2 zirconium silicon oxide
  • the gate oxide layer 120 surrounds the fifth trench 140 in the fourth trench.
  • the gate oxide layer 120 surrounds the fifth trench 140 in the fourth trench.
  • FIGS. 28 and 29 please refer to FIGS. 28 and 29 to form a conductive layer filling the fifth trench 140 using a deposition process. 130, wherein the material of the conductive layer 130 includes tungsten, but is not limited thereto.
  • the method of preparing the semiconductor structure further includes: forming an insulating layer 150 covering the dielectric layer 110 and connected to the first support structure 80 and the second support structure 90 to The insulation arrangement between adjacent conductive layers 130 is achieved.
  • the insulating layer 150 , the first support structure 80 and the second support structure 90 are made of the same material, and may all include silicon nitride.
  • the embodiments of the present disclosure also provide a semiconductor structure, which is obtained by the preparation method in the above embodiments. Therefore, the semiconductor structure also has the beneficial effects in the above embodiments, and this embodiment will not be described in detail here.
  • an embodiment of the present disclosure also provides a memory, which includes the semiconductor structure, the storage structure 160 and the bit line structure 170 in the above embodiment.
  • the semiconductor structure, the memory structure and the bit line structure are all disposed on the substrate 10 .
  • the semiconductor structure may include an active layer 22 , a gate oxide layer 120 and a conductive layer 130 .
  • the gate oxide layer 120 and the conductive layer 130 constitute the word line structure 190 .
  • the gate oxide layer 120 surrounds the channel area of the active layer 22; the conductive layer 130 extends in a direction perpendicular to the substrate 10.
  • the conductive layer 130 is used to connect all the active layers 22 located in the same column, and the conductive layer 130 wraps
  • the portion of the channel region of the active layer 22 forms a transistor with the active layer 22 to form a gate all-around field effect transistor (Gate All-Around, GAA for short).
  • the substrate 10 may include a first region 11 , a second region 12 and a third region 13 connected in sequence, wherein the bit line structure 170 is disposed on the first region 11 and the semiconductor structure may be disposed on the second region 12 , the storage structure 160 may be disposed on the third area 13 .
  • the memory structure 160 is electrically connected to one of the first doped region 221 or the second doped region 222 , and the bit line structure 170 is electrically connected to the other one of the first doped region 221 or the second doped region 222 .
  • the memory structure 160 may be connected to the first doping region 221
  • the bit line structure 170 may be connected to the second doping region 222 .
  • the memory structure 160 may be connected to the second doped region 222 and the bit line structure 170 may be connected to the first doped region.
  • the extension direction of the storage structure 160 is parallel to the substrate 10. In this way, multiple stacked storage structures can be formed under the same equivalent area. In this way, the storage capacity of the storage structure can be increased, thereby improving the storage capacity of the memory. capacity.
  • the memory in this embodiment includes a plurality of silicon pillars (not shown in the figure) arranged on the third area.
  • the plurality of silicon pillars are arranged in one-to-one correspondence with the plurality of active layers 22 , and one silicon pillar and one active layer 22 are arranged in a one-to-one correspondence.
  • the layers are located on the same layer.
  • the memory structure 160 may have multiple capacitor structures, and each capacitor structure may include a first electrode layer, a dielectric layer and a second electrode layer surrounding the silicon pillars in sequence.
  • the first electrode layer and the second electrode layer are made of the same material, and the dielectric layer also has a high dielectric constant. In this way, the storage capacity of the storage structure can be increased.
  • the bit line structure 170 includes a plurality of bit lines, the plurality of bit lines are spaced apart along the second direction, and the plurality of bit lines extend parallel to each other along the first direction, and each bit line is used to connect the same layer.
  • bit lines are arranged in steps in a direction perpendicular to the substrate 10. As shown in Figure 31, in the direction perpendicular to the substrate 10, the bit lines are arranged in steps from bottom to top, which facilitates the arrangement of multiple bit lines in a three-dimensional structure. Wires realize electrical contact connection.
  • the preparation of the remaining data lines can be facilitated, and the spacing between these data lines can also be increased to prevent interference of transmission signals.
  • it can also reduce the parasitic capacitance between the upper and lower bit lines and improve the performance of the memory.
  • the memory also includes an isolation layer 180 that wraps each bit line to prevent electrical connections between the bit lines.
  • the material of the isolation layer includes silicon oxide or silicon nitride.

Abstract

本公开实施例提供一种半导体结构及其制备方法、存储器，涉及半导体技术领域，用于解决半导体结构的制备难度大的技术问题，该半导体结构的制备方法包括提供基底；在基底上形成沿第一方向间隔设置的多列堆叠结构，每列堆叠结构包括多个交替层叠设置的第一牺牲层和有源层。本公开实施例通过去除部分第一牺牲层，以形成第一沟槽和第二沟槽，通过第一沟槽和第二沟槽暴露出部分的有源层，之后，可以通过离子掺杂工艺对暴露出来的有源层进行掺杂，以形成第一掺杂区和第二掺杂区，如此，在降低了半导体结构的制备难度同时，也提高了半导体结构的良率。

Description

半导体结构及其制备方法、存储器
本申请要求于2022年04月26日提交中国专利局、申请号为202210446021.0、申请名称为“半导体结构及其制备方法、存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法、存储器。
背景技术
动态随机存取存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。动态随机存取存储器由多个重复的存储单元组成，每个存储单元通常包括电容器和晶体管，电容器存储数据信息，晶体管控制电容器中的数据信息的读取。
为了提高半导体结构的存储容量，半导体结构从二维结构向三维结构发展，但是在形成三维的半导体结构时，难以对半导体结构的有源区进行的掺杂，增加半导体结构的制备难度的同时，也降低了半导体结构的良率。
发明内容
鉴于上述问题，本公开实施例提供一种半导体结构及其制备方法、存储器，用于降低有源层的制备难度。
本公开实施例的第一方面提供一种半导体结构的制备方法，其包括：
提供基底；
在所述基底上形成沿第一方向间隔设置的多列堆叠结构，每列所述堆叠结构包括多个交替层叠设置的第一牺牲层和有源层；
去除部分所述第一牺牲层，形成沿第二方向间隔设置的第一沟槽和第二沟槽，每个所述有源层的部分表面暴露在所述第一沟槽和所述第二沟槽中；其中，所述第二方向与所述第一方向相交，所述第一方向和所述第二方向且均平行于所述基底的表面；
对暴露出来的所述有源层进行离子掺杂，以在每个所述有源层中形成间隔设置的第一掺杂区和第二掺杂区，位于所述第一掺杂区和所述第二掺杂区之间的有源层构成沟道区。
与现有技术相比，本公开实施例提供的半导体结构的制备方法具有如下优点：
通过去除部分第一牺牲层，以形成第一沟槽和第二沟槽，通过第一沟槽和第二沟槽暴露出部分的有源层，之后，可以通过离子掺杂工艺对暴露出来的有源层进行掺杂，以形成第一掺杂区和第二掺杂区，如此，在降低了半导体结构的制备难度同时，也提高了半导体结构的良率。
在一些实施例中，去除部分所述第一牺牲层的步骤包括：
形成第二牺牲层，所述第二牺牲层填充满任意相邻的所述堆叠结构之间的区域，并覆盖在所述堆叠结构的顶面上；
去除部分所述第二牺牲层，在垂直于所述基底的方向上形成多个刻蚀孔，每个所述刻蚀孔位于相邻的所述堆叠结构之间，并暴露出该所述堆叠结构的侧面，沿着所述刻蚀孔去除部分所述第一牺牲层。
在一些实施例中，所述刻蚀孔包括第一刻蚀孔和第二刻蚀孔，所述第一刻蚀孔对应于所述第一掺杂区，所述第二刻蚀孔对应于所述第二掺杂区。
在一些实施例中，在所述基底上形成沿第一方向间隔设置的多列堆叠结构的步骤包括：
在所述基底上形成层叠且交替设置的第一初始牺牲层和初始有源层；
在所述初始有源层上形成掩膜层，并图形化所述掩膜层，在所述掩膜层内形成沿第一方向间隔设置的多个开口；
去除暴露在所述开口内的所述第一初始牺牲层和所述初始有源层，被保留下来的所述第一初始牺牲层和初始有源层构成多列堆叠结构，任意相邻两列所述堆叠结构之间形成沿所述第二方向延伸的第三沟槽。
在一些实施例中，所述第三沟槽的槽底位于所述基底内。
在一些实施例中，形成所述第一掺杂区和所述第二掺杂区之后，所述制备方法还包括：
在位于任意相邻两列堆叠结构之间的所述第二牺牲层内形成第三刻蚀孔，所述第三刻蚀孔对应于所述沟道区，所述第三刻蚀孔位于所述第一刻蚀孔和所述第二刻蚀孔之间，且未暴露出所述堆叠结构的侧面；
在所述第三刻蚀孔内形成第一支撑结构，以及在所述第一沟槽和所述第二沟槽内形成第二支撑结构。
在一些实施例中，在形成所述第一支撑结构和所述第二支撑结构之后，所述制备方法还包括：
去除剩余的所述第二牺牲层和所述第一牺牲层，以形成填充区；
在所述填充区中形成介质层，并去除部分所述介质层暴露出所述沟道区；
在所述有源层的沟道区的表面依次形成栅氧化层和导电层。
在一些实施例中，去除剩余所述的第二牺牲层和所述第一牺牲层的步骤包括：
湿法刻蚀位于任意相邻的所述堆叠结构之间的所述第二牺牲层，湿法刻蚀每列所述堆叠结构中的所述第一牺牲层，以形成所述填充区。
在一些实施例中，形成所述导电层之后，所述制备方法还包括：
形成绝缘层，所述绝缘层覆盖在所述介质层上，并与所述第一支撑结构和所述第二支撑结构连接。
在一些实施例中，所述绝缘层、所述第一支撑结构和所述第二支撑结构的材质相同。
在一些实施例中，所述第一掺杂区、所述第二掺杂区和所述沟道区的掺杂离子类型相同，且所述沟道区的掺杂离子的浓度小于所述第一掺杂区和所述第二掺杂区的掺杂离子的浓度。
在一些实施例中，在所述基底上形成层叠且交替设置的第一初始牺牲层和初始掺杂层的步骤，包括：
通过外延生长工艺在所述基底上形成交替层叠设置的第一初始牺牲层和初始掺杂层，所述第一初始牺牲层包括锗化硅、磷化硅或氮化硅。
本公开实施例的第二方面提供一种半导体结构，该半导体结构通过第一方面提供的半导体结构的制备方法制得。
本公开实施例的第三方面提供一种存储器，所述存储器包括第二方面提供的半导体结构，所述存储器还包括存储结构和位线结构，所述存储结构与所述第一掺杂区或所述第二掺杂区中的一者电连接，所述位线结构与所述第一掺杂区或所述第二掺杂区中的另一者电连接。
在一些实施例中，所述位线结构包括多条平行间隔排布的位线，多条所述位线在垂直于所述基底的方向上呈阶梯布置。除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施例提供的半导体结构及其制备方法、存储器所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的制备方法的工艺流程图；
图2为本公开实施例提供的半导体结构的制备方法中形成第一初始牺牲层和初始有源层的结构示意图；
图3为沿图2中A-A方向的剖视图；
图4为本公开实施例提供的半导体结构的制备方法中形成掩膜层的结构示意图；
图5为沿图4中A-A方向的剖视图；
图6为本公开实施例提供的半导体结构的制备方法中形成堆叠结构的结构示意图；
图7为沿图6中A-A方向的剖视图；
图8为本公开实施例提供的半导体结构的制备方法中形成第二牺牲层后在A-A方向上的剖视图；
图9为本公开实施例提供的半导体结构的制备方法中形成第二牺牲层后在B-B方向上的剖视图；
图10为本公开实施例提供的半导体结构的制备方法中形成第二光刻胶层的结构示意图；
图11为本公开实施例提供的半导体结构的制备方法中形成刻蚀孔的结构示意图；
图12为本公开实施例提供的半导体结构的制备方法中形成刻蚀孔后在A-A方向的剖视图；
图13为本公开实施例提供的半导体结构的制备方法中形成刻蚀孔后在B-B方向的剖视图；
图14为本公开实施例提供的半导体结构的制备方法中形成第一掺杂区和第二掺杂区的结构示意图；
图15为本公开实施例提供的半导体结构的制备方法中形成第三刻蚀孔的结构示意图；
图16为本公开实施例提供的半导体结构的制备方法中形成支撑结构在A-A方向的剖视图；
图17为本公开实施例提供的半导体结构的制备方法中形成支撑结构在B-B方向的剖视图；
图18为本公开实施例提供的半导体结构的制备方法中去除剩余第二牺牲层后在A-A方向的剖视图；
图19为本公开实施例提供的半导体结构的制备方法中去除剩余第二牺牲层后在B-B方向的剖视图；
图20为本公开实施例提供的半导体结构的制备方法中去除剩余第一牺牲层后在A-A方向的剖视图；
图21为本公开实施例提供的半导体结构的制备方法中去除剩余第一牺牲层后在B-B方向的剖视图；
图22为本公开实施例提供的半导体结构的制备方法中形成介质层后在A-A方向的剖视图；
图23为本公开实施例提供的半导体结构的制备方法中形成介质层后在B-B方向的剖视图；
图24为本公开实施例提供的半导体结构的制备方法中去除部分介质层后在A-A方向的剖视图；
图25为本公开实施例提供的半导体结构的制备方法中去除部分介质层后在B-B方向的剖视图；
图26为本公开实施例提供的半导体结构的制备方法中形成栅氧化层后在A-A方向的剖视图；
图27为本公开实施例提供的半导体结构的制备方法中形成栅氧化层后在B-B方向的剖视图；
图28为本公开实施例提供的半导体结构的制备方法中形成导电层后在A-A方向的剖视图；
图29为本公开实施例提供的半导体结构的制备方法中形成导电层后在B-B方向的剖视图；
图30为本公开实施例提供的存储器的示意图一；
图31为本公开实施例提供的存储器的示意图二。
附图标记：
10：基底；11：第一区域；12：第二区域；13：第三区域；20：堆叠结构；21：第一牺牲层；211：第一沟槽；212：第二沟槽；22：有源层；221：第一掺杂区；222：第二掺杂区；223：沟道区；23：第一初始牺牲层；24：初始有源层；25：第三沟槽；30：掩膜层；31：第一开口；40：第二牺牲层；50：刻蚀孔；51：第一刻蚀孔；52：第二刻蚀孔；60：第二光刻胶层；70：第三刻蚀孔；80：第一支撑结构；90：第二支撑结构；100：填充区；100a：第一填充区；100b：第二填充区；110：介质层；111：第四沟槽；120：栅氧化层；130：导电层；140：第五沟槽；150：绝缘层；160：存储结构；170：位线结构；180：隔离层；190：字线结构。
具体实施方式
正如背景技术所述，相关技术中在制备三维结构的半导体结构时，鉴于多个有源层沿垂直方向重合，难以对有源层进行离子掺杂，以形成源漏区，如此会降低半导体结构的良率。基于此，本公开实施例提供的半导体结构的制备方法中，去除部分第一牺牲层，以形成第一沟槽和第二沟槽，通过第一沟槽和第二沟槽暴露出部分的有源层，之后，可以通过离子掺杂工艺对暴露出来的有源层进行掺杂，以形成第一掺杂区和第二掺杂区，如此，在降低了半导体结构的制备难度同时，也提高了半导体结构的良率。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
请参考图1，本公开实施例提供的半导体结构的制备方法，包括如下步骤：
步骤S100：提供基底。
参考图2和图3，基底10提供支撑，用于支撑其上的膜层。基底10可以为半导体基底。示例性的，基底10可以为硅基底、锗基底、碳化硅(SiC)基底、锗化硅(SiGe)基底、绝缘体上锗(Germanium on Insulator，简称GOI)基底或者绝缘体上硅(Silicon on Insulator，简称SOI)基底等。
步骤S200：在基底上形成沿第一方向间隔设置的多列堆叠结构，每列堆叠结构包括多个交替层叠设置的第一牺牲层和有源层。
示例性地，在基底10上形成层叠且交替设置的第一初始牺牲层23和初始有源层24，即，在基底10上形成多层初始有源层24和多层第一初始牺牲层23，多层初始有源层24和多层第一初始牺牲层23沿垂直于基底10的方向依次层叠且交替设置，且第一初始牺牲层23设置在基底10上。其中，初始有源层24和第一初始牺牲层23的个数可以依据实际需求进行设置。
在一些可能的实现方式中，初始有源层24和第一初始牺牲层23可以通过沉积工艺形成，其中，沉积工艺可以包括化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等。
在另一些可能的实现方式中，第一初始牺牲层23通过外延生长工艺(Epitaxy，简称EPI)形成，如此，可以避免第一初始牺牲层23与初始有源层24和基底10之间晶格不匹配的问题，降低第一初始牺牲层23与基底10，以及第一初始牺牲层23与初始有源层24界面之间产生的应力，提高了后续形成的半导体结构的稳定性。
第一初始牺牲层23的材质包括锗化硅或者磷化硅，如此，可以使得第一初始牺牲层23与初始有源层24具有较大的刻蚀选择比，以便于后续的工艺有选择性地去除第一牺牲层，减少对有源层的刻蚀，提高了半导体结构的良率。
在本实施例中，可以先通过沉积工艺在第一初始牺牲层上形成一定厚度的硅层，之后，对硅层进行离子掺杂，以形成初始有源层24。其中，在一示例中，可以向硅层注入N型离子(磷P或砷As等Ⅴ族元素离子)形成N型的初始有源层24。在另一示例中，可以向硅层中注入P型离子(硼B或镓Ga等Ⅲ族元素离子)形成P型的初始有源层24。
请参考图4和图5，待形成第一初始牺牲层23和初始有源层24之后，在初始有源层上形成掩膜层30，并图形化掩膜层30，在掩膜层30内形成沿第一方向Y间隔设置的多个开口31，其中，每个开口31沿第二方向延伸。第二方向为图4中的X方向。
在一种可行的实施方式中，可以在掩膜层30上形成第一光刻胶层(图中未示出)，比如，可以利用涂覆的工艺在掩膜层30上形成第一光刻胶层，之后，采用曝光、显影或者刻蚀的方式，在第一光刻胶层内形成第一掩膜图案。其中，第一掩膜图案包括多个第一凸起以及位于相邻的第一凸起之间的第一开口区，多个第一凸起沿第一方向间隔设置，且每个第一凸起沿第二方向延伸，第二方向与第一方向相互垂直。其中，第一方向为图4中的Y方向。
之后，通过干法刻蚀或者湿法刻蚀，去除暴露在开口区内的掩膜层30，以在掩膜层30内形成多个第一方向间隔设置的开口31。
之后，请参考图6和图7，继续通过干法刻蚀或者湿法刻蚀，去除暴露在开口31内的第一初始牺牲层23和初始有源层24，被保留下来的第一初始牺牲层23和初始有源层24构成多列堆叠结构20，任意相邻两列堆叠结构20之间形成沿第二方向延伸的第三沟槽25。
其中，每列堆叠结构20包括多个交替层叠设置的第一牺牲层21和有源层22，第一牺牲层21设置在基底10上。
需要说明的是，本示例中，还可以继续去除部分厚度的基底10，以使得第三沟槽25的槽底的位于基底10内，如此，可以便于后续更好地去除第一牺牲层21，保证形成的有源层22的完整性。
其中，第一方向为图6中的Y方向，第二方向为图6中的X方向，如此，可以保证形成有源层的延伸方向与基底相互平行，进而可以形成的三维堆叠的存储单元，与相关技术中二维的存储单元相比，可以在有效的面积内设置更多的存储单元，进而提高了半导体结构的存储容量。
需要说明的是，在本实施例中，掩膜层30可以单一膜层，也可以为叠层结构。当掩膜层30为叠层结构时，掩膜层30可以包括第一掩膜层和第二掩膜层，第一掩膜层设置在初始有源层24上，第二掩膜层设置在第一掩膜层上，如此，可以将掩膜图案从第一光刻胶层上先转移到第二掩膜层内，然后以具有掩膜图案的第二掩膜层作为掩膜，刻蚀第一掩膜层，以将掩膜图案转移到第一掩膜层上，最后，再以具有掩膜图案的第一掩膜层作为掩膜，刻蚀多层第一初始牺牲层23和初始有源层24。如此可以提高掩膜图案的转移过程中的精准性，提高半导体结构的制备精度，进而提高了半 导体结构的良率。
其中，第一掩膜层的材质可以包括氧化硅，但不仅限于此。第二掩膜层的材质可以包括氮化硅，但不仅限于此。
步骤S300：去除部分第一牺牲层，形成沿第二方向间隔设置的第一沟槽和第二沟槽，每个有源层的部分表面暴露在第一沟槽和第二沟槽中；其中，第二方向与第一方向相交，第一方向和第二方向且均平行于基底的表面。
示例性地，请参考图8和图9，形成第二牺牲层40，第二牺牲层40填充满任意相邻的堆叠结构20之间的区域，并覆盖在堆叠结构20的顶面上。
利用物理气相沉积工艺或者化学气相沉积工艺，在第三沟槽内沉积第二牺牲层40，第二牺牲层40延伸至第三沟槽25外，并覆盖在堆叠结构20的顶面上。其中，第二牺牲层40的材质包括氧化硅，但不仅限于此。
需要说明的是，待形成第二牺牲层40之后，可以利用化学机械研磨工艺(Chemical Mechanical Polishing，简称CMP)，平坦化处理第二牺牲层40，以保证第二牺牲层40的顶面为平整的顶面，如此，可以便于后续在第二牺牲层40上制备其他的膜层，提高了半导体结构的制备精度。
之后，去除部分第二牺牲层40，在垂直于基底10的方向上形成多个刻蚀孔50，每个刻蚀孔50位于相邻的堆叠结构20之间，并暴露出该堆叠结构20的侧面，沿着刻蚀孔50去除部分第一牺牲层20。
示例性地，请参考图10，可以利用涂覆的工艺在第二牺牲层40形成第二光刻胶层60，之后，采用曝光、显影或者刻蚀的方式，在第二光刻胶层60内形成第二掩膜图案。其中，第二掩膜图案包括多个第二凸起以及位于相邻的第二凸起之间的第二开口区，多个第二凸起沿第二方向X间隔设置，且每个第二凸起沿第一方向Y延伸。
请参考图11，以第二光刻胶层60为掩膜，去除暴露在第二开口区内的第二牺牲层40，以在第二牺牲层40内形成多个刻蚀孔50，其中，刻蚀孔50的深度方向垂直于基底10，且刻蚀孔50暴露出基底10的顶面。
在第一方向Y上，每个刻蚀孔50的侧壁为相邻列堆叠结构20的相对的表面，以图11所示的方位为例，每个刻蚀孔50暴露出其中一个堆叠结构20的前表面和后表面。如此，可以使每个刻蚀孔均暴露出第一牺牲层的部分，以便于后续能够有选择性地去除部分第一牺牲层，保证了半导体结构的制备工艺的正常进行。
本实施例中，多个刻蚀孔50可以呈多行两列的方式进行排布，且每行刻蚀孔50位于相邻的堆叠结构20之间。其中，刻蚀孔50可以包括第一刻蚀孔51和第二刻蚀孔52，第一刻蚀孔51暴露出来的有源层22，用于形成后续的第一掺杂区221和第二掺杂区222中之一，第二刻蚀孔52暴露出来的有源层22，用于形成后续的第一掺杂区221和第二掺杂区222的另外一个。
之后，参考图12和图13，继续利用干法刻蚀或者湿法刻蚀，去除暴露在刻蚀孔50内的第一牺牲层21，以在每个第一牺牲层21内形成第一沟槽211和第二沟槽212，第一沟槽211和第二沟槽212的深度方向与第一方向Y相同，并在第一方向Y上贯穿第一牺牲层21。
需要说明的是，在第二方向X上，第一沟槽211和第二沟槽212的长度可以相同，也可以不同，在一示例中，当第一沟槽211和第二沟槽212的长度相同时，在后续形成第一掺杂区221和第二掺杂区222的面积近似相同。在另一示例中，第一沟槽211和第二沟槽212的长度不同时，在后续形成第一掺杂区221和第二掺杂区222的面积不同，如此，可以有针对性地对半导体结构的性能进行控制，提高了半导体结构的使用性。
步骤S400：对暴露出来的有源层进行离子掺杂，以在每个有源层中形成间隔设置的第一掺杂区和第二掺杂区，位于第一掺杂区和第二掺杂区之间的有源层构成沟道区。
请参考图14，可以通过离子扩散或者等离子体掺杂工艺(Plasma doping system，简称PALD)来形成第一掺杂区221和第二掺杂区222。
位于第一掺杂区221和第二掺杂区222之间的有源层22为沟道区223其中，第一掺杂区221和第二掺杂区222的掺杂离子的类型可以相同，且第一掺杂区221的掺杂离子的类型与沟道区223的掺杂离子的类型可以相同，也可以不同。
在一示例中，第一掺杂区221的掺杂离子的类型与沟道区223的掺杂离子可以相同，当有源层22的掺杂离子为N型离子时，可以通过等离子掺杂工艺对暴露在第一沟槽和第二沟槽内的有源层掺杂N型离子，增加暴露在第一沟槽211和第二沟槽212内的有源层22中N型离子的浓度，进而使得沟道区223的掺杂离子的浓度小于第一掺杂区221和第二掺杂区222的掺杂离子的浓度。需要说明的是，当有源层22的掺杂离子为P型离子时，第一掺杂区221和第二掺杂区222的形 成同上述的描述，本实施例不再多加赘述。
在另一示例中，第一掺杂区221的掺杂离子的类型与沟道区223的掺杂离子的类型可以不同，当有源层22的掺杂离子为N型离子时，可以通过等离子掺杂工艺对暴露在第一沟槽211和第二沟槽212内的有源层22掺杂P型离子，以使得有源层22形成PNP的结构。当有源层22的掺杂离子为P型离子时，可以通过等离子掺杂工艺对暴露在第一沟槽211和第二沟槽212内的有源层22掺杂N型离子，以使得有源层22形成NPN的结构。
本实施例通过去除部分第一牺牲层，以形成第一沟槽和第二沟槽，通过第一沟槽和第二沟槽暴露出部分的有源层，之后，可以通过离子掺杂工艺对暴露出来的有源层进行掺杂，以形成第一掺杂区和第二掺杂区，如此，在降低了半导体结构的制备难度同时，也提高了半导体结构的良率。
在一些实施例中，在形成第一掺杂区和第二掺杂区之后，半导体结构的制备方法包括：
请参考图15和图16，在位于任意相邻两列堆叠结构20之间的第二牺牲层40内形成第三刻蚀孔70，即在位于第三沟槽25内的第二牺牲层40内形成第三刻蚀孔70，第三刻蚀孔70位于第一刻蚀孔51和第二刻蚀孔52之间，并对应于沟道区223。也就是说，第三刻蚀孔70在堆叠结构上的投影至少覆盖沟道区223。
其中，第三刻蚀孔70未暴露出堆叠结构20的侧面，即在第一方向Y，第三刻蚀孔70的宽度小于第三沟槽25的宽度，如此，可以保证后续形成第一支撑结构与有源层之间具有间隙，便于晶体管的其他膜层的形成。
待形成第三刻蚀孔70之后，请参考图16和图17，在第三刻蚀孔内形成第一支撑结构80，以及在第一沟槽211和第二沟槽212内形成第二支撑结构90。
示例性地，可以通过物理气相沉积工艺或者化学气相沉积工艺形成绝缘材质，位于第三刻蚀孔70内的绝缘材质构成第一支撑结构80，位于第一沟槽211和第二沟槽212内的绝缘材质构成第二支撑结构90。其中，第一支撑结构80和第二支撑结构90的材质包括氮化硅，但不仅限于此。
第二支撑结构90用于在垂直方向上，任意两层的有源层22进行支撑，防止有源层22发生倾斜或者倒塌，提高了半导体结构的良率。
在一些实施例中，在形成第一支撑结构和第二支撑结构的步骤之后，半导体结构的制备方法还包括：
请参考图18至图21，去除剩的第二牺牲层和第一牺牲层，剩余的第二牺牲层和剩余的第一牺牲层的区域，构成填充区。
示例性地，继续参考图18和图19所示，可以通过湿法刻蚀位于任意相邻的堆叠结构20之间的第二牺牲层40，以暴露出每列堆叠结构20中的侧面。
之后，请参考图20和图21，湿法刻蚀每列堆叠结构20中的第一牺牲层21，以形成填充区100。其中，填充区100可以包括相互连通的第一填充区100a和第二填充区100b，第一填充区100a为剩余的第二牺牲层40所在的区域，第二填充区100b为剩余的第一牺牲层21所在的区域。
待形成填充区100之后，请参考图22和图23，在填充区100中形成介质层110，并去除部分介质层110暴露出有源层22的沟道区223。
示例性地，可以利用沉积工艺形成填充满填充区100的介质层110，之后，请参考图24和图25，图形化介质层110，去除部分的介质层110，以在介质层110内形成第四沟槽111，第四沟槽111暴露出有源层22的沟道区223。
之后，请参考图26至图29，在有源层22的沟道区223的表面依次形成栅氧化层120和导电层130，栅氧化层120和导电层130构成字线结构190。
在一种可能的实施方式中，可以通过选择性沉积工艺形成栅氧化层120，比如，可以通过ALD工艺，有选择性地仅在各个有源层22的沟道区223表面上形成栅氧化层120，如此，可以避免形成栅氧化层120的材质填充满第四沟槽，避免再采用刻蚀工艺去除部分形成栅氧化层120的材质，进而可以简化栅氧化层120的制备工艺，从而降低半导体结构的制备工艺的生产成本。
在本实施例中，栅氧化层120具有高介电常数，如此，可以增大栅氧化层的存储电荷的能力，防止导电层产生的电子或者少数的载流体通过栅氧化层进入漏极中，降低栅诱导漏极泄露电流，提高了半导体结构的性能。
其中，具有高k介电常数的材料可以包括氧化铪(HfO 2)、氧化铪硅(HfSiO 2)、氧化镧(LaO)、氧化锆(ZrO 2)、氧化锆硅(ZrSiO 2)、氧化钽(Ta 2O 5)、氧化钛(TiO 2)、氧化钡锶钛(BaSrTiO 3)、氧化钡钛(BaTiO 3)、氧化锶钛(SrTiO 3)、氧化锂(Li 2O)、氧化铝(Al 2O 3)、氧化铅钪钽(PbScTaO)、铌酸铅锌(PbZnNbO 3)或其组合。
待形成栅氧化层120之后，栅氧化层120在第四沟槽内围成第五沟槽140，之后，请参考图 28和图29，利用沉积工艺形成填充满第五沟槽140的导电层130，其中，导电层130的材质包括钨，但不仅限于此。
在一些实施例中，形成导电层之后，半导体结构的制备方法还包括：形成绝缘层150，绝缘层150覆盖在介质层110上，并与第一支撑结构80和第二支撑结构90连接，以实现相邻的导电层130之间的绝缘设置。
其中，绝缘层150、第一支撑结构80和第二支撑结构90的材质相同，均可以包括氮化硅。
本公开实施例还提供了一种半导体结构，该半导体结构通过上述实施例中的制备方法得到，因此，半导体结构也具有上述实施例中的有益效果，本实施例在此就不再多加赘述。
请参考图30，本公开实施例还提供了一种存储器，该存储器包括上述实施例中的半导体结构、存储结构160和位线结构170。
半导体结构、存储结构和位线结构均设置在基底10上，其中，半导体结构可以包括有源层22、栅氧化层120和导电层130，栅氧化层120和导电层130构成字线结构190。其中，栅氧化层120环绕有源层22的沟道区；导电层130沿垂直于基底10的方向延伸，导电层130用于连接位于同一列上所有的有源层22，且导电层130包裹有源层22的沟道区的部分与有源层22形成晶体管，形成栅极全环绕场效晶体管(Gate All-Around，简称GAA))。
示例性地，基底10可以包括顺次连接的第一区域11、第二区域12和第三区域13，其中，位线结构170设置在第一区域11上，半导体结构可以设置在第二区域12上，存储结构160可以设置在第三区域13上。
存储结构160与第一掺杂区221或第二掺杂区222中的一者电连接，位线结构170与第一掺杂区221或第二掺杂区222中的另一者电连接。在一示例中，存储结构160可以与第一掺杂区221连接，位线结构170与第二掺杂区222连接。在另一示例中，存储结构160可以与第二掺杂区222连接，位线结构170与第一掺杂区连接。
在本实施例中，存储结构160的延伸方向平行于基底10，如此，在相同的等效面积下，可以形成堆叠多个存储结构，如此，可以增加存储结构的存储容量，进而提高存储器的存储容量。
本实施例中的存储器包括设置在第三区域上的多个硅柱(图中未示出)，多个硅柱与多个有源层22一一对应设置，且一个硅柱和一个有源层位于同一层上，存储结构160可以多个电容结构，且每个电容结构均可以包括依次环绕硅柱的第一电极层、介电层和第二电极层。
其中，第一电极层和第二电极层的材质相同，介电层也具有高介电常数，如此，可以提高存储结构的存储容量。
在一些实施例中，位线结构170包括多条位线，多条位线沿第二方向间隔设置，且多条位线沿第一方向相互平行延伸，每条位线用于连接位于同一层上所有有源层的第一掺杂区，或者用于连接位于同一层上的所有有源层的第二掺杂区。
多条位线在垂直于基底10的方向上呈阶梯布置，如图31所示，在沿垂直于基底10的方向上，位线从下向上依次阶梯设置，便于在三维结构中对多条位线实现电接触连接。
本实施例通过使任意两条位线上下错位设置，如此，可以方便其余数据线的制备，同时也增加了这些数据线之间的间距，防止传输信号发生干涉。此外，还可以降低上下两层的位线之间的寄生电容，提高存储器的性能。
存储器还包括隔离层180，隔离层180包裹各个位线，以防止各个位线之间形成电连接。其中，隔离层的材质包括氧化硅或者氮化硅。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括如下步骤：
    提供基底；
    在所述基底上形成沿第一方向间隔设置的多列堆叠结构，每列所述堆叠结构包括多个交替层叠设置的第一牺牲层和有源层；
    去除部分所述第一牺牲层，形成沿第二方向间隔设置的第一沟槽和第二沟槽，每个所述有源层的部分表面暴露在所述第一沟槽和所述第二沟槽中；其中，所述第二方向与所述第一方向相交，所述第一方向和所述第二方向且均平行于所述基底的表面；
    对暴露出来的所述有源层进行离子掺杂，以在每个所述有源层中形成间隔设置的第一掺杂区和第二掺杂区，位于所述第一掺杂区和所述第二掺杂区之间的有源层构成沟道区。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，去除部分所述第一牺牲层的步骤包括：
    形成第二牺牲层，所述第二牺牲层填充满任意相邻的所述堆叠结构之间的区域，并覆盖在所述堆叠结构的顶面上；
    去除部分所述第二牺牲层，在垂直于所述基底的方向上形成多个刻蚀孔，每个所述刻蚀孔位于相邻的所述堆叠结构之间，并暴露出该所述堆叠结构的侧面，沿着所述刻蚀孔去除部分所述第一牺牲层。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，所述刻蚀孔包括第一刻蚀孔和第二刻蚀孔，所述第一刻蚀孔对应于所述第一掺杂区，所述第二刻蚀孔对应于所述第二掺杂区。
  4. 根据权利要求1-3任一项所述的半导体结构的制备方法，其中，在所述基底上形成沿第一方向间隔设置的多列堆叠结构的步骤包括：
    在所述基底上形成层叠且交替设置的第一初始牺牲层和初始有源层；
    在所述初始有源层上形成掩膜层，并图形化所述掩膜层，在所述掩膜层内形成沿第一方向间隔设置的多个开口；
    去除暴露在所述开口内的所述第一初始牺牲层和所述初始有源层，被保留下来的所述第一初始牺牲层和初始有源层构成多列堆叠结构，任意相邻两列所述堆叠结构之间形成沿所述第二方向延伸的第三沟槽。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，所述第三沟槽的槽底位于所述基底内。
  6. 根据权利要求3所述的半导体结构的制备方法，其中，形成所述第一掺杂区和所述第二掺杂区之后，所述制备方法还包括：
    在位于任意相邻两列堆叠结构之间的所述第二牺牲层内形成第三刻蚀孔，所述第三刻蚀孔对应于所述沟道区，所述第三刻蚀孔位于所述第一刻蚀孔和所述第二刻蚀孔之间，且未暴露出所述堆叠结构的侧面；
    在所述第三刻蚀孔内形成第一支撑结构，以及在所述第一沟槽和所述第二沟槽内形成第二支撑结构。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，在形成所述第一支撑结构和所述第二支撑结构之后，所述制备方法还包括：
    去除剩余的所述第二牺牲层和所述第一牺牲层，以形成填充区；
    在所述填充区中形成介质层，并去除部分所述介质层暴露出所述沟道区；
    在所述有源层的沟道区的表面依次形成栅氧化层和导电层。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，去除剩余所述的第二牺牲层和所述第一牺牲层的步骤包括：
    湿法刻蚀位于任意相邻的所述堆叠结构之间的所述第二牺牲层，湿法刻蚀每列所述堆叠结构中的所述第一牺牲层，以形成所述填充区。
  9. 根据权利要求7所述的半导体结构的制备方法，其中，形成所述导电层之后，所述制备方法还包括：
    形成绝缘层，所述绝缘层覆盖在所述介质层上，并与所述第一支撑结构和所述第二支撑结构连接。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，所述绝缘层、所述第一支撑结构和 所述第二支撑结构的材质相同。
  11. 根据权利要求1-3任一项所述的半导体结构的制备方法，其中，所述第一掺杂区、所述第二掺杂区和所述沟道区的掺杂离子类型相同，且所述沟道区的掺杂离子的浓度小于所述第一掺杂区和所述第二掺杂区的掺杂离子的浓度。
  12. 根据权利要求1-3任一项所述的半导体结构的制备方法，其中，在所述基底上形成层叠且交替设置的第一初始牺牲层和初始掺杂层的步骤，包括：
    通过外延生长工艺在所述基底上形成交替层叠设置的第一初始牺牲层和初始掺杂层，所述第一初始牺牲层包括锗化硅、磷化硅或氮化硅。
  13. 一种半导体结构，所述半导体结构通过权利要求1-12任一项所述的半导体结构的制备方法制得。
  14. 一种存储器，所述存储器包括如权利要求13所述的半导体结构，所述存储器还包括存储结构和位线结构，所述存储结构与所述第一掺杂区或所述第二掺杂区中的一者电连接，所述位线结构与所述第一掺杂区或所述第二掺杂区中的另一者电连接。
  15. 根据权利要求14所述的存储器，其中，所述位线结构包括多条平行间隔排布的位线，多条所述位线在垂直于所述基底的方向上呈阶梯布置。
PCT/CN2022/104019 2022-04-26 2022-07-06 半导体结构及其制备方法、存储器 WO2023206812A1 (zh)

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