WO2023206948A1 - 一种动态存储器及其制作方法、存储装置 - Google Patents

一种动态存储器及其制作方法、存储装置 Download PDF

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Publication number
WO2023206948A1
WO2023206948A1 PCT/CN2022/121034 CN2022121034W WO2023206948A1 WO 2023206948 A1 WO2023206948 A1 WO 2023206948A1 CN 2022121034 W CN2022121034 W CN 2022121034W WO 2023206948 A1 WO2023206948 A1 WO 2023206948A1
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electrode
semiconductor layer
bit line
layer
memory
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PCT/CN2022/121034
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English (en)
French (fr)
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王祥升
王桂磊
赵超
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北京超弦存储器研究院
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Publication of WO2023206948A1 publication Critical patent/WO2023206948A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of semiconductor devices. Specifically, the present disclosure relates to a dynamic memory, a manufacturing method thereof, and a storage device.
  • DRAM Dynamic Random Access Memory
  • static memory DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density.
  • DRAM memory is increasingly used in electronic devices such as servers, smartphones, and personal computers.
  • DRAM memory usually includes multiple storage units. In order to increase the storage capacity of DRAM memory, the number of storage units needs to be increased. However, increasing the number of memory cells takes up a larger area, making the structure less compact and not conducive to device integration.
  • the present disclosure proposes a dynamic memory and a manufacturing method thereof to solve the problem of a large occupied area of DRAM memory in the existing technology.
  • embodiments of the present disclosure provide a dynamic memory
  • the memory unit includes:
  • a transistor includes a semiconductor layer, a gate, a source and a drain; the semiconductor layer includes a source contact area, a channel area and a drain contact area connected in sequence; the gate corresponds to the channel area, the source is connected to the source contact area, and the drain The pole is connected to the drain contact area;
  • the word line extends along the second direction and is electrically connected to the gate
  • the dynamic memory also includes a bit line extending along the first direction.
  • the bit line is electrically connected to the source of the transistor.
  • the bit line is also electrically connected to the source of the transistor in each memory unit distributed in the first direction.
  • the source electrode and the bit line are formed of the same material on the same line; and/or the drain electrode and the capacitor are formed of the same material on the same line.
  • the source contact region of the semiconductor layer has a via for the bit line to pass through, and the portion of the bit line located within the via forms the source and is in contact with the sidewall of the via.
  • the semiconductor layer is perpendicular to the first direction.
  • the capacitor includes an inner electrode, a dielectric layer, and an outer electrode located at the drain.
  • the inner electrode, the dielectric layer, and the outer electrode all surround the drain contact region of the semiconductor layer.
  • the inner electrode, the dielectric layer, and the outer electrode are along the edge away from the semiconductor layer. The orientation of the layers is distributed sequentially.
  • the outer electrodes of the memory cells in two adjacent layers of memory arrays are in contact with each other, or are partially integrally formed;
  • the internal electrode forms a drain.
  • the capacitor includes an internal electrode, a dielectric layer and an external electrode; both the dielectric layer and the external electrode surround the drain contact area of the semiconductor layer, the dielectric layer and the external electrode are sequentially distributed in a direction away from the semiconductor layer, and at least part of the semiconductor layer The drain contact region forms the internal electrode of the capacitor.
  • the transistors of at least two memory cells are connected to the same bit line.
  • each transistor connected to the same bit line is arranged symmetrically with respect to the bit line.
  • the material of the semiconductor layer includes epitaxial monocrystalline silicon; and/or the material of the bit line includes tungsten.
  • a dynamic memory including:
  • the support layer located on one side of the substrate, includes a plurality of isolation walls arranged in an array in the second direction and/or the third direction, and support pillars connected to two opposite isolation walls respectively;
  • a plurality of storage arrays are spaced apart in the first direction;
  • the storage array includes a plurality of storage units arranged in arrays in the second direction and the third direction, and at least two storage units are located on the same support column;
  • the word line extends along the second direction or the third direction and is electrically connected to multiple memory cells in the memory array respectively;
  • Bit lines extend along the first direction and are electrically connected to memory cells in multiple memory arrays respectively;
  • the first direction is perpendicular to the substrate
  • the second direction and the third direction are perpendicular to each other and perpendicular to the first direction respectively.
  • At least two memory cells are electrically connected to the same bit line.
  • At least two memory cells electrically connected to the same bit line are located on the same support column between two opposing isolation walls;
  • At least two memory cells electrically connected to the same bit line are arranged symmetrically with respect to the bit line.
  • the storage unit includes:
  • the transistor includes a semiconductor layer, a gate electrode, a source electrode and a drain electrode; the semiconductor layer includes a source contact area, a channel area and a drain contact area connected in sequence; the gate electrode corresponds to the channel area and is electrically connected to the word line; the source electrode They are electrically connected to the source contact area and bit line respectively, and the drain electrode is connected to the drain contact area;
  • the support pillars are made of semiconductor material to form the semiconductor layer in the transistor.
  • the source contact region of the semiconductor layer has a via for the bit line to pass through, and the portion of the bit line located within the via forms the source and is in contact with the sidewall of the via.
  • the capacitor includes an internal electrode, a dielectric layer and an external electrode; both the dielectric layer and the external electrode surround the drain contact area of the semiconductor layer, the dielectric layer and the external electrode are sequentially distributed in a direction away from the semiconductor layer, and at least part of the semiconductor layer The drain contact region forms the internal electrode of the capacitor.
  • an embodiment of the present disclosure provides a storage device, including the dynamic memory provided by the first aspect of the embodiment of the present disclosure; or including the dynamic memory provided by the second aspect of the embodiment of the present disclosure.
  • embodiments of the present disclosure provide a method for making a dynamic memory, including:
  • a plurality of stacked semiconductor layers are produced on one side of the substrate;
  • the semiconductor layer includes a source contact region, a channel region and a drain contact region connected in sequence;
  • the bit line is electrically connected to the source electrode, and at least one bit line is electrically connected to the source electrode connected to the source contact area of the stacked plurality of semiconductor layers;
  • the entire body including the semiconductor layer, gate electrode, source electrode and drain electrode forms a transistor.
  • a plurality of stacked semiconductor layers are fabricated on one side of the substrate, including:
  • each superlattice thin film layer includes a sacrificial layer and a semiconductor layer that are stacked in sequence;
  • the sacrificial layer is removed, so that multiple semiconductor layers are stacked in sequence and spaced apart from each other.
  • fabricating gates and word lines includes:
  • fabricating the drain and capacitor includes:
  • fabricating the source and bit lines includes:
  • a bit line is made that runs through multiple through holes, and the portion of the bit line located within the through hole forms the source.
  • the dynamic memory in the embodiment of the present disclosure includes a substrate and a plurality of stacked memory arrays disposed on the substrate.
  • the memory array includes a plurality of memory cells arranged in an array.
  • the memory unit includes a transistor and a capacitor, the capacitor is electrically connected to the transistor, and the capacitor is located at the drain of the transistor.
  • the dynamic memory also includes a word line and a bit line.
  • the word line is located at the gate of the transistor and is electrically connected to the transistor.
  • the bit line runs through the semiconductor layer of the transistor in multiple memory cells.
  • the bit line is located at the source.
  • the transistors are electrically connected through bit lines.
  • Figure 1 is a schematic top structural view of a dynamic memory provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of section AA in Figure 1;
  • Figure 3 is a schematic structural diagram of section BB in Figure 1;
  • Figure 4 is a schematic structural diagram of the section CC in Figure 3;
  • Figure 5 is a schematic structural diagram of the section DD in Figure 3;
  • Figure 6 is a schematic diagram of the manufacturing process of a dynamic memory provided by an embodiment of the present disclosure.
  • FIG. 7a to 7j are schematic structural diagrams of different processes for making dynamic memory provided by embodiments of the present disclosure.
  • 121-transistor 123-word line; 124-bit line; 125-gate; 126-gate insulating layer; 127-capacitor; 1271-internal electrode; 1272-dielectric layer; 1273-external electrode; 128-interlayer insulating layer ;
  • the memory cell in DRAM memory usually includes a 1T1C structure in the logic circuit, that is, a transistor and a capacitor. Structurally, it includes a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and a capacitor. Its structure is relatively simple, and the capacity of the memory cell per unit volume (also known as (density) is higher.
  • MOS transistor Metal-Oxide-Semiconductor Field-Effect Transistor
  • the main working principle of DRAM memory is to use capacitors to store charges, and determine whether a binary bit is 1 or 0 based on the amount of charge stored in the capacitor.
  • the memory unit is usually laid out in a two-dimensional space.
  • additional memory units need to be added. The number results in occupying a large area on a limited substrate, making the structure not compact enough, which is not conducive to device integration.
  • 3D DRAM is realized by arranging 1T1C structure memory cells in 3D space.
  • the dynamic memory 10 in the embodiment of the present disclosure includes a substrate 11 and multiple storage arrays 12 stacked on the substrate 11 .
  • the storage array 12 includes multiple array arrangements. storage unit 120.
  • each memory unit in each layer of memory array is distributed in a two-dimensional space, specifically in a plane parallel to the substrate, along the row (hereinafter referred to as the second direction) and column direction (hereinafter referred to as the third direction) ) array distribution, the multi-layer memory array is distributed at intervals in a direction vertical to the substrate (hereinafter referred to as the first direction). Realize the characteristics of storage units distributed in 3D space.
  • Figure 1 is a top view of a memory unit with a three-dimensional structure.
  • Figure 2 is a schematic structural diagram of the section AA in Figure 1;
  • Figure 3 is a schematic structural diagram of the section BB in Figure 1;
  • Figure 4 is a schematic structural diagram of the section CC in Figure 3.
  • Figure 5 is the structural schematic diagram of the section DD in Figure 3.
  • the first direction is perpendicular to the substrate 11
  • the second direction and the third direction are perpendicular to each other and perpendicular to the first direction respectively.
  • Storage unit 120 includes:
  • the transistor 121 includes a semiconductor layer 22, a gate electrode 125, a source electrode and a drain electrode; the semiconductor layer 22 includes a source contact region 32, a channel region 31 and a drain contact region 33 connected in sequence; the gate electrode 125 corresponds to the channel region 31, The source electrode is connected to the source contact area 32, and the drain electrode is connected to the drain contact area 33;
  • Capacitor 127 electrically connected to the drain
  • Word line 123 is electrically connected to gate 125;
  • the dynamic memory 10 further includes a bit line 124.
  • the bit line 124 is electrically connected to the source of the transistor 121.
  • At least one bit line 124 is electrically connected to the source of the transistor 121 in the plurality of stacked memory cells 120.
  • the material of the substrate 11 includes silicon, and a multi-layer memory array 12 is provided on the substrate 11 .
  • Each layer of the memory array 12 includes a plurality of memory cells 120 arranged in an array. It should be noted that the number of layers of the storage array 12 and the number of storage units 120 in each layer of the storage array 12 can be adjusted according to actual conditions.
  • Each memory cell 120 includes a transistor 121 and a capacitor 127 .
  • the transistor 121 includes a semiconductor layer 22
  • the material of the semiconductor layer 22 may be single crystal silicon formed by epitaxial equipment, or other Group 4 semiconductor materials, and the specifics may be determined according to the actual situation.
  • the semiconductor layer 22 includes a source contact region 32 , a drain contact region 33 , and a channel region 31 disposed between the source contact region 32 and the drain contact region 33 .
  • the source contact region 32 and the drain contact region 33 are not limited to the regions indicated by 32 and 33 shown in the drawings, and may be regions other than the channel region corresponding to the gate.
  • the single-layer memory cells distributed in an array share a semiconductor layer for the memory cells in one row or column.
  • the shared semiconductor layer is a strip structure extending along the row or column direction, and the strip structure is connected to the gate electrode.
  • the corresponding area is the channel area, and the areas on both sides of the channel can be the source contact area or the drain contact area.
  • the source contact area or the drain contact area can also be called the source or the drain.
  • the memory unit 120 includes a capacitor 127 , and a capacitor electrode of the capacitor 127 is disposed at the drain contact region 33 of the transistor 121 .
  • the dynamic memory 10 includes multiple word lines 123. There are multiple memory cells 120 (memory cells 120 arranged in the same direction) in each layer of the memory array 12 that share one word line 123. That is, multiple memory cells 120 in each layer of the memory array 12 share one word line 123.
  • the transistor 121 of the memory cell 120 is electrically connected through a word line 123 (the word line 123 is connected to the gate electrode 125 of the transistor 121).
  • the extending direction of the word line 123 and the extending direction of the semiconductor layer 22 are perpendicular to each other.
  • the word lines of memory cells in different layers are spaced apart from each other.
  • the dynamic memory 10 also includes a plurality of bit lines 124. As shown in FIGS. 1, 2 and 3, the source contact area 32 on the semiconductor layer in each layer of memory cells is provided with a through hole 25, and the bit lines 124 are located on the semiconductor layer.
  • the through hole 25 at the source contact region 32 of the layer 22 extends in a direction perpendicular to the substrate, and the sidewalls of the bit line are in contact with the sidewalls of the through hole 25 on the semiconductor layer.
  • Each bit line 124 penetrates the transistors 121 in the multi-layer memory array 12 , and the plurality of transistors 121 penetrated by the bit lines 124 are electrically connected through the bit lines 124 .
  • the material of the bit line 124 includes tungsten and other materials with good conductive properties, and the details can be determined according to actual conditions.
  • a high voltage is applied to the gate 125 of the transistor 121 through the word line 123 , and the source contact region 32 and the drain contact region 33 of the semiconductor layer 22 The channel region 31 between them is turned on, so that the transistor 121 is in an on state.
  • the data signal is transmitted to the transistor 121 through the bit line 124, and then transmitted to the capacitor 127 through the transistor 121 to write data into the memory unit 120.
  • the level of the data signal voltage determines the amount of charge on the capacitor 127, which in turn determines whether the binary value of the written data signal is 0 or 1.
  • the dynamic memory 10 When the dynamic memory 10 is in the read mode, a high voltage is applied to the gate 125 of the transistor 121 through the word line 123, so that the transistor 121 is in the on state, and the electrical signal in the capacitor 127 is transmitted to the external read and write circuit through the bit line 124 (Fig. 1 to FIG. 3 ), that is, the read-write circuit reads the data in the storage unit 120 through the bit line 124 .
  • the dynamic memory 10 with a three-dimensional structure is formed by stacking the storage array 12 including a plurality of storage units 120, which increases the storage capacity of the dynamic memory 10 while avoiding the need to store the storage units 120.
  • the area of the dynamic memory 10 is too large, thus making the structural layout of the memory unit 120 more compact, which improves storage density and is more conducive to device integration.
  • the bit lines 124 to penetrate the semiconductor layers of the transistors 121 in the multiple memory cells 120, multiple stacked transistors 121 can be electrically connected through one bit line 124, that is, the multiple stacked transistors 121 share one
  • the bit line 124 is therefore beneficial to simplifying the structure and manufacturing process of the dynamic memory.
  • the drain contact region 33 of the semiconductor layer 22 is electrically connected to the capacitor 127, and the source contact region 32 of the semiconductor layer 22 is electrically connected to the bit line 124 by directly contacting the capacitor 127 and the bit line 124. connection, so no specially made metal electrodes (source or drain) are required.
  • the semiconductor layer 22 is fabricated, at least part of the source contact region 32 on the semiconductor layer 22 is conductive through an in-situ doping process to form a source electrode, so that the semiconductor layer At least part of the drain contact region 33 on 22 is conductive to form a drain.
  • the source is integrally formed with the bit line 124 .
  • the source electrode and the bit line 124 are formed on the same line from the same material.
  • the drain is integrally formed with capacitor 127 .
  • the drain electrode and the capacitor 127 are formed of the same material on the same line.
  • the source contact region 32 of the semiconductor layer 22 has a via 25 for the bit line to pass through, and the portion of the bit line 124 located within the via 25 forms the source and is in contact with the sidewalls of the via 25 .
  • semiconductor layer 22 is perpendicular to the first direction.
  • the semiconductor layer may be parallel to the second direction or parallel to the third direction.
  • the capacitor 127 includes an inner electrode 1271 , a dielectric layer 1272 and an outer electrode 1273 located at the drain contact region 33 .
  • the inner electrode 1271 , the dielectric layer 1272 and the outer electrode 1273 all surround the drain contact region 33 of the semiconductor layer 22 , and the internal electrode 1271 , the dielectric layer 1272 and the external electrode 1273 are sequentially distributed in a direction away from the semiconductor layer 22 .
  • the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 are sequentially grown at the drain contact region 33 of the semiconductor layer 22, and the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 are all surrounded by The semiconductor layer 22 is provided and distributed sequentially in a direction away from the semiconductor layer 22 .
  • the outer electrode 1273, the inner electrode 1271, and the dielectric layer 1272 overlap each other to form the capacitor 127.
  • the thickness of the dielectric layer 1272 does not need to be very thin (the smaller the thickness of the dielectric layer 1272, the greater the capacity of the capacitor 127. In order to increase the capacity of the capacitor 127, the thickness of the dielectric layer 1272 can be reduced). Therefore, it is beneficial to reduce the cost of the dynamic memory 10. Difficulty of production.
  • the materials of the inner electrode 1271 and the outer electrode 1273 include titanium nitride and other materials with good conductive properties.
  • the material of the dielectric layer 1272 is selected from materials with high dielectric constant, which can be determined according to the actual situation.
  • the capacitors 127 of the memory cells 120 in two adjacent layers of memory arrays 12 share the external electrode 1273 .
  • the external electrodes 1273 of the memory cells 120 in two adjacent layers of memory arrays 12 are in contact with each other, or are partially integrally formed.
  • the external electrode 1273 located between the two layers of memory cells 120 is both the external electrode 1273 of the capacitor 127 in the memory unit 120 of the upper layer and the external electrode of the capacitor 127 of the memory unit 120 of the next layer. 1273, thus simplifying the structure of the dynamic memory 10 and helping to reduce the thickness of the dynamic memory 10 in the first direction in FIG. 3 .
  • only one layer of external electrode 1273 needs to be fabricated between two adjacent layers of memory cells 120, thus simplifying the fabrication process of the dynamic memory 10.
  • At least a portion of internal electrode 1271 forms a drain.
  • the capacitor 127 includes an internal electrode 1271, a dielectric layer 1272, and an external electrode 1273; the dielectric layer 1272 and the external electrode 1273 both surround the drain contact region 33 of the semiconductor layer 22, and the dielectric layer 1272 and the external electrode 1273 are along the edges away from the semiconductor layer. 22 are sequentially distributed, and at least part of the drain contact region 33 of the semiconductor layer 22 forms the internal electrode 1271 of the capacitor 127 .
  • the transistor 121 further includes a gate insulating layer 126 , the gate electrode 125 and the gate insulating layer 126 surround the channel region of the semiconductor layer 22 , and the gate electrode 125 and the gate insulating layer 126 are sequentially distributed in a direction away from the semiconductor layer 22 .
  • the gate electrode 125 and the gate insulating layer 126 surround the semiconductor layer 22 , and the gate electrode 125 and the gate insulating layer 126 are sequentially distributed in a direction away from the semiconductor layer 22 .
  • gates 125 of transistors 121 located at different layers are insulated from each other by interlayer insulating layers 128 .
  • At least two transistors 121 share a bit line 124 in the same layer of memory array 12 .
  • the transistors 121 of at least two memory cells 120 are connected to the same bit line 124.
  • the transistors 121 in two adjacent memory cells 120 (the transistors 121 located on the same straight line in FIG. 1 ) share the bit line 124 , so the increase in While reducing the number of memory units 120 and improving storage density, it also avoids occupying too much area, which is beneficial to improving the integration of the device.
  • the number of transistors 121 sharing the bit line 124 can be adjusted according to the actual situation. The greater the number of transistors 121 sharing the bit line 124, the more conducive to reducing the area of the dynamic memory 10 , improve the integration level of the dynamic memory 10.
  • each transistor 121 connected to the same bit line 124 is arranged symmetrically with respect to the bit line 124 .
  • it can be axially symmetrical with respect to the bit line 124, or rotationally symmetrical with respect to the bit line 124, and so on.
  • an embodiment of the present disclosure also provides another dynamic memory 10.
  • the dynamic memory 10 includes: a substrate 11, a support layer 24, a plurality of memory arrays 12, word lines 123 and bit lines 124.
  • the support layer 24 is located on one side of the substrate 11 and includes a plurality of isolation walls arranged in an array in the second direction and/or the third direction, and support columns respectively connected to two opposite isolation walls.
  • the plurality of memory arrays 12 are spaced apart in the first direction; the memory array 12 includes a plurality of memory units 120 arranged in arrays in the second direction and the third direction, and at least two memory units 120 are located on the same support column.
  • the word line 123 extends along the second direction or the third direction and is electrically connected to the plurality of memory cells 120 in the memory array 12 respectively.
  • the bit lines 124 extend along the first direction and are electrically connected to the memory cells 120 in the plurality of memory arrays 12 respectively.
  • the first direction is perpendicular to the substrate 11
  • the second direction and the third direction are perpendicular to each other and perpendicular to the first direction respectively.
  • the support layer 24 adopts a matching structure of isolation walls and support columns, which can realize the three-dimensional spatial layout of each storage unit 120 in the dynamic memory 10 and is beneficial to increasing the density of the storage unit 120.
  • Arranging at least two storage units 120 on the same support column between two opposite isolation walls can further increase the density of the storage units 120 in the two-dimensional space parallel to the substrate.
  • the bit lines 124 in the dynamic memory 10 extend along the first direction, that is, the bit lines 124 are arranged vertically perpendicular to the direction of the substrate, which is beneficial to increasing the density of each memory unit 120 in the dynamic memory 10 .
  • At least two memory cells 120 are electrically connected to the same bit line 124 in the same layer of memory array 12 .
  • multiple memory cells 120 share one bit line 124, which not only helps to increase the density of the memory cells 120, but also helps to simplify the structure and manufacturing process of the dynamic memory.
  • At least two memory cells 120 electrically connected to the same bit line 124 are located on the same support column between two opposing isolation walls. This is beneficial to compressing the layout space between the memory cells 120 sharing one bit line 124, that is, further increasing the density of the memory cells 120.
  • At least two memory cells 120 electrically connected to the same bit line 124 are arranged symmetrically with respect to the bit line 124 . This can facilitate the establishment of connections between at least two memory cells 120 and the same bit line 124 .
  • the memory unit 120 includes a transistor 121 and a capacitor 127 .
  • the transistor 121 includes a semiconductor layer 22, a gate electrode 125, a source electrode and a drain electrode; the semiconductor layer 22 includes a source contact region 32, a channel region 31 and a drain contact region 33 connected in sequence; the gate electrode 125 corresponds to the channel region 31, and It is electrically connected to the word line 123; the source electrode is electrically connected to the source contact area 32 and the bit line 124 respectively, and the drain electrode is connected to the drain contact area 33.
  • Capacitor 127 is electrically connected to the drain.
  • the support pillars are made of semiconductor material to form the semiconductor layer 22 in the transistor 121 .
  • the support pillars are made of semiconductor material, that is, at least part of the support pillars directly forms the semiconductor layer 22 in the transistor. This can not only reduce the size of the device and increase the density of the memory cell, but also save the preparation process. , reduce materials and reduce costs.
  • the source contact region 32 of the semiconductor layer 22 has a via 25 for the bit line 124 to pass through, and the portion of the bit line 124 located within the via 25 forms the source and is in contact with the sidewall of the via 25 .
  • the capacitor 127 includes an internal electrode 1271, a dielectric layer 1272, and an external electrode 1273; the dielectric layer 1272 and the external electrode 1273 both surround the drain contact region 33 of the semiconductor layer 22, and the dielectric layer 1272 and the external electrode 1273 are along the edges away from the semiconductor layer. 22 are sequentially distributed, and at least part of the drain contact region 33 of the semiconductor layer 22 forms the internal electrode 1271 of the capacitor 127 .
  • an embodiment of the present disclosure also provides a storage device, which includes the dynamic memory 10 in the above embodiments and has the beneficial effects of the dynamic memory 10 in any of the above embodiments, which will not be discussed here.
  • the storage device in the embodiment of the present disclosure may be the main memory of a computer, etc., and the details may be determined according to the actual situation, and are not limited here.
  • embodiments of the present disclosure also provide a method for manufacturing dynamic memory 10, as shown in Figure 6, including the following steps S101-S105:
  • S102 Make multiple stacked semiconductor layers on one side of the substrate; the semiconductor layer includes a source contact region, a channel region and a drain contact region connected in sequence.
  • fabricating multiple stacked semiconductor layers on one side of the substrate in step S102 includes:
  • Each superlattice thin film layer includes a sacrificial layer and a semiconductor layer that are stacked in sequence.
  • the multi-layer superlattice thin film layer is etched to obtain a foundation hole that exposes part of the substrate; in the foundation hole, the diameter of the portion located on the sacrificial layer is larger than the diameter of the portion located on the semiconductor layer.
  • the support material is filled into the foundation pile holes through a deposition process to form a support layer. Since the diameter of the part located on the sacrificial layer is larger than the diameter of the part located on the semiconductor layer in the pile hole produced by the aforementioned process, the support layer prepared in this step can extend to the space between the two adjacent semiconductor layers. After the sacrificial layer is removed, support can be provided for the two adjacent semiconductor layers.
  • the sacrificial layer is removed, so that multiple semiconductor layers are stacked in sequence and spaced apart from each other.
  • S103 Make the gate electrode and word line so that the gate electrode corresponds to the channel region and the word line is electrically connected to the gate electrode.
  • fabricating the gate electrode and word line in step S103 includes: fabricating a gate insulating layer surrounding the channel region in the semiconductor layer; fabricating a gate electrode surrounding the gate insulating layer.
  • S104 Make the drain electrode and the capacitor so that the drain electrode is connected to the drain contact area and the capacitor is electrically connected to the drain electrode.
  • fabricating the drain and capacitor in step S104 includes:
  • An internal electrode is formed surrounding the drain contact region in the semiconductor layer, and at least part of the internal electrode forms a drain electrode.
  • S105 Make the source electrode and the bit line so that the source electrode is connected to the source contact area, the bit line is electrically connected to the source electrode, and at least one bit line is electrically connected to the source electrode connected to the source contact area of multiple stacked semiconductor layers. .
  • the entire body including the semiconductor layer, gate electrode, source electrode and drain electrode forms a transistor.
  • fabricating the source and bit lines in step S105 includes:
  • the source contact areas in the stacked semiconductor layers are etched to obtain through holes penetrating both sides of the semiconductor layers.
  • a bit line is made that runs through multiple through holes, and the portion of the bit line located within the through hole forms the source.
  • the dynamic memory 10 prepared through the above steps S101-S105 includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11.
  • the memory array 12 includes a plurality of memory cells 120 arranged in an array.
  • the memory cells 120 Includes transistor 121 and capacitor 127.
  • the dynamic memory 10 also includes a word line 123 and a bit line 124.
  • the word line 123 is located at the gate 125 of the transistor 121 and is electrically connected to the transistor 121.
  • the bit line 124 penetrates the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120.
  • the bit line 124 is located at the source contact region 32 , and the transistors 121 in the plurality of memory cells 120 are electrically connected through the bit lines 124 .
  • a dynamic memory 10 with a three-dimensional structure is formed, which increases the storage capacity of the dynamic memory 10 and avoids the problem caused by arranging the storage units 120 on the same plane.
  • the area of the dynamic memory 10 is too large, which makes the structural layout of the memory unit 120 more compact, which improves the storage density and is more conducive to device integration.
  • the word lines 123 can be etched through a modified etching process, so that the degree of the word lines 123 located on different layers is inconsistent, even if the word lines 123 on different layers are in a stepped shape. .
  • the length of the word line 123 in the second direction in FIG. 2 gradually decreases, so it can be conveniently located on different layers.
  • the word line 123 is connected to the read and write circuit through wiring (not shown in Figures 1 and 2).
  • Figure 7a first, a substrate 11 is provided, and the material of the substrate 11 includes silicon.
  • Figure 7a-1 is a cross-sectional view along the first direction
  • Figure 7a-2 is a top view.
  • each layer of the superlattice film 20 includes a sacrificial layer distributed along the first direction in Fig. 7b. 21 and semiconductor layer 22.
  • the material of the sacrificial layer 21 includes silicon germanium (SiGe).
  • the material of the semiconductor layer 22 includes single crystal silicon.
  • the semiconductor layer 22 includes a source contact region 32 and a drain contact region 33. Channel area 31 between contact areas 33.
  • the number of layers of the superlattice film 20 can be determined according to actual conditions, for example, it can be 8 layers, 16 layers or 32 layers. It should be noted that FIG. 7b only shows three sacrificial layers 21 for illustration, and does not represent a limitation of this solution.
  • Figure 7b-1 is a cross-sectional view along the first direction
  • Figure 7b-2 is a top view.
  • the multi-layer sacrificial layer 21 and the semiconductor layer 22 are then etched to remove part of the material of the sacrificial layer 21 and the semiconductor layer 22 so that the semiconductor layers 22 form a spaced-apart structure.
  • the number of semiconductor layers 22 and the distance d between the semiconductor layers 22 can be adjusted according to actual conditions.
  • Figure 7c-1 is a cross-sectional view along the first direction
  • Figure 7c-2 is a top view.
  • Figure 7d-1 is a cross-sectional view along the first direction
  • Figure 7d-2 is a top view.
  • a support layer 24 is deposited through an atomic deposition process or a chemical vapor deposition process (the support layer 24 is located at both ends of the semiconductor layer 22 ), and the support layer 24 fills the trench 23 .
  • the material of the support layer 24 includes materials with good insulating properties such as silicon nitride and silicon oxide, and can be determined according to actual conditions. It should be noted that the purpose of making the trench 23 and the support layer 24 is so that after the sacrificial layer 21 is subsequently removed, the support layer 24 can support the multi-layer semiconductor layer 22 and prevent the structure from collapsing.
  • the material of the support layer 24 includes oxides and nitrides (such as silicon oxide and silicon nitride), and the details can be adjusted according to actual conditions.
  • Figure 7e-1 is a cross-sectional view along the first direction
  • Figure 7e-2 is a top view.
  • FIG. 7f next, by adjusting the etching selectivity ratio of the sacrificial layer 21 and the semiconductor layer 22 (making the etching rate of the sacrificial layer 21 greater than the etching rate of the semiconductor layer 22), the sacrificial layer 21 between the semiconductor layers 22 is The semiconductor layer 22 is etched and removed, leaving the semiconductor layer 22 as a plurality of semiconductor layers 22 .
  • the support layers 24 at both ends of the semiconductor layer 22 can support the semiconductor layer 22 .
  • Figure 7f-1 is a cross-sectional view along the first direction
  • Figure 7f-2 is a top view.
  • the gate insulating layer 126 surrounding the semiconductor layer 22 , the gate electrode 125 and the interlayer insulating layer 128 are sequentially grown on the semiconductor layer 22 , and the conductive material continues to grow between the gate electrodes 125 on the same layer. , to form the connection word line 123.
  • the word lines 123 are etched through a modified etching process, so that the lengths of the word lines 123 located on different layers are inconsistent, that is, the word lines 123 on different layers are stepped.
  • Figure 7g-1 is a cross-sectional view along the first direction
  • Figure 7g-2 is a top view.
  • the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 surrounding the semiconductor layer 22 are sequentially grown in the area where the capacitor 127 is to be formed on the semiconductor layer 22 (ie, the drain contact region 33 of the semiconductor layer 22).
  • the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 constitute the capacitor 127.
  • the external electrode 1273 located between the two semiconductor layers 22 is not only the external electrode 1273 of the capacitor 127 corresponding to the semiconductor layer 22 of the upper layer, but also the external electrode 1273 of the capacitor 127 corresponding to the semiconductor layer 22 of the lower layer. This simplifies the structure of the dynamic memory and also simplifies the manufacturing process of the dynamic memory.
  • the materials of the inner electrode 1271 and the outer electrode 1273 include titanium nitride, and the details can be determined according to actual conditions.
  • Figure 7h-1 is a cross-sectional view along the first direction
  • Figure 7h-2 is a top view.
  • Figure 7i-1 is a cross-sectional view along the first direction
  • Figure 7i-2 is a top view.
  • bit line 124 As shown in FIG. 7j , metal material is then filled into the through hole 25 to form the bit line 124 .
  • Source contact regions 32 of transistors 121 located at different layers are electrically connected through bit lines 124 .
  • the blank area between the word line 123 and the bit line 124 can also be filled with an isolation material with good insulation properties (not shown in FIG. 7j ) to avoid gaps in the structure of the dynamic memory 10 .
  • Figure 7j-1 is a cross-sectional view along the first direction
  • Figure 7j-2 is a top view.
  • the manufacturing method in the embodiment of the present disclosure it is relatively easy to manufacture the dynamic memory 10 with a stacked structure, making it possible to mass-produce the dynamic memory 10 with a stacked structure.
  • the dynamic memory 10 includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11.
  • the memory array 12 includes a plurality of memory cells 120 arranged in an array.
  • the memory cells 120 Includes transistor 121 and capacitor 127.
  • the dynamic memory 10 also includes a word line 123 and a bit line 124.
  • the word line 123 is located at the gate 125 of the transistor 121 and is electrically connected to the transistor 121.
  • the bit line 124 penetrates the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120.
  • the bit line 124 is located at the source contact region 32 , and the transistors 121 in the plurality of memory cells 120 are electrically connected through the bit lines 124 .
  • a dynamic memory 10 with a three-dimensional structure is formed, which increases the storage capacity of the dynamic memory 10 and avoids the problem caused by arranging the storage units 120 on the same plane.
  • the area of the dynamic memory 10 is too large, which makes the structural layout of the memory unit 120 more compact, which improves the storage density and is more conducive to device integration.
  • multiple stacked transistors can be electrically connected through one bit line, thereby simplifying the structure and manufacturing process of the dynamic memory.
  • the capacitor 127 includes an inner electrode 1271, a dielectric layer 1272 and an outer electrode 1273 located at the drain contact region 33.
  • the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 all surround the drain of the semiconductor layer 22.
  • the contact area 33 , the internal electrode 1271 , the dielectric layer 1272 and the external electrode 1273 are sequentially distributed along the direction away from the semiconductor layer 22 .
  • the capacitors 127 of the memory cells 120 in two adjacent layers of memory arrays 12 share the external electrode 1273, that is, the external electrode 1273 located between the two layers of memory cells 120 is the memory unit located in the upper layer.
  • the external electrode 1273 of the capacitor 127 in the memory unit 120 is also the external electrode 1273 of the capacitor 127 in the memory unit 120 of the next layer. Therefore, the structure and manufacturing process of the dynamic memory 10 can be simplified.
  • At least two transistors 121 share the bit line 124. Therefore, while increasing the number of memory cells 120 and improving the storage density, it also avoids occupying too many cells. area, which is conducive to improving the integration of the device.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present disclosure, “plurality” means two or more unless otherwise specified.

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Abstract

本公开提供一种动态存储器及其制作方法、存储装置，该动态存储器包括衬底和层叠的设置在衬底上的多个存储阵列，存储阵列包括多个阵列排布的存储单元，存储单元包括晶体管和电容。动态存储器的字线位于晶体管的栅极处并与晶体管连接，位线贯穿多个存储单元，多个存储单元中的晶体管通过位线连接。通过将包括多个存储单元的存储阵列层叠设置，形成了具有立体结构的动态存储器，在提高了动态存储器存储容量的同时，使得存储单元的结构布局更加紧凑。另一方面，通过使位线贯穿多个存储单元，多个层叠设置的晶体管通过一个位线即可实现连接，由此简化了动态存储器的结构和制作工艺。

Description

一种动态存储器及其制作方法、存储装置
相关交叉引用
本公开要求于2022年4月25日在国家知识产权局提交的申请号为202210465087.4的中国专利申请的优先权，该优先权申请的全部内容通过引用并入本文。
技术领域
本公开涉及半导体器件技术领域，具体而言，本公开涉及一种动态存储器及其制作方法、存储装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，和静态存储器相比，DRAM存储器具有结构较为简单、制造成本较低、容量密度较高的优点，随着技术的发展，DRAM存储器越来越广泛地被应用于服务器、智能手机、个人电脑等电子装置之中。
DRAM存储器通常包括多个存储单元，为了提高DRAM存储器的存储容量，需要增加存储单元的数量。然而，增加存储单元的数量又占用较大的面积，使得结构不够紧凑，不利于器件的集成。
发明内容
本公开针对现有方式的缺点，提出一种动态存储器及其制作方法，用以解决现有技术中DRAM存储器存在的占用面积较大的问题。
第一个方面，本公开实施例提供了一种动态存储器，
包括衬底和层叠的设置在衬底上的多个存储阵列，多个存储阵列在第一方向上间隔分布，存储阵列包括多个在第二方向和第三方向阵列排布的 存储单元，第一方向垂直于衬底，第二方向与第三方向相互垂直、且分别与第一方向垂直，存储单元包括：
晶体管，包括半导体层、栅极、源极和漏极；半导体层包括依次连接的源接触区、沟道区和漏接触区；栅极与沟道区对应，源极与源接触区连接，漏极与漏接触区连接；
电容，与漏极电连接；
字线，沿着第二方向延伸与栅极电连接；
动态存储器还包括位线，沿着第一方向延伸，位线与晶体管的源极电连接，位线同时与第一方向上分布的各存储单元中晶体管的源极电连接。
在一些实施例中，源极与位线由相同的材料形成在同一条线上；和/或，漏极与电容由相同的材料形成在同一条线上。
在一些实施例中，半导体层的源接触区具有用于位线穿过的通孔，位线的位于通孔内的部分形成源极且与通孔的侧壁接触。
在一些实施例中，半导体层垂直于第一方向。
在一些实施例中，电容包括位于漏极处的内电极、介质层和外电极，内电极、介质层和外电极均围绕半导体层的漏接触区，内电极、介质层和外电极沿远离半导体层的方向依次分布。
在一些实施例中，相邻两层存储阵列中存储单元的外电极相互接触、或部分一体成型；
和/或，至少部分内电极形成漏极。
在一些实施例中，电容包括内电极、介质层和外电极；介质层和外电极均围绕半导体层的漏接触区，介质层和外电极沿远离半导体层的方向依次分布，半导体层的至少部分漏接触区形成电容的内电极。
在一些实施例中，在同一层存储阵列中，至少两个存储单元的晶体管与相同的位线连接。
在一些实施例中，与相同位线连接的各晶体管相对位线对称布置。
在一些实施例中，半导体层的材料包括外延单晶硅；和/或，位线的材料包括钨。
第二个方面，本公开实施例提供了一种动态存储器，包括：
衬底；
支撑层，位于衬底一侧，包括多个在第二方向和/或第三方向阵列排布的隔离墙、以及分别与两个相对的隔离墙连接的支撑柱；
多个存储阵列，在第一方向上间隔分布；存储阵列包括多个在第二方向和第三方向阵列排布的存储单元，至少两个存储单元位于相同的支撑柱上；
字线，沿第二方向或第三方向延伸，分别与存储阵列中的多个存储单元电连接；
位线，沿第一方向延伸，分别与多个存储阵列中的存储单元电连接；
其中，第一方向垂直于衬底，第二方向与第三方向相互垂直、且分别与第一方向垂直。
在一些实施例中，在同一层存储阵列中，至少两个存储单元与相同的位线电连接。
在一些实施例中，与相同的位线电连接的至少两个存储单元位于两个相对的隔离墙之间的相同的支撑柱上；
和/或，与相同的位线电连接的至少两个存储单元相对位线对称布置。
在一些实施例中，存储单元包括：
晶体管，包括半导体层、栅极、源极和漏极；半导体层包括依次连接的源接触区、沟道区和漏接触区；栅极与沟道区对应，并与字线电连接；源极分别与源接触区、位线电连接，漏极与漏接触区连接；
电容，与漏极电连接。
在一些实施例中，支撑柱采用半导体材料制成，以形成晶体管中的半导体层。
在一些实施例中，半导体层的源接触区具有用于位线穿过的通孔，位线的位于通孔内的部分形成源极且与通孔的侧壁接触。
在一些实施例中，电容包括内电极、介质层和外电极；介质层和外电极均围绕半导体层的漏接触区，介质层和外电极沿远离半导体层的方向依 次分布，半导体层的至少部分漏接触区形成电容的内电极。
第三个方面，本公开实施例提供了一种存储装置，包括本公开实施例中第一个方面提供的动态存储器；或，包括本公开实施例中第二个方面提供的动态存储器。
第四个方面，本公开实施例提供了一种动态存储器的制作方法，包括：
提供衬底；
在衬底的一侧制作层叠的多个半导体层；半导体层包括依次连接的源接触区、沟道区和漏接触区；
制作栅极和字线，使得栅极与沟道区对应、字线与栅极电连接；
制作漏极和电容，使得漏极与漏接触区连接、电容与漏极电连接；
制作源极和位线，使得源极与源接触区连接、位线与源极电连接，至少一根位线分别与层叠的多个半导体层的源接触区所连接的源极电连接；
其中，包括半导体层、栅极、源极和漏极的整体形成晶体管。
在一些实施例中，在衬底的一侧制作层叠的多个半导体层，包括：
通过外延生长工艺在衬底的一侧层叠地制作多层超晶格薄膜层，每一层超晶格薄膜层包括依次层叠设置的牺牲层和半导体层；
对多层超晶格薄膜层进行刻蚀，得到露出部分衬底的基桩孔；在基桩孔中，位于牺牲层的部分的直径大于位于半导体层的部分的直径；
通过沉积工艺在基桩孔内填充支撑材料，以形成支撑层；
去除牺牲层，使得多个半导体层依次层叠且相互间隔。
在一些实施例中，制作栅极和字线，包括：
制作环绕半导体层中沟道区的栅绝缘层；
制作环绕栅绝缘层的栅极。
在一些实施例中，制作漏极和电容，包括：
制作环绕半导体层中漏接触区的内电极，至少部分内电极形成漏极；
制作环绕内电极的介质层；
制作环绕介质层的外电极，使得包括内电极、介质层和外电极的整体形成电容。
在一些实施例中，制作源极和位线，包括：
对层叠的多个半导体层中源接触区进行刻蚀，得到贯穿半导体层两侧的通孔；
制作贯穿多个通孔的位线，位线的位于通孔内的部分形成源极。
本公开实施例提供的技术方案带来的有益技术效果包括：
本公开实施例中的动态存储器包括衬底和层叠的设置在衬底上的多个存储阵列，存储阵列包括多个阵列排布的存储单元。存储单元包括晶体管和电容，电容与晶体管电连接，电容位于晶体管的漏极处。动态存储器还包括字线和位线，字线位于晶体管的栅极处并与晶体管电连接，位线贯穿多个存储单元中晶体管的半导体层，位线位于源极处，多个存储单元中的晶体管通过位线电连接。通过将包括多个存储单元的存储阵列层叠设置，形成了具有立体结构的动态存储器，在提高了动态存储器存储容量的同时，避免了将存储单元设置在同一个平面上时造成动态存储器的面积过大，使得存储单元的结构布局更加紧凑，在提高了存储密度的同时更加有利于器件的集成。另一方面，通过使位线贯穿多个存储单元中晶体管的半导体层，多个层叠设置的晶体管通过一个位线即可实现电连接，由此简化了动态存储器的结构和制作工艺。
本公开实施例的优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
本公开上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本公开实施例提供的动态存储器的俯视结构示意图；
图2为图1中截面AA处的结构示意图；
图3为图1中截面BB处的结构示意图；
图4为图3中截面CC处的结构示意图；
图5为图3中截面DD处的结构示意图；
图6为本公开实施例提供的动态存储器的制作流程示意图；
图7a至图7j为本公开实施例提供的制作动态存储器的不同过程的结构示意图。
图中：
10-动态存储器；11-衬底；12-存储阵列；120-存储单元；
121-晶体管；123-字线；124-位线；125-栅极；126-栅绝缘层；127-电容；1271-内电极；1272-介质层；1273-外电极；128-层间绝缘层；
20-超晶格薄膜；21-牺牲层；22-半导体层；23-沟槽；24-支撑层；25-通孔；
31-沟道区；32-源接触区；33-漏接触区。
具体实施方式
下面结合本公开中的附图描述本公开的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本公开实施例的技术方案的示例性描述，对本公开实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本公开的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。应该理解，当我们称元件被“连接”或“耦接”到另一元件时，它可以直接连接或耦接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
DRAM存储器中的存储单元在逻辑电路中通常包括1T1C结构，即一个晶体管和一个电容。在结构上，包括一个MOS管(金属-氧化物半导体场效应晶体管，Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)以及一个电容器，其结构较为简单，单位体积内的存储单元的容量(也称为密度)较高。DRAM存储器的主要工作原理是利用电容存储电荷，通过电容内所存储电荷的多少来判断一个二进制比特是1还是0。
本领域的发明人考虑到，在现有的1T1C存储器(即存储单元中设置一个MOS管和一个电容器)中，存储单元通常在二维空间布局，当存储器采用高密度设计时，需要增加存储单元的数量，导致在有限的衬底上占用较大的面积，使得结构不够紧凑，不利于器件的集成化。
本公开实施例提供的动态存储器以及存储装置，旨在改善如上技术问题。通过3D空间内设置1T1C结构的存储单元，实现3D DRAM。
下面结合附图详细介绍一下本公开实施例提供的动态存储器以及存储装置。
结合图1、图2和图3所示，本公开实施例中的动态存储器10包括衬底11和层叠的设置在衬底11上的多个存储阵列12，存储阵列12包括多个阵列排布的存储单元120。
具体的，每层存储阵列中的各存储单元在二维空间分布，具体分布于平行于衬底的平面内，沿着行(以下称为第二方向)和列方向(以下称为第三方向)阵列分布，多层存储阵列在垂直衬底的方向上间隔分布(以下称为第一方向)。实现在3D空间分布的存储单元的特点。
如图1所示为三维立体结构的存储单元的俯视图，图2为图1中截面AA处的结构示意图；图3为图1中截面BB处的结构示意图；图4为图3中截面CC处的结构示意图；图5为图3中截面DD处的结构示意图。第一方向垂直于衬底11，第二方向与第三方向相互垂直、且分别与第一方向垂直。
存储单元120包括：
晶体管121，包括半导体层22、栅极125、源极和漏极；半导体层22包括依次连接的源接触区32、沟道区31和漏接触区33；栅极125与沟道区31对应，源极与源接触区32连接，漏极与漏接触区33连接；
电容127，与漏极电连接；
字线123，与栅极125电连接；
动态存储器10还包括位线124，位线124与晶体管121的源极电连接，至少一根位线124分别与层叠的多个存储单元120中晶体管121的源极电连接。
在一些实施例中，衬底11的材料包括硅，在衬底11之上设置有多层存储阵列12，每一层存储阵列12中包括多个阵列排布的存储单元120。需要说明的是，存储阵列12的层数，以及每一层存储阵列12中存储单元120的数量可根据实际情况进行调整。每一存储单元120中包括1个晶体管121和1个电容127。如图1所示，晶体管121中包括半导体层22，半导体层22的材料可以是外延设备形成的单晶硅，或者是其他四族半导体材料，具体可根据实际情况进行确定。半导体层22包括源接触区32、漏接触区33以及设置在源接触区32和漏接触区33之间的沟道区31。
源接触区32和漏接触区33不限于附图中所示的32和33指代的区域，可以是除栅极对应的沟道区域之外的区域。一些实施例中，阵列分布的单层存储单元，一行或一列上的存储单元的半导体层共用，共用的半导体层为沿着行或列方向延伸的条状结构，该条状结构中与栅极对应的区域为沟道区域，沟道两侧的区域可以为源接触区域或漏接触区域，源接触区域或漏接触区域也可以称为源极或漏极。
存储单元120中包括电容127，电容127的电容电极设置在晶体管121的漏接触区33处。动态存储器10中包括多个字线123，每一层存储阵列12中有多个存储单元120(沿同一方向排列的存储单元120)共用一个字线123，即每一层存储阵列12中多个存储单元120的晶体管121通过字线123电连接(字线123连接晶体管121的栅极125)，字线123的延伸方向与半导体层22的延伸方向互相垂直。不同层的存储单元的字线相互间隔设置。
动态存储器10中还包括多个位线124，结合图1、图2和图3所示，每层存储单元中的所述半导体层上源接触区32设置有通孔25，位线124位于半导体层22的源接触区32处的所述通孔25中沿着垂直衬底的方向 延伸，该位线的侧壁与所述半导体层上所述通孔25的侧壁接触。每一个位线124贯穿多层存储阵列12中的晶体管121，被位线124贯穿的多个晶体管121通过位线124电连接。位线124的材料包括钨等具有良好导电性能的材料，具体可根据实际情况进行确定。
结合图1、图2和图3所示，在动态存储器10处于写入模式时，通过字线123对晶体管121的栅极125施加高电压，半导体层22的源接触区32以及漏接触区33之间的沟道区31导通，使晶体管121处于开启状态，数据信号通过位线124传输至晶体管121，然后通过晶体管121传输至电容127，以实现将数据写入存储单元120。数据信号电压的高低决定电容127上电荷的多少，进而决定了写入的数据信号的二进制是0还是1。在动态存储器10处于读取模式时，通过字线123对晶体管121的栅极125施加高电压，使晶体管121处于开启状态，电容127中的电信号通过位线124传输至外部读写电路(图1至图3中未示出)，即读写电路通过位线124将存储单元120中的数据读出。
在本公开的实施例中，通过将包括多个存储单元120的存储阵列12层叠设置，形成了具有立体结构的动态存储器10，在提高了动态存储器10存储容量的同时，避免了将存储单元120设置在同一个平面上时造成动态存储器10的面积过大，因此使得存储单元120的结构布局更加紧凑，在提高了存储密度的同时更加有利于器件的集成。另一方面，通过使位线124贯穿多个存储单元120中晶体管121的半导体层，多个层叠设置的晶体管121通过一个位线124即可实现电连接，即多个层叠设置的晶体管121共用一个位线124，因此有利于简化动态存储器的结构和制作工艺。
在一些实施例中，使半导体层22直接与电容127以及位线124接触连接即可实现半导体层22的漏接触区33与电容127电连接、半导体层22的源接触区32与位线124电连接，因此不需要专门制作金属电极(源极或漏极)。
在一些实施例中，在动态存储器10的制作过程中，制作了半导体层22后，通过原位掺杂工艺使得半导体层22上的至少部分源接触区32导 体化以形成源极，使得半导体层22上的至少部分漏接触区33导体化以形成漏极。
在一些实施例中，源极与位线124一体成型。具体地，源极与位线124由相同的材料形成在同一条线上。
在一些实施例中，漏极与电容127一体成型。具体地，漏极与电容127由相同的材料形成在同一条线上。
在一些实施例中，半导体层22的源接触区32具有用于位线穿过的通孔25，位线124的位于通孔25内的部分形成源极且与通孔25的侧壁接触。
在一些实施例中，半导体层22垂直于第一方向。例如，半导体层可以平行于第二方向，亦或是平行于第三方向。
在一些实施例中，结合图1、图3和图4所示，电容127包括位于漏接触区33处的内电极1271、介质层1272和外电极1273，内电极1271、介质层1272和外电极1273均围绕半导体层22的漏接触区33漏接触区，内电极1271、介质层1272和外电极1273沿远离半导体层22的方向依次分布。
具体的，在动态存储器10的制作过程中，在半导体层22的漏接触区33处依次生长出内电极1271、介质层1272和外电极1273，内电极1271、介质层1272和外电极1273均环绕半导体层22设置，且沿远离半导体层22的方向依次分布。外电极1273，内电极1271、介质层1272互相重叠，以形成电容127。通过使外电极1273、内电极1271、介质层1272环绕半导体层22设置，可以增大外电极1273与内电极1271互相交叠的面积，有利于提高电容127的容量。另外，介质层1272的厚度也不需要很薄(介质层1272厚度越小，电容127容量越大，为提高电容127的容量可以减小介质层1272的厚度)，因此有利于降低动态存储器10的制作难度。内电极1271以及外电极1273的材料包括氮化钛等具有良好导电性能的材料，介质层1272的材料选用具有高介电常数的材料，具体可根据实际情况进行确定。
在一些实施例中，相邻两层存储阵列12中存储单元120的电容127共用外电极1273。具体的，相邻两层存储阵列12中存储单元120的外电极1273相互接触、或部分一体成型。如图3所示，位于两层存储单元120之间的外电极1273既是位于上一层的存储单元120中电容127的外电极1273，也是位于下一层的存储单元120中电容127的外电极1273，因此简化了动态存储器10的结构，并且有利于降低动态存储器10在图3中第一方向上的厚度。另一方面，在动态存储器10的制作过程中，相邻两层存储单元120之间只需要制作一层外电极1273，由此简化了动态存储器10的制作工艺。
在一些实施例中，至少部分内电极1271形成漏极。
在一些实施例中，电容127包括内电极1271、介质层1272和外电极1273；介质层1272和外电极1273均围绕半导体层22的漏接触区33，介质层1272和外电极1273沿远离半导体层22的方向依次分布，半导体层22的至少部分漏接触区33形成电容127的内电极1271。
在一些实施例中，晶体管121还包括栅绝缘层126，栅极125和栅绝缘层126围绕半导体层22的沟道区，栅极125和栅绝缘层126沿远离半导体层22的方向依次分布。具体的，结合图1、图2、图3和图5所示，栅极125和栅绝缘层126围绕半导体层22，栅极125和栅绝缘层126沿远离半导体层22的方向依次分布。通过使栅绝缘层126和栅极125环绕半导体层22设置，可以增大栅极125与半导体层22交叠的面积，因此可以使对晶体管121开闭的控制更加容易。在一些实施例中，位于不同层的晶体管121的栅极125通过层间绝缘层128互相绝缘。
在一些实施例中，在同一层存储阵列12中，至少两个晶体管121共用位线124。具体的，在同一层存储阵列12中，至少两个存储单元120的晶体管121与相同的位线124连接。结合图1和图3所示，在同一层存储阵列12中，相邻的两个存储单元120中(图1中位于同一条直线上的晶体管121)的晶体管121共用位线124，因此在增加了存储单元120数量、提高存储密度的同时，也避免了占用过多的面积，有利于提高器件的 集成度。需要说明的是，同一层存储阵列12中，共用位线124的晶体管121的数量可根据实际情况进行调整，共用位线124的晶体管121的数量越多，越有利于减小动态存储器10的面积，提高动态存储器10的集成度。
在一些实施例中，与相同位线124连接的各晶体管121相对该位线124对称布置。例如，可以相对该位线124轴对称，或是相对该位线124旋转对称，等等。
基于同一发明构思，本公开实施例还提供了另一种动态存储器10，该动态存储器10包括：衬底11，支撑层24，多个存储阵列12，字线123和位线124。
支撑层24位于衬底11一侧，包括多个在第二方向和/或第三方向阵列排布的隔离墙、以及分别与两个相对的隔离墙连接的支撑柱。
多个存储阵列12在第一方向上间隔分布；存储阵列12包括多个在第二方向和第三方向阵列排布的存储单元120，至少两个存储单元120位于相同的支撑柱上。
字线123沿第二方向或第三方向延伸，分别与存储阵列12中的多个存储单元120电连接。
位线124沿第一方向延伸，分别与多个存储阵列12中的存储单元120电连接。
其中，第一方向垂直于衬底11，第二方向与第三方向相互垂直、且分别与第一方向垂直。
在本实施例中，支撑层24采用隔离墙与支撑柱的配合结构，可以实现动态存储器10中各存储单元120的三维空间布局，有利于提高存储单元120的密度。
在两个相对的隔离墙之间的相同的支撑柱上布设至少两个存储单元120，可以进一步提高平行于衬底的二维空间内存储单元120的密度。
动态存储器10中的位线124沿第一方向延伸，即位线124垂直于衬底方向垂直布设，有利于提高动态存储器10中各存储单元120的密度。
在一些实施例中，在同一层存储阵列12中，至少两个存储单元120与相同的位线124电连接。
在本实施例中，多个存储单元120共用一个位线124，不仅有利于提高存储单元120的密度，还有利于简化动态存储器的结构和制作工艺。
在一些实施例中，与相同的位线124电连接的至少两个存储单元120位于两个相对的隔离墙之间的相同的支撑柱上。这样有利于压缩共用一个位线124的各存储单元120之间布局空间，即进一步提高存储单元120的密度。
在一些实施例中，与相同的位线124电连接的至少两个存储单元120相对位线124对称布置。这样可以便于实现至少两个存储单元120与同一根位线124建立连接。
在一些实施例中，存储单元120包括：晶体管121和电容127。
晶体管121包括半导体层22、栅极125、源极和漏极；半导体层22包括依次连接的源接触区32、沟道区31和漏接触区33；栅极125与沟道区31对应，并与字线123电连接；源极分别与源接触区32、位线124电连接，漏极与漏接触区33连接。
电容127与漏极电连接。
在一些实施例中，支撑柱采用半导体材料制成，以形成晶体管121中的半导体层22。
在本实施例中，支撑柱采用半导体材料制成，即支撑柱的至少部分直接形成晶体管中的半导体层22，这样不仅可以缩小器件体积，以利于增大存储单元的密度，还能节约制备工序，减材降本。
在一些实施例中，半导体层22的源接触区32具有用于位线124穿过的通孔25，位线124的位于通孔25内的部分形成源极且与通孔25的侧壁接触。
在一些实施例中，电容127包括内电极1271、介质层1272和外电极1273；介质层1272和外电极1273均围绕半导体层22的漏接触区33，介质层1272和外电极1273沿远离半导体层22的方向依次分布，半导体层 22的至少部分漏接触区33形成电容127的内电极1271。
基于同一发明构思，本公开实施例还提供了一种存储装置，该存储装置包括上述实施例中的动态存储器10，具有上述实施例中任一种的动态存储器10的有益效果，在此不再赘述。具体地，本公开实施例中的存储装置可以为计算机的主存等，具体可根据实际情况进行确定，此处不作限定。
基于同一种发明构思，本公开实施例还提供了一种动态存储器10的制作方法，如图6所示，包括以下步骤S101-S105：
S101：提供衬底。
S102：在衬底的一侧制作层叠的多个半导体层；半导体层包括依次连接的源接触区、沟道区和漏接触区。
在一些实施例中，步骤S102中的在衬底的一侧制作层叠的多个半导体层，包括：
通过外延生长工艺在衬底的一侧层叠地制作多层超晶格薄膜层，每一层超晶格薄膜层包括依次层叠设置的牺牲层和半导体层。
对多层超晶格薄膜层进行刻蚀，得到露出部分衬底的基桩孔；在基桩孔中，位于牺牲层的部分的直径大于位于半导体层的部分的直径。
通过沉积工艺在基桩孔内填充支撑材料，以形成支撑层。由于前述工艺制得的基桩孔中，位于牺牲层的部分的直径大于位于半导体层的部分的直径，因此本步骤制备得到的支撑层能够向相邻两层半导体层之间的空间进行延伸，以待牺牲层被去除后，能够对相邻两层半导体层提供支撑。
去除牺牲层，使得多个半导体层依次层叠且相互间隔。
S103：制作栅极和字线，使得栅极与沟道区对应、字线与栅极电连接。
在一些实施例中，步骤S103中的制作栅极和字线，包括：制作环绕半导体层中沟道区的栅绝缘层；制作环绕栅绝缘层的栅极。
S104：制作漏极和电容，使得漏极与漏接触区连接、电容与漏极电连接。
在一些实施例中，步骤S104中的制作漏极和电容，包括：
制作环绕半导体层中漏接触区的内电极，至少部分内电极形成漏极。
制作环绕内电极的介质层。
制作环绕介质层的外电极，使得包括内电极、介质层和外电极的整体形成电容。
S105：制作源极和位线，使得源极与源接触区连接、位线与源极电连接，至少一根位线分别与层叠的多个半导体层的源接触区所连接的源极电连接。其中，包括半导体层、栅极、源极和漏极的整体形成晶体管。
在一些实施例中，步骤S105中的制作源极和位线，包括：
对层叠的多个半导体层中源接触区进行刻蚀，得到贯穿半导体层两侧的通孔。
制作贯穿多个通孔的位线，位线的位于通孔内的部分形成源极。
经过以上步骤S101-S105制备得到的动态存储器10，包括衬底11和层叠的设置在衬底11上的多个存储阵列12，存储阵列12包括多个阵列排布的存储单元120，存储单元120包括晶体管121和电容127。动态存储器10还包括字线123和位线124，字线123位于晶体管121的栅极125处并与晶体管121电连接，位线124贯穿多个存储单元120中晶体管121的半导体层22，位线124位于源接触区32处，多个存储单元120中的晶体管121通过位线124电连接。通过将包括多个存储单元120的存储阵列12层叠设置，形成了具有立体结构的动态存储器10，在提高了动态存储器10存储容量的同时，避免了将存储单元120设置在同一个平面上时造成动态存储器10的面积过大，使得存储单元120的结构布局更加紧凑，在提高了存储密度的同时更加有利于器件的集成。
需要说明的是，在动态存储器10的制作过程中，可通过修饰刻蚀工艺对字线123进行刻蚀，使位于不同层的字线123的程度不一致，即使不同层的字线123呈阶梯状。结合图1和图2所示，沿图2中第一方向上，字线123在图2中第二方向(逐渐远离衬底1111)上的长度逐渐减小，因此可以方便地使位于不同层的字线123通过走线与读写电路(图1和图 2中未示出)。
下面结合附图详细介绍本公开实施例中动态存储器10的制作方法。
如图7a所示，首先，提供一衬底11，衬底11的材料包括硅。图7a-1是沿第一方向的截面图，图7a-2是俯视图。
如图7b所示，接着，通过外延生长工艺在衬底11的一侧层叠地制作多层超晶格薄膜20，每一层超晶格薄膜20包括沿图7b中第一方向分布的牺牲层21和半导体层22，牺牲层21的材料包括硅锗(SiGe)，半导体层22的材料包括单晶硅，半导体层22包括源接触区32、漏接触区33以及设置在源接触区32和漏接触区33之间的沟道区31。超晶格薄膜20的层数可根据实际情况进行确定，例如，可以是8层、16层或者32层。需要说明的是，如图7b中仅示出了三层牺牲层21作为示意，并不代表对本方案的限定。图7b-1是沿第一方向的截面图，图7b-2是俯视图。
如图7c所示，接着，对多层牺牲层21和半导体层22进行刻蚀，去除部分牺牲层21和半导体层22的材料，以使半导体层22形成间隔设置的结构。半导体层22的数量以及半导体层22之间的距离d可根据实际情况进行调整。图7c-1是沿第一方向的截面图，图7c-2是俯视图。
如图7d所示，接着，对牺牲层21位于半导体层22两端的部分进行刻蚀，以形成沟槽23。沟槽23在图7d中第三方向上的宽度w可根据实际情况进行调整。图7d-1是沿第一方向的截面图，图7d-2是俯视图。
如图7e所示，接着，通过原子沉积工艺或者化学气相沉积工艺沉积支撑层24(支撑层24位于半导体层22的两端)，并使支撑层24填充沟槽23。支撑层24的材料包括氮化硅和氧化硅等具有良好绝缘性能的材料，具体可根据实际情况进行确定。需要说明的是，制作沟槽23以及支撑层24的目的是为了后续去除牺牲层21后，支撑层24能够对多层半导体层22进行支撑，防止结构坍塌。支撑层24的材料包括氧化物和氮化物等(例如氧化硅和氮化硅)，具体可根据实际情况进行调整。图7e-1是沿第一方向的截面图，图7e-2是俯视图。
如图7f所示，接着，通过调整牺牲层21和半导体层22的蚀刻选择 比(使牺牲层21被蚀刻的速率大于半导体层22被蚀刻的速率)，将半导体层22之间的牺牲层21刻蚀并去除，留下的半导体层22作为多个半导体层22。半导体层22两端的支撑层24可以对半导体层22起到支撑作用。图7f-1是沿第一方向的截面图，图7f-2是俯视图。
如图7g所示，接着，在半导体层22上依次生长出围绕半导体层22的栅绝缘层126、栅极125和层间绝缘层128，在位于同层的栅极125之间继续生长导电材料，以形成连接字线123。通过修饰刻蚀工艺对字线123进行刻蚀，使位于不同层的字线123的长度不一致，即使不同层的字线123呈阶梯状。图7g-1是沿第一方向的截面图，图7g-2是俯视图。
如图7h所示，接着，在半导体层22上待制作电容127的区域(即半导体层22的漏接触区33处)依次生长环绕半导体层22的内电极1271、介质层1272和外电极1273，内电极1271、介质层1272和外电极1273构成电容127。位于两层半导体层22之间的外电极1273既是位于上一层的半导体层22所对应的电容127的外电极1273，也是位于下一层的半导体层22所对应的电容127的外电极1273，由此简化了动态存储器的结构，也简化动态存储器的制作工艺。内电极1271和外电极1273的材料包括氮化钛，具体可根据实际情况进行确定。图7h-1是沿第一方向的截面图，图7h-2是俯视图。
如图7i所示，接着，通过刻蚀工艺在半导体层22的源接触区32处开设通孔25，并使多层半导体层22的通孔25基本对齐。图7i-1是沿第一方向的截面图，图7i-2是俯视图。
如图7j所示，接着，在通孔25中填充金属材料，以形成位线124。位于不同层的晶体管121的源接触区32通过位线124电连接。需要说明的是，字线123和位线124之间的空白区域还可以填充具有良好绝缘性能的隔离材料(图7j中未示出)，避免动态存储器10的结构中出现空隙。图7j-1是沿第一方向的截面图，图7j-2是俯视图。
采用本公开实施例中的制作方法，制作层叠结构的动态存储器10在工艺上较为容易，使得层叠结构动态存储器10的大规模量产成为可能。
应用本公开实施例，至少能够实现如下有益效果：
1.在本公开的实施例中，动态存储器10包括衬底11和层叠的设置在衬底11上的多个存储阵列12，存储阵列12包括多个阵列排布的存储单元120，存储单元120包括晶体管121和电容127。动态存储器10还包括字线123和位线124，字线123位于晶体管121的栅极125处并与晶体管121电连接，位线124贯穿多个存储单元120中晶体管121的半导体层22，位线124位于源接触区32处，多个存储单元120中的晶体管121通过位线124电连接。通过将包括多个存储单元120的存储阵列12层叠设置，形成了具有立体结构的动态存储器10，在提高了动态存储器10存储容量的同时，避免了将存储单元120设置在同一个平面上时造成动态存储器10的面积过大，使得存储单元120的结构布局更加紧凑，在提高了存储密度的同时更加有利于器件的集成。另一方面，通过使位线贯穿多个存储单元中晶体管的半导体层22，多个层叠设置的晶体管通过一个位线即可实现电连接，由此简化了动态存储器的结构和制作工艺。
2.在本公开的实施例中，电容127包括位于漏接触区33处的内电极1271、介质层1272和外电极1273，内电极1271、介质层1272和外电极1273均围绕半导体层22的漏接触区33，内电极1271、介质层1272和外电极1273沿远半导体层22的方向依次分布。通过使外电极1273、内电极1271、介质层1272环绕半导体层22设置，可以增大外电极1273与内电极1271的面积，有利于提高电容127的容量。
3.在本公开的实施例中，相邻两层存储阵列12中存储单元120的电容127共用外电极1273，即位于两层存储单元120之间的外电极1273既是位于上一层的存储单元120中电容127的外电极1273，也是位于下一层的存储单元120中电容127的外电极1273，因此可以简化动态存储器10的结构和制作工艺。
4.在本公开的实施例中，在同一层存储阵列12中，至少两个晶体管121共用位线124，因此在增加了存储单元120数量、提高存储密度的同 时，也避免了占用过多的面积，有利于提高器件的集成度。
在本公开的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述仅是本公开的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (23)

  1. 一种动态存储器，其中，包括衬底和层叠的设置在所述衬底上的多个存储阵列，多个存储阵列在第一方向上间隔分布，所述存储阵列包括多个在第二方向和第三方向阵列排布的存储单元，所述第一方向垂直于所述衬底，所述第二方向与所述第三方向相互垂直、且分别与所述第一方向垂直，所述存储单元包括：
    晶体管，包括半导体层、栅极、源极和漏极；所述半导体层包括依次连接的源接触区、沟道区和漏接触区；所述栅极与所述沟道区对应，所述源极与所述源接触区连接，所述漏极与所述漏接触区连接；
    电容，与所述漏极电连接；
    字线，沿着所述第二方向延伸与所述栅极电连接；
    所述动态存储器还包括位线，沿着第一方向延伸，所述位线与所述晶体管的所述源极电连接，所述位线同时与所述第一方向上分布的各所述存储单元中晶体管的源极电连接。
  2. 根据权利要求1所述的动态存储器，其中，所述源极与所述位线由相同的材料形成在同一条线上；和/或，所述漏极与所述电容由相同的材料形成在同一条线上。
  3. 根据权利要求1所述的动态存储器，其中，所述半导体层的源接触区具有用于所述位线穿过的通孔，所述位线的位于所述通孔内的部分形成所述源极且与所述通孔的侧壁接触。
  4. 根据权利要求1所述的动态存储器，其中，所述半导体层垂直于所述第一方向。
  5. 根据权利要求4所述的动态存储器，其中，所述电容包括内电极、 介质层和外电极，所述内电极、所述介质层和所述外电极均围绕所述半导体层的漏接触区，所述内电极、所述介质层和所述外电极沿远离所述半导体层的方向依次分布。
  6. 根据权利要求5所述的动态存储器，其中，相邻两层所述存储阵列中所述存储单元的所述外电极相互接触、或部分一体成型；
    和/或，至少部分所述内电极形成所述漏极。
  7. 根据权利要求4所述的动态存储器，其中，所述电容包括内电极、介质层和外电极；所述介质层和所述外电极均围绕所述半导体层的漏接触区，所述介质层和所述外电极沿远离所述半导体层的方向依次分布，所述半导体层的至少部分漏接触区形成所述电容的所述内电极。
  8. 根据权利要求1所述的动态存储器，其中，在同一层存储阵列中，至少两个所述存储单元的所述晶体管与相同的所述位线连接。
  9. 根据权利要求8所述的动态存储器，其中，与相同所述位线连接的各所述晶体管相对所述位线对称布置。
  10. 根据权利要求1至9中任一项所述的动态存储器，其中，所述半导体层的材料包括外延单晶硅；
    和/或，所述位线的材料包括钨。
  11. 一种动态存储器，其中，包括：
    衬底；
    支撑层，位于所述衬底一侧，包括多个在第二方向和/或第三方向阵列排布的隔离墙、以及分别与两个相对的所述隔离墙连接的支撑柱；
    多个存储阵列，在第一方向上间隔分布；所述存储阵列包括多个在第 二方向和第三方向阵列排布的存储单元，至少两个所述存储单元位于相同的所述支撑柱上；
    字线，沿所述第二方向或所述第三方向延伸，分别与所述存储阵列中的多个所述存储单元电连接；
    位线，沿所述第一方向延伸，分别与多个所述存储阵列中的所述存储单元电连接；
    其中，所述第一方向垂直于所述衬底，所述第二方向与所述第三方向相互垂直、且分别与所述第一方向垂直。
  12. 根据权利要求11所述的动态存储器，其中，在同一层所述存储阵列中，至少两个所述存储单元与相同的所述位线电连接。
  13. 根据权利要求12所述的动态存储器，其中，与相同的所述位线电连接的至少两个所述存储单元位于两个相对的所述隔离墙之间的相同的所述支撑柱上；
    和/或，与相同的所述位线电连接的至少两个所述存储单元相对所述位线对称布置。
  14. 根据权利要求11所述的动态存储器，其中，所述存储单元包括：
    晶体管，包括半导体层、栅极、源极和漏极；所述半导体层包括依次连接的源接触区、沟道区和漏接触区；所述栅极与所述沟道区对应，并与所述字线电连接；所述源极分别与所述源接触区、所述位线电连接，所述漏极与所述漏接触区连接；
    电容，与所述漏极电连接。
  15. 根据权利要求14所述的动态存储器，其中，所述支撑柱采用半导体材料制成，以形成所述晶体管中的半导体层。
  16. 根据权利要求15所述的动态存储器，其中，所述半导体层的源接触区具有用于所述位线穿过的通孔，所述位线的位于所述通孔内的部分形成所述源极且与所述通孔的侧壁接触。
  17. 根据权利要求15所述的动态存储器，其中，所述电容包括内电极、介质层和外电极；所述介质层和所述外电极均围绕所述半导体层的漏接触区，所述介质层和所述外电极沿远离所述半导体层的方向依次分布，所述半导体层的至少部分漏接触区形成所述电容的所述内电极。
  18. 一种存储装置，其中，包括权利要求1至10中任一项所述的动态存储器；或，包括权利要求11至17中任一项所述的动态存储器。
  19. 一种动态存储器的制作方法，其中，包括：
    提供衬底；
    在所述衬底的一侧制作层叠的多个半导体层；所述半导体层包括依次连接的源接触区、沟道区和漏接触区；
    制作栅极和字线，使得所述栅极与所述沟道区对应、所述字线与所述栅极电连接；
    制作漏极和电容，使得所述漏极与所述漏接触区连接、所述电容与所述漏极电连接；
    制作源极和位线，使得所述源极与所述源接触区连接、所述位线与所述源极电连接，至少一根所述位线分别与层叠的多个所述半导体层的源接触区所连接的所述源极电连接；
    其中，包括所述半导体层、所述栅极、所述源极和所述漏极的整体形成晶体管。
  20. 根据权利要求19所述的制作方法，其中，所述在所述衬底的一侧制作层叠的多个半导体层，包括：
    通过外延生长工艺在衬底的一侧层叠地制作多层超晶格薄膜层，每一层超晶格薄膜层包括依次层叠设置的牺牲层和半导体层；
    对所述多层超晶格薄膜层进行刻蚀，得到露出部分衬底的基桩孔；在所述基桩孔中，位于所述牺牲层的部分的直径大于位于所述半导体层的部分的直径；
    通过沉积工艺在所述基桩孔内填充支撑材料，以形成支撑层；
    去除所述牺牲层，使得所述多个半导体层依次层叠且相互间隔。
  21. 根据权利要求20所述的制作方法，其中，所述制作栅极和字线，包括：
    制作环绕所述半导体层中所述沟道区的栅绝缘层；
    制作环绕所述栅绝缘层的栅极。
  22. 根据权利要求20所述的制作方法，其中，所述制作漏极和电容，包括：
    制作环绕所述半导体层中所述漏接触区的内电极，至少部分所述内电极形成所述漏极；
    制作环绕所述内电极的介质层；
    制作环绕所述介质层的外电极，使得包括所述内电极、所述介质层和所述外电极的整体形成所述电容。
  23. 根据权利要求20所述的制作方法，其中，所述制作源极和位线，包括：
    对层叠的多个半导体层中所述源接触区进行刻蚀，得到贯穿所述半导体层两侧的通孔；
    制作贯穿多个所述通孔的位线，所述位线的位于所述通孔内的部分形成所述源极。
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