WO2024045328A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024045328A1
WO2024045328A1 PCT/CN2022/129920 CN2022129920W WO2024045328A1 WO 2024045328 A1 WO2024045328 A1 WO 2024045328A1 CN 2022129920 W CN2022129920 W CN 2022129920W WO 2024045328 A1 WO2024045328 A1 WO 2024045328A1
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Prior art keywords
layer
along
gate
trench
forming
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PCT/CN2022/129920
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English (en)
French (fr)
Inventor
冯道欢
李晓杰
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长鑫存储技术有限公司
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Priority to US18/449,771 priority Critical patent/US20240081041A1/en
Publication of WO2024045328A1 publication Critical patent/WO2024045328A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • semiconductor structures such as DRAM with three-dimensional structures have emerged.
  • semiconductor structures such as DRAM with three-dimensional structure still have problems such as poor gate control ability and high power consumption of transistors, which limits the further improvement of the performance of semiconductor structures.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to improve the gate control capability of the semiconductor structure and reduce the power consumption of the semiconductor structure, thereby improving the performance of the semiconductor structure.
  • the present disclosure provides a semiconductor structure including:
  • the stacked structure including a plurality of memory cells spaced apart along the first direction, the memory cells including a transistor structure, the transistor structure including an active structure and a gate layer , at least part of the active structure is distributed around part of the periphery of the gate layer, and the shape of the projection of the active structure on the top surface of the substrate is a U-shape opening toward the second direction, wherein, The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction.
  • the gate layer includes:
  • a first gate layer, part of the active structure is distributed around the periphery of the first gate layer
  • a second gate layer is distributed around at least part of the periphery of the active structure, and the first gate layer is electrically connected to the second gate layer.
  • it also includes:
  • a word line extends along the first direction and is electrically connected to the first gate layer and the second gate layer in a plurality of memory cells spaced apart along the first direction.
  • the word line is located at an end of the memory cell along the second direction and is connected to an end of the first gate layer along the second direction and the second gate. The end contacts of the layer along the second direction are electrically connected.
  • the active structure includes:
  • a channel layer extends along the first direction, the channel layer is distributed around the periphery of the first gate layer, and the second gate layer is distributed around the periphery of the channel layer;
  • the drain region is protruding along the second direction on the side of the channel layer away from the word line, and the source region and the drain region are spaced apart from the channel layer along the first opposite ends of the direction.
  • the transistor structure further includes:
  • a first gate dielectric layer located between the first gate layer and the channel layer
  • a second gate dielectric layer is located between the second gate electrode layer and the channel layer, and the thickness of the first gate dielectric layer along the third direction is less than or equal to the thickness of the second gate dielectric layer along the third direction. a thickness in a third direction, wherein the third direction is perpendicular to the top surface of the substrate;
  • a first insulating dielectric layer is located between the word line and the channel layer.
  • the thickness of the first gate layer along the third direction is greater than or equal to the thickness of the second gate layer along the third direction, wherein the third direction is in contact with the substrate.
  • the top surface is vertical.
  • the storage unit further includes:
  • a capacitor structure extending along the second direction, including a lower electrode layer electrically connected to the drain region of the transistor structure, a dielectric layer covering the lower electrode layer, and an upper electrode covering the dielectric layer layer.
  • the stacked structure includes a plurality of storage layers spaced apart along a third direction, and each storage layer includes a plurality of storage units spaced apart along the first direction, wherein, The third direction is perpendicular to the top surface of the substrate; the semiconductor structure further includes:
  • a bit line extends along the third direction and is electrically connected to the source regions in a plurality of memory cells spaced apart along the third direction.
  • it also includes:
  • a first support pillar extends along the third direction, and the first support pillar is located between the capacitor structure and the bit line;
  • a second support column extending along the third direction, and the second support column is located between the storage units adjacent along the first direction;
  • An interlayer insulating layer is located between adjacent storage layers arranged at intervals along the third direction.
  • the material of the active structure is an oxide semiconductor.
  • the present disclosure also provides a method for forming a semiconductor structure, including the following steps:
  • the stacked layer including a plurality of storage areas spaced apart along a first direction, wherein the first direction is parallel to the top surface of the substrate;
  • a memory cell including a transistor structure is formed in the storage area, the transistor structure includes an active structure and a gate layer, at least a portion of the active structure is distributed around a portion of the periphery of the gate layer, and the active structure
  • the shape of the projection on the top surface of the substrate is a U-shape opening toward the second direction, wherein both the first direction and the second direction are parallel to the top surface of the substrate, and the The first direction intersects the second direction.
  • forming a stacked layer on the substrate includes:
  • Interlayer insulating layers and stacked unit layers alternately stacked along a third direction are formed on the substrate.
  • the stacked unit layer includes a first isolation layer, a sacrificial layer, and a second isolation layer sequentially stacked along the third direction. layer, wherein the third direction is perpendicular to the top surface of the substrate.
  • a memory cell including a transistor structure in the storage area before forming a memory cell including a transistor structure in the storage area, the following steps are further included:
  • a first support column is formed in the first support groove, and a second support column is formed in the second support groove.
  • the storage area includes a transistor area and a capacitance area located outside the transistor area along the second direction; the step of forming a memory cell including a transistor structure in the storage area includes:
  • a first gate layer is formed in the first trench, and the channel layer is distributed around the periphery of the first gate layer.
  • the gate layer includes the first gate layer, and the The active structure includes the channel layer.
  • the following steps are also included:
  • the specific steps of forming a second gate layer covering the sacrificial layer in the second trench and the third trench include:
  • the second gate layer covering the second gate dielectric layer is formed in the second trench and the third trench.
  • the specific steps of forming a first gate layer in the first trench and the channel layer distributed around the periphery of the first gate layer include:
  • the first gate layer is formed on the channel layer in the first trench, and the thickness of the first gate layer along the third direction is greater than or equal to the second gate layer. The thickness of the layer along said third direction.
  • forming the first gate layer on the channel layer in the first trench includes:
  • a first gate dielectric layer covering the channel layer is formed in the first trench, and the thickness of the first gate dielectric layer along the third direction is less than or equal to the thickness of the second gate dielectric layer along the third direction. The thickness in the third direction;
  • the first gate layer covering the first gate dielectric layer is formed in the first trench.
  • the following steps are further included:
  • a word line extending along the first direction is formed on the substrate, and the word line is connected to the first gate layer and the plurality of memory cells spaced apart along the first direction.
  • the second gate layer is electrically connected.
  • forming a word line extending along the first direction on the substrate includes:
  • a word line extending along the first direction is formed on an end of the transistor structure along the second direction, and the end of the word line and the first gate layer along the second direction and the The end portions of the second gate layer along the second direction are electrically connected.
  • the storage area further includes a capacitance area and a bit line area located on the same side of the transistor area along the second direction, and the capacitance area and the bit line area are along the first direction.
  • Spaced arrangement after forming word lines extending along the first direction on the substrate, the following steps are also included:
  • a bit line electrically connected to the source region is formed in the fifth trench.
  • the following steps are further included:
  • a capacitor structure electrically connected to the drain region is formed in the capacitor trench.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • a transistor structure with a fully surrounding channel is formed.
  • some active structures in the transistor structure are The source structure is arranged in a U-shape opening in a direction parallel to the top surface of the substrate (for example, the second direction), thereby improving the gate control capability of the transistor structure while reducing the power consumption of the semiconductor structure, thereby achieving electrical control of the semiconductor structure.
  • some embodiments of the present disclosure form the channel layer by removing the sacrificial layer in the stacked layer when forming the semiconductor structure. Therefore, there is no need to form the channel layer through complex epitaxial growth processes and doping processes, simplifying the development of the semiconductor structure. process technology, and helps to increase the stacking height of the stacked structure in the semiconductor structure and improve the manufacturing yield of the semiconductor structure.
  • FIG. 1 is a schematic top view of a semiconductor structure in an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional view of Figure 1 at position a-a;
  • Figure 3 is a schematic cross-sectional view of Figure 1 at position b-b;
  • Figure 4 is a schematic cross-sectional view of Figure 1 at the c-c position
  • Figure 5 is a schematic cross-sectional view of Figure 1 at the d-d position
  • Figure 6 is a schematic three-dimensional structural diagram of a memory unit in an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure.
  • FIGS. 8 to 22 are schematic diagrams of the main process structures in the process of forming semiconductor structures according to embodiments of the present disclosure.
  • Figure 1 is a schematic top view of the semiconductor structure in the embodiment of the present disclosure.
  • Figure 2 is a schematic cross-sectional view of Figure 1 at position a-a.
  • Figure 3 is a schematic view of Figure 1 at position b-b.
  • Figure 4 is a schematic cross-sectional view of Figure 1 at position c-c.
  • Figure 5 is a schematic cross-sectional view of Figure 1 at position d-d.
  • Figure 6 is a schematic three-dimensional structural view of a memory unit in an embodiment of the present disclosure.
  • the semiconductor structure includes:
  • the stacked structure is located on the substrate 31.
  • the stacked structure includes a plurality of memory units MU arranged at intervals along the first direction D1.
  • the memory unit MU includes a transistor structure.
  • the transistor structure includes an active structure and a gate layer, at least part of the active structure. It is distributed around the periphery of part of the gate layer, and the shape of the projection of the active structure on the top surface of the substrate 31 is a U-shape opening toward the second direction D2, wherein the first direction D1 and the second direction D2 are both in contact with the substrate.
  • the top surface of the bottom 31 is parallel, and the first direction D1 and the second direction D2 intersect.
  • the semiconductor structure may be, but is not limited to, a DRAM.
  • the embodiment of the present disclosure takes the semiconductor structure as a DRAM as an example for description.
  • the substrate 31 may be, but is not limited to, a silicon substrate.
  • the embodiment of the present disclosure takes the substrate 31 as a silicon substrate as an example for description.
  • the substrate 31 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • Substrate 31 serves to support device structures thereon.
  • a plurality of memory cells are arranged at intervals along the first direction D1 on the top surface of the substrate 31 .
  • the shape of the projection of the active structure on the top surface of the substrate 31 is a U-shape opening toward the second direction D2 means that the shape of the contour of the projection of the active structure on the top surface of the substrate 31 is a U-shape, And the U-shaped opening faces the second direction.
  • the active structure includes a channel layer, and a source region and a drain region located on the same side of the channel layer.
  • Embodiments of the present disclosure provide a U-shaped active structure and at the same time distribute the active structure around the periphery of the gate layer to form a transistor structure including a channel full surrounding structure, thereby improving the gate control capability of the transistor structure while reducing the cost.
  • the power consumption of the semiconductor structure can improve the electrical performance of the semiconductor structure.
  • the top surface of the substrate 31 refers to the surface of the substrate 31 facing the stacked structure.
  • “multiple” refers to two or more.
  • the first direction D1 and the second direction D2 may intersect perpendicularly or obliquely.
  • the embodiment of the present disclosure takes the first direction D1 and the second direction D2 to intersect perpendicularly as an example for description.
  • the gate layer includes:
  • the first gate layer 21 has some active structures distributed around the periphery of the first gate layer 21;
  • the second gate layer 22 is distributed around at least part of the periphery of the active structure, and the first gate layer 21 is electrically connected to the second gate layer 22 .
  • the gate layer includes a first gate layer 21 and a second gate layer 22 that are electrically connected to each other.
  • Part of the active structure, including the channel layer 20 is distributed around the periphery of the first gate layer 21 to form a trench.
  • the second gate layer 22 is distributed around the periphery of part of the active structure to form a gate full surround structure, as shown in (b) of FIG. 6 , so that the transistor structure in the embodiment of the present disclosure also has a gate structure.
  • the extremely full surround structure and the channel full surround structure further improve the gate control capability of the transistor structure, simplify the control operation of the memory unit, and further improve the electrical performance of the semiconductor structure.
  • (b) in FIG. 6 shows a schematic cross-sectional view of (a) in FIG. 6 at the position of the dotted arrow.
  • the semiconductor structure further includes:
  • the word line 10 extends along the first direction D1 and is electrically connected to the first gate layer 21 and the second gate layer 22 in the plurality of memory units MU arranged at intervals along the first direction D1.
  • the word line 10 extends along the first direction D1, that is, the semiconductor structure has a horizontal word line structure.
  • the first gate layer 21 and the second gate layer 22 located in the same memory unit MU are electrically connected through the word line 10, and the word line 10 is electrically connected to the first gate layer 21 and the second gate layer 22 in a plurality of memory units MU spaced apart along the first direction D1.
  • a gate layer 21 and a second gate layer 22 are used to simultaneously transmit control signals to the first gate layer 21 and the second gate layer 22 in the plurality of memory units MU through the word line 10 .
  • the word line 10 is located in the memory unit MU along the second direction D2 and is electrically connected to the end of the first gate layer 21 along the second direction D2 and the end of the second gate layer 22 along the second direction D2.
  • the word line 10 is located at the end of the memory unit MU along the second direction D2, and the thickness of the word line 10 along the third direction D3 is greater than or equal to the thickness of the transistor structure along the third direction D3.
  • the thickness in the direction D3 enables the word line 10 to fully contact and electrically connect with the first gate layer 21 and the second gate layer 22 in the transistor structure, thereby improving the connection between the word line 10 and the first gate layer 21 and the second gate layer.
  • the connection stability between layers 22 is further improved to further improve the yield of the semiconductor structure.
  • the top surface of the word line 10 along the third direction D3 is located above the top surface of the second gate layer 22
  • the bottom surface of the word line 10 along the third direction D3 is located above the top surface of the second gate layer 22 .
  • the word line 10 protrudes from the second gate layer 22 along the third direction D3 , where the third direction D3 is perpendicular to the top surface of the substrate 31 .
  • the gate layers in the plurality of memory units MU spaced apart along the first direction D1 are independent of each other to simplify the manufacturing process of the gate layers.
  • the second gate layers 22 in the plurality of memory units MU spaced apart along the first direction D1 are connected (for example, through a selective deposition process), thereby simplifying the formation process of the word line 10 .
  • active structures include:
  • the channel layer 20 extends along the first direction D1, the channel layer 20 is distributed around the periphery of the first gate layer 21, and the second gate layer 22 is distributed around the periphery of the channel layer 20;
  • the source region 11 is protruding along the second direction D2 on the side of the channel layer 20 away from the word line 10;
  • the drain region 12 is protruding along the second direction D2 on the side of the channel layer 20 away from the word line 10 .
  • the source region 11 and the drain region 12 are spaced apart from each other on the side of the channel layer 20 away from the word line 10 along the first edge. Opposite ends of direction D1.
  • the active structure includes a channel layer 20 and a source region 11 and a drain region 12 located on the same side of the channel layer 20 along the second direction D2, and the source region 11 and the drain region 12 are both located on the same side of the channel layer 20 along the second direction D2.
  • the channel layer 20 is connected and spaced at the opposite ends of the channel layer 20 along the first direction D1, so that the channel layer 20, the source region 11 and the drain region 12 form a whole body on the top of the substrate 31.
  • the shape of the projection on the surface is a U shape with the opening facing the second direction D2.
  • the source region 11 and the drain region 12 are aligned and arranged along the first direction D1.
  • a first axis in the source region 11 and a second axis in the drain region 12 are aligned along the first direction D1 , wherein the first axis passes through the center of the source region 11 and along the first direction D1 Extending, the second axis passes through the center of the drain region 12 and extends along the first direction D1.
  • the transistor structure further includes:
  • the first gate dielectric layer 24 is located between the first gate layer 21 and the channel layer 20;
  • the second gate dielectric layer 23 is located between the second gate layer 22 and the channel layer 20 , and the thickness of the first gate dielectric layer 24 along the third direction D3 is less than or equal to the thickness of the second gate dielectric layer 23 along the third direction D3 thickness, wherein the third direction D3 is perpendicular to the top surface of the substrate 31;
  • the first insulating dielectric layer is located between the word line 10 and the channel layer 20 .
  • the thickness of the first gate dielectric layer 24 along the third direction D3 refers to the distance between the inner surface of the first gate dielectric layer 24 facing the first gate electrode layer 21 and the outer surface of the first gate dielectric layer 24 away from the first gate electrode layer 21 .
  • the thickness of the second gate dielectric layer 23 along the third direction D3 refers to the thickness of the inner surface of the second gate dielectric layer 23 facing the channel layer 20 and the outer surface of the second gate dielectric layer 23 away from the channel layer 20 along the third direction. distance on D3.
  • the thickness of the first gate dielectric layer 24 along the third direction D1 is set to be less than or equal to the thickness of the second gate dielectric layer 23 along the third direction D3.
  • the thickness of the first gate dielectric layer 24 is reduced. , can prevent the channel layer 20 from being too large, thereby improving the channel performance of the transistor structure; on the other hand, increasing the thickness of the second gate dielectric layer 23 can increase the thickness of the first gate layer 21 and the second gate The distance between the layers 22 thereby reduces the mutual influence between the first gate layer 21 and the second gate layer 22 .
  • the material of the first gate dielectric layer 24 and the second gate dielectric layer 23 are the same, for example, both are oxide materials (such as silicon dioxide).
  • the thickness of the first gate layer 21 along the third direction D3 is greater than or equal to the second gate layer 22
  • the thickness of the second gate layer 22 along the third direction D3 refers to the distance along the third direction between the inner surface of the second gate layer 22 facing the channel layer 20 and the outer surface away from the channel layer 20 .
  • the memory unit MU further includes:
  • the capacitor structure 14 extends along the second direction D2 and includes a lower electrode layer 28 electrically connected to the drain region 12 of the transistor structure, a dielectric layer 29 covering the lower electrode layer 28, and an upper electrode layer 30 covering the dielectric layer 29.
  • the material of the lower electrode layer 28 can be the same as the material of the upper electrode layer 30 , for example, both are conductive materials such as TiN or metal tungsten, and the material of the dielectric layer 29 is a material with a higher dielectric constant (high K).
  • the memory unit MU also includes a capacitor isolation layer 32 covering the capacitor structure 14. The capacitor isolation layer 32 is used to isolate adjacent capacitor structures 14 and avoid signal crosstalk between adjacent capacitor structures 14.
  • the stacked structure includes a plurality of storage layers spaced apart along the third direction D3, and each storage layer includes a plurality of memory units MU spaced apart along the first direction D1, wherein the third direction D3 and The top surface of substrate 31 is vertical; the semiconductor structure also includes:
  • the bit line 13 extends along the third direction D3 and is electrically connected to the source regions 11 in a plurality of memory cells MU arranged at intervals along the third direction D3.
  • the stacked structure includes memory units MU alternately stacked along the third direction D3 and an interlayer insulating layer 27.
  • the interlayer insulating layer 27 is used to electrically isolate two adjacent memory units MU along the third direction D3.
  • the material of the interlayer insulating layer 27 may be a nitride material (eg, silicon nitride).
  • the bit line 13 extends along the third direction D3, and the bit line 13 is continuously in contact and electrically connected with the source regions 11 in a plurality of memory cells MU spaced apart along the third direction D3.
  • the plurality of bit lines 13 are arranged at intervals along the first direction D1. For example, as shown in FIG.
  • adjacent bit lines along the first direction D1 include a plurality of capacitor structures 14 spaced apart along the third direction D3.
  • the number of word lines 10 is multiple, and the plurality of word lines 10 are spaced apart along the third direction D3.
  • the length of the one word line 10 closer to the substrate 31 along the first direction D1 is greater than the length of the other word line 10 along the first direction D1 (that is, closer to the substrate 31 ).
  • One word line 10 of the substrate 31 protrudes from another word line 10 along the first direction D1, so that the plurality of word lines 10 together form a step-like structure.
  • the semiconductor structure further includes a covering layer 26 located on the side of the stacked structure and covering the sidewalls of the plurality of word lines 10 spaced apart along the third direction D3.
  • the material of the covering layer 26 may be an oxide material (such as silicon dioxide).
  • the semiconductor structure further includes:
  • the first support pillar 50 extends along the third direction D3, and the first support pillar 50 is located between the capacitor structure 14 and the bit line 13;
  • the second support column 40 extends along the third direction D3, and the second support column 40 is located between the adjacent memory units MU along the first direction D1;
  • the interlayer insulating layer 27 is located between adjacent storage layers arranged at intervals along the third direction D3.
  • first support column 50 and the second support column 40 are used to support the stacked structure, prevent the stacked structure from tipping or collapsing, and improve the stability of the stacked structure.
  • the material of the first support pillar 50 and the second support pillar 40 may be the same, for example, both are nitride materials (eg, silicon nitride).
  • the material of the active structure is an oxide semiconductor material.
  • the oxide semiconductor material is In 2 O 3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), Any one or a combination of two or more ZnON (zinc oxynitride).
  • the material of the active structure is IGZO.
  • Embodiments of the present disclosure also provide a method for forming a semiconductor structure.
  • FIG. 7 is a flow chart of a method for forming a semiconductor structure in an embodiment of the disclosure.
  • FIGS. 8 to 22 illustrate the process of forming a semiconductor structure according to embodiments of the present disclosure.
  • the main process structure schematic diagram wherein, Figure 8 is a top structural schematic diagram of the semiconductor structure formed by the embodiment of the present disclosure, Figures 9-22 are from the four positions a-a, b-b, c-c and d-d in Figure 8
  • the main cross-sectional schematic diagram of the position in the formation process of the semiconductor structure clearly shows the formation process of the semiconductor structure.
  • Schematic diagrams of semiconductor structures formed according to embodiments of the present disclosure can be seen in FIGS. 1-6 .
  • the method of forming a semiconductor structure includes the following steps:
  • Step S71 provide substrate 31
  • Step S72 forming a stacked layer on the substrate 31.
  • the stacked layer includes a plurality of storage areas spaced apart along the first direction D1, where the first direction D1 is parallel to the top surface of the substrate 31;
  • Step S73 forming a memory unit MU including a transistor structure in the storage area.
  • the transistor structure includes an active structure and a gate layer. At least part of the active structure is distributed around the periphery of part of the gate layer, and the active structure is on the top of the substrate 31.
  • the shape of the projection on the surface is a U-shape opening toward the second direction D2, where both the first direction D1 and the second direction D2 are parallel to the top surface of the substrate 31, and the first direction D1 intersects the second direction D2.
  • the step of forming the stacked layer on the substrate 31 includes:
  • Interlayer insulating layers 27 and stacked unit layers alternately stacked along the third direction D3 are formed on the substrate 31 .
  • the stacked unit layer includes a first isolation layer 91 , a sacrificial layer 90 , and a second isolation layer sequentially stacked along the third direction D3 .
  • the substrate 31 may be, but is not limited to, a silicon substrate.
  • the embodiment of the present disclosure takes the substrate 31 as a silicon substrate as an example for description.
  • the interlayer insulating layer 27 , the first isolation layer 91 , the sacrificial layer 90 and the second isolation layer 92 may be alternately deposited on the top surface of the substrate 31 using a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process to form a stack. layer.
  • any two of the interlayer insulating layer 27, the first isolation layer 91, the sacrificial layer 90, and the second isolation layer 92 should have a higher etching selectivity ratio (for example, the etching selectivity ratio between any two Greater than 3) to facilitate subsequent selective etching.
  • the material of the first isolation layer 91 and the second isolation layer 92 is both an oxide material (such as silicon dioxide), the material of the sacrificial layer 90 is a polysilicon material, and the material of the interlayer insulating layer 27 is nitride. materials (e.g. silicon nitride).
  • a memory cell including a transistor structure in the storage area before forming a memory cell including a transistor structure in the storage area, the following steps are further included:
  • the first support column 50 is formed in the first support groove 101, and the second support column 40 is formed in the second support groove 100, as shown in Figure 11.
  • the stacked layer is etched along the third direction D3 to form the first support groove 101 and the second support groove 100 .
  • an insulating dielectric material such as nitride (eg, silicon nitride) is filled into the first support groove 101 and the second support groove 100 to form the first support pillar 50 and the second support pillar 40 .
  • the first support pillar 50 and the second support pillar 40 are used to support the stacked layer to prevent the stacked layer from tipping or collapsing in subsequent processes; on the other hand, the first support pillar 50 is also used to isolate the subsequently formed capacitor structure and The bit line, second support pillar 40 is also used to isolate adjacent storage areas.
  • the storage area includes a transistor area and a capacitance area located outside the transistor area along the second direction D2; the step of forming a memory cell including a transistor structure in the storage area includes:
  • a first gate layer 21 and a channel layer 20 distributed around the periphery of the first gate layer 21 are formed in the first trench 150.
  • the gate layer includes the first gate layer 21, and the active structure includes the channel layer. 20, as shown in Figure 16.
  • the following steps are also included:
  • the first isolation layer 91 and the second isolation layer 92 in the transistor area are removed, and the second trench 130 and the third trench 131 located on opposite sides of the sacrificial layer 90 in the third direction D3 are formed in the stacked unit, as shown in FIG. 13 shown;
  • a second gate layer 22 covering the sacrificial layer 90 is formed in the second trench 130 and the third trench 131.
  • the gate layer includes a first gate layer 21 and a second gate layer. twenty two.
  • the specific steps of forming the second gate layer 22 covering the sacrificial layer 90 in the second trench 130 and the third trench 131 include:
  • a second gate electrode layer 22 covering the second gate dielectric layer 23 is formed in the second trench 130 and the third trench 131, as shown in FIG. 14 .
  • specific steps of forming the first gate layer 21 in the first trench 150 and the channel layer 20 distributed around the periphery of the first gate layer 21 include:
  • the first gate layer 21 is formed on the channel layer 20 in the first trench 150 , and the thickness of the first gate layer 21 along the third direction D3 is greater than or equal to the thickness of the second gate layer 22 along the third direction D3 thickness of.
  • the step of forming the first gate layer 21 on the channel layer 20 in the first trench 150 includes:
  • a first gate dielectric layer 24 covering the channel layer 20 is formed in the first trench 150 .
  • the thickness of the first gate dielectric layer 24 along the third direction D3 is less than or equal to the thickness of the second gate dielectric layer 23 along the third direction D3 . thickness of;
  • the first gate layer 21 covering the first gate dielectric layer 24 is formed in the first trench 150 .
  • the stacked layer further includes an isolation region located outside the transistor region along the second direction D2, and the isolation region and the capacitance region are distributed on opposite sides of the transistor region along the second direction D2.
  • an etching process may be used to remove the stacked layer in the isolation area to form an isolation trench 120 exposing the substrate 31 .
  • a lateral etching process can be used to remove part of the first isolation layer 91 and part of the second isolation layer 92 in the transistor area from the isolation trench 120 to form a second trench 130 located under the sacrificial layer 90 in the storage area.
  • the third trench 131 located above the sacrificial layer 90, as shown in FIG. 13 .
  • an atomic layer deposition process can be used to deposit an insulating dielectric material such as oxide (such as silicon dioxide) in the second trench 130 and the third trench 131 along the second trench 130 and the third trench 131 to form a covering.
  • the second gate dielectric layer 23 covers the entire inner wall of the second trench 130 and the entire inner wall of the third trench 131 .
  • an atomic layer deposition process is used to deposit TiN and other conductive materials in the second trench 130 and the third trench 131 along the second trench 130 and the third trench 131 to form a filling layer covering the surface of the second gate dielectric layer 23 .
  • the second gate 22 fills the second trench 130 and the third trench 131, as shown in FIG. 14 .
  • a lateral etching process may be used to remove part of the sacrificial layer 90 in the transistor area from the isolation trench 120 to form the first trench 150, as shown in FIG. 15 .
  • the channel layer 20 covering the entire inner wall of the first trench 150 , the first gate dielectric layer 24 covering the surface of the channel layer 20 , and the first gate dielectric layer 24 covering the first gate dielectric layer 24 are sequentially formed in the first trench 150 .
  • the first gate layer 21 fills the first trench 150 on the surface, as shown in FIG. 16 .
  • the thickness of the first gate dielectric layer 24 along the third direction D3 refers to the distance between the inner surface of the first gate dielectric layer 24 facing the first gate electrode layer 21 and the outer surface of the first gate dielectric layer 24 away from the first gate electrode layer 21 .
  • the thickness of the second gate dielectric layer 23 along the third direction D3 refers to the thickness of the inner surface of the second gate dielectric layer 24 facing the channel layer 20 and the outer surface of the second gate dielectric layer 24 away from the channel layer 20 along the third direction. distance on D3.
  • the thickness of the second gate layer 22 along the third direction D3 refers to the distance along the third direction between the inner surface of the second gate layer 22 facing the channel layer 20 and the outer surface away from the channel layer 20 .
  • the thickness of the first gate layer 21 along the third direction D3 is greater than or equal to the thickness of the second gate layer 22 along the third direction D3, and the thickness of the first gate dielectric layer 24 along the third direction D3 less than or equal to the third direction D3.
  • the thickness of the second gate dielectric layer 23 along the third direction D3 can further improve the electrical performance of the semiconductor structure while controlling the size of the memory cell.
  • the following steps are further included:
  • a word line 10 extending along the first direction D1 is formed on the substrate 31.
  • the word line 10 is electrically connected to the first gate layer 21 and the second gate layer 22 in a plurality of memory cells spaced apart along the first direction D1. connect.
  • the step of forming the word line 10 extending along the first direction D1 on the substrate 31 includes:
  • a word line 10 extending along the first direction D1 is formed at an end of the transistor structure along the second direction D2.
  • the word line 10 and the end of the first gate layer 21 along the second direction D2 and the second gate layer 22 extend along the second direction D2.
  • the ends of the two directions D2 are in contact and electrically connected.
  • a selective etching process may be used to remove part of the channel layer 20 along the isolation trench 120 to form a fourth trench between the first gate dielectric layer 24 and the second gate dielectric layer 23 .
  • An insulating dielectric material such as oxide (eg, silicon dioxide) is deposited in the fourth trench to form a first insulating dielectric layer 170 .
  • oxide eg, silicon dioxide
  • a portion of the first gate dielectric layer 24 , a portion of the second gate dielectric layer 23 and a portion of the first insulating dielectric layer 170 in the storage area are removed along the isolation trench 120 to form words between adjacent interlayer insulating layers 27 . Line trench.
  • Conductive materials such as TiN are deposited in the word line trenches using an atomic layer deposition process to form a word line 10 that connects the first gate layer 21 and the second gate layer 22 and extends along the first direction D1, as shown in Figure 18 .
  • the remaining first insulating dielectric layer 170 is used to electrically isolate the word line 10 and the channel layer 20 .
  • the storage area also includes a capacitor area and a bit line area located on the same side of the transistor area along the second direction D2.
  • the capacitance area and the bit line area are spaced apart along the first direction D1; formed on the substrate 31 After the word line 10 extending along the first direction D1, the following steps are also included:
  • the stacked layer in the bit line area is removed, and part of the sacrificial layer 90 in the transistor area is removed to form a fifth trench 200 located in the bit line area and a source trench located in the transistor area.
  • the source trench exposes the channel layer 20 along the third The end of D3 in three directions;
  • a bit line 13 electrically connected to the source region 11 is formed in the fifth trench 200, as shown in FIG. 20 .
  • an insulating dielectric material such as oxide (such as silicon dioxide) is deposited in the isolation trench 120 to form a covering layer 26, as shown in FIG. 19, to avoid subsequent processing processes from affecting the word line 10.
  • an etching process is used to remove the stacked layer in the bit line region, and a fifth trench 200 is formed to expose the substrate 31 .
  • Part of the sacrificial layer 90 in the transistor region is removed along the fifth trench 200 to form a source trench connected to the fifth trench 200 .
  • a source region 11 is formed that fills the source trench and is in contact with the channel layer 20
  • a bit line 13 extending along the third direction D3 is formed in the fifth trench 200 , and the bit line 13 is continuous with the channel layer 20 .
  • a plurality of source regions 11 arranged at intervals in the third direction D3 are in contact and electrically connected, as shown in FIG. 20 .
  • the material of the bit line 13 is a conductive material such as metal tungsten.
  • the following steps are also included:
  • the capacitor trench exposes the end of the channel layer 20 along the third direction D3 department;
  • a capacitor structure 14 electrically connected to the drain region 12 is formed in the capacitor trench.
  • a portion of the stacked layer on the side of the capacitor region away from the transistor region is removed to form a sixth trench 210 exposing the substrate 31 , as shown in FIG. 21 .
  • the sacrificial layer 90 in the capacitor area and the remaining sacrificial layer 90 in the transistor area are removed along the sixth trench 210 to form a capacitor trench located in the capacitor area and a drain trench located in the transistor area, and the capacitor trench is connected to the drain trench.
  • a drain region 12 that is filled with the drain groove and is in contact with the channel layer 20 is formed in the drain groove, and a capacitor structure 14 that is in contact and electrically connected with the drain region 12 is formed in the capacitor groove, and the capacitor structure 14
  • the remaining first isolation layer 91 and the second isolation layer 92 in the capacitor region together serve as the capacitor isolation layer 32 .
  • the bit line 13 may be formed first, and then the capacitor structure 14 may be formed, or the capacitor structure 14 may be formed first, and then the bit line 13 may be formed. Those skilled in the art may make a choice according to actual needs.
  • the material of the active structure is an oxide semiconductor material.
  • the materials of the channel layer 20, the source region 11 and the drain region 12 in the active structure are all oxide semiconductor materials.
  • the oxide semiconductor material is In 2 O 3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), Any one or a combination of two or more ZnON (zinc oxynitride).
  • the material of the active structure is IGZO.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • a transistor structure with a fully surrounding channel is formed.
  • the transistor structure is The active structure is arranged in a U-shape extending in a direction parallel to the top surface of the substrate (for example, the second direction), thereby improving the gate control capability of the transistor structure while reducing the power consumption of the semiconductor structure, thereby achieving electrical control of the semiconductor structure.
  • some embodiments of the present disclosure form the channel layer by removing the sacrificial layer in the stacked layer when forming the semiconductor structure. Therefore, there is no need to form the channel layer through complex epitaxial growth processes and doping processes, simplifying the semiconductor process.
  • the manufacturing process of the structure helps to increase the stacking height of the stacked structure in the semiconductor structure and improves the manufacturing yield of the semiconductor structure.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构包括：衬底；堆叠结构，位于所述衬底上，所述堆叠结构包括沿所述第一方向间隔排布的多个存储单元，所述存储单元包括晶体管结构，所述晶体管结构包括有源结构和栅极层，至少部分所述有源结构环绕部分所述栅极层的外周分布，且所述有源结构在所述衬底的顶面上的投影的形状为朝第二方向开口的U形，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交。本公开在提高晶体管结构栅控能力的同时，降低所述半导体结构的功耗。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年09月01日递交的中国专利申请号202211066753.3、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
为了在满足DRAM等半导体结构尺寸不断微缩、且存储密度不断提高的要求，具有三维构造的DRAM等半导体结构应运而生。但是，具有三维构造的DRAM等半导体结构还存在晶体管的栅控能力较差、功耗较高等问题，从而限制了半导体结构性能的进一步提升。
因此，如何提高半导体结构栅控能力，并降低半导体结构的功耗，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于改善半导体结构的栅控能力，并降低半导体结构的功耗，从而提升半导体结构的性能。
根据一些实施例，本公开提供了一种半导体结构，包括：
衬底；
堆叠结构，位于所述衬底上，所述堆叠结构包括沿所述第一方向间隔排布的多个存储单元，所述存储单元包括晶体管结构，所述晶体管结构包括有源结构和栅极层，至少部分所述有源结构环绕部分所述栅极层的外周分布，且所述有源结构在所述衬底的顶面上的投影的形状为朝第二方向开口的U形，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交。
在一些实施例中，所述栅极层包括：
第一栅极层，部分所述有源结构环绕所述第一栅极层的外周分布；
第二栅极层，所述第二栅极层至少环绕部分所述有源结构的外周分布，且所述第一栅极层电连接所述第二栅极层。
在一些实施例中，还包括：
字线，沿所述第一方向延伸，并与沿所述第一方向间隔排布的多个所述存储单元内的所述第一栅极层和所述第二栅极层电连接。
在一些实施例中，所述字线位于所述存储单元沿所述第二方向的端部，且与所述第一栅极层沿所述第二方向的端部和所述第二栅极层沿所述第二方向的端部接触电连接。
在一些实施例中，所述有源结构包括：
沟道层，沿所述第一方向延伸，所述沟道层环绕所述第一栅极层的外周分布，所述第二栅极层环绕所述沟道层的外周分布；
源极区，沿所述第二方向凸设于所述沟道层的背离所述字线的侧面；
漏极区，沿所述第二方向凸设于所述沟道层的背离所述字线的侧面，所述源极区和所述漏极区间隔位于所述沟道层沿所述第一方向的相对两端。
在一些实施例中，所述晶体管结构还包括：
第一栅介质层，位于所述第一栅极层与所述沟道层之间；
第二栅介质层，位于所述第二栅极层与所述沟道层之间，且所述第一栅介质层沿第三方向的厚度小于或者等于所述第二栅介质层沿所述第三方向的厚度，其中，所述第三方向与所述衬底的顶面垂直；
第一绝缘介质层，位于所述字线和所述沟道层之间。
在一些实施例中，所述第一栅极层沿第三方向的厚度大于或者等于所述第二栅极层沿所述第三方向的厚度，其中，所述第三方向与所述衬底的顶面垂直。
在一些实施例中，所述存储单元还包括：
电容结构，沿所述第二方向延伸，包括与所述晶体管结构的所述漏极区接触电连接的下电极层、覆盖所述下电极层的电介质层、以及覆盖所述电介质层的上电极层。
在一些实施例中，所述堆叠结构包括沿第三方向间隔排布的多个存储层，每个所述存储层包括沿所述第一方向间隔排布的多个所述存储单元，其中，所述第三方向与所述衬底的顶面垂直；所述半导体结构还包括：
位线，沿所述第三方向延伸，且与沿所述第三方向间隔排布的多个所述存储单元中的所述源极区电连接。
在一些实施例中，还包括：
第一支撑柱，沿所述第三方向延伸，且所述第一支撑柱位于所述电容结构与所述位线之间；
第二支撑柱，沿所述第三方向延伸，且所述第二支撑柱位于沿所述第一方向相邻的所述存储单元之间；
层间绝缘层，位于沿第三方向间隔排布的相邻所述存储层之间。
在一些实施例中，所述有源结构的材料为氧化物半导体。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括如下步骤：
提供衬底；
形成堆叠层于所述衬底上，所述堆叠层包括沿第一方向间隔排布的多个存储区域，其中，所述第一方向与所述衬底的顶面平行；
于所述存储区域形成包括晶体管结构的存储单元，所述晶体管结构包括有源结构和栅极层，至少部分所述有源结构环绕部分所述栅极层的外周分布，且所述有源结构在所述衬底的顶面上的投影的形状为朝第二方向开口的U形，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交。
在一些实施例中，形成堆叠层于所述衬底上的步骤包括：
于所述衬底上形成沿第三方向交替堆叠的层间绝缘层和堆叠单元层，所述堆叠单元层包括沿所述第三方向依次堆叠的第一隔离层、牺牲层、和第二隔离层，其中，所述第三方向与所述衬底的顶面垂直。
在一些实施例中，于所述存储区域形成包括晶体管结构的存储单元之前，还包括如下步骤：
刻蚀所述堆叠层，形成位于所述存储区域内的第一支撑槽、以及位于沿所述第一方向相邻的所述存储区域之间的第二支撑槽；
于所述第一支撑槽内形成第一支撑柱、并于所述第二支撑槽内形成第二支撑柱。
在一些实施例中，所述存储区域包括晶体管区域、以及沿所述第二方向位于所述晶体管区域外部的电容区域；于所述存储区域形成包括晶体管结构的存储单元的步骤包括：
去除所述晶体管区域的所述牺牲层，形成第一沟槽；
于所述第一沟槽内形成第一栅极层、以及环绕所述第一栅极层的外周分布的所述沟道层，所述栅极层包括所述第一栅极层，所述有源结构包括所述沟道层。
在一些实施例中，形成第一沟槽之前，还包括如下步骤：
去除所述晶体管区域的所述第一隔离层和所述第二隔离层，于所述堆叠单元内形成位于所述牺牲层在所述第三方向上相对两侧的第二沟槽和第三沟槽；
于所述第二沟槽和所述第三沟槽内形成覆盖于所述牺牲层上的第二栅极层，所述栅极层包括所述第一栅极层和所述第二栅极层。
在一些实施例中，于所述第二沟槽和所述第三沟槽内形成覆盖于所述牺牲层上的第二栅极层的具体步骤包括：
形成覆盖所述第二沟槽内壁和所述第三沟槽内壁的第二栅介质层；
于所述第二沟槽内和所述第三沟槽内形成覆盖于所述第二栅介质层上的所述第二栅极层。
在一些实施例中，于所述第一沟槽内形成第一栅极层、以及环绕所述第一栅极层的外周分布的所述沟道层的具体步骤包括：
形成覆盖所述第一沟槽的整个内壁的所述沟道层；
于所述第一沟槽内形成位于所述沟道层上的所述第一栅极层，且所述第一栅极层沿所述第三方向的厚度大于或者等于所述第二栅极层沿所述第三方向的厚度。
在一些实施例中，于所述第一沟槽内形成位于所述沟道层上的所述第一栅极层的步骤包括：
于所述第一沟槽内形成覆盖于所述沟道层上的第一栅介质层，所述第一栅介质层沿所述第三方向的厚度小于或者等于所述第二栅介质层沿所述第三方向的厚度；
于所述第一沟槽内形成覆盖于所述第一栅介质层上的所述第一栅极层。
在一些实施例中，于所述第一沟槽内形成第一栅极层、以及环绕所述第一栅极层的外周分布的所述沟道层之后，还包括如下步骤：
于所述衬底上形成沿所述第一方向延伸的字线，所述字线与沿所述第一方向间隔排布的多个所述存储单元内的所述第一栅极层和所述第二栅极层电连接。
在一些实施例中，于所述衬底上形成沿所述第一方向延伸的字线的步骤包括：
沿所述第二方向去除部分的所述沟道层，形成第四沟槽；
于所述第四沟槽内形成第一绝缘介质层；
于所述晶体管结构沿所述第二方向的端部形成沿所述第一方向延伸的字线，所述字线与所述第一栅极层沿所述第二方向的端部和所述第二栅极层沿所述第二方向的端部接触电连接。
在一些实施例中，所述存储区域还包括位于所述晶体管区域沿所述第二方向的同一侧的电容区域和位线区域，所述电容区域和所述位线区域沿所述第一方向间隔排布；于所述衬底上形成沿所述第一方向延伸的字线之后，还包括如下步骤：
去除所述位线区域的所述堆叠层、并去除所述晶体管区域的部分所述牺牲层，形成位于所述位线区域的第五沟槽、以及位于所述晶体管区域内的源极槽，所述源极槽露出所述沟道层沿所述第三方向的端部；
于所述源极槽内形成与所述沟道层接触电连接的源极区；
于所述第五沟槽内形成与所述源极区接触电连接的位线。
在一些实施例中，于所述衬底上形成沿所述第一方向延伸的字线之后，还包括如下步骤：
去除所述电容区域的所述牺牲层、并去除所述晶体管区域保留的所述牺牲层，形成位于所述电容区域的电容槽、以及位于所述晶体管区域内的漏极槽，所述电容槽露出所述沟道层沿所述第三方向的端部；
于所述漏极槽内形成与所述沟道层接触电连接的漏极区；
于所述电容槽内形成与所述漏极区接触电连接的电容结构。
本公开一些实施例提供的半导体结构及其形成方法，通过将晶体管结构中的至少部分有源结构环绕栅极层的外周分布，形成沟道全环绕的晶体管结构，同时，将晶体管结构中的有源结构设置为朝平行于衬底的顶面方向(例如第二方向)开口的U形，从而在提高晶体管结构栅控能力的同时，降低所述半导体结构的功耗，从而实现对半导体结构电性能的提高。另外，本公开一些实施例在形成半导体结构时，通过去除堆叠层中的牺牲层来形成沟道层，因而无需通过复杂的外延生长工艺和掺杂工艺来形成沟道层，简化了半导体结构的制程工艺，且有助于提高半导体结构中堆叠结构的堆叠高度，并提高半导体结构的制造良率。
附图说明
附图1是本公开实施例中半导体结构的俯视结构示意图；
附图2是附图1在a-a位置的截面示意图；
附图3是附图1在b-b位置的截面示意图；
附图4是附图1在c-c位置的截面示意图；
附图5是附图1在d-d位置的截面示意图；
附图6是本公开实施例中存储单元的立体结构示意图；
附图7是本公开实施例中半导体结构的形成方法流程图；
附图8-附图22是本公开实施例在形成半导体结构的过程中主要的工艺结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式作详细说明。
本公开实施例提供了一种半导体结构，附图1是本公开实施例中半导体结构的俯视结构示意图，附图2是附图1在a-a位置的截面示意图，附图3是附图1在b-b位置的截面示意图，附图4是附图1在c-c位置的截面示意图，附图5是附图1在d-d位置的截面示意图，附图6是本公开实施例中存储单元的立体结构示意图。如图1-图6所示，半导体结构，包括：
衬底31；
堆叠结构，位于衬底31上，堆叠结构包括沿第一方向D1间隔排布的多个存储单元MU，存储单元MU包括晶体管结构，晶体管结构包括有源结构和栅极层，至少部分有源结构环绕部分栅极层的外周分布，且有源结构在衬底31的顶面上的投影的形状为朝第二方向D2开口的U形，其中，第一方向D1和第二方向D2均与衬底31的顶面平行，且第一方向D1与第二方向D2相交。
半导体结构可以是但不限于DRAM，本公开实施例以半导体结构为DRAM为例进行说明。具体来说，衬底31可以是但不限于硅衬底，本公开实施例以衬底31为硅衬底为例进行说明。在其他实施例中，衬底31还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。衬底31用于支撑在其上的器件结构。多个存储单元在衬底31的顶面上沿第一方向D1间隔排布。有源结构在衬底31的顶面上的投影的形状为朝第二方向D2开口的U形是指，有源结构在衬底31的顶面上的投影的轮廓线的形状为U形，且U形的U形开口朝向第二方向。有源结构包括沟道层、以及位于沟道层同一侧的源极区和漏极区。本公开实施例通过设置具有U形的有源结构，同时使得有源结构环绕栅极层的外周分布，形成包括沟道全环绕结构的晶体管结构，从而在提高晶体管结构栅控能力的同时，降低半导体结构的功耗，实现对半导体结构电性能的提高。衬底31的顶面是指衬底31朝向堆叠结构的表面。本公开实施例中的多个是指两个以上。第一方向D1与第二方向D2可以是垂直相交，也可以是倾斜相交。本公开实施例以第一方向D1和第二方向D2垂直相交为例进行说明。
在一些实施例中，栅极层包括：
第一栅极层21，部分有源结构环绕第一栅极层21的外周分布；
第二栅极层22，第二栅极层22至少环绕部分有源结构的外周分布，且第一栅极层21电连接第二栅极层22。
具体来说，栅极层包括相互电连接的第一栅极层21和第二栅极层22，部分有源结构，包括沟道层20，环绕第一栅极层21的外周分布，形成沟道全环绕结构，第二栅极层22环绕部分有源结构的外周分布，形成栅极全环绕结构，如图6中的(b)所示，使得本公开实施例中的晶体管结构同时具备栅极全环绕结构和沟道全环绕结构，从而进一步提高了晶体管结构的栅控能力，简化了存储单元的控制操作，进一步提高了半导体结构的电性能。图6中的(b)示出了图6中的(a)在虚线箭头位置的截面示意图。
在一些实施例中，半导体结构还包括：
字线10，沿第一方向D1延伸，并与沿第一方向D1间隔排布的多个存储单元MU内的第一栅极层21和第二栅极层22电连接。
具体来说，字线10沿第一方向D1延伸，即半导体结构具有水平字线结构。位于同一存储单元MU内的第一栅极层21和第二栅极层22通过字线10电连接，且字线10电连接沿第一方向D1间隔排布的多个存储单元MU内的第一栅极层21和第二栅极层22，以通过字线10同时向多个存储单元MU内的第一栅极层21和第二栅极层22传输控制信号。
为了简化存储单元MU内第一栅极层21和第二栅极层22的连接操作，且简化字线10的形成工艺，在一些实施例中，字线10位于存储单元MU沿第二方向D2的端部，且与第一栅极层21沿第二方向D2的端部和第二栅极层22沿第二方向D2的端部接触电连接。
具体来说，如图6中的(a)所示，字线10位于存储单元MU沿第二方向D2的端部，且字线10沿第三方向D3的厚度大于或者等于晶体管结构沿第三方向D3的厚度，从而使得字线10能够充分与晶体管结构中的第一栅极层21和第二栅极层22接触电连接，提高字线10与第一栅极层21和第二栅极层22之间的连接稳定性，从而进一步改善半导体结构的良率。在一示例中，如图2和图3所示，字线10沿第三方向D3的顶面位于第二栅极层22的顶面之上，且字线10沿第三方向D3的底面位于第二栅极层22的底面之下，即字线10沿第三方向D3突出于第二栅极层22，其中，第三方向D3与衬底31的顶面垂直。
在一示例中，如图1所示，沿第一方向D1间隔排布的多个存储单元MU中的栅极层相互独立，以简化栅极层的制程工艺。在另一示例中，沿第一方向D1间隔排布的多个存储单元MU中的第二栅极层22连接(例如通过选择性沉积工艺实现)，从而简化字线10的形成工艺。
在一些实施例中，有源结构包括：
沟道层20，沿第一方向D1延伸，沟道层20环绕第一栅极21层的外周分布，第二栅极层22环绕沟道层20的外周分布；
源极区11，沿第二方向D2凸设于沟道层20的背离字线10的侧面；
漏极区12，沿第二方向D2凸设于沟道层20的背离字线10的侧面，源极区11和漏极区12间隔位于沟道层20背离字线10的侧面上沿第一方向D1的相对两端。
具体来说，有源结构包括沟道层20、以及位于沟道层20沿第二方向D2的同一侧的源极区11和漏极区12，且源极区11与漏极区12均与沟道层20连接、且间隔分布于沟道层20沿第一方向D1的相对两端，从而使得沟道层20、源极区11和漏极区12共同构成的整体在衬底31的顶面上的投影的形状为开口朝向第二方向D2的U形。在一示例中，源极区11与漏极区12沿第一方向D1对准排布。举例来说，源极区11中的第一轴线与漏极区12中的第二轴线沿第一方向D1对准，其中，第一轴线穿过源极区11的中心且沿第一方向D1延伸，第二轴线穿过漏极区12的中心且沿第一方向D1延伸。
在一些实施例中，晶体管结构还包括：
第一栅介质层24，位于第一栅极层21与沟道层20之间；
第二栅介质层23，位于第二栅极层22与沟道层20之间，且第一栅介质层24沿第三方向D3的厚度小于或者等于第二栅介质层23沿第三方向D3的厚度，其中，第三方向D3与衬底31的顶面垂直；
第一绝缘介质层，位于字线10和沟道层20之间。
第一栅介质层24沿第三方向D3的厚度是指，第一栅介质层24朝向第一栅极层21的内表面与第一栅介质层24背离第一栅极层21的外表面在沿第三方向D3上的距离。第二栅介质层23沿第三方向D3的厚度是指，第二栅介质层23朝向沟道层20的内表面与第二栅介质层23背离沟道层20的外表面在沿第三方向D3上的距离。本公开实施例将第一栅介质层24沿第三方向D1的厚度设置为小于或者等于第二栅介质层23沿第三方向D3的厚度，一方面，减小第一栅介质层24的厚度，可以避免沟道层20的尺寸过大，从而改善晶体管结构的沟道性能；另一方面，增大第二栅介质层23的厚度，可以增大第一栅极层21与第二栅极层22之间的距离，从而降低第一栅极层21与第二栅极层22之间的相互影响。在一示例中，第一栅介质层24的材料和第二栅介质层23的材料相同，例如均为氧化物材料(例如二氧化硅)。
为了在进一步缩小沟道层20的尺寸的同时，进一步提高晶体管结构的栅控能力，在一些实施例中，第一栅极层21沿第三方向D3的厚度大于或者等于第二栅极层22沿第三方向D3的厚度，其中，第三方向D3与衬底31的顶面垂直。第二栅极层22沿第三方向D3的厚度是指，第二栅极层22朝向沟道层20的内表面与背离沟道层20的外表面在沿第三方向上的距离。
在一些实施例中，存储单元MU还包括：
电容结构14，沿第二方向D2延伸，包括与晶体管结构的漏极区12接触电连接的下电极层28、覆盖下电极层28的电介质层29、以及覆盖电介质层29的上电极层30。在一示例中，下电极层28的材料可以与上电极层30的材料相同，例如均为TiN或者金属钨等导电材料，电介质层29的材料为具有较高介电常数(高K)的材料。存储单元MU中还包括覆盖电容结构14的电容隔离层32，电容隔离层32用于隔离相邻的电容结构14，避免相邻电容结构14之间的信号串扰。
在一些实施例中，堆叠结构包括沿第三方向D3间隔排布的多个存储层，每个存储层包括沿第一方向D1间隔排布的多个存储单元MU，其中，第三方向D3与衬底31的顶面垂直；半导体结构还包括：
位线13，沿第三方向D3延伸，且与沿第三方向D3间隔排布的多个存储单元MU中的源极区11电连接。
具体来说，堆叠结构包括沿第三方向D3交替堆叠的存储单元MU和层间绝缘层27，层间绝缘层27用于电性隔离沿第三方向D3相邻的两个存储单元MU。在一示例中，层间绝缘层27的材料可以为氮化物材料(例如氮化硅)。位线13沿第三方向D3延伸，且位线13连续与沿第三方向D3间隔排布的多个存储单元MU中的源极区11接触电连接。多条位线13沿第一方向D1间隔排布。举例来说，如图5所示，沿第一方向D1相邻的位线之间包括多个沿第三方向D3间隔排布的电容结构14。在堆叠结构包括沿第三方向D3间隔排布的多个存储层时，字线10的数量为多条，且多条字线10沿第三方向D3间隔排布。在沿第三方向D3相邻的两条字线10中，较靠近衬底31的一条字线10沿第一方向D1的长度大于另一条字线10沿第一方向D1的长度(即较靠近衬底31的一条字线10沿第一方向D1突出于另一条字线10)，从而使得多条字线10的共同构成台阶状结构。半导体结构还包括位于堆叠结构的侧面、且覆盖沿第三方向D3间隔排布的多条字线10的侧壁的覆盖层26。在一示例中，覆盖层26的材料可以为氧化物材料(例如二氧化硅)。
在一些实施例中，半导体结构还包括：
第一支撑柱50，沿第三方向D3延伸，且第一支撑柱50位于电容结构14与位线13之间；
第二支撑柱40，沿第三方向D3延伸，且第二支撑柱40位于沿第一方向D1相邻的存储单元MU之 间；
层间绝缘层27，位于沿第三方向D3间隔排布的相邻存储层之间。
具体来说，第一支撑柱50和第二支撑柱40用于支撑堆叠结构，避免堆叠结构出现倾倒或者坍塌，提高堆叠结构的稳定性。在一示例中，第一支撑柱50的材料和第二支撑柱40的材料可以相同，例如均为氮化物材料(例如氮化硅)。
在一些实施例中，有源结构的材料为氧化物半导体材料。在一示例中，氧化物半导体材料为In 2O 3(氧化铟)、ZnO(氧化锌)、IZO(氧化铟锌)、IGZO(铟镓锌氧化物)、IZTO(铟锡锌氧化物)、ZnON(氮氧化锌)中的任一种或者两种以上的组合。优选的，有源结构的材料为IGZO。
本公开实施例还提供了一种半导体结构的形成方法，附图7是本公开实施例中半导体结构的形成方法流程图，附图8-附图22是本公开实施例在形成半导体结构的过程中主要的工艺结构示意图，其中，图8是本公开实施例形成的半导体结构的俯视结构示意图，图9-图22是从图8中的a-a位置、b-b位置、c-c位置和d-d位置这四个位置在半导体结构形成过程中的主要截面示意图，以清楚的表示半导体结构的形成工艺。本公开实施例形成的半导体结构的示意图可以参见图1-图6。如图1-图22所示，半导体结构的形成方法，包括如下步骤：
步骤S71，提供衬底31；
步骤S72，形成堆叠层于衬底31上，堆叠层包括沿第一方向D1间隔排布的多个存储区域，其中，第一方向D1与衬底31的顶面平行；
步骤S73，于存储区域形成包括晶体管结构的存储单元MU，晶体管结构包括有源结构和栅极层，至少部分有源结构环绕部分栅极层的外周分布，且有源结构在衬底31的顶面上的投影的形状为朝第二方向D2开口的U形，其中，第一方向D1和第二方向D2均与衬底31的顶面平行，且第一方向D1与第二方向D2相交。
在一些实施例中于，形成堆叠层于衬底31上的步骤包括：
于衬底31上形成沿第三方向D3交替堆叠的层间绝缘层27和堆叠单元层，堆叠单元层包括沿第三方向D3依次堆叠的第一隔离层91、牺牲层90、和第二隔离层92，其中，第三方向D3与衬底31的顶面垂直，如图9所示。
具体来说，衬底31可以是但不限于硅衬底，本公开实施例以衬底31为硅衬底为例进行说明。可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺于衬底31的顶面上交替沉积层间绝缘层27、第一隔离层91、牺牲层90和第二隔离层92，形成堆叠层。其中，层间绝缘层27、第一隔离层91、牺牲层90、第二隔离层92中任意两者之间应具有较高的刻蚀选择比(例如任意两者之间的刻蚀选择比大于3)，以便于后续进行选择性刻蚀。
在一些实施例中，第一隔离层91和第二隔离层92的材料均为氧化物材料(例如二氧化硅)，牺牲层90的材料为多晶硅材料，层间绝缘层27的材料为氮化物材料(例如氮化硅)。
在一些实施例中，于存储区域形成包括晶体管结构的存储单元之前，还包括如下步骤：
刻蚀堆叠层，形成位于存储区域内的第一支撑槽101、以及位于沿第一方向D1相邻的存储区域之间的第二支撑槽100，如图10所示；
于第一支撑槽101内形成第一支撑柱50、并于第二支撑槽100内形成第二支撑柱40，如图11所示。
具体来说，在形成堆叠层之后，沿第三方向D3刻蚀堆叠层，形成第一支撑槽101和第二支撑槽100。接着，填充氮化物(例如氮化硅)等绝缘介质材料于第一支撑槽101和第二支撑槽100内，形成第一支撑柱50和第二支撑柱40。第一支撑柱50和第二支撑柱40一方面用于支撑堆叠层，避免堆叠层在后续工艺中出现倾倒或者坍塌；另一方面，第一支撑柱50还用于隔离后续形成的电容结构和位线，第二支撑 柱40还用于隔离相邻的存储区域。
在一些实施例中，存储区域包括晶体管区域、以及沿第二方向D2位于晶体管区域外部的电容区域；于存储区域形成包括晶体管结构的存储单元的步骤包括：
去除晶体管区域的牺牲层90，形成第一沟槽150，如图15所示；
于第一沟槽150内形成第一栅极层21、以及环绕第一栅极层21的外周分布的沟道层20，栅极层包括第一栅极层21，有源结构包括沟道层20，如图16所示。
在一些实施例中，形成第一沟槽150之前，还包括如下步骤：
去除晶体管区域的第一隔离层91和第二隔离层92，于堆叠单元内形成位于牺牲层90在第三方向D3上相对两侧的第二沟槽130和第三沟槽131，如图13所示；
于第二沟槽130和第三沟槽131内形成覆盖于牺牲层90上的第二栅极层22，如图14所示，栅极层包括第一栅极层21和第二栅极层22。
在一些实施例中，于第二沟槽130和第三沟槽131内形成覆盖于牺牲层90上的第二栅极层22的具体步骤包括：
形成覆盖第二沟槽130内壁和第三沟槽131内壁的第二栅介质层23；
于第二沟槽130内和第三沟槽131内形成覆盖于第二栅介质层23上的第二栅极层22，如图14所示。
在一些实施例中，于第一沟槽150内形成第一栅极层21、以及环绕第一栅极层21的外周分布的沟道层20的具体步骤包括：
形成覆盖第一沟槽150的整个内壁的沟道层20；
于第一沟槽150内形成位于沟道层20上的第一栅极层21，且第一栅极层21沿第三方向D3的厚度大于或者等于第二栅极层22沿第三方向D3的厚度。
在一些实施例中，于第一沟槽150内形成位于沟道层20上的第一栅极层21的步骤包括：
于第一沟槽150内形成覆盖于沟道层20上的第一栅介质层24，第一栅介质层24沿第三方向D3的厚度小于或者等于第二栅介质23层沿第三方向D3的厚度；
于第一沟槽150内形成覆盖于第一栅介质层24上的第一栅极层21。
具体来说，堆叠层还包括沿第二方向D2位于晶体管区域外侧的隔离区域，隔离区域和电容区域分布于晶体管区域沿第二方向D2的相对两侧。在形成第一支撑柱50和第二支撑柱40之后，可以采用刻蚀工艺去除隔离区域的堆叠层，形成暴露衬底31的隔离槽120。之后，可以采用侧向刻蚀工艺、自隔离槽120去除晶体管区域内部分的第一隔离层91和部分的第二隔离层92，于存储区域内形成位于牺牲层90下方的第二沟槽130、以及位于牺牲层90上方的第三沟槽131，如图13所示。
接着，可以采用原子层沉积工艺沿第二沟槽130和第三沟槽131沉积氧化物(例如二氧化硅)等绝缘介质材料于第二沟槽130内和第三沟槽131内，形成覆盖第二沟槽130的整个内壁和第三沟槽131的整个内壁的第二栅介质层23。之后，采用原子层沉积工艺沿第二沟槽130和第三沟槽131沉积TiN等导电材料于第二沟槽130和第三沟槽131内，形成覆盖第二栅介质层23表面、且填充满第二沟槽130和第三沟槽131的第二栅极22，如图14所示。然后，可以采用侧向刻蚀工艺、自隔离槽120去除晶体管区域的部分牺牲层90，形成第一沟槽150，如图15所示。之后，于第一沟槽150内依次形成覆盖第一沟槽150的整个内壁的沟道层20、覆盖沟道层20的表面的第一栅介质层24、以及覆盖第一栅介质层24的表面且填充满第一沟槽150的第一栅极层21，如图16所示。
第一栅介质层24沿第三方向D3的厚度是指，第一栅介质层24朝向第一栅极层21的内表面与第一栅介质层24背离第一栅极层21的外表面在沿第三方向D3上的距离。第二栅介质层23沿第三方向D3的厚度是指，第二栅介质层24朝向沟道层20的内表面与第二栅介质层24背离沟道层20的外表面在沿 第三方向D3上的距离。第二栅极层22沿第三方向D3的厚度是指，第二栅极层22朝向沟道层20的内表面与背离沟道层20的外表面在沿第三方向上的距离。通过使得第一栅极层21沿第三方向D3的厚度大于或者等于第二栅极层22沿第三方向D3的厚度、且第一栅介质层24沿第三方向D3的厚度小于或者等于第二栅介质23层沿第三方向D3的厚度，能够在控制存储单元尺寸的同时，进一步提高半导体结构的电性能。
在一些实施例中，于第一沟槽150内形成第一栅极层21、以及环绕第一栅极层21的外周分布的沟道层20之后，还包括如下步骤：
于衬底31上形成沿第一方向D1延伸的字线10，字线10与沿第一方向D1间隔排布的多个存储单元内的第一栅极层21和第二栅极层22电连接。
在一些实施例中，于衬底31上形成沿第一方向D1延伸的字线10的步骤包括：
沿第二方向D2去除部分的沟道层20，形成第四沟槽；
于第四沟槽内形成第一绝缘介质层170，如图17所示；
于晶体管结构沿第二方向D2的端部形成沿第一方向D1延伸的字线10，字线10与第一栅极层21沿第二方向D2的端部和第二栅极层22沿第二方向D2的端部接触电连接。
具体来说，可以采用选择性刻蚀工艺沿隔离槽120去除部分的沟道层20，形成位于第一栅介质层24和第二栅介质层23之间的第四沟槽。沉积氧化物(例如二氧化硅)等绝缘介质材料于第四沟槽内，形成第一绝缘介质层170。接着，沿隔离槽120去除存储区域内部分的第一栅介质层24、部分的第二栅介质层23和部分的第一绝缘介质层170，形成位于相邻层间绝缘层27之间的字线沟槽。采用原子层沉积工艺沉积TiN等导电材料于字线沟槽内，形成连接第一栅极层21和第二栅极层22、且沿第一方向D1延伸的字线10，如图18所示。残余的第一绝缘介质层170用于电性隔离字线10与沟道层20。
在一些实施例中，存储区域还包括位于晶体管区域沿第二方向D2的同一侧的电容区域和位线区域，电容区域和位线区域沿第一方向D1间隔排布；于衬底31上形成沿第一方向D1延伸的字线10之后，还包括如下步骤：
去除位线区域的堆叠层、并去除晶体管区域的部分牺牲层90，形成位于位线区域的第五沟槽200、以及位于晶体管区域内的源极槽，源极槽露出沟道层20沿第三方向D3的端部；
于源极槽内形成与沟道层20接触电连接的源极区11；
于第五沟槽200内形成与源极区11接触电连接的位线13，如图20所示。
具体来说，沉积氧化物(例如二氧化硅)等绝缘介质材料于隔离槽120内，形成覆盖层26，如图19所示，以避免后续制程工艺对字线10造成影响。之后，采用刻蚀工艺去除位线区域的堆叠层，形成暴露衬底31的第五沟槽200。沿第五沟槽200去除晶体管区域的部分牺牲层90，形成与第五沟槽200连通的源极槽。接着，形成填充满源极槽、且与沟道层20接触连接的源极区11，并于第五沟槽200内形成沿第三方向D3延伸的位线13，且位线13连续与沿第三方向D3间隔排布的多个源极区11接触电连接，如图20所示。在一示例中，位线13的材料为金属钨等导电材料。
在一些实施例中，于衬底31上形成沿第一方向D1延伸的字线10之后，还包括如下步骤：
去除电容区域的牺牲层90、并去除晶体管区域保留的牺牲层90，形成位于电容区域的电容槽、以及位于晶体管区域内的漏极槽，电容槽露出沟道层20沿第三方向D3的端部；
于漏极槽内形成与沟道层20接触电连接的漏极区12；
于电容槽内形成与漏极区12接触电连接的电容结构14。
具体来说，去除电容区域远离晶体管区域一侧的部分堆叠层，形成暴露衬底31的第六沟槽210，如图21所示。沿第六沟槽210去除电容区域的牺牲层90、以及晶体管区域残留的牺牲层90，形成位于电 容区域的电容槽、位于晶体管区域的漏极槽，且电容槽与漏极槽连通。然后，于漏极槽内形成填充满漏极槽且与沟道层20接触连接的漏极区12，并于电容槽内形成与漏极区12接触电连接的电容结构14，且电容结构14与晶体管结构的漏极区12接触电连接的下电极层28、覆盖下电极层28的电介质层29、以及覆盖电介质层29的上电极层30。电容区域残留的第一隔离层91和第二隔离层92共同作为电容隔离层32。本公开实施例可以先形成位线13、再形成电容结构14，也可以先形成电容结构14、在形成位线13，本领域技术人员可以根据实际需要进行选择。
在一些实施例中，有源结构的材料为氧化物半导体材料。举例来说，有源结构中的沟道层20、源极区11和漏极区12的材料均为氧化物半导体材料。在一示例中，氧化物半导体材料为In 2O 3(氧化铟)、ZnO(氧化锌)、IZO(氧化铟锌)、IGZO(铟镓锌氧化物)、IZTO(铟锡锌氧化物)、ZnON(氮氧化锌)中的任一种或者两种以上的组合。优选的，有源结构的材料为IGZO。
本公开实施例一些实施例提供的半导体结构及其形成方法，通过将晶体管结构中的至少部分有源结构环绕栅极层的外周分布，形成沟道全环绕的晶体管结构，同时，将晶体管结构中的有源结构设置为沿平行于衬底的顶面方向(例如第二方向)延伸的U形，从而在提高晶体管结构栅控能力的同时，降低半导体结构的功耗，从而实现对半导体结构电性能的提高。另外，本公开实施例一些实施例在形成半导体结构时，通过去除堆叠层中的牺牲层来形成沟道层，因而无需通过复杂的外延生长工艺和掺杂工艺来形成沟道层，简化了半导体结构的制程工艺，且有助于提高半导体结构中堆叠结构的堆叠高度，并提高半导体结构的制造良率。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (23)

  1. 一种半导体结构，包括：
    衬底；
    堆叠结构，位于所述衬底上，所述堆叠结构包括沿第一方向间隔排布的多个存储单元，所述存储单元包括晶体管结构，所述晶体管结构包括有源结构和栅极层，至少部分所述有源结构环绕部分所述栅极层的外周分布，且所述有源结构在所述衬底的顶面上的投影的形状为朝第二方向开口的U形，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交。
  2. 根据权利要求1所述的半导体结构，其中，所述栅极层包括：
    第一栅极层，部分所述有源结构环绕所述第一栅极层的外周分布；
    第二栅极层，所述第二栅极层至少环绕部分所述有源结构的外周分布，且所述第一栅极层电连接所述第二栅极层。
  3. 根据权利要求2所述的半导体结构，还包括：
    字线，沿所述第一方向延伸，并与沿所述第一方向间隔排布的多个所述存储单元内的所述第一栅极层和所述第二栅极层电连接。
  4. 根据权利要求3所述的半导体结构，其中，所述字线位于所述存储单元沿所述第二方向的端部，且与所述第一栅极层沿所述第二方向的端部和所述第二栅极层沿所述第二方向的端部接触电连接。
  5. 根据权利要求3所述的半导体结构，其中，所述有源结构包括：
    沟道层，沿所述第一方向延伸，所述沟道层环绕所述第一栅极层的外周分布，所述第二栅极层环绕所述沟道层的外周分布；
    源极区，沿所述第二方向凸设于所述沟道层的背离所述字线的侧面；
    漏极区，沿所述第二方向凸设于所述沟道层的背离所述字线的侧面，所述源极区和所述漏极区间隔位于所述沟道层沿所述第一方向的相对两端。
  6. 根据权利要求5所述的半导体结构，其中，所述晶体管结构还包括：
    第一栅介质层，位于所述第一栅极层与所述沟道层之间；
    第二栅介质层，位于所述第二栅极层与所述沟道层之间，且所述第一栅介质层沿第三方向的厚度小于或者等于所述第二栅介质层沿所述第三方向的厚度，其中，所述第三方向与所述衬底的顶面垂直；
    第一绝缘介质层，位于所述字线和所述沟道层之间。
  7. 根据权利要求2所述的半导体结构，其中，所述第一栅极层沿第三方向的厚度大于或者等于所述第二栅极层沿所述第三方向的厚度，其中，所述第三方向与所述衬底的顶面垂直。
  8. 根据权利要求5所述的半导体结构，其中，所述存储单元还包括：
    电容结构，沿所述第二方向延伸，包括与所述晶体管结构的所述漏极区接触电连接的下电极层、覆盖所述下电极层的电介质层、以及覆盖所述电介质层的上电极层。
  9. 根据权利要求8所述的半导体结构，其中，所述堆叠结构包括沿第三方向间隔排布的多个存储层，每个所述存储层包括沿所述第一方向间隔排布的多个所述存储单元，其中，所述第三方向与所述衬底的顶面垂直；所述半导体结构还包括：
    位线，沿所述第三方向延伸，且与沿所述第三方向间隔排布的多个所述存储单元中的所述源极区电连接。
  10. 根据权利要求9所述的半导体结构，还包括：
    第一支撑柱，沿所述第三方向延伸，且所述第一支撑柱位于所述电容结构与所述位线之间；
    第二支撑柱，沿所述第三方向延伸，且所述第二支撑柱位于沿所述第一方向相邻的所述存储单元之 间；
    层间绝缘层，位于沿第三方向间隔排布的相邻所述存储层之间。
  11. 根据权利要求1所述的半导体结构，其中，所述有源结构的材料为氧化物半导体。
  12. 一种半导体结构的形成方法，包括如下步骤：
    提供衬底；
    形成堆叠层于所述衬底上，所述堆叠层包括沿第一方向间隔排布的多个存储区域，其中，所述第一方向与所述衬底的顶面平行；
    于所述存储区域形成包括晶体管结构的存储单元，所述晶体管结构包括有源结构和栅极层，至少部分所述有源结构环绕部分所述栅极层的外周分布，且所述有源结构在所述衬底的顶面上的投影的形状为朝第二方向开口的U形，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，形成堆叠层于所述衬底上的步骤包括：
    于所述衬底上形成沿第三方向交替堆叠的层间绝缘层和堆叠单元层，所述堆叠单元层包括沿所述第三方向依次堆叠的第一隔离层、牺牲层、和第二隔离层，其中，所述第三方向与所述衬底的顶面垂直。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，于所述存储区域形成包括晶体管结构的存储单元之前，还包括如下步骤：
    刻蚀所述堆叠层，形成位于所述存储区域内的第一支撑槽、以及位于沿所述第一方向相邻的所述存储区域之间的第二支撑槽；
    于所述第一支撑槽内形成第一支撑柱、并于所述第二支撑槽内形成第二支撑柱。
  15. 根据权利要求13所述的半导体结构的形成方法，其中，所述存储区域包括晶体管区域、以及沿所述第二方向位于所述晶体管区域外部的电容区域；于所述存储区域形成包括晶体管结构的存储单元的步骤包括：
    去除所述晶体管区域的所述牺牲层，形成第一沟槽；
    于所述第一沟槽内形成第一栅极层、以及环绕所述第一栅极层的外周分布的沟道层，所述栅极层包括所述第一栅极层，所述有源结构包括所述沟道层。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，形成第一沟槽之前，还包括如下步骤：
    去除所述晶体管区域的所述第一隔离层和所述第二隔离层，于所述堆叠单元内形成位于所述牺牲层在所述第三方向上相对两侧的第二沟槽和第三沟槽；
    于所述第二沟槽和所述第三沟槽内形成覆盖于所述牺牲层上的第二栅极层，所述栅极层包括所述第一栅极层和所述第二栅极层。
  17. 根据权利要求16所述的半导体结构的形成方法，其中，于所述第二沟槽和所述第三沟槽内形成覆盖于所述牺牲层上的第二栅极层的具体步骤包括：
    形成覆盖所述第二沟槽内壁和所述第三沟槽内壁的第二栅介质层；
    于所述第二沟槽内和所述第三沟槽内形成覆盖于所述第二栅介质层上的所述第二栅极层。
  18. 根据权利要求17所述的半导体结构的形成方法，其中，于所述第一沟槽内形成第一栅极层、以及环绕所述第一栅极层的外周分布的所述沟道层的具体步骤包括：
    形成覆盖所述第一沟槽的整个内壁的所述沟道层；
    于所述第一沟槽内形成位于所述沟道层上的所述第一栅极层，且所述第一栅极层沿所述第三方向的厚度大于或者等于所述第二栅极层沿所述第三方向的厚度。
  19. 根据权利要求18所述的半导体结构的形成方法，其中，于所述第一沟槽内形成位于所述沟道层上的所述第一栅极层的步骤包括：
    于所述第一沟槽内形成覆盖于所述沟道层上的第一栅介质层，所述第一栅介质层沿所述第三方向的厚度小于或者等于所述第二栅介质层沿所述第三方向的厚度；
    于所述第一沟槽内形成覆盖于所述第一栅介质层上的所述第一栅极层。
  20. 根据权利要求16所述的半导体结构的形成方法，其中，于所述第一沟槽内形成第一栅极层、以及环绕所述第一栅极层的外周分布的所述沟道层之后，还包括如下步骤：
    于所述衬底上形成沿所述第一方向延伸的字线，所述字线与沿所述第一方向间隔排布的多个所述存储单元内的所述第一栅极层和所述第二栅极层电连接。
  21. 根据权利要求20所述的半导体结构的形成方法，其中，于所述衬底上形成沿所述第一方向延伸的字线的步骤包括：
    沿所述第二方向去除部分的所述沟道层，形成第四沟槽；
    于所述第四沟槽内形成第一绝缘介质层；
    于所述晶体管结构沿所述第二方向的端部形成沿所述第一方向延伸的字线，所述字线与所述第一栅极层沿所述第二方向的端部和所述第二栅极层沿所述第二方向的端部接触电连接。
  22. 根据权利要求20所述的半导体结构的形成方法，其中，所述存储区域还包括位于所述晶体管区域沿所述第二方向的同一侧的电容区域和位线区域，所述电容区域和所述位线区域沿所述第一方向间隔排布；于所述衬底上形成沿所述第一方向延伸的字线之后，还包括如下步骤：
    去除所述位线区域的所述堆叠层、并去除所述晶体管区域的部分所述牺牲层，形成位于所述位线区域的第五沟槽、以及位于所述晶体管区域内的源极槽，所述源极槽露出所述沟道层沿所述第三方向的端部；
    于所述源极槽内形成与所述沟道层接触电连接的源极区；
    于所述第五沟槽内形成与所述源极区接触电连接的位线。
  23. 根据权利要求22所述的半导体结构的形成方法，其中，于所述衬底上形成沿所述第一方向延伸的字线之后，还包括如下步骤：
    去除所述电容区域的所述牺牲层、并去除所述晶体管区域保留的所述牺牲层，形成位于所述电容区域的电容槽、以及位于所述晶体管区域内的漏极槽，所述电容槽露出所述沟道层沿所述第三方向的端部；
    于所述漏极槽内形成与所述沟道层接触电连接的漏极区；
    于所述电容槽内形成与所述漏极区接触电连接的电容结构。
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