WO2023231196A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2023231196A1
WO2023231196A1 PCT/CN2022/115021 CN2022115021W WO2023231196A1 WO 2023231196 A1 WO2023231196 A1 WO 2023231196A1 CN 2022115021 W CN2022115021 W CN 2022115021W WO 2023231196 A1 WO2023231196 A1 WO 2023231196A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
region
forming
trench
semiconductor
Prior art date
Application number
PCT/CN2022/115021
Other languages
English (en)
French (fr)
Inventor
李晓杰
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/093,779 priority Critical patent/US20230389265A1/en
Publication of WO2023231196A1 publication Critical patent/WO2023231196A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • DRAM Semiconductor structures such as DRAM mostly use two-dimensional structures, which results in low storage density and low integration of semiconductor structures, making it difficult to meet the demand for semiconductor storage capacity in different fields.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to solve the problem of low integration of the semiconductor structure, so as to improve the performance of the semiconductor structure and expand the application field of the semiconductor structure.
  • the present disclosure provides a method for forming a semiconductor structure, including the following steps:
  • a stacked layer is formed on the top surface of the substrate.
  • the stacked layer includes a plurality of semiconductor layers spaced apart along a first direction.
  • the stacked layer includes a transistor region and is distributed on opposite sides of the transistor region along a second direction.
  • the capacitance region and the bit line region, the semiconductor layer includes semiconductor pillars arranged at intervals along a third direction, the first direction is a direction perpendicular to the top surface of the substrate, the second direction and the The third directions are all directions parallel to the top surface of the substrate, and the second direction intersects the third direction;
  • word line in the transistor area, the word line extending along the third direction and continuously covering the semiconductor pillars arranged at intervals along the third direction;
  • a bit line is formed in the bit line region, the bit line extends along the first direction, and is electrically connected to the semiconductor pillars arranged at intervals along the first direction.
  • the specific steps of forming the stacked layer on the top surface of the substrate include:
  • the stacked layer is etched to form a first trench exposing the substrate, and the first trench separates the semiconductor layer into semiconductor pillars spaced apart along the third direction.
  • the semiconductor pillar includes a conductive pillar located in the capacitor region; the specific steps of forming a capacitor extending along the second direction in the capacitor region include:
  • a conductive layer covering the conductive pillar, a dielectric layer covering the conductive layer, an upper electrode layer covering the dielectric layer, and a common electrode layer covering the upper electrode layer are formed in the first gap to form a structure including The conductive pillar, the conductive layer, the dielectric layer, the upper electrode layer and the capacitor of the common electrode layer.
  • the specific steps of forming a capacitor including the conductive pillar, the conductive layer, the dielectric layer, the upper electrode layer and the common electrode layer include:
  • a first opening is formed between the two semiconductor layers, and the conductive pillar, as well as the conductive layer, the dielectric layer, the upper electrode layer and the common electrode layer remaining in the first gap form the The capacitor.
  • the semiconductor pillar includes an active pillar located in the transistor region, the active pillar includes a channel region, and sources distributed on opposite sides of the channel region along the second direction.
  • the word lines extending along the third direction and continuously covering the channel regions spaced apart along the third direction are formed in the second gap.
  • the specific steps of forming a second gap in the transistor region that exposes at least the channel region, and forming a second trench in the bit line region that exposes the substrate include:
  • the first sacrificial layer of the transistor region is removed along the second trench, and the channel region and the drain region are exposed between two adjacent semiconductor layers in the transistor region. and a second gap in the source region.
  • the bottom of the second trench exposes the top surface of the substrate
  • the second trench extends into the substrate.
  • the stacked layer includes two transistor regions distributed on opposite sides of one bit line region along the second direction, and the transistor region is away from one of the bit line regions.
  • the side has one of the capacitor regions; the specific steps of removing the first sacrificial layer of the transistor region along the second trench include:
  • the first sacrificial layer of the two transistor regions is removed simultaneously along the second trench.
  • the specific step of forming the word lines extending along the third direction in the second gap and continuously covering the channel regions spaced along the third direction includes: :
  • the initial word line layer covering the inner wall of the second gap and the inner wall of the second trench, the initial word line layer at least continuously covering the active pillars arranged at intervals along the third direction;
  • the initial word line layer and the isolation layer in the second trench, above the source region and above the drain region are removed to form a third layer between two adjacent drain regions.
  • Two openings, a third opening located between two adjacent source regions, the initial word line layer remaining above the channel region serves as the word line, and the remaining word line layer remains between the two adjacent word lines.
  • the isolation layer between them serves as a word line isolation layer.
  • the stacked layers include the semiconductor layers and the first sacrificial layer alternately stacked along the first direction, the semiconductor pillars include active pillars located in the transistor region, the active pillars Includes channel area;
  • the thickness of the first sacrificial layer in the first direction is greater than 4 times the gap width between two adjacent channel regions in the semiconductor layer along the third direction.
  • the specific steps of forming an initial word line layer covering the inner wall of the second gap and the inner wall of the second trench include:
  • a lateral atomic layer deposition process is used to form an initial word line layer covering the inner wall of the second gap and the inner wall of the second trench.
  • the dielectric layer in the second trench is removed.
  • the specific step of forming the word lines extending along the third direction in the second gap and continuously covering the channel regions spaced along the third direction includes: :
  • initial word line material along the second trench to form an initial word line layer covering the surface of the initial gate layer.
  • the initial word line layer at least continuously covers all the elements spaced apart along the third direction. Describe the active column;
  • the initial gate layer, the initial word line layer and the isolation layer in the second trench, above the source region and above the drain region are removed to form two adjacent ones.
  • the second opening between the drain regions, the third opening between two adjacent source regions, the initial gate layer remaining above the channel region serves as a gate layer, and the initial gate layer remaining above the gate
  • the initial word line layer above the electrode layer and between the two adjacent gate electrode layers along the third direction serves as the word line, and all remaining words between the two adjacent word lines are
  • the isolation layer serves as a word line isolation layer.
  • the semiconductor layer is made of silicon material including doped ions.
  • the present disclosure also provides a semiconductor structure formed by using the method for forming a semiconductor structure as described in any one of the above.
  • the semiconductor structure and its formation method provided by the present disclosure form a stacked layer on the top surface of the substrate, and the stacked layer includes a plurality of semiconductor layers spaced apart in a direction perpendicular to the top surface of the substrate. And each of the semiconductor layers includes a plurality of semiconductor pillars arranged at intervals in a direction parallel to the top surface of the substrate, so that the plurality of semiconductor pillars in the stacked layer are stacked in a three-dimensional array, and are subsequently formed horizontally.
  • Capacitors, horizontal word lines and vertical bit lines transform the traditional two-dimensional semiconductor structure into a three-dimensional semiconductor structure. While improving the integration of the semiconductor structure, it can also increase the storage density of the semiconductor structure and improve the performance of the semiconductor structure.
  • the present disclosure can also enable two transistors to share a bit line, thereby helping to further reduce the size of the semiconductor structure and increase the storage capacity of the semiconductor structure.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • 2-23 is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to the specific embodiment of the present disclosure.
  • FIG. 1 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure.
  • Figures 2-23 are diagrams of the process of forming the semiconductor structure in the specific embodiment of the present disclosure. Schematic diagram of the main process structure.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the method for forming the semiconductor structure includes the following steps:
  • Step S11 forming a stacked layer 21 on the top surface of the substrate 20.
  • the stacked layer 21 includes a plurality of semiconductor layers 212 spaced apart along the first direction D1.
  • the stacked layer 21 includes a transistor region and a transistor region along the second direction.
  • D2 is distributed in the capacitor area and the bit line area on opposite sides of the transistor area.
  • the semiconductor layer 212 includes semiconductor pillars 26 spaced apart along the third direction D3.
  • the first direction D1 is perpendicular to the substrate.
  • the direction of the top surface of the substrate 20 , the second direction D2 and the third direction D3 are both directions parallel to the top surface of the substrate 20 , and the second direction D2 intersects the third direction D3 , as shown in Figure 5, wherein (a) in Figure 5 is a schematic structural view from above, and (b) in Figure 5 is a schematic cross-sectional view of (a) in Figure 5 at position AA.
  • the substrate 20 may be, but is not limited to, a silicon substrate.
  • the substrate 20 is a silicon substrate as an example for description.
  • the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate 20 is used to support a semiconductor device thereon.
  • the top surface of the substrate 20 refers to the surface of the substrate 20 used to form the stacked layer 21 .
  • specific steps of forming the stacked layer 21 on the top surface of the substrate 20 include:
  • the stacked layer 21 is etched to form a first trench 25 that exposes the substrate 20 .
  • the first trench 25 separates the semiconductor layer 212 into semiconductor pillars arranged at intervals along the third direction D3 26, as shown in Figure 5.
  • epitaxial growth may be used to alternately form the first sacrificial layer 211 and the semiconductor layer 212 on the top surface of the substrate 20 along the first direction D1 to form the stacked layer 21, as shown in FIG. 2 shown.
  • the specific number of alternately deposited layers of the first sacrificial layer 211 and the semiconductor layer 212 in the stacked layer 21 can be selected by those skilled in the art according to actual needs. The more layers the first sacrificial layer 211 and the semiconductor layer 212 are alternately deposited in the stacked layer 21 , the greater the storage capacity of the formed semiconductor structure.
  • the semiconductor layer 212 is made of silicon material including doped ions
  • the first sacrificial layer 211 is made of silicon germanium.
  • the doping ions may be but are not limited to phosphorus ions.
  • a silicon material including doped ions to form the semiconductor layer 212, there is no need to do doping when subsequently forming the channel region, source region and drain region in the transistor, thereby simplifying the formation of the semiconductor structure. Craftsmanship.
  • the silicon material including doped ions and the silicon germanium material have a high etching selectivity ratio, thereby facilitating the subsequent selective removal of the first sacrificial layer 211 without causing damage to the semiconductor layer 212.
  • a second sacrificial layer is deposited on the top surface of the stacked layer 21 .
  • the second sacrificial layer may have a single-layer structure or a multi-layer structure.
  • the second sacrificial layer includes a first liner layer 22 covering the top surface of the stacked layer 21 and a second liner layer 23 located on the top surface of the first liner layer 22 , as shown in Figure 3, wherein (a) in Figure 3 is a schematic top view of the structure, and (b) in Figure 3 is a schematic cross-sectional view of (a) in Figure 3 at position AA.
  • the material of the first liner layer 22 may be, but is not limited to, an oxide material (such as silicon dioxide), and the material of the second liner layer 23 may be, but is not limited to, a nitride material (such as silicon nitride). ).
  • the plurality mentioned in this specific embodiment refers to two or more.
  • a patterned first photoresist layer 24 is formed on the surface of the second liner layer 23, and the first photoresist layer 24 has a first etching window 241 exposing the second liner layer 23,
  • (a) in Figure 4 is a schematic top view of the structure
  • (b) in Figure 4 is a schematic cross-sectional view of (a) in Figure 4 at position AA.
  • the second liner layer 23 , the first liner layer 22 and the stacked layer 21 are etched downward along the first etching window 241 to form a plurality of first liner layers exposing the substrate 20 .
  • a trench 25, and a plurality of the first trenches 25 are spaced apart along the third direction D3, thereby dividing each of the semiconductor layers 212 into a plurality of spaced apart ones along the third direction D3.
  • Semiconductor pillars 26 are formed, and each first sacrificial layer 211 is divided into a plurality of sacrificial pillars 27 spaced apart along the third direction D3, as shown in FIG. 5 .
  • the first liner layer 22 and the second liner layer 23 are used to improve the morphology of the first trench on the one hand, and to avoid patterning the first photoresist layer 24 on the other hand.
  • the process causes damage to the semiconductor layer 212 on the topmost layer of the stacked layer 21 .
  • Step S12 Form a capacitor extending along the second direction D2 in the capacitance region, as shown in Figure 12, where (a) in Figure 12 is a schematic top view of the structure, and (b) in Figure 12 is a diagram. (a) in 12 is a schematic cross-sectional view at position AA.
  • the semiconductor pillar 26 includes a conductive pillar 261 located in the capacitor region; the specific steps of forming a capacitor extending along the second direction D2 in the capacitor region include:
  • FIG. 8 wherein in FIG. 8 (a) is a schematic diagram of the structure from above, and (b) in Figure 8 is a schematic cross-sectional view of (a) in Figure 8 at position AA;
  • a conductive layer 301 covering the conductive pillar 261, a dielectric layer 302 covering the conductive layer 301, an upper electrode layer 303 covering the dielectric layer 302, and an upper electrode layer covering the conductive pillar 261 are formed in the first gap 29.
  • the common electrode layer 304 of 303 forms a capacitor including the conductive pillar 261, the conductive layer 301, the dielectric layer 302, the upper electrode layer 303 and the common electrode layer 304.
  • the specific steps of forming a capacitor including the conductive pillar 261, the conductive layer 301, the dielectric layer 302, the upper electrode layer 303 and the common electrode layer 304 include:
  • FIG. 9 An upper electrode layer 303 covering the surface of the dielectric layer 302 is formed, as shown in Figure 9 , where (a) in Figure 9 is a schematic top view of the structure, and (b) in Figure 9 is a schematic diagram of the top view of (a) in Figure 9 Cross-sectional diagram of AA position;
  • a common electrode layer 304 covering the surface of the upper electrode layer 303 is formed, as shown in Figure 10 , where (a) in Figure 10 is a schematic top view of the structure, and (b) in Figure 10 is (a) in Figure 10 Schematic cross-section at position AA;
  • the first opening 31 is formed between the two adjacent semiconductor layers 212 in the area, the conductive pillar 261, and the conductive layer 301, the dielectric layer 302, and the remaining in the first gap 29.
  • the upper electrode layer 303 and the common electrode layer 304 form the capacitor, as shown in FIG. 12 .
  • the third sacrificial layer 28 is formed on the surface of the second liner layer 23, as shown in Figure 6, where (a) in Figure 6 is a schematic top view of the structure, and (b) in Figure 6 is (a) in Figure 6 is a schematic cross-sectional view at position AA.
  • the material of the third sacrificial layer 28 may be, but is not limited to, an oxide material (such as silicon dioxide).
  • a patterned second photoresist layer is formed on the surface of the third sacrificial layer 28 , and the second photoresist layer has a second etching window exposing the third sacrificial layer 28 .
  • a lateral atomic layer deposition process is used to continuously deposit conductive materials such as metal tungsten or TiN on the inner walls of a plurality of first gaps 29 arranged at intervals along the first direction D1 to form a continuous covering of the intervals along the first direction D1
  • conductive materials such as metal tungsten or TiN
  • a plurality of conductive pillars 261 are arranged on the surface of the conductive layer 301 .
  • a material with a higher dielectric constant (HK) is deposited on the surface of the conductive layer 301 to form the dielectric layer 302 .
  • Conductive materials such as metallic tungsten or TiN are deposited on the surface of the dielectric layer 302 to form the upper electrode layer 303, as shown in FIG. 9 .
  • Conductive materials such as polysilicon are deposited in the first gap 29 to form the common electrode layer 304 covering the upper electrode layer 303 and filling the first gap 29, as shown in FIG. 10 .
  • a patterned third photoresist layer is formed above the stacked layer 21, and the third photoresist layer has exposed portions of the conductive layer 301, the dielectric layer 302, and the upper electrode layer 303. and the third etching window of the common electrode layer 304 . Etch the conductive layer 301, the dielectric layer 302, the upper electrode layer 303 and the common electrode layer 304 downward along the third etching window to remove the third layer covering the transistor area.
  • the first opening 31 is formed between the conductive pillar 261 and the conductive layer 301, the dielectric layer 302, the upper electrode layer 303 and the common electrode layer 304 remaining in the first gap 29.
  • the capacitor is shown in Figure 12. Wherein, the conductive pillar 261 and the conductive layer 301 together serve as the lower electrode layer of the capacitor.
  • This specific embodiment facilitates the formation of the capacitive isolation layer 32 to isolate the capacitor and the capacitor by making the length of the first gap 29 along the second direction D2 greater than the length of the capacitor along the second direction D2.
  • the transistor area is used to prevent the subsequent process of forming the word line from causing damage to the formed capacitor.
  • Step S13 Form a word line 40 in the transistor area.
  • the word line 40 extends along the third direction D3 and continuously covers the semiconductor pillars 26 arranged at intervals along the third direction D3, as shown in
  • (a) in Figure 18 is a schematic top view of the structure
  • (b) in Figure 18 is a schematic cross-sectional view of (a) in Figure 18 at position AA
  • (c) in Figure 18 is a diagram (a) in 18 is a schematic cross-sectional view at the BB position.
  • the semiconductor pillar 26 includes an active pillar 36 located in the transistor region (see FIG. 18 ).
  • the active pillar 36 includes a channel region and is distributed along the second direction D2.
  • the source region and the drain region on opposite sides of the channel region, the drain region is adjacent to the capacitor region, and the source region is adjacent to the bit line region; formed in the transistor region
  • the specific steps of word line 40 include:
  • Figure 15 is a schematic top view of the structure
  • Figure 15 is a schematic diagram of the structure in Figure 15
  • (a) is a schematic cross-sectional view at position AA
  • (c) in Figure 15 is a schematic cross-sectional view of (a) at position BB in Figure 15;
  • the word lines 40 extending along the third direction D3 and continuously covering the channel regions arranged at intervals along the third direction D3 are formed in the second gap 35 , as shown in FIG. 18 .
  • the specific steps of forming a second gap 35 in the transistor region that exposes at least the channel region, and forming a second trench 34 in the bit line region that exposes the substrate include: :
  • FIG. 14 where (a) in FIG. 14 is a top view.
  • Structural schematic diagram, (b) in Figure 14 is a schematic cross-sectional view of (a) in Figure 14 at position AA;
  • the first sacrificial layer 211 in the transistor region is removed along the second trench 34, and the channel region is exposed between the two adjacent semiconductor layers 212 in the transistor region.
  • the second gap 35 between the drain region and the source region is as shown in FIG. 15 .
  • the bottom of the second trench 34 exposes the top surface of the substrate 20 , that is, the substrate 20 is used as an etching stop layer during the etching process, thereby accurately controlling the etching end point. , to avoid causing damage to the substrate 20 .
  • the second trench 34 extends to the inside of the substrate 20 to increase the contact area between bit lines subsequently formed in the second trench 34 and the substrate 20 .
  • the stacked layer 21 includes two transistor regions distributed on opposite sides of one bit line region along the second direction D2, and the transistor region is away from the bit line region. has one side of the capacitor region; the specific steps of removing the first sacrificial layer 211 of the transistor region along the second trench 34 include:
  • the first sacrificial layer 211 of the two transistor regions is removed simultaneously along the second trench 34 .
  • one bit line region is provided in the stacked layer 21, and one transistor region is provided on opposite sides of the bit line region distributed along the second direction D2, and each transistor region is A capacitor region is provided on one side of each transistor region away from the bit line region, so that two subsequently formed transistors can share a bit line, thereby further reducing the volume of the semiconductor structure and improving the quality of the semiconductor structure. degree of integration.
  • the word lines 40 extending along the third direction D3 and continuously covering the channel regions spaced apart along the third direction D3 are formed in the second gap 35
  • the specific steps include:
  • An initial word line layer 37 covering the inner wall of the second gap 35 and the inner wall of the second trench 34 is formed, and the initial word line layer 37 at least continuously covers the spaced-apart portions arranged along the third direction D3.
  • the active pillar 36 is as shown in Figure 16, where (a) in Figure 16 is a schematic structural view from above, (b) in Figure 16 is a schematic cross-sectional view of (a) in Figure 16 at position AA, in Figure 16 (c) is a schematic cross-sectional view of (a) in Figure 16 at the BB position, and (d) in Figure 16 is an enlarged schematic view in the dotted box of (c) in Figure 16;
  • An isolation layer 39 is formed to cover the surface of the initial word line layer 37 and fill the second gap 35 and the second trench 34 , as shown in FIG. 17 , where (a) in FIG. 17 is a top view.
  • Structural diagram (b) in Figure 17 is a schematic cross-sectional view of (a) in Figure 17 at position AA, (c) in Figure 17 is a schematic cross-sectional view of (a) in Figure 17 at position BB;
  • the initial word line layer 37 and the isolation layer 39 in the second trench 34, above the source region and above the drain region are removed to form a layer between the two adjacent drain regions.
  • the second opening between two adjacent source regions, the third opening between two adjacent source regions, the initial word line layer 37 remaining above the channel region serves as the word line 40, and the remaining two adjacent source regions are used as the word line 40.
  • the isolation layer 39 between the word lines 40 serves as a word line isolation layer 41, as shown in FIG. 18 .
  • the specific steps of forming the initial word line layer 37 covering the inner wall of the second gap 35 and the inner wall of the second trench 34 include:
  • a lateral atomic layer deposition process is used to form an initial word line layer 37 covering the inner wall of the second gap 35 and the inner wall of the second trench 34 .
  • an in-situ water vapor oxidation or a lateral deposition process may be used to form a gate dielectric layer 38 covering the surface of the active pillar 36 , as shown in FIG. 16 .
  • a lateral atomic layer deposition process is used to deposit conductive materials such as metal tungsten or TiN on the surface of the gate dielectric layer 38 to form an initial character covering the inner wall of the second gap 35 and the inner wall of the second trench 34 .
  • Line layer 37 The lateral deposition process can ensure that the initial word line layer 37 fully covers the inner wall of the second gap 35 , thereby further improving the electrical performance of the semiconductor structure.
  • the stacked layer 21 includes the semiconductor layer 212 and the first sacrificial layer 211 that are alternately stacked along the first direction D1, and the semiconductor pillar 26 includes an active pillar 36 located in the transistor region.
  • the active pillar 36 includes a channel region;
  • the thickness A of the first sacrificial layer 211 in the first direction D1 is greater than 4 times the gap width B between the two adjacent channel regions in the semiconductor layer 212 along the third direction D3. , that is, A>4B.
  • the thickness A of the first sacrificial layer 211 in the first direction D1 is greater than the two adjacent channel regions in the semiconductor layer 212 along the third direction D3 4 times the width B of the gap between them, so that when depositing the word line material used to form the initial word line layer 37, the word line materials are first connected into a line along the third direction D3, thereby ensuring that the final The formed word line 40 extends along the third direction D3 and can fully and completely continuously cover all the channel regions in the semiconductor layer 212 that are spaced along the third direction D3.
  • the word lines extending along the third direction D3 and continuously covering the channel regions spaced apart along the third direction D3 are formed in the second gap 35 40 specific steps include:
  • Gate material is deposited on the inner wall of the second gap 35 and the inner wall of the second trench 34 along the second trench 34 to form an initial gate layer 50 covering the active pillar 36.
  • the two adjacent initial gate layers 50 in the third direction D3 are independent of each other, as shown in FIG. 22 , where (c) in FIG. 22 is a schematic cross-sectional structural diagram, and (d) in FIG. 22 is a schematic diagram of the cross-sectional structure. (c) The enlarged diagram in the dotted box;
  • Initial word line material is deposited along the second trench 34 to form an initial word line layer 37 covering the surface of the initial gate layer 50 .
  • the initial word line layer 37 at least continuously covers the surface along the third direction D3
  • the active pillars 36 are arranged at intervals, as shown in Figure 23, where (c) in Figure 23 is a schematic cross-sectional structural diagram, and (d) in Figure 23 is the dotted line frame in (c) in Figure 23 Enlarge the diagram;
  • the initial gate layer 50 , the initial word line layer 37 and the isolation layer in the second trench 34 , above the source region and above the drain region are removed to form two adjacent layers.
  • a second opening between two drain regions, a third opening between two adjacent source regions, the initial gate layer 50 remaining above the channel region serves as a gate layer, and the remaining initial gate layer 50 above the channel region serves as a gate layer.
  • the initial word line layer 37 above the gate layer and between the two adjacent gate layers along the third direction D3 serves as the word line, remaining in the two adjacent gate layers.
  • the isolation layer between word lines serves as a word line isolation layer.
  • an in-situ water vapor oxidation or lateral deposition process may be used to form a gate dielectric layer covering the surface of the active pillar 36 .
  • conductive materials such as TiN are deposited on the surface of the gate dielectric layer using a lateral atomic layer deposition process to form the initial gate layer 50 located above the gate dielectric layer.
  • the plurality of initial gate layers 50 are respectively located above the plurality of channel regions, and any two adjacent initial gate layers 50 are independent of each other.
  • a lateral atomic layer deposition process is used to deposit metal tungsten and other conductive materials on the surface of the initial gate layer 50 to form at least all the active pillars 36 that are continuously covered at intervals along the third direction D3.
  • the initial word line layer 37 By first forming the initial gate layer 50 , on the one hand, it can be further ensured that the subsequently formed initial word line layer 37 can fully and continuously cover the channels arranged at intervals along the third direction D3 area; on the other hand, the adhesion between the initial word line layer 37 and the initial gate layer 50 can also be enhanced.
  • Step S14 Form a bit line 44 in the bit line region.
  • the bit line 44 extends along the first direction D1 and is in contact and electrically connected with the semiconductor pillars 26 arranged at intervals along the first direction D1.
  • FIG 21 where (a) in Figure 21 is a schematic structural view from above, (b) in Figure 21 is a schematic cross-sectional view of (a) in Figure 21 at position AA, and (c) in Figure 21 This is a schematic cross-sectional view of (a) at the BB position in Figure 21.
  • a dielectric layer 43 filled with the first opening 31, the second opening, the third opening and the second trench 34 is formed, as shown in Figure 20, wherein (a) in Figure 20 is Top structural schematic diagram, (b) in Figure 20 is a schematic cross-sectional view of (a) in Figure 20 at position AA, (c) in Figure 20 is a schematic cross-sectional view of (a) in Figure 20 at position BB;
  • the dielectric layer 43 in the second trench 34 is removed.
  • bit lines 44 are electrically connected to the source regions of the semiconductor pillars 26 arranged at intervals along the first direction D1, and one of the bit lines 44 is simultaneously connected to the source regions along the second direction D2.
  • the two source regions located on opposite sides of the bit line 44 are contacted and electrically connected.
  • This specific embodiment also provides a semiconductor structure, which can be formed using the semiconductor structure forming method as shown in FIGS. 1 to 23 .
  • the schematic diagram of the semiconductor structure provided in this specific embodiment can be seen in FIG. 21 .
  • the semiconductor structure and its formation method provided by this embodiment are formed by forming a stacked layer on the top surface of the substrate, and the stacked layer includes a plurality of semiconductors spaced apart in a direction perpendicular to the top surface of the substrate. layer, and each of the semiconductor layers includes a plurality of semiconductor pillars arranged at intervals in a direction parallel to the top surface of the substrate, so that the plurality of semiconductor pillars in the stacked layer are stacked in a three-dimensional array. Subsequently, Horizontal capacitors, horizontal word lines and vertical bit lines are formed to transform the traditional two-dimensional semiconductor structure into a three-dimensional semiconductor structure. While improving the integration of the semiconductor structure, it can also increase the storage density of the semiconductor structure and improve the performance of the semiconductor structure. In addition, this specific embodiment can also realize that two transistors share a bit line, thereby helping to further reduce the size of the semiconductor structure and increase the storage capacity of the semiconductor structure.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构的形成方法包括如下步骤：形成堆叠层于衬底的顶面，所述堆叠层包括沿第一方向间隔排布的多个半导体层，所述堆叠层包括晶体管区域、电容区域和位线区域，所述半导体层包括沿第三方向间隔排布的半导体柱；于所述电容区域内形成沿所述第二方向延伸的电容器；于所述晶体管区域内形成字线，所述字线沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述半导体柱；于所述位线区域内形成位线，所述位线沿所述第一方向延伸。本公开在提高半导体结构集成度的同时，还能够增大半导体结构的存储密度，改善半导体结构的性能。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年05月30日递交的中国专利申请号202210614481.X、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
DRAM等半导体结构多采用二维结构，从而导致半导体结构的存储密度和集成度均不高，难以满足不同领域对半导体存储容量的需求。
因此，如何提高半导体结构的集成度，从而改善半导体结构的性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于解决半导体结构的集成度较低的问题，以改善半导体结构的性能，扩大半导体结构的应用领域。
根据一些实施例，本公开提供了一种半导体结构的形成方法，包括如下步骤：
形成堆叠层于衬底的顶面，所述堆叠层包括沿第一方向间隔排布的多个半导体层，所述堆叠层包括晶体管区域、以及沿第二方向分布于所述晶体管区域相对两侧的电容区域和位线区域，所述半导体层包括沿第三方向间隔排布的半导体柱，所述第一方向为垂直于所述衬底的顶面的方向，所述第二方向和所述第三方向均为平行于所述衬底的顶面的方向，且所述第二方向与所述第三方向相交；
于所述电容区域内形成沿所述第二方向延伸的电容器；
于所述晶体管区域内形成字线，所述字线沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述半导体柱；
于所述位线区域内形成位线，所述位线沿所述第一方向延伸、且与沿所述第一方向间隔排布的所述半导体柱接触电连接。
在一些实施例中，形成堆叠层于衬底的顶面的具体步骤包括：
沿所述第一方向交替沉积半导体层和第一牺牲层于所述衬底的顶面，形成所述堆叠层；
刻蚀所述堆叠层，形成暴露所述衬底的第一沟槽，所述第一沟槽将所述半导体层分隔为沿所述第三方向间隔排布的半导体柱。
在一些实施例中，于所述半导体柱包括位于所述电容区域的导电柱；于所述电容区域内形成沿所述第二方向延伸的电容器的具体步骤包括：
去除所述电容区域的所述第一牺牲层，形成位于所述电容区域内的相邻两层所述半导体层之间的第一空隙；
于所述第一空隙内形成覆盖所述导电柱的导电层、覆盖所述导电层的电介质层、覆盖所述电介质层的上电极层、以及覆盖所述上电极层的公共电极层，形成包括所述导电柱、所述导电层、所述电介质层、所述上电极层和所述公共电极层的电容器。
在一些实施例中，形成包括所述导电柱、所述导电层、所述电介质层、所述上电极层和所述公共电极层的电容器的具体步骤包括：
形成连续覆盖沿所述第一方向间隔排布的所述第一空隙的内壁的导电层；
形成覆盖所述导电层表面的电介质层；
形成覆盖所述电介质层表面的上电极层；
形成覆盖所述上电极层表面的公共电极层；
去除覆盖于所述晶体管区域内的所述第一牺牲层侧壁上的所述导电层、所述电介质层、所述上电极层和所述公共电极层，于所述电容区域内相邻的两层所述半导体层之间形成第一开口，所述导电柱、以 及所述第一空隙内残留的所述导电层、所述电介质层、所述上电极层和所述公共电极层形成所述电容器。
在一些实施例中，所述半导体柱包括位于所述晶体管区域的有源柱，所述有源柱包括沟道区、以及沿所述第二方向分布于所述沟道区相对两侧的源极区和漏极区，所述漏极区与所述电容区域相邻，所述源极区与所述位线区域相邻；于所述晶体管区域内形成字线的具体步骤包括：
去除所述晶体管区域的所述第一牺牲层、以及所述位线区域的所述堆叠层，于所述晶体管区域内形成至少暴露所述沟道区的第二空隙、并于所述位线区域内形成暴露所述衬底的第二沟槽；
于所述第二空隙内形成沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述沟道区的所述字线。
在一些实施例中，于所述晶体管区域内形成至少暴露所述沟道区的第二空隙、并于所述位线区域内形成暴露所述衬底的第二沟槽的具体步骤包括：
形成填充满所述第一开口的电容隔离层；
去除所述位线区域的所述堆叠层，于所述位线区域形成暴露所述衬底的第二沟槽；
沿所述第二沟槽去除所述晶体管区域的所述第一牺牲层，于所述晶体管区域内的相邻两层所述半导体层之间形成暴露所述沟道区、所述漏极区和所述源极区的第二空隙。
在一些实施例中，所述第二沟槽的底部暴露所述衬底的顶面；或者，
所述第二沟槽延伸至所述衬底内部。
在一些实施例中，所述堆叠层中包括沿所述第二方向分布于一个所述位线区域相对两侧的两个所述晶体管区域，且所述晶体管区域背离所述位线区域的一侧具有一个所述电容区域；沿所述第二沟槽去除所述晶体管区域的所述第一牺牲层的具体步骤包括：
沿所述第二沟槽同时去除两个所述晶体管区域的所述第一牺牲层。
在一些实施例中，于所述第二空隙内形成沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述沟道区的所述字线的具体步骤包括：
形成覆盖所述第二空隙内壁和所述第二沟槽的内壁的初始字线层，所述初始字线层至少连续包覆沿所述第三方向间隔排布的所述有源柱；
形成覆盖所述初始字线层表面、并填充满所述第二空隙和所述第二沟槽的隔离层；
去除所述第二沟槽内、所述源极区上方和所述漏极区上方的所述初始字线层和所述隔离层，形成位于相邻两个所述漏极区域之间的第二开口、位于相邻两个源极区之间的第三开口，残留于所述沟道区上方的所述初始字线层作为所述字线，残留于相邻两条所述字线之间的所述隔离层作为字线隔离层。
在一些实施例中，所述堆叠层包括沿所述第一方向交替堆叠的所述半导体层和第一牺牲层，所述半导体柱包括位于所述晶体管区域的有源柱，所述有源柱包括沟道区；
所述第一牺牲层在所述第一方向上的厚度大于4倍的所述半导体层中沿所述第三方向相邻的两个所述沟道区之间间隙宽度。
在一些实施例中，形成覆盖所述第二空隙内壁和所述第二沟槽的内壁的初始字线层的具体步骤包括：
采用侧向原子层沉积工艺形成覆盖所述第二空隙内壁和所述第二沟槽的内壁的初始字线层。
在一些实施例中，于所述位线区域内形成位线之前，还包括如下步骤：
去除所述电容隔离层；
形成填充满所述第一开口、所述第二开口、所述第三开口和所述第二沟槽的介质层；
去除所述第二沟槽内的所述介质层。
在一些实施例中，于所述第二空隙内形成沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述沟道区的所述字线的具体步骤包括：
沿所述第二沟槽沉积栅极材料于所述第二空隙内壁和所述第二沟槽的内壁，形成包覆所述有源柱的初始栅极层，沿所述第三方向相邻的两个所述初始栅极层相互独立；
沿所述第二沟槽沉积初始字线材料，形成覆盖于所述初始栅极层表面的初始字线层，所述初始字线层至少连续包覆沿所述第三方向间隔排布的所述有源柱；
形成覆盖所述初始字线层表面、并填充满所述第二空隙和所述第二沟槽的隔离层；
去除所述第二沟槽内、所述源极区上方和所述漏极区上方的所述初始栅极层、所述初始字线层和所 述隔离层，形成位于相邻两个所述漏极区之间的第二开口、位于相邻两个源极区之间的第三开口，残留于所述沟道区上方的所述初始栅极层作为栅极层，残留于所述栅极层上方、以及沿所述第三方向相邻的两个所述栅极层之间的所述初始字线层作为所述字线，残留于相邻两条所述字线之间的所述隔离层作为字线隔离层。
在一些实施例中，所述半导体层的材料为包括掺杂离子的硅材料。
根据另一些实施例，本公开还提供了一种半导体结构，采用如上任一项所述的半导体结构的形成方法形成。
本公开提供的半导体结构及其形成方法，通过形成堆叠层于衬底的顶面，且所述堆叠层中包括沿垂直于所述衬底的顶面的方向间隔排布的多个半导体层，且每个所述半导体层包括沿平行于所述衬底的顶面的方向间隔排布的多个半导体柱，从而使得所述堆叠层中的多个半导体柱呈三维阵列堆叠，后续通过形成水平电容器、水平字线和垂直位线，将传统的二维半导体结构转变为三维半导体结构，在提高半导体结构集成度的同时，还能够增大半导体结构的存储密度，改善半导体结构的性能。另外，本公开还能实现两个晶体管共享一条位线，从而有助于进一步缩小半导体结构的尺寸，提高半导体结构的存储容量。
附图说明
附图1是本公开具体实施方式中半导体结构的形成方法流程图；
附图2-23是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本公开具体实施方式中半导体结构的形成方法流程图，附图2-23是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。本具体实施方式中所述的半导体结构可以是但不限于DRAM。如图1-图23所示，所述半导体结构的形成方法，包括如下步骤：
步骤S11，形成堆叠层21于衬底20的顶面，所述堆叠层21包括沿第一方向D1间隔排布的多个半导体层212，所述堆叠层21包括晶体管区域、以及沿第二方向D2分布于所述晶体管区域相对两侧的电容区域和位线区域，所述半导体层212包括沿第三方向D3间隔排布的半导体柱26，所述第一方向D1为垂直于所述衬底20的顶面的方向，所述第二方向D2和所述第三方向D3均为平行于所述衬底20的顶面的方向，且所述第二方向D2与所述第三方向D3相交，如图5所示，其中，图5中的(a)为俯视结构示意图，图5中的(b)为图5中的(a)在AA位置的截面示意图。
具体来说，所述衬底20可以是但不限于硅衬底，本具体实施方式以所述衬底20为硅衬底为例进行说明。在其他示例中，所述衬底20可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20用于支撑在其上方的半导体器件。所述衬底20的顶面是指所述衬底20用于形成所述堆叠层21的表面。
在一些实施例中，形成堆叠层21于衬底20的顶面的具体步骤包括：
沿所述第一方向D1交替沉积半导体层212和第一牺牲层211于所述衬底20的顶面，形成所述堆叠层21，如图2所示，其中，图2中的(a)为俯视结构示意图，图2中的(b)为图2中的(a)在AA位置的截面示意图；
刻蚀所述堆叠层21，形成暴露所述衬底20的第一沟槽25，所述第一沟槽25将所述半导体层212分隔为沿所述第三方向D3间隔排布的半导体柱26，如图5所示。
具体来说，可以采用外延生长的方式沿所述第一方向D1交替形成第一牺牲层211和所述半导体层212于所述衬底20的顶面，形成所述堆叠层21，如图2所示。所述堆叠层21中所述第一牺牲层211和所述半导体层212交替沉积的具体层数，本领域技术人员可以根据实际需要进行选择。所述堆叠层21中所述第一牺牲层211和所述半导体层212交替沉积的层数越多，形成的所述半导体结构的存储容量越大。在一些实施例中，所述半导体层212的材料为包括掺杂离子的硅材料，所述第一牺牲层211的材料为锗化硅。其中，所述掺杂离子可以是但不限于磷离子。通过采用包括掺杂离子的硅材料来形成所述半导体层212，使得后续在形成晶体管中的沟道区、源极区和漏极区时无需再进行掺杂，从而简化所述半导体结构的形成工艺。包括掺杂离子的硅材料与锗化硅材料之间具有较高的刻蚀选择比，从而便于后续 选择性的去除所述第一牺牲层211，而不对所述半导体层212造成损伤。
然后，沉积第二牺牲层于所述堆叠层21的顶面。所述第二牺牲层可以为单层结构，也可以为多层结构。在一实施例中，所述第二牺牲层包括覆盖于所述堆叠层21顶面的的第一衬垫层22、以及位于所述第一衬垫层22顶面的第二衬垫层23，如图3所示，其中，图3中的(a)为俯视结构示意图，图3中的(b)为图3中的(a)在AA位置的截面示意图。其中，所述第一衬垫层22的材料可以是但不限于氧化物材料(例如二氧化硅)，所述第二衬垫层23的材料可以是但不限于氮化物材料(例如氮化硅)。本具体实施方式中所述的多个是指两个以上。
形成图案化的第一光阻层24于所述第二衬垫层23的表面，且所述第一光阻层24中具有暴露所述第二衬垫层23的第一刻蚀窗口241，如图4所示，其中，图4中的(a)为俯视结构示意图，图4中的(b)为图4中的(a)在AA位置的截面示意图。沿所述第一刻蚀窗口241向下刻蚀所述第二衬垫层23、所述第一衬垫层22和所述堆叠层21，形成多个暴露所述衬底20的所述第一沟槽25，且多个所述第一沟槽25沿所述第三方向D3间隔排布，从而将每个所述半导体层212分隔为沿所述第三方向D3间隔排布的多个半导体柱26，并将每个所述第一牺牲层211分隔为沿所述第三方向D3间隔排布的多个牺牲柱27，如图5所示。所述第一衬垫层22和所述第二衬垫层23一方面用于改善所述第一沟槽的形貌，另一方面还用于避免图案化所述第一光阻层24的工艺对所述堆叠层21最顶层的所述半导体层212造成损伤。
步骤S12，于所述电容区域内形成沿所述第二方向D2延伸的电容器，如图12所示，其中，图12中的(a)为俯视结构示意图，图12中的(b)为图12中的(a)在AA位置的截面示意图。
在一些实施例中，于所述半导体柱26包括位于所述电容区域的导电柱261；于所述电容区域内形成沿所述第二方向D2延伸的电容器的具体步骤包括：
去除所述电容区域的所述第一牺牲层211，形成位于所述电容区域内的相邻两层所述半导体层212之间的第一空隙29，如图8所示，其中，图8中的(a)为俯视结构示意图，图8中的(b)为图8中的(a)在AA位置的截面示意图；
于所述第一空隙29内形成覆盖所述导电柱261的导电层301、覆盖所述导电层301的电介质层302、覆盖所述电介质层302的上电极层303、以及覆盖所述上电极层303的公共电极层304，形成包括所述导电柱261、所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304的电容器。
在一些实施例中，形成包括所述导电柱261、所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304的电容器的具体步骤包括：
形成连续覆盖沿所述第一方向D1间隔排布的所述第一空隙29的内壁的导电层301；
形成覆盖所述导电301表面的电介质层302；
形成覆盖所述电介质层302表面的上电极层303，如图9所示，其中，图9中的(a)为俯视结构示意图，图9中的(b)为图9中的(a)在AA位置的截面示意图；
形成覆盖所述上电极层303表面的公共电极层304，如图10所示，其中，图10中的(a)为俯视结构示意图，图10中的(b)为图10中的(a)在AA位置的截面示意图；
去除覆盖于所述晶体管区域内的所述第一牺牲层211侧壁上的所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304，于所述电容区域内相邻的两层所述半导体层212之间形成第一开口31，所述导电柱261、以及所述第一空隙29内残留的所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304形成所述电容器，如图12所示。
具体来说，形成第三牺牲层28于所述第二衬垫层23的表面，如图6所示，其中，图6中的(a)为俯视结构示意图，图6中的(b)为图6中的(a)在AA位置的截面示意图。所述第三牺牲层28的材料可以是但不限于氧化物材料(例如二氧化硅)。接着，形成图案化的第二光阻层于所述第三牺牲层28表面，所述第二光阻层中具有暴露所述第三牺牲层28的第二刻蚀窗口。沿所述第二刻蚀窗口向下刻蚀所述第三牺牲层28，暴露所述晶体管区域上方的所述第二衬垫层23，如图7所示，其中，图7中的(a)为俯视结构示意图，图7中的(b)为图7中的(a)在AA位置的截面示意图。残留的所述第三牺牲层28覆盖于所述晶体管区域和所述位线区域的所述堆叠层21上方。然后，可以采用侧向刻蚀工艺去除所述电容区域的所述第一牺牲层211，形成位于所述电容区域内的相邻两层所述半导体层212之间的第一空隙29，如图8所示。采用侧向刻蚀工艺形成所述第一空隙29能够简化所述半导体结构的制程工艺，且能够 避免对所述晶体管区域和所述位线区域的所述堆叠层21造成损伤。
采用侧向原子层沉积工艺连续沉积金属钨或者TiN等导电材料于沿所述第一方向D1间隔排布的多个所述第一空隙29的内壁，形成连续覆盖沿所述第一方向D1间隔排布的多个所述导电柱261表面的所述导电层301。接着，沉积具有较高介电常数(HK)的材料于所述导电层301表面，形成所述电介质层302。沉积金属钨或者TiN等导电材料于所述电介质层302表面，形成所述上电极层303，如图9所示。沉积多晶硅等导电材料于所述第一空隙29内，形成覆盖所述上电极层303并填充满所述第一空隙29的所述公共电极层304，如图10所示。去除所述堆叠层21顶面上的所述第一衬垫层22、所述第二衬垫层23、所述第三牺牲层28、所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304之后，得到如图11所示的结构，其中，图11中的(a)为俯视结构示意图，图11中的(b)为图11中的(a)在AA位置的截面示意图。
之后，形成图案化的第三光阻层于所述堆叠层21的上方，且所述第三光阻层中具有暴露部分所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304的第三刻蚀窗口。沿所述第三刻蚀窗口向下刻蚀所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304，去除覆盖于所述晶体管区域内的所述第一牺牲层211侧壁上的所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304，于所述电容区域内相邻的两层所述半导体层212之间形成第一开口31，所述导电柱261、以及所述第一空隙29内残留的所述导电层301、所述电介质层302、所述上电极层303和所述公共电极层304形成所述电容器，如图12所示。其中，所述导电柱261和所述导电层301共同作为所述电容器的下电极层。沉积氧化物等绝缘介质材料于所述第一开口31内，形成电容隔离层32，如图13所示，其中，图13中的(a)为俯视结构示意图，图13中的(b)为图13中的(a)在AA位置的截面示意图。
本具体实施方式通过使得所述第一空隙29沿所述第二方向D2的长度大于所述电容器沿所述第二方向D2的长度，便于形成所述电容隔离层32来隔离所述电容器和所述晶体管区域，避免后续形成字线的工艺对已形成的所述电容器造成损伤。
步骤S13，于所述晶体管区域内形成字线40，所述字线40沿所述第三方向D3延伸、且连续包覆沿所述第三方向D3间隔排布的所述半导体柱26，如图18所示，其中，图18中的(a)为俯视结构示意图，图18中的(b)为图18中的(a)在AA位置的截面示意图，图18中的(c)为图18中的(a)在BB位置的截面示意图。
在一些实施例中，所述半导体柱26包括位于所述晶体管区域的有源柱36(参见图18)，所述有源柱36包括沟道区、以及沿所述第二方向D2分布于所述沟道区相对两侧的源极区和漏极区，所述漏极区与所述电容区域相邻，所述源极区与所述位线区域相邻；于所述晶体管区域内形成字线40的具体步骤包括：
去除所述晶体管区域的所述第一牺牲层211、以及所述位线区域的所述堆叠层21，于所述晶体管区域内形成至少暴露所述沟道区的第二空隙35、并于所述位线区域内形成暴露所述衬底20的第二沟槽34，如图15所示，其中，图15中的(a)为俯视结构示意图，图15中的(b)为图15中的(a)在AA位置的截面示意图，图15中的(c)为图15中的(a)在BB位置的截面示意图；
于所述第二空隙35内形成沿所述第三方向D3延伸、且连续包覆沿所述第三方向D3间隔排布的所述沟道区的所述字线40，如图18所示。
在一些实施例中，于所述晶体管区域内形成至少暴露所述沟道区的第二空隙35、并于所述位线区域内形成暴露所述衬底的第二沟槽34的具体步骤包括：
形成填充满所述第一开口31的电容隔离层32；
去除所述位线区域的所述堆叠层21，于所述位线区域形成暴露所述衬底20的第二沟槽34，如图14所示，其中，图14中的(a)为俯视结构示意图，图14中的(b)为图14中的(a)在AA位置的截面示意图；
沿所述第二沟槽34去除所述晶体管区域的所述第一牺牲层211，于所述晶体管区域内的相邻两层所述半导体层212之间形成暴露所述沟道区、所述漏极区和所述源极区的第二空隙35，如图15所示。
在一些实施例中，所述第二沟槽34的底部暴露所述衬底20的顶面，即在刻蚀过程中以所述衬底20作为刻蚀截止层，从而准确的控制刻蚀终点，避免对所述衬底20造成损伤。
在另一些实施例中，所述第二沟槽34延伸至所述衬底20内部，以增大后续于所述第二沟槽34内形成的位线与所述衬底20的接触面积。
在一些实施例中，所述堆叠层21中包括沿所述第二方向D2分布于一个所述位线区域相对两侧的两个所述晶体管区域，且所述晶体管区域背离所述位线区域的一侧具有一个所述电容区域；沿所述第二沟槽34去除所述晶体管区域的所述第一牺牲层211的具体步骤包括：
沿所述第二沟槽34同时去除两个所述晶体管区域的所述第一牺牲层211。
具体来说，通过在所述堆叠层21中设置一个所述位线区域，并在沿所述第二方向D2分布于所述位线区域相对两侧各设置一个所述晶体管区域，以及在每个所述晶体管区域背离所述位线区域的一侧设置一个电容区域，从而能够使得后续形成的两个晶体管能够共用一条位线，从而能够进一步缩小所述半导体结构的体积，提高所述半导体结构的集成度。
在一些实施例中，于所述第二空隙35内形成沿所述第三方向D3延伸、且连续包覆沿所述第三方向D3间隔排布的所述沟道区的所述字线40的具体步骤包括：
形成覆盖所述第二空隙35内壁和所述第二沟槽34的内壁的初始字线层37，所述初始字线层37至少连续包覆沿所述第三方向D3间隔排布的所述有源柱36，如图16所示，其中，图16中的(a)为俯视结构示意图，图16中的(b)为图16中的(a)在AA位置的截面示意图，图16中的(c)为图16中的(a)在BB位置的截面示意图，图16中的(d)为图16中的(c)的虚线框中的放大示意图；
形成覆盖所述初始字线层37表面、并填充满所述第二空隙35和所述第二沟槽34的隔离层39，如图17所示，其中，图17中的(a)为俯视结构示意图，图17中的(b)为图17中的(a)在AA位置的截面示意图，图17中的(c)为图17中的(a)在BB位置的截面示意图；
去除所述第二沟槽34内、所述源极区上方和所述漏极区上方的所述初始字线层37和所述隔离层39，形成位于相邻两个所述漏极区域之间的第二开口、位于相邻两个源极区之间的第三开口，残留于所述沟道区上方的所述初始字线层37作为所述字线40，残留于相邻两条所述字线40之间的所述隔离层39作为字线隔离层41，如图18所示。
在一些实施例中，形成覆盖所述第二空隙35内壁和所述第二沟槽34的内壁的初始字线层37的具体步骤包括：
采用侧向原子层沉积工艺形成覆盖所述第二空隙35内壁和所述第二沟槽34的内壁的初始字线层37。
具体来说，在形成所述第二空隙35之后，可以采用原位水汽氧化或者侧向沉积工艺形成覆盖所述有源柱36表面的栅极介质层38，如图16所示。之后，再采用侧向原子层沉积工艺沉积金属钨或者TiN等导电材料于所述栅极介质层38表面，形成覆盖所述第二空隙35内壁和所述第二沟槽34的内壁的初始字线层37。侧向沉积工艺能够确保所述初始字线层37充分覆盖所述第二空隙35的内壁，从而进一步改善所述半导体结构的电性能。
在一些实施例中，所述堆叠层21包括沿所述第一方向D1交替堆叠的所述半导体层212和第一牺牲层211，所述半导体柱26包括位于所述晶体管区域的有源柱36，所述有源柱36包括沟道区；
所述第一牺牲层211在所述第一方向D1上的厚度A大于4倍的所述半导体层212中沿所述第三方向D3相邻的两个所述沟道区之间间隙宽度B，即A＞4B。
具体来说，通过将所述第一牺牲层211在所述第一方向D1上的厚度A设置为大于所述半导体层212中沿所述第三方向D3相邻的两个所述沟道区之间间隙宽度B的4倍，从而使得在沉积用于形成所述初始字线层37的字线材料时，所述字线材料沿所述第三方向D3先连接成一条线，从而确保最终形成的所述字线40沿所述第三方向D3延伸、且能够充分、完全的连续包覆所述半导体层212中沿所述第三方向D3间隔排布的所有所述沟道区。
在另一些实施例中，于所述第二空隙35内形成沿所述第三方向D3延伸、且连续包覆沿所述第三方向D3间隔排布的所述沟道区的所述字线40的具体步骤包括：
沿所述第二沟槽34沉积栅极材料于所述第二空隙35内壁和所述第二沟槽34的内壁，形成包覆所述有源柱36的初始栅极层50，沿所述第三方向D3相邻的两个所述初始栅极层50相互独立，如图22所示，其中，图22中的(c)为截面结构示意图，图22中的(d)为图22中的(c)虚线框中的放大示意图；
沿所述第二沟槽34沉积初始字线材料，形成覆盖于所述初始栅极层50表面的初始字线层37，所述初始字线层37至少连续包覆沿所述第三方向D3间隔排布的所述有源柱36，如图23所示，其中，图23中的(c)为截面结构示意图，图23中的(d)为图23中的(c)虚线框中的放大示意图；
形成覆盖所述初始字线层37表面、并填充满所述第二空隙35和所述第二沟槽34的隔离层；
去除所述第二沟槽34内、所述源极区上方和所述漏极区上方的所述初始栅极层50、所述初始字线层37和所述隔离层，形成位于相邻两个所述漏极区之间的第二开口、位于相邻两个源极区之间的第三开口，残留于所述沟道区上方的所述初始栅极层50作为栅极层，残留于所述栅极层上方、以及沿所述第三方向D3相邻的两个所述栅极层之间的所述初始字线层37作为所述字线，残留于相邻两条所述字线之间的所述隔离层作为字线隔离层。
具体来说，在形成所述第二沟槽34和所述第二空隙35之后，可以采用原位水汽氧化或者侧向沉积工艺形成覆盖所述有源柱36表面的栅极介质层。之后，采用侧向原子层沉积工艺沉积TiN等导电材料于所述栅极介质层表面，形成位于所述栅极介质层上方的所述初始栅极层50。多个所述初始栅极层50分别位于多个所述沟道区上方，且任意相邻的两个所述初始栅极层50相互独立。之后，再采用侧向原子层沉积工艺沉积金属钨等导电材料于所述初始栅极层50表面，形成至少连续包覆沿所述第三方向D3间隔排布的所述有源柱36的所述初始字线层37。通过先形成所述初始栅极层50，一方面，可以进一步确保后续形成的所述初始字线层37能够充分、且连续的包覆沿所述第三方向D3间隔排布的所述沟道区；另一方面，还能够增强所述初始字线层37与所述初始栅极层50之间的粘附性。
步骤S14，于所述位线区域内形成位线44，所述位线44沿所述第一方向D1延伸、且与沿所述第一方向D1间隔排布的所述半导体柱26接触电连接，如图21所示，其中，图21中的(a)为俯视结构示意图，图21中的(b)为图21中的(a)在AA位置的截面示意图，图21中的(c)为图21中的(a)在BB位置的截面示意图。
在一些实施例中，于所述位线区域内形成位线之前，还包括如下步骤：
去除所述电容隔离层32，如图19所示，其中，图19中的(a)为俯视结构示意图，图19中的(b)为图19中的(a)在AA位置的截面示意图，图19中的(c)为图19中的(a)在BB位置的截面示意图；
形成填充满所述第一开口31、所述第二开口、所述第三开口和所述第二沟槽34的介质层43，如图20所示，其中，图20中的(a)为俯视结构示意图，图20中的(b)为图20中的(a)在AA位置的截面示意图，图20中的(c)为图20中的(a)在BB位置的截面示意图；
去除所述第二沟槽34内的所述介质层43。
具体来说，在去除所述第二沟槽37内的所述介质层43之后，可以沉积金属钨等导电材料于所述第二沟槽37内，形成沿所述第一方向D1延伸、且与沿所述第一方向D1间隔排布的所述半导体柱26中的所述源极区接触电连接的所述位线44，且一条所述位线44同时与沿所述第二方向D2位于所述位线44相对两侧的两个所述源极区接触电连接。
本具体实施方式还提供了一种半导体结构，所述半导体结构可以采用如图1-图23所述的半导体结构的形成方法形成。本具体实施方式提供的半导体结构的示意图可以参见图21。
本具体实施方式提供的半导体结构及其形成方法，通过形成堆叠层于衬底的顶面，且所述堆叠层中包括沿垂直于所述衬底的顶面的方向间隔排布的多个半导体层，且每个所述半导体层包括沿平行于所述衬底的顶面的方向间隔排布的多个半导体柱，从而使得所述堆叠层中的多个半导体柱呈三维阵列堆叠，后续通过形成水平电容器、水平字线和垂直位线，将传统的二维半导体结构转变为三维半导体结构，在提高半导体结构集成度的同时，还能够增大半导体结构的存储密度，改善半导体结构的性能。另外，本具体实施方式还能实现两个晶体管共享一条位线，从而有助于进一步缩小半导体结构的尺寸，提高半导体结构的存储容量。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种半导体结构的形成方法，包括如下步骤：
    形成堆叠层于衬底的顶面，所述堆叠层包括沿第一方向间隔排布的多个半导体层，所述堆叠层包括晶体管区域、以及沿第二方向分布于所述晶体管区域相对两侧的电容区域和位线区域，所述半导体层包括沿第三方向间隔排布的半导体柱，所述第一方向为垂直于所述衬底的顶面的方向，所述第二方向和所述第三方向均为平行于所述衬底的顶面的方向，且所述第二方向与所述第三方向相交；
    于所述电容区域内形成沿所述第二方向延伸的电容器；
    于所述晶体管区域内形成字线，所述字线沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述半导体柱；
    于所述位线区域内形成位线，所述位线沿所述第一方向延伸、且与沿所述第一方向间隔排布的所述半导体柱接触电连接。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，形成堆叠层于衬底的顶面的具体步骤包括：
    沿所述第一方向交替沉积半导体层和第一牺牲层于所述衬底的顶面，形成所述堆叠层；
    刻蚀所述堆叠层，形成暴露所述衬底的第一沟槽，所述第一沟槽将所述半导体层分隔为沿所述第三方向间隔排布的半导体柱。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述半导体柱包括位于所述电容区域的导电柱；于所述电容区域内形成沿所述第二方向延伸的电容器的具体步骤包括：
    去除所述电容区域的所述第一牺牲层，形成位于所述电容区域内的相邻两层所述半导体层之间的第一空隙；
    于所述第一空隙内形成覆盖所述导电柱的导电层、覆盖所述导电层的电介质层、覆盖所述电介质层的上电极层、以及覆盖所述上电极层的公共电极层，形成包括所述导电柱、所述导电层、所述电介质层、所述上电极层和所述公共电极层的电容器。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，形成包括所述导电柱、所述导电层、所述电介质层、所述上电极层和所述公共电极层的电容器的具体步骤包括：
    形成连续覆盖沿所述第一方向间隔排布的所述第一空隙的内壁的导电层；
    形成覆盖所述导电层表面的电介质层；
    形成覆盖所述电介质层表面的上电极层；
    形成覆盖所述上电极层表面的公共电极层；
    去除覆盖于所述晶体管区域内的所述第一牺牲层侧壁上的所述导电层、所述电介质层、所述上电极层和所述公共电极层，于所述电容区域内相邻的两层所述半导体层之间形成第一开口，所述导电柱、以及所述第一空隙内残留的所述导电层、所述电介质层、所述上电极层和所述公共电极层形成所述电容器。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，所述半导体柱包括位于所述晶体管区域的有源柱，所述有源柱包括沟道区、以及沿所述第二方向分布于所述沟道区相对两侧的源极区和漏极区，所述漏极区与所述电容区域相邻，所述源极区与所述位线区域相邻；于所述晶体管区域内形成字线的具体步骤包括：
    去除所述晶体管区域的所述第一牺牲层、以及所述位线区域的所述堆叠层，于所述晶体管区域内形成至少暴露所述沟道区的第二空隙、并于所述位线区域内形成暴露所述衬底的第二沟槽；
    于所述第二空隙内形成沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述沟道区的所述字线。
  6. 根据权利要求5所述的半导体结构的形成方法，其中，于所述晶体管区域内形成至少暴露所述沟道区的第二空隙、并于所述位线区域内形成暴露所述衬底的第二沟槽的具体步骤包括：
    形成填充满所述第一开口的电容隔离层；
    去除所述位线区域的所述堆叠层，于所述位线区域形成暴露所述衬底的第二沟槽；
    沿所述第二沟槽去除所述晶体管区域的所述第一牺牲层，于所述晶体管区域内的相邻两层所述半导体层之间形成暴露所述沟道区、所述漏极区和所述源极区的第二空隙。
  7. 根据权利要求5所述的半导体结构的形成方法，其中，所述第二沟槽的底部暴露所述衬底的顶面； 或者，
    所述第二沟槽延伸至所述衬底内部。
  8. 根据权利要求6所述的半导体结构的形成方法，其中，所述堆叠层中包括沿所述第二方向分布于一个所述位线区域相对两侧的两个所述晶体管区域，且所述晶体管区域背离所述位线区域的一侧具有一个所述电容区域；沿所述第二沟槽去除所述晶体管区域的所述第一牺牲层的具体步骤包括：
    沿所述第二沟槽同时去除两个所述晶体管区域的所述第一牺牲层。
  9. 根据权利要求6所述的半导体结构的形成方法，其中，于所述第二空隙内形成沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述沟道区的所述字线的具体步骤包括：
    形成覆盖所述第二空隙内壁和所述第二沟槽的内壁的初始字线层，所述初始字线层至少连续包覆沿所述第三方向间隔排布的所述有源柱；
    形成覆盖所述初始字线层表面、并填充满所述第二空隙和所述第二沟槽的隔离层；
    去除所述第二沟槽内、所述源极区上方和所述漏极区上方的所述初始字线层和所述隔离层，形成位于相邻两个所述漏极区域之间的第二开口、位于相邻两个源极区之间的第三开口，残留于所述沟道区上方的所述初始字线层作为所述字线，残留于相邻两条所述字线之间的所述隔离层作为字线隔离层。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，所述堆叠层包括沿所述第一方向交替堆叠的所述半导体层和第一牺牲层，所述半导体柱包括位于所述晶体管区域的有源柱，所述有源柱包括沟道区；
    所述第一牺牲层在所述第一方向上的厚度大于4倍的所述半导体层中沿所述第三方向相邻的两个所述沟道区之间间隙宽度。
  11. 根据权利要求9所述的半导体结构的形成方法，其中，形成覆盖所述第二空隙内壁和所述第二沟槽的内壁的初始字线层的具体步骤包括：
    采用侧向原子层沉积工艺形成覆盖所述第二空隙内壁和所述第二沟槽的内壁的初始字线层。
  12. 根据权利要求9所述的半导体结构的形成方法，其中，于所述位线区域内形成位线之前，还包括如下步骤：
    去除所述电容隔离层；
    形成填充满所述第一开口、所述第二开口、所述第三开口和所述第二沟槽的介质层；
    去除所述第二沟槽内的所述介质层。
  13. 根据权利要求6所述的半导体结构的形成方法，其中，于所述第二空隙内形成沿所述第三方向延伸、且连续包覆沿所述第三方向间隔排布的所述沟道区的所述字线的具体步骤包括：
    沿所述第二沟槽沉积栅极材料于所述第二空隙内壁和所述第二沟槽的内壁，形成包覆所述有源柱的初始栅极层，沿所述第三方向相邻的两个所述初始栅极层相互独立；
    沿所述第二沟槽沉积初始字线材料，形成覆盖于所述初始栅极层表面的初始字线层，所述初始字线层至少连续包覆沿所述第三方向间隔排布的所述有源柱；
    形成覆盖所述初始字线层表面、并填充满所述第二空隙和所述第二沟槽的隔离层；
    去除所述第二沟槽内、所述源极区上方和所述漏极区上方的所述初始栅极层、所述初始字线层和所述隔离层，形成位于相邻两个所述漏极区之间的第二开口、位于相邻两个源极区之间的第三开口，残留于所述沟道区上方的所述初始栅极层作为栅极层，残留于所述栅极层上方、以及沿所述第三方向相邻的两个所述栅极层之间的所述初始字线层作为所述字线，残留于相邻两条所述字线之间的所述隔离层作为字线隔离层。
  14. 根据权利要求1所述的半导体结构的形成方法，其中，所述半导体层的材料为包括掺杂离子的硅材料。
  15. 一种半导体结构，采用如权利要求1所述的半导体结构的形成方法形成。
PCT/CN2022/115021 2022-05-30 2022-08-26 半导体结构及其形成方法 WO2023231196A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/093,779 US20230389265A1 (en) 2022-05-30 2023-01-05 Semiconductor structure and method for forming semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210614481.X 2022-05-30
CN202210614481.XA CN117222223A (zh) 2022-05-30 2022-05-30 半导体结构及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/093,779 Continuation US20230389265A1 (en) 2022-05-30 2023-01-05 Semiconductor structure and method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023231196A1 true WO2023231196A1 (zh) 2023-12-07

Family

ID=89026790

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/115021 WO2023231196A1 (zh) 2022-05-30 2022-08-26 半导体结构及其形成方法

Country Status (3)

Country Link
CN (1) CN117222223A (zh)
TW (1) TW202347728A (zh)
WO (1) WO2023231196A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047377A1 (en) * 2015-08-14 2017-02-16 Macronix International Co., Ltd. Memory device and method for manufacturing the same
CN113130494A (zh) * 2019-12-30 2021-07-16 爱思开海力士有限公司 存储器件及其制造方法
CN113284897A (zh) * 2020-02-19 2021-08-20 爱思开海力士有限公司 存储器件
CN113903741A (zh) * 2020-07-07 2022-01-07 爱思开海力士有限公司 半导体器件
CN114121819A (zh) * 2021-11-19 2022-03-01 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047377A1 (en) * 2015-08-14 2017-02-16 Macronix International Co., Ltd. Memory device and method for manufacturing the same
CN113130494A (zh) * 2019-12-30 2021-07-16 爱思开海力士有限公司 存储器件及其制造方法
CN113284897A (zh) * 2020-02-19 2021-08-20 爱思开海力士有限公司 存储器件
CN113903741A (zh) * 2020-07-07 2022-01-07 爱思开海力士有限公司 半导体器件
CN114121819A (zh) * 2021-11-19 2022-03-01 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件

Also Published As

Publication number Publication date
TW202347728A (zh) 2023-12-01
CN117222223A (zh) 2023-12-12

Similar Documents

Publication Publication Date Title
US9613967B1 (en) Memory device and method of fabricating the same
US8120103B2 (en) Semiconductor device with vertical gate and method for fabricating the same
WO2023216360A1 (zh) 三维存储器及其形成方法
CN112992775A (zh) 半导体存储器及其形成方法
WO2023092706A1 (zh) 一种半导体结构的制备方法、半导体结构和半导体存储器
WO2022057328A1 (zh) 半导体结构的制作方法及半导体结构
KR20230087592A (ko) 반도체 소자의 제조 방법 및 반도체 소자
US20230005919A1 (en) Semiconductor structure and method for forming semiconductor structure
US20230171947A1 (en) Semiconductor structure and manufacturing method thereof
CN112750783A (zh) 半导体结构及其形成方法
WO2023231196A1 (zh) 半导体结构及其形成方法
WO2022183642A1 (zh) 半导体结构及其形成方法
WO2022236980A1 (zh) 存储器的制作方法
US20230389265A1 (en) Semiconductor structure and method for forming semiconductor structure
WO2023245799A1 (zh) 半导体结构及其形成方法
WO2023201849A1 (zh) 半导体结构及其形成方法
WO2024041040A1 (zh) 半导体器件及其制备方法
WO2023168778A1 (zh) 存储器及其形成方法
WO2023178738A1 (zh) 存储器及其形成方法
CN117529103B (zh) 半导体结构及其形成方法
WO2024045328A1 (zh) 半导体结构及其形成方法
CN117529105B (zh) 半导体结构及其形成方法
WO2024051062A1 (zh) 半导体结构及其形成方法
US20230345712A1 (en) Semiconductor structure and method for forming semiconductor structure
EP4277448A1 (en) Memory and method for forming same