WO2023092706A1 - 一种半导体结构的制备方法、半导体结构和半导体存储器 - Google Patents

一种半导体结构的制备方法、半导体结构和半导体存储器 Download PDF

Info

Publication number
WO2023092706A1
WO2023092706A1 PCT/CN2021/137551 CN2021137551W WO2023092706A1 WO 2023092706 A1 WO2023092706 A1 WO 2023092706A1 CN 2021137551 W CN2021137551 W CN 2021137551W WO 2023092706 A1 WO2023092706 A1 WO 2023092706A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
dielectric wall
etching
layer
remaining
Prior art date
Application number
PCT/CN2021/137551
Other languages
English (en)
French (fr)
Inventor
于业笑
刘忠明
陈龙阳
白世杰
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/844,209 priority Critical patent/US20230164983A1/en
Publication of WO2023092706A1 publication Critical patent/WO2023092706A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory.
  • Embodiments of the present disclosure hope to propose a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory, which can form a novel semiconductor structure with fewer number of photomasks for metal wiring.
  • An embodiment of the present disclosure provides a method for preparing a semiconductor structure, the method comprising:
  • a substrate is provided; an active region is included in the substrate;
  • first dielectric walls and second dielectric walls extending along a first direction on the substrate; the first dielectric walls and the second dielectric walls are alternately distributed;
  • An embodiment of the present disclosure also provides a semiconductor structure prepared by the preparation method in the above solution.
  • An embodiment of the present disclosure also provides a semiconductor memory, including the semiconductor structure in the above solution.
  • the embodiments of the present disclosure provide a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor memory, capable of forming a first dielectric wall and a second dielectric wall extending along a first direction on the provided substrate, wherein , the first dielectric wall and the second dielectric wall are distributed alternately; then, the first dielectric wall and the second dielectric wall are etched to form a trench extending along the second direction, wherein the height of the remaining first dielectric wall in the trench is greater than the height of the remaining second dielectric wall; then, etching the remaining second dielectric wall in the trench to form first contact holes arranged at intervals in the trench, wherein the first contact holes expose the source area.
  • the trench provides the buried area of the metal wiring
  • the first contact hole provides the contact point between the metal wiring and the active area, and only two photomasks are needed for two etchings; thus, with less photomasks
  • the number of times forms a novel semiconductor structure that can carry out metal wiring, providing a new choice for the semiconductor process.
  • FIG. 1 is a flow chart 1 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2A is a schematic diagram 1 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2B is a second schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3A is a third schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 3B is a schematic diagram 4 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4A is a schematic diagram five of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4B is a sixth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 5 is a second flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 6A is a schematic diagram VII of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 6B is a schematic diagram eight of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7A is a schematic diagram 9 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram ten of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 8A is a schematic diagram eleventh of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 8B is a schematic diagram twelve of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 9A is a schematic diagram thirteen of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 9B is a fourteenth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 10 is a flowchart three of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 11A is a fifteenth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 11B is a sixteenth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 12A is a schematic diagram of a seventeenth method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 12B is a schematic diagram eighteenth of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 13A is a nineteenth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 13B is a schematic diagram 20 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Fig. 14A is a schematic diagram 21 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 14B is a schematic diagram 22 of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • Fig. 15A is a schematic diagram twenty-three of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • Fig. 15B is a schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the disclosure twenty-fourth;
  • FIG. 16A is a twenty-fifth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 16B is a twenty-sixth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 17A is a twenty-seventh schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 17B is a twenty-eighth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 18A is a twenty-ninth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 18B is a schematic diagram thirty-one of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 19 is a flowchart 4 of a semiconductor structure preparation method provided by an embodiment of the present disclosure.
  • FIG. 20A is a schematic diagram thirty-two of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 20B is a schematic diagram thirty-three of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 21A is a schematic diagram thirty-four of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 21B is a thirty-five schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 22 is a flowchart five of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 23 is a thirty-six schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 24A is a thirty-seventh schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 24B is a thirty-eighth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 25 is a flowchart six of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 26 is a thirty-ninth schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 27 is a schematic diagram forty of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 28A is a schematic diagram forty-one of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 28B is a schematic diagram forty-two of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 29A is a schematic diagram forty-three of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 29B is a schematic diagram forty-four of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 30 is a flowchart VII of a semiconductor structure preparation method provided by an embodiment of the present disclosure.
  • FIG. 31A is a schematic diagram forty-five of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 31B is a schematic diagram forty-six of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 32A is a schematic diagram forty-seventh of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 32B is a schematic diagram forty-eight of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 33 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first/second in the application documents, add the following explanation.
  • first/second/third are only used to distinguish similar objects and do not mean With regard to the specific ordering of objects, it can be understood that “first/second/third” can be interchanged in specific order or sequential order if allowed, so that the embodiments of the present disclosure described here can operate in a performed in an order other than that shown or described.
  • Dynamic random access memory is a semiconductor element commonly used in electronic equipment such as computers. It is composed of a plurality of storage units, and each storage unit usually includes a transistor and a capacitor. Among them, the gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the stored data can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.
  • DRAM Dynamic Random Access Memory
  • FIG. 1 is an optional schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, which will be described in conjunction with the steps shown in FIG. 1 .
  • the substrate includes an active region.
  • FIG. 2B is a side sectional view.
  • the substrate 00 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a germanium arsenic substrate, an on-insulator substrate, etc. Silicon (Silicon On Insulator, SOI for short) substrate or Germanium On Insulator (Germanium On Insulator, GOI for short) substrate, etc.
  • the substrate 00 may be doped or non-doped.
  • the substrate 00 may be an N-type substrate or a P-type substrate.
  • the substrate 00 includes an active region 01 .
  • the substrate is a clean single crystal flake for semiconductor processing, which has specific crystal planes and appropriate electrical, optical and mechanical properties.
  • the semiconductor structures are all processed on the substrate.
  • first dielectric walls and second dielectric walls extending along a first direction on the substrate; the first dielectric walls and the second dielectric walls are alternately distributed.
  • the semiconductor device may form the first dielectric wall and the second dielectric wall extending along the first direction on the substrate.
  • 2A and 2B are respectively a top view and a side sectional view.
  • a first dielectric wall 11 and a second dielectric wall 12 extending along the first direction X are formed on the substrate 00, and the first The dielectric walls 11 and the second dielectric walls 12 are distributed alternately.
  • the material of the first dielectric wall may be silicon nitride (SiN), and the material of the second dielectric wall may be silicon oxide (SiO 2 ).
  • the semiconductor device may etch the first dielectric wall and the second dielectric wall to form trenches extending along the second direction.
  • 3A and FIG. 3B are top view and front sectional view respectively. As shown in FIG. 3A and FIG. The direction Y extends and is arranged at intervals. In the groove 13, the height of the remaining first dielectric wall 11 is greater than the height of the remaining second dielectric wall 12. Therefore, in FIG. 3B, the remaining first dielectric wall 11 in the groove 13 blocks the remaining Two medium walls 12 . In this way, the position of the remaining second dielectric wall in the trench 13 forms a square hole as shown in FIG. 3A .
  • the height of the remaining first dielectric wall 11 in the trench 13 accounts for 10% of the height of the trench 13. 13 Three quarters of the depth.
  • the semiconductor device may firstly form mandrels with wide intervals through a photolithography process.
  • the mandrels 301 extend along the second direction Y.
  • side walls can be formed on both sides of the mandrel.
  • the side walls 311 cover both sides of the mandrel 301 , and the side walls 311 also extend along the second direction Y.
  • the trench 13 is formed by etching using the sidewall as a mask.
  • the pitch thereof is smaller than that of the mandrels 301, therefore, the size of the trench 13 formed by etching is smaller than the size of the mandrels 301, that is, the trench 13 is formed by using a larger photomask. Smaller grooves.
  • the semiconductor device may etch the remaining second dielectric wall in the trench to form first contact holes arranged at intervals in the trench; wherein the first contact hole penetrates the remaining second dielectric wall, Thereby exposing the active area.
  • 4A and 4B are top view and front sectional view respectively. As shown in FIG. 4A and FIG. 4B , the remaining second dielectric wall 12 in the trench 13 is etched to form a first contact hole 14 . The first contact holes 14 are arranged at intervals and expose the active region 01 .
  • the semiconductor device may first deposit a third barrier layer in the trench, and then form a second mask on the third barrier layer through a photolithography process.
  • 20A and FIG. 20B are top view and front sectional view respectively.
  • the third barrier layer 50 is deposited on the trench 13 to cover the trench 13;
  • the second mask 60, the second mask 60 includes concave holes (that is, the second etching pattern 601) arranged at intervals; wherein, the concave holes need to be aligned with the grid holes of the remaining second dielectric wall 12 in the trench 13 , so that the first contact hole 14 can be formed at the position of the remaining second dielectric wall 12, as shown in FIG. 4A.
  • the semiconductor device can be etched at least once along the second etching pattern 601 to remove the third barrier layer 50 and etch the remaining second dielectric wall 12 in the trench 13 to form the first dielectric wall 12 as shown in FIG. 4A .
  • Contact hole 14 is one of the semiconductor device.
  • the first dielectric wall and the second dielectric wall extending along the first direction and distributed alternately are formed on the substrate first, and then the first dielectric wall and the second dielectric wall are etched to form A groove extending in a second direction.
  • an appropriate etching rate ratio is selected so that the height of the remaining first dielectric wall in the trench is greater than the height of the remaining second dielectric wall.
  • a grid hole is formed at the second dielectric wall, which provides a location basis for the setting of the first contact hole.
  • the remaining second dielectric walls in the trench are etched to form first contact holes arranged at intervals.
  • the trench provides the buried area of the metal wiring
  • the first contact hole provides the contact point between the metal wiring and the active area, and only two photomasks are required for the two etchings. Therefore, a novel semiconductor structure capable of metal wiring is formed with fewer photomask times, which provides a new option for the semiconductor process.
  • S105 to S107 shown in FIG. 5 are also included, which will be described in combination with each step.
  • the first conductive layer may be formed in the trench.
  • the first conductive layer fills the first contact hole and at least a part of the trench.
  • 6A and FIG. 6B are top view and front sectional view respectively.
  • a first conductive layer 15 is formed in the trench 13, and the first conductive layer 15 fills the first contact hole and the trench 13 A part of , that is, the thickness of the first conductive layer 15 is smaller than the depth of the trench 13 .
  • the semiconductor device can also form a second isolation layer 17 made of the same material as the first dielectric wall 11 on both sides of the first conductive layer 15, and the second isolation layer 17 isolates the first conductive layer 15 from other parts.
  • the semiconductor device can first deposit a metal isolation layer, such as TiN, in the first contact hole to prevent the metal material from diffusing into the active region; then, deposit a metal layer, as shown in FIG. 23, the metal layer 70 covers the metal isolation layer.
  • a metal isolation layer such as TiN
  • the metal layer 70 is ground until Up to the top of the trench 13, that is, using a damascene process, the metal layer 70 is ground to form the first conductive layer 15 as shown in FIGS. 24A and 24B .
  • the first conductive layer 15 may be used for a bit line structure.
  • the remaining second dielectric wall outside the trench can be etched to form a second contact hole, and the second contact hole exposes the active region.
  • the semiconductor device may firstly form a first isolation layer on the first conductive layer.
  • 7A and 7B are top view and front sectional view respectively. As shown in FIG. 7A and FIG. 7B, a first isolation layer 16 is formed on the first conductive layer 15, and the first isolation layer 16 covers the first conductive layer 15 and fills The rest of the groove 13 is removed.
  • the first isolation layer 16 is made of the same material as the first dielectric wall 11 .
  • the semiconductor device can use the first isolation layer and the remaining first dielectric wall outside the trench as a mask to etch the remaining second dielectric wall outside the trench to form a second contact hole.
  • the semiconductor device can adopt a higher etching selectivity ratio of the material of the second dielectric wall 12 than the material of the first isolation layer 16 and the first dielectric wall 11.
  • the material of the first isolation layer 16 and the first dielectric wall 11 is silicon nitride
  • the material of the second dielectric wall 12 is silicon oxide
  • then adopt the higher etching selectivity ratio of silicon oxide than silicon nitride Etching is performed, so that only the remaining second dielectric wall 12 outside the trench 13 is etched, and the first isolation layer 16 and the first dielectric wall 11 are reserved.
  • 8A and FIG. 8B are top view and front sectional view respectively. As shown in FIG. 8A and FIG. 8B, the remaining second dielectric wall 12 outside the trench 13 is etched to form a second contact hole 18, the second contact hole 18 exposes the active area 01 .
  • the second conductive layer may be formed in the second contact hole.
  • 9A and 9B are top view and front cross-sectional view respectively. As shown in FIG. 9A and FIG. 9B , the second conductive layer 19 is formed in the second contact hole 18 of the semiconductor device. The second conductive layer 19 fills part of the second contact hole 18 and is in contact with the active region 01 .
  • the semiconductor device may first form a second isolation layer in the second contact hole.
  • FIG. 31B is a front sectional view. As shown in FIG. 31B , the second isolation layer 17 covers the first conductive layer 15 side. Then, the semiconductor device can deposit a conductive medium, and the material of the conductive medium can be polysilicon.
  • Figure 31A and Figure 31B are a top view and a front sectional view respectively, as shown in Figure 31A and Figure 31B, the conductive medium 90 fills the second contact hole 18, and covers the first conductive layer 15, and the second isolation layer 17 isolates the conductive medium 90 from the first conductive layer 15.
  • the semiconductor device can use high selectivity to etch the conductive medium 90, that is, the etching rate of the conductive medium 90 is higher than the etching rate of other materials; such etching, until the height of the conductive medium 90 is lower than the height of the second contact hole 18
  • the remaining first dielectric wall 11 and first isolation layer 16 outside the trench are exposed, as shown in FIG. 32A .
  • the remaining conductive medium 90 forms the second conductive layer 19 ; and the second isolation layer 17 separates the first conductive layer 15 from the second conductive layer 19 .
  • the first conductive layer is formed in the trench, and is in contact with the active region through the first contact hole; at the same time, the remaining second dielectric wall outside the trench is used as a mask to etch and form the first conductive layer at its corresponding position.
  • Two contact holes are filled with the second conductive layer. In this way, no photomask is needed, and the second contact hole is formed by pattern etching of the semiconductor structure itself, thereby achieving the purpose of self-alignment.
  • the first conductive layer is formed by filling the trench
  • the second conductive layer is formed by filling the second contact hole, both of which are buried structures, thereby reducing the height of the semiconductor structure, which is conducive to improving the vertical direction. Integration density.
  • S103 shown in FIG. 1 may be implemented through S201 to S204 shown in FIG. 10 , which will be described in conjunction with each step.
  • the semiconductor device may sequentially deposit the first barrier layer and the second barrier layer on the first dielectric wall and the second dielectric wall.
  • the barrier layer is used to form a downwardly transferred pattern as required, and to protect regions that do not need to be etched during etching.
  • 11A and 11B are respectively a top view and a front sectional view. As shown in FIG. 11A and FIG. 11B, a first barrier layer 20 and a second barrier layer 30 are sequentially deposited on the first dielectric wall 11 and the second dielectric wall 12 Due to the shading relationship, the alternating structure of the first dielectric wall 11 and the second dielectric wall 12 is not shown in FIG. 11B ).
  • Materials of the first barrier layer 20 and the second barrier layer 30 may include: SiON (silicon oxynitride) and SOH (Spin-on Hardmasks, spin-on hardmask).
  • the semiconductor device may etch the second barrier layer to form mandrels extending along the second direction, wherein the mandrels are arranged at intervals.
  • the semiconductor device can firstly form a first mask 40 on the second barrier layer 30 through a photolithography process, and the shape of the first mask 40 is characterized as being along the second A first etching pattern extending in direction Y. Then, the semiconductor device can etch the second barrier layer 30 along the first etching pattern to form the mandrel 301 shown in FIG. 12A and FIG. 12B .
  • the mandrels 301 extend along the second direction Y and are arranged at intervals.
  • the semiconductor device may cover the sides of the mandrel to form sidewalls.
  • the semiconductor device may first deposit a hard mask layer 31 using an ALD (Atomic Layer Deposition) process to cover the first barrier layer 20 and the mandrel 301 .
  • ALD Atomic Layer Deposition
  • the semiconductor device can fill the gap between the hard mask layers 31 into the third dielectric layer 32 , and the third dielectric layer 32 serves as a barrier layer in subsequent etching.
  • the semiconductor device can etch back the hard mask layer 31, remove the top of the hard mask layer 31 until the mandrel 301 is exposed, and keep the sides of the hard mask layer 31 as sidewalls 311, as shown in FIG. 15A and FIG. 15B Show.
  • the side wall 311 also extends along the second direction Y.
  • the semiconductor device can be etched using the sidewall as a mask to remove the first barrier layer, and etch the first dielectric wall and the second dielectric wall to form trenches extending along the second direction.
  • a mandrel 301 remains in the middle of the side wall 311 .
  • the semiconductor device can first be etched with a high selectivity etching rate to remove the remaining mandrel 301 in the middle of the sidewall 311.
  • a high selectivity ratio means that the etch rate of the material of the mandrel 301 is much greater than that of other materials rate, the resulting structure is shown in Figure 16A and Figure 16B.
  • the semiconductor device can use the sidewall 311 as a mask to etch the first barrier layer 20 to form the first intermediate structure 201 as shown in FIG.
  • first intermediate structure 201 and the side wall 311 also extend along the second direction Y, and the gap between the first intermediate structure 201 exposes the first dielectric wall 11 and the second dielectric wall 12 .
  • the semiconductor device can use the first intermediate structure 201 as a mask to etch the first dielectric wall 11 and the second dielectric wall 12 according to the etching rate ratio; here, the etching rate ratio
  • the etching rate ratio of the material of the first dielectric wall to the material of the second dielectric wall may be 1:4.
  • the structure shown in FIG. 18B can be obtained.
  • the first dielectric wall 11 and the second dielectric wall 12 are etched to form a trench 13; in the trench 13, the remaining The height of the first dielectric wall 11 is greater than that of the remaining second dielectric wall 12 , that is, in FIG. 18B , the remaining first dielectric wall 11 in the groove 13 covers the remaining second dielectric wall 12 .
  • the semiconductor device can remove the remaining first intermediate structure 201 to obtain the structure shown in FIG. 3A and FIG. 3B .
  • the ratio of the etching rate of the material of the first dielectric wall to the material of the second dielectric wall is 1:4
  • the height of the remaining first dielectric wall 11 in the trench 13 accounts for a quarter of the depth of the trench 13 the third.
  • the first mask 40 is first formed by a photolithography process, and then etched along the first mask 40
  • the mandrel 301 is formed; then, sidewalls 311 are formed covering the sides of the mandrel 301 ; finally, trenches 13 are formed by etching with the sidewalls 311 as a mask. Since the side walls 311 are formed in the spaced regions of the mandrels 301, their pitches are smaller than the pitches between the mandrels 301. Therefore, the width of the groove 13 formed by using the sidewall 311 as a mask is smaller than the distance between the mandrels 301 . In this way, even though the photolithography process limits the achievable critical dimension, the mandrel 301 can be used to form the trench 13 with a smaller critical dimension, which expands the limit of the process dimension that can be achieved by the semiconductor device.
  • S202 shown in FIG. 10 may be implemented through S2021-S2022, which will be described in conjunction with each step.
  • the first mask includes a first etching pattern extending along a second direction.
  • the semiconductor device may firstly form a first mask on the second barrier layer.
  • the first mask can be obtained through a photolithography process.
  • Fig. 11A and Fig. 11B have illustrated the first mask, are top view and front sectional view respectively, as shown in Fig. 11A and Fig. 11B, the first mask 40 is formed on the second barrier layer 30, the first mask 40 The first etching pattern extends along the second direction Y.
  • the second barrier layer 30 can be etched along the first etching pattern to form the mandrel 301 shown in FIG. 12A and FIG. 12B; the mandrel 301 It also extends in the second direction Y.
  • S203 shown in FIG. 10 may be implemented through S2031 to S2032, which will be described in conjunction with each step.
  • the semiconductor device may first deposit a hard mask layer 31 by using an ALD process to cover the first barrier layer 20 and the mandrel 301 .
  • the hard mask layer 31 can be etched back, the top of the hard mask layer 31 is removed until the mandrel 301 is exposed, and the hard mask layer 31 remains.
  • the side part serves as a side wall 311, as shown in Fig. 15A and Fig. 15B.
  • S204 shown in FIG. 10 may be implemented through S2041 to S2043, which will be described in conjunction with each step.
  • a mandrel 301 remains in the middle of the side wall 311 .
  • the semiconductor device may first be etched at a high selectivity rate to remove the remaining mandrel 301 in the middle of the sidewall 311, and the obtained structure is shown in FIG. 16A and FIG. 16B.
  • the first barrier layer 20 can be etched using the sidewall 311 as a mask to form the first middle layer as shown in FIGS. 17A and 17B. structure 201, and expose the first dielectric wall 11 and the second dielectric wall 12. As shown in FIG. 17A , the first intermediate structure 201 extends along the second direction Y, and the gap between the first intermediate structure 201 exposes the first dielectric wall 11 and the second dielectric wall 12 .
  • the first dielectric wall 11 and the second dielectric wall 12 is etched to form the trench 13 shown in FIG. 3A and FIG. 3B ; in the trench 13 , the height of the remaining first dielectric wall 11 is greater than the height of the remaining second dielectric wall 12 .
  • the etching rate ratio in S2043 includes: a ratio of the etching rate of the material of the first dielectric wall to the material of the second dielectric wall is 1:4. Correspondingly, the etching is carried out according to the etching rate ratio of 1:4, and the height of the remaining first dielectric wall 11 in the trench 13 accounts for three quarters of the depth of the trench 13 .
  • S104 shown in FIG. 1 may be implemented through S301 to S303 shown in FIG. 19 , which will be described in conjunction with each step.
  • the semiconductor device may deposit a third barrier layer on the trench to cover the trench.
  • 20A and 20B are top view and front sectional view respectively. As shown in FIG. 20A and FIG. 20B , the third barrier layer 50 is deposited on the trench 13 to cover the trench 13 .
  • the second mask includes second etching patterns arranged at intervals.
  • the semiconductor device can form a second mask 60 on the third barrier layer 50 through a photolithography process, wherein the second mask 60 includes second etchings arranged at intervals. Eclipse graph 601.
  • the second etching pattern 601 is a concave hole on the second mask 60, and the concave hole needs to be aligned with the remaining square holes of the second dielectric wall 12 in the trench 13, so that A first contact hole 14 is formed at the position of the remaining second dielectric wall 12, as shown in FIG. 4A.
  • the semiconductor device may etch at least once along the second etching pattern to remove the third barrier layer, and etch the remaining second dielectric wall in the trench to form the first contact holes arranged at intervals.
  • the semiconductor device can first etch the third barrier layer 50 along the second etching pattern 601 to form the second intermediate structure 501 as shown in FIG. 21A and FIG. 21B; the second etching pattern 601 is transferred to the second intermediate structure 501 . Then, the semiconductor device can use the second intermediate structure 501 as a mask to etch the remaining second dielectric wall 12 in the trench 13 to form the first contact hole 14 as shown in FIG. 4A .
  • the third barrier layer 50 may include multiple material layers, and the semiconductor device may perform multiple etchings using different etching rate ratios according to different materials, thereby controlling the second etching rate on the second intermediate structure 501.
  • the depth of the concave hole in the pattern 601 can further control the depth of the obtained first contact hole 14 . In this way, at the position of the first contact hole 14, the active region 01 is exposed; while at the remaining positions, the active region 01 is not exposed.
  • the first contact holes arranged at intervals are etched along the second etching pattern to expose the active region. This provides the metal wiring with a contact point to the active area with only one pass through the mask.
  • S303 shown in FIG. 19 may be implemented through S3031 to S3032, which will be described in conjunction with each step.
  • the semiconductor device may first etch the third barrier layer 50 along the second etching pattern 601 to form the second intermediate structure 501 as shown in FIG. 21A and FIG. 21B .
  • the semiconductor device can use the second intermediate structure 501 as a mask to etch the remaining second dielectric wall 12 in the trench 13 to form the first contact hole 14 as shown in FIG. 4A .
  • S105 shown in FIG. 5 may be implemented through S401 to S403 shown in FIG. 22 , which will be described in conjunction with each step.
  • the first contact hole 14 exposes the active region 01 , which can serve as a contact point between the metal layer and the active region 01 .
  • a metal isolation layer needs to be deposited in the first contact hole.
  • the metal isolation layer partially fills the first contact hole 14 and covers the exposed active region 01 .
  • the material of the metal isolation layer may be titanium nitride (TiN), which can block the diffusion of the metal material into the active region.
  • the semiconductor device may deposit the metal layer.
  • FIG. 23 is a front sectional view. As shown in FIG. 23 , the metal layer 70 covers the metal isolation layer and fills the first contact hole 14 (not shown due to occlusion) and the trench 13 . Wherein, the material of the metal layer 70 may be tungsten (W) or copper (Cu).
  • the semiconductor device can grind the metal layer 70 until the top of the trench 13, that is, use the damascene process to grind the metal layer 70 to form the first metal layer 70 as shown in FIGS. 24A and 24B.
  • a conductive layer 15 is shown in FIGS. 24A and 24B.
  • the first conductive layer 15 may be used for a bit line structure.
  • the first conductive layer is formed in the trench and is in contact with the active region through the first contact hole.
  • a buried bit line structure is formed, which reduces the height of the semiconductor structure and is conducive to improving the semiconductor structure in the vertical direction.
  • S106 shown in FIG. 5 may be implemented through S501 to S502 shown in FIG. 25 , which will be described in conjunction with each step.
  • first isolation layer On the first conductive layer, form a first isolation layer; the material of the first isolation layer is the same as that of the first dielectric wall.
  • the semiconductor device may first form a first isolation layer on the first conductive layer, wherein the material of the first isolation layer is the same as that of the first dielectric wall.
  • the semiconductor device may firstly etch the first conductive layer 15 with a high selective etching rate, so as to reduce the height of the first conductive layer.
  • a high selectivity ratio means that the etching rate of the material of the first conductive layer 15 is much higher than that of other materials.
  • the semiconductor device can deposit a fourth barrier layer 80 on the first conductive layer 15 .
  • the fourth barrier layer 80 covers the remaining second dielectric wall 12 outside the trench.
  • the semiconductor device can polish the fourth barrier layer 80 until the remaining second dielectric wall 12 outside the trench is exposed, and the remaining fourth barrier layer 80 forms the first isolation layer 16 .
  • the semiconductor device can use the first isolation layer 16 and the rest of the trench.
  • the first dielectric wall 11 is used as a mask, and the remaining second dielectric wall 12 outside the trench is etched to form a second contact hole 18 at the position of the second dielectric wall 12 .
  • the second contact hole 18 exposes the active region 01 .
  • the remaining second dielectric wall outside the trench is used as a photomask, and the second contact hole is formed by etching at its corresponding position, and filled with the second conductive layer.
  • the second conductive layer is a buried structure, which reduces the height of the semiconductor structure and has It is beneficial to improve the integration degree in the vertical direction.
  • S501 shown in FIG. 25 may be implemented through S5011 to S5013, which will be described in conjunction with each step.
  • the semiconductor device may firstly etch the first conductive layer 15 with a high selective etching rate, so as to reduce the height of the first conductive layer.
  • the semiconductor device may deposit a fourth barrier layer 80 on the first conductive layer 15 .
  • the fourth barrier layer 80 covers the remaining second dielectric wall 12 outside the trench.
  • the semiconductor device can grind the fourth barrier layer 80 until the remaining second dielectric wall 12 outside the trench is exposed, and the remaining fourth barrier layer 80 forms the first Isolation layer 16.
  • S107 shown in FIG. 5 may be implemented through S601 to S603 shown in FIG. 30 , which will be described in conjunction with each step.
  • the semiconductor device may form a second isolation layer in the second contact hole.
  • FIG. 31B is a front sectional view. As shown in FIG. 31B , the second isolation layer 17 covers the side of the first conductive layer 15 . Wherein, the material of the second isolation layer 17 is the same as that of the first dielectric wall 11 .
  • the semiconductor device may deposit a conductive medium.
  • 31A and 31B are top view and front sectional view respectively.
  • the conductive medium 90 fills the second contact hole 18 and covers the first conductive layer 15; the second isolation layer 17
  • the conductive medium 90 is isolated from the first conductive layer 15 .
  • the material of the conductive medium 90 may be polysilicon.
  • FIG. 32A and FIG. 32B are top view and front sectional view respectively. Combining with FIG. 31A, FIG. 31B, FIG. 32A and FIG.
  • the conductive medium 90 that is, the etching rate of the conductive medium 90 is higher than that of other materials; it is etched in this way until the height of the conductive medium 90 is lower than the top of the second contact hole 18, revealing the remaining first contact hole 18 outside the trench.
  • the dielectric wall 11 and the first isolation layer 16 are shown in FIG. 32A. In this way, the remaining conductive medium 90 forms the second conductive layer 19 ; and the second isolation layer 17 separates the first conductive layer 15 from the second conductive layer 19 .
  • the second isolation layer 17 is formed on the side of the first conductive layer 15 using the same material as the first dielectric wall 11 .
  • the material properties can be used to select a suitable etching selectivity to etch the conductive medium 90, so that the first dielectric wall 11 and the second isolation layer 17 are preserved; meanwhile, the second isolation layer 17 separates the first conductive layer 15 and the second Conductive layer 19 is isolated to avoid short circuit.
  • the embodiment of the present disclosure also provides a semiconductor structure 08, which is prepared by the preparation method provided in the foregoing embodiments.
  • An embodiment of the present disclosure also provides a semiconductor memory 09 .
  • the semiconductor memory 09 includes at least a semiconductor structure 08 .
  • the semiconductor memory 09 shown in FIG. 33 includes at least a dynamic random access memory DRAM.
  • Embodiments of the present disclosure provide a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor memory, capable of forming a first dielectric wall and a second dielectric wall extending along a first direction on a provided substrate, wherein the first dielectric The walls and the second dielectric walls are alternately distributed; then, the first dielectric wall and the second dielectric wall are etched to form a groove extending along the second direction, wherein the height of the remaining first dielectric wall in the groove is greater than that of the remaining first dielectric wall Then, etching the remaining second dielectric wall in the trench to form first contact holes arranged at intervals in the trench, wherein the first contact holes expose the active region in the substrate.
  • the trench provides the buried area of the metal wiring
  • the first contact hole provides the contact point between the metal wiring and the active area, and only two photomasks are needed for two etchings; thus, with less photomasks
  • the number of times forms a novel semiconductor structure that can carry out metal wiring, providing a new choice for the semiconductor process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体结构的制备方法、半导体结构和半导体存储器，所述方法包括：提供衬底（00）；衬底（00）内包括有源区（01）；在衬底（00）上形成沿第一方向延伸的第一介质墙（11）和第二介质墙（12）；第一介质墙（11）和第二介质墙（12）交替分布；刻蚀第一介质墙（11）和第二介质墙（12），形成沿第二方向延伸的沟槽（13）；其中，沟槽（13）间隔设置；在沟槽（13）内，剩余的第一介质墙（11）的高度大于剩余的第二介质墙（12）的高度；刻蚀沟槽（13）内剩余的第二介质墙（12），在沟槽内形成间隔设置的第一接触孔（14）；第一接触孔（14）暴露有源区（01）。

Description

一种半导体结构的制备方法、半导体结构和半导体存储器
相关申请的交叉引用
本公开基于申请号为202111403797.6、申请日为2021年11月24日、发明名称为“一种半导体结构的制备方法、半导体结构和半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体工艺领域，尤其涉及一种半导体结构的制备方法、半导体结构和半导体存储器。
背景技术
随着半导体技术的不断发展，集成电路不断追求高速度、高集成密度和低功耗。因而，集成电路中半导体器件结构尺寸也在不断微缩。
现有的半导体结构越来越难以满足发展的需要，半导体结构需要不断推陈出新，设计更多新颖的半导体结构。
发明内容
本公开实施例期望提出一种半导体结构的制备方法、半导体结构和半导体存储器，能够以较少的光罩次数形成新颖的半导体结构，以进行金属布线。
本公开的技术方案是这样实现的：
本公开实施例提供一种半导体结构的制备方法，所述方法包括：
提供衬底；所述衬底内包括有源区；
在所述衬底上形成沿第一方向延伸的第一介质墙和第二介质墙；所述第一介质墙和所述第二介质墙交替分布；
刻蚀所述第一介质墙和所述第二介质墙，形成沿第二方向延伸的沟槽；其中，所述沟槽间隔设置；在所述沟槽内，剩余的所述第一介质墙的高度大于剩余的所述第二介质墙的高度；
刻蚀所述沟槽内剩余的所述第二介质墙，在所述沟槽内形成间隔设置的第一接触孔；所述第一接触孔暴露所述有源区。
本公开实施例还提供一种半导体结构，所述半导体结构由上述方案中的制备方法制备而成。
本公开实施例还提供一种半导体存储器，包括上述方案中的半导体结构。
由此可见，本公开实施例提供了一种半导体结构的制备方法、半导体结构和半导体存储器，能够在所提供的衬底上形成沿第一方向延伸的第一介质墙和第二介质墙，其中，第一介质墙和第二介质墙交替分布；而后，刻蚀第一介质墙和第二介质墙，形成沿第二方向延伸的沟槽，其中，沟槽内剩余的第一介质墙的高度大于剩余的第二介质墙的高度；而后，刻蚀沟槽内剩余的第二介质墙，在沟槽内形成间隔设置的第一接触孔，其中，第一接触孔暴露出衬底中的有源区。这样，沟槽提供了金属布线的埋入区域，第一接触孔则提供了金属布线与有源区的接触点，而两次刻蚀仅需要两次光罩；从而，以较少的光罩次数形成了可以进行金属布线的新颖半导体结构，为半导体工艺提供了新的选择。
附图说明
图1为本公开实施例提供的一种半导体结构制备方法的流程图一；
图2A为本公开实施例提供的一种半导体结构制备方法的示意图一；
图2B为本公开实施例提供的一种半导体结构制备方法的示意图二；
图3A为本公开实施例提供的一种半导体结构制备方法的示意图三；
图3B为本公开实施例提供的一种半导体结构制备方法的示意图四；
图4A为本公开实施例提供的一种半导体结构制备方法的示意图五；
图4B为本公开实施例提供的一种半导体结构制备方法的示意图六；
图5为本公开实施例提供的一种半导体结构制备方法的流程图二；
图6A为本公开实施例提供的一种半导体结构制备方法的示意图七；
图6B为本公开实施例提供的一种半导体结构制备方法的示意图八；
图7A为本公开实施例提供的一种半导体结构制备方法的示意图九；
图7B为本公开实施例提供的一种半导体结构制备方法的示意图十；
图8A为本公开实施例提供的一种半导体结构制备方法的示意图十一；
图8B为本公开实施例提供的一种半导体结构制备方法的示意图十二；
图9A为本公开实施例提供的一种半导体结构制备方法的示意图十三；
图9B为本公开实施例提供的一种半导体结构制备方法的示意图十四；
图10为本公开实施例提供的一种半导体结构制备方法的流程图三；
图11A为本公开实施例提供的一种半导体结构制备方法的示意图十五；
图11B为本公开实施例提供的一种半导体结构制备方法的示意图十六；
图12A为本公开实施例提供的一种半导体结构制备方法的示意图十七；
图12B为本公开实施例提供的一种半导体结构制备方法的示意图十八；
图13A为本公开实施例提供的一种半导体结构制备方法的示意图十九；
图13B为本公开实施例提供的一种半导体结构制备方法的示意图二十；
图14A为本公开实施例提供的一种半导体结构制备方法的示意图二十一；
图14B为本公开实施例提供的一种半导体结构制备方法的示意图二十二；
图15A为本公开实施例提供的一种半导体结构制备方法的示意图二十三；
图15B为本公开实施例提供的一种半导体结构制备方法的示意图二十四；
图16A为本公开实施例提供的一种半导体结构制备方法的示意图二十五；
图16B为本公开实施例提供的一种半导体结构制备方法的示意图二十六；
图17A为本公开实施例提供的一种半导体结构制备方法的示意图二十七；
图17B为本公开实施例提供的一种半导体结构制备方法的示意图二十八；
图18A为本公开实施例提供的一种半导体结构制备方法的示意图二十九；
图18B为本公开实施例提供的一种半导体结构制备方法的示意图三十一；
图19为本公开实施例提供的一种半导体结构制备方法的流程图四；
图20A为本公开实施例提供的一种半导体结构制备方法的示意图三十二；
图20B为本公开实施例提供的一种半导体结构制备方法的示意图三十三；
图21A为本公开实施例提供的一种半导体结构制备方法的示意图三十四；
图21B为本公开实施例提供的一种半导体结构制备方法的示意图三十五；
图22为本公开实施例提供的一种半导体结构制备方法的流程图五；
图23为本公开实施例提供的一种半导体结构制备方法的示意图三十六；
图24A为本公开实施例提供的一种半导体结构制备方法的示意图三十七；
图24B为本公开实施例提供的一种半导体结构制备方法的示意图三十八；
图25为本公开实施例提供的一种半导体结构制备方法的流程图六；
图26为本公开实施例提供的一种半导体结构制备方法的示意图三十九；
图27为本公开实施例提供的一种半导体结构制备方法的示意图四十；
图28A为本公开实施例提供的一种半导体结构制备方法的示意图四十一；
图28B为本公开实施例提供的一种半导体结构制备方法的示意图四十二；
图29A为本公开实施例提供的一种半导体结构制备方法的示意图四十三；
图29B为本公开实施例提供的一种半导体结构制备方法的示意图四十四；
图30为本公开实施例提供的一种半导体结构制备方法的流程图七；
图31A为本公开实施例提供的一种半导体结构制备方法的示意图四十五；
图31B为本公开实施例提供的一种半导体结构制备方法的示意图四十六；
图32A为本公开实施例提供的一种半导体结构制备方法的示意图四十七；
图32B为本公开实施例提供的一种半导体结构制备方法的示意图四十八；
图33为本公开实施例提供的一种半导体存储器的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图和实施例对本公开的技术方案进一步详细阐述，所描述的实施例不应视为对本公开的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
如果申请文件中出现“第一/第二”的类似描述则增加以下的说明，在以下的描述中，所涉及的术语“第一/第二/第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一/第二/第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体元件，其由多个存储单元构成，每个存储单 元通常包括晶体管和电容器。其中，晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
动态存储器的发展追求高速度、高集成密度、低功耗等性能指标，随着半导体器件结构尺寸的微缩，尤其是在关键尺寸小于15nm的DRAM制造过程中，现有结构所遇到的技术壁垒越来越明显。因此，在现有结构的基础上，开发出更多新颖的结构，是打破现有技术壁垒的有利手段。
图1是本公开实施例提供的半导体结构的制备方法的一个可选的流程示意图，将结合图1示出的步骤进行说明。
S101、提供衬底；衬底内包括有源区。
本公开实施例中，图2B为侧视剖面图，如图2B所示，衬底00可以为半导体衬底，例如硅衬底、锗衬底、硅锗衬底、锗砷衬底、绝缘体上硅(Silicon On Insulator，简称SOI)衬底或者绝缘体上锗(Germanium On Insulator，简称GOI)衬底等。衬底00可以为掺杂或者非掺杂，示例性的，衬底00可以为N型衬底或者P型衬底。衬底00中包括了有源区01。
需要说明的是，衬底是用于半导体加工的洁净单晶薄片，其具有特定晶面和适当电学、光学和机械特性。半导体结构均在衬底上加工而成。
S102、在衬底上形成沿第一方向延伸的第一介质墙和第二介质墙；第一介质墙和第二介质墙交替分布。
本公开实施例中，半导体设备可以在衬底上形成沿第一方向延伸的第一介质墙和第二介质墙。图2A和图2B分别为俯视图和侧视剖面图，如图2A和图2B所示，衬底00上形成了沿第一方向X延伸的第一介质墙11和第二介质墙12，第一介质墙11和第二介质墙12交替分布。
在本公开实施例中，第一介质墙的材料可以是氮化硅(SiN)，第二介质墙的材料可以是氧化硅(SiO 2)。
S103、刻蚀第一介质墙和第二介质墙，形成沿第二方向延伸的沟槽；其中，沟槽间隔设置；在沟槽内，剩余的第一介质墙的高度大于剩余的第二介质墙的高度。
本公开实施例中，半导体设备可以对第一介质墙和第二介质墙进行刻蚀，形成沿第二方向延伸的沟槽。图3A和图3B分别为俯视图和前视剖面图，如图3A和图3B所示，第一介质墙11和第二介质墙12被刻蚀形成沟槽13，其中，沟槽13沿第二方向Y延伸，且间隔设置。在沟槽13内，剩余的第一介质墙11的高度大于剩余的第二介质墙12的高度，因此，在图3B中，沟槽13内剩余的第一介质墙11遮挡住了剩余的第二介质墙12。这样，沟槽13内剩余的第二介质墙的位置形成了如图3A所示的方格孔。
在本公开实施例中，若采用第一介质墙的材料与第二介质墙的材料的刻蚀速率之比为1:4，则沟槽13内剩余的第一介质墙11的高度占沟槽13 深度的四分之三。
在本公开实施例中，半导体设备可以先通过光刻工艺形成间隔较宽的心轴，如图12A和图12B所示，心轴301沿第二方向Y延伸。而后，可以在心轴的两侧形成侧墙，如图15A和图15B所示，侧墙311覆盖心轴301的两侧，侧墙311同样沿第二方向Y延伸。最后，以侧墙为掩膜，刻蚀形成沟槽13。由于侧墙311形成在心轴301的间隔区域中，其间距小于心轴301的间距，因此，刻蚀形成的沟槽13的尺寸小于心轴301的尺寸，即利用尺寸较大的光罩形成了尺寸较小的沟槽。
S104、刻蚀沟槽内剩余的第二介质墙，在沟槽内形成间隔设置的第一接触孔；第一接触孔暴露有源区。
本公开实施例中，半导体设备可以对沟槽内剩余的第二介质墙进行刻蚀，在沟槽内形成间隔设置的第一接触孔；其中，第一接触孔贯穿剩余的第二介质墙，从而暴露出有源区。图4A和图4B分别为俯视图和前视剖面图，如图4A和图4B所示，沟槽13内剩余的第二介质墙12被刻蚀形成了第一接触孔14。第一接触孔14间隔设置，且暴露出了有源区01。
在本公开实施例中，半导体设备可以在沟槽先沉积第三阻挡层，再通过光刻工艺在第三阻挡层上形成第二掩膜。图20A和图20B分别为俯视图和前视剖面图，如图20A和图20B所示，第三阻挡层50沉积在沟槽13上，将沟槽13覆盖；第三阻挡层50上形成了第二掩膜60，第二掩膜60包括了间隔设置的凹孔(即第二刻蚀图形601)；其中，该凹孔需要对齐于沟槽13内剩余的第二介质墙12的方格孔，这样，则可以在剩余的第二介质墙12的位置形成第一接触孔14，如图4A所示。而后，半导体设备可以沿第二刻蚀图形601进行至少一次刻蚀，将第三阻挡层50去除，并将沟槽13内剩余的第二介质墙12刻蚀形成如图4A所示的第一接触孔14。
可以理解的是，本公开实施例先在衬底上形成沿第一方向延伸且交替分布的第一介质墙和第二介质墙，再对第一介质墙和第二介质墙进行刻蚀，形成沿第二方向延伸的沟槽。这样，利用第一介质墙和第二介质墙的不同材料，选择适当的刻蚀速率比，使得沟槽内剩余的第一介质墙的高度大于剩余的第二介质墙的高度，在剩余的第二介质墙处形成了方格孔，为第一接触孔的设置提供了位置基础。
而后，对齐于方格孔，将沟槽内剩余的第二介质墙刻蚀形成间隔设置的第一接触孔。这样，沟槽提供了金属布线的埋入区域，第一接触孔则提供了金属布线与有源区的接触点，而两次刻蚀仅需要两次光罩。从而，以较少的光罩次数形成了可以进行金属布线的新颖半导体结构，为半导体工艺提供了新的选择。
在本公开的一些实施例中，图1示出的S104之后，还包括图5示出的S105～S107，将结合各步骤进行说明。
S105、在沟槽内形成第一导电层；第一导电层填充第一接触孔，且填 充至少部分沟槽。
本公开实施例中，半导体设备在沟槽内形成了第一接触孔后，可以在沟槽内形成第一导电层。第一导电层填充了第一接触孔，且填充了至少一部分的沟槽。图6A和图6B分别为俯视图和前视剖面图，如图6A和图6B所示，沟槽13内形成了第一导电层15，第一导电层15填充了第一接触孔和沟槽13的一部分，即第一导电层15的厚度小于沟槽13的深度。同时，半导体设备在第一导电层15的两侧还可以形成与第一介质墙11的材料相同的第二隔离层17，第二隔离层17将第一导电层15与其他部分隔离。
在本公开实施例中，由于金属材料若直接和有源区接触，会向有源区中扩散，破坏有源区的电特性。因此，半导体设备可以先在第一接触孔内沉积金属隔离层，例如TiN，以阻挡金属材料向有源区中扩散；而后，沉积金属层，如图23所示，金属层70覆盖了金属隔离层，且填充了第一接触孔14(因遮挡而未示出)和沟槽13，其中，金属层70的材料可以是钨(W)或铜(Cu)；而后，研磨金属层70，直到沟槽13的顶部为止，即采用大马士革工艺，将金属层70研磨形成如图24A和24B所示的第一导电层15。
在本公开实施例中，第一导电层15可以用于位线结构。
S106、刻蚀沟槽外剩余的第二介质墙，形成第二接触孔；第二接触孔暴露有源区。
本公开实施例中，半导体设备在形成了第一导电层后，可以对沟槽外剩余的第二介质墙进行刻蚀，形成第二接触孔，第二接触孔暴露出有源区。
在本公开实施例中，半导体设备可以首先在第一导电层上形成第一隔离层。图7A和图7B分别为俯视图和前视剖面图，如图7A和图7B所示，第一导电层15上形成了第一隔离层16，第一隔离层16覆盖第一导电层15并填充了沟槽13的剩余部分。第一隔离层16和第一介质墙11的材料相同。
而后，半导体设备能够以第一隔离层和沟槽外剩余的第一介质墙为掩膜，刻蚀沟槽外剩余的第二介质墙，形成第二接触孔。这里，由于第一隔离层16和第一介质墙11的材料相同，半导体设备可以采用第二介质墙12的材料比第一隔离层16和第一介质墙11的材料较高的刻蚀选择比进行刻蚀，例如，第一隔离层16和第一介质墙11的材料为氮化硅，第二介质墙12的材料为氧化硅，则采用氧化硅比氮化硅较高的刻蚀选择比进行刻蚀，这样，则仅仅对沟槽13外剩余的第二介质墙12进行刻蚀，保留了第一隔离层16和第一介质墙11。图8A和图8B分别为俯视图和前视剖面图，如图8A和图8B所示，沟槽13外剩余的第二介质墙12被刻蚀后形成了第二接触孔18，第二接触孔18暴露出了有源区01。
S107、在第二接触孔内形成第二导电层。
本公开实施例中，半导体设备在形成了第二接触孔后，可以在在第二接触孔内形成第二导电层。图9A和图9B分别为俯视图和前视剖面图，如图9A和图9B所示，半导体设备在第二接触孔18内形成了第二导电层19。 第二导电层19填充了部分第二接触孔18，且与有源区01接触。
在本公开实施例中，半导体设备可以在第二接触孔内，先形成第二隔离层，图31B为前视剖面图，如图31B所示，第二隔离层17覆盖第一导电层15的侧面。而后，半导体设备可以沉积导电介质，导电介质的材料可以是多晶硅，图31A和图31B分别为俯视图和前视剖面图，如图31A和图31B所示，导电介质90填满了第二接触孔18，并覆盖了第一导电层15，第二隔离层17将导电介质90和第一导电层15隔离开。而后，半导体设备可以采用高选择比刻蚀导电介质90，即导电介质90的刻蚀速率高于其他材料的刻蚀速率；如此刻蚀，直到导电介质90的高度低于第二接触孔18的顶部，显露出沟槽外剩余的第一介质墙11和第一隔离层16，如图32A所示。这样，剩余的导电介质90形成了第二导电层19；而第二隔离层17则将第一导电层15和第二导电层19隔离开。
可以理解的是，在沟槽内形成第一导电层，通过第一接触孔与有源区接触；同时，利用沟槽外剩余的第二介质墙作为掩膜，在其对应位置刻蚀形成第二接触孔，并填入第二导电层。这样，不需要光罩，而利用半导体结构自身的图形刻蚀形成第二接触孔，达到了自对准的目的。
同时，第一导电层填入沟槽而形成，第二导电层填入第二接触孔而形成，其均为埋入式结构，从而降低了半导体结构的高度，有利于提高在垂直方向上的集成密度。
在本公开的一些实施例中，可以通过图10示出的S201～S204实现图1示出的S103，将结合各步骤进行说明。
S201、在第一介质墙和第二介质墙上，依次沉积第一阻挡层和第二阻挡层。
本公开实施例中，半导体设备可以在第一介质墙和第二介质墙上依次沉积第一阻挡层和第二阻挡层。需要说明的是，阻挡层用于根据需要形成向下转移的图案(pattern)，以及在刻蚀中对不需要刻蚀的区域进行保护。图11A和图11B分别为俯视图和前视剖面图，如图11A和图11B所示，第一介质墙11和第二介质墙12上依次沉积了第一阻挡层20和第二阻挡层30(由于遮挡关系，在图11B中未表现出第一介质墙11和第二介质墙12的交替结构)。第一阻挡层20和第二阻挡层30的材料可以包括：SiON(氮氧化硅)和SOH(Spin-on Hardmasks，旋涂硬掩模)。
S202、刻蚀第二阻挡层，形成沿第二方向延伸的心轴；心轴间隔设置。
本公开实施例中，半导体设备可以刻蚀第二阻挡层，形成沿第二方向延伸的心轴，其中，心轴间隔设置。
在本公开实施例中，如图11A和图11B所示，半导体设备可以先通过光刻工艺在第二阻挡层30上形成第一掩膜40，第一掩膜40的形状表征为沿第二方向Y延伸的第一刻蚀图形。而后，半导体设备可以沿第一刻蚀图形刻蚀第二阻挡层30，形成图12A和图12B中所示的心轴301。心轴301 沿第二方向Y延伸，且间隔设置。
S203、覆盖心轴的侧面形成侧墙。
本公开实施例中，半导体设备可以覆盖心轴的侧面形成侧墙。
在本公开实施例中，如图13A和图13B所示，半导体设备可以先采用ALD(Atomic Layer Deposition，原子层沉积)工艺沉积硬掩膜层31，以覆盖第一阻挡层20与心轴301。
而后，如图14A和图14B所示，半导体设备可以在硬掩膜层31间的空隙填充入第三介质层32，第三介质层32在后续的刻蚀中作为阻挡层。
而后，半导体设备可以对硬掩膜层31进行回刻，去除硬掩膜层31的顶部直到暴露心轴301，保留硬掩膜层31的侧部作为侧墙311，如图15A和图15B所示。侧墙311同样沿第二方向Y延伸。
S204、以侧墙为掩膜进行刻蚀，去除第一阻挡层，将第一介质墙和第二介质墙刻蚀形成沟槽。
本公开实施例中，半导体设备能够以侧墙为掩膜进行刻蚀，去除第一阻挡层，并将第一介质墙和第二介质墙刻蚀形成沿第二方向延伸的沟槽。
在本公开实施例中，参考图15A和图15B，侧墙311中间剩余有心轴301。半导体设备可以首先使用高选择比的刻蚀速率进行刻蚀，去除侧墙311中间剩余的心轴301，这里，高选择比是指心轴301的材料的刻蚀速率远大于其他材料的刻蚀速率，得到的结构如图16A和图16B所示。而后，结合图16B和图17B，半导体设备能够以侧墙311为掩膜，刻蚀第一阻挡层20，形成如图17B所示的第一中间结构201，并暴露出第一介质墙11和第二介质墙12。如图17A所示，第一中间结构201与侧墙311同样沿第二方向Y延伸，第一中间结构201的间隙处暴露出了第一介质墙11和第二介质墙12。
而后，结合图17B和图18B，半导体设备能够以第一中间结构201为掩膜，按照刻蚀速率比，对第一介质墙11和第二介质墙12进行刻蚀；这里，刻蚀速率比可以是第一介质墙的材料与第二介质墙的材料的刻蚀速率之比为1:4。这样，可以得到如图18B所示的结构，在第一中间结构201的间隙处，第一介质墙11和第二介质墙12被刻蚀形成了沟槽13；在沟槽13内，剩余的第一介质墙11的高度大于剩余的第二介质墙12的高度，即在图18B中，沟槽13内剩余的第一介质墙11遮挡住了剩余的第二介质墙12。
而后，半导体设备可以将剩余的第一中间结构201清除，从而得到如图3A和图3B所示的结构。这里，若采用第一介质墙的材料与第二介质墙的材料的刻蚀速率之比为1:4，则沟槽13内剩余的第一介质墙11的高度占沟槽13深度的四分之三。
可以理解的是，本公开实施例中，半导体设备在沉积了第一阻挡层20和第二阻挡层30后，先通过光刻工艺形成第一掩膜40，并沿第一掩膜40刻蚀形成心轴301；而后，覆盖心轴301的侧面形成侧墙311；最后，以侧墙311为掩膜，刻蚀形成沟槽13。由于侧墙311形成在心轴301的间隔区 域，其间距小于心轴301之间的间距。因此，以侧墙311为掩膜所形成的沟槽13，其宽度小于也心轴301之间的间距。这样，即使光刻工艺限制了所能达到的关键尺寸，也能够借助心轴301形成了关键尺寸更小的沟槽13，扩展了半导体设备所能达到的工艺尺寸限度。
在本公开的一些实施例中，可以通过S2021～S2022实现图10示出的S202，将结合各步骤进行说明。
S2021、在第二阻挡层上形成第一掩膜；第一掩膜包括沿第二方向延伸的第一刻蚀图形。
本公开实施例中，半导体设备可以首先在第二阻挡层上形成第一掩膜。其中，第一掩膜可以通过光刻工艺获得。图11A和图11B示例出了第一掩膜，分别是俯视图和前视剖面图，如图11A和图11B所示，第二阻挡层30上形成了第一掩膜40，第一掩膜40的第一刻蚀图形沿第二方向Y延伸。
S2022、沿第一刻蚀图形刻蚀第二阻挡层，形成沿第二方向延伸的心轴。
本公开实施例中，半导体设备在形成了第一掩膜40后，可以沿第一刻蚀图形刻蚀第二阻挡层30，形成图12A和图12B中所示的心轴301；心轴301同样沿第二方向Y延伸。
在本公开的一些实施例中，可以通过S2031～S2032实现图10示出的S203，将结合各步骤进行说明。
S2031、沉积硬掩膜层；硬掩膜层覆盖第一阻挡层及心轴。
本公开实施例中，如图13A和图13B所示，半导体设备可以先采用ALD工艺沉积硬掩膜层31，以覆盖第一阻挡层20与心轴301。
S2032、对硬掩膜层进行回刻，去除硬掩膜层的顶部直到暴露心轴，保留硬掩膜层的侧部作为侧墙。
本公开实施例中，半导体设备在沉积了硬掩膜层31后，可以对硬掩膜层31进行回刻，去除硬掩膜层31的顶部直到暴露心轴301，保留硬掩膜层31的侧部作为侧墙311，如图15A和图15B所示。
在本公开的一些实施例中，可以通过S2041～S2043实现图10示出的S204，将结合各步骤进行说明。
S2041、去除侧墙中间的心轴。
本公开实施例中，参考图15A和图15B，侧墙311中间剩余有心轴301。半导体设备可以首先使用高选择比的刻蚀速率进行刻蚀，去除侧墙311中间剩余的心轴301，得到的结构如图16A和图16B所示。
S2042、以侧墙为掩膜，刻蚀第一阻挡层，形成第一中间结构。
本公开实施例中，半导体设备去除了侧墙311中间剩余的心轴301后，能够以侧墙311为掩膜，刻蚀第一阻挡层20，形成如图17A和17B所示的第一中间结构201，并暴露出第一介质墙11和第二介质墙12。如图17A所示，第一中间结构201沿第二方向Y延伸，第一中间结构201的间隙处暴露出了第一介质墙11和第二介质墙12。
S2043、以第一中间结构为掩膜，按照刻蚀速率比刻蚀第一介质墙和第二介质墙，形成沟槽。
本公开实施例中，半导体设备形成了图17B示出的第一中间结构201后，能够以第一中间结构201为掩膜，按照刻蚀速率比，对第一介质墙11和第二介质墙12进行刻蚀，形成图3A和图3B示出的沟槽13；在沟槽13内，剩余的第一介质墙11的高度大于剩余的第二介质墙12的高度。
在本公开的一些实施例中，S2043中所述的刻蚀速率比包括：第一介质墙的材料与第二介质墙的材料的刻蚀速率之比为1:4。则对应的，按照1:4的刻蚀速率比进行刻蚀，沟槽13内剩余的第一介质墙11的高度占沟槽13深度的四分之三。
在本公开的一些实施例中，可以通过图19示出的S301～S303实现图1示出的S104，将结合各步骤进行说明。
S301、在沟槽上沉积第三阻挡层。
本公开实施例中，在形成沟槽后，半导体设备可以在沟槽上沉积第三阻挡层将沟槽覆盖。图20A和图20B分别为俯视图和前视剖面图，如图20A和图20B所示，第三阻挡层50沉积在沟槽13上，将沟槽13覆盖。
S302、在第三阻挡层上形成第二掩膜；第二掩膜包括间隔设置的第二刻蚀图形。
本公开实施例中，继续参考图20A和图20B，半导体设备可以通过光刻工艺在第三阻挡层50上形成第二掩膜60，其中，第二掩膜60包括了间隔设置的第二刻蚀图形601。
在本公开实施例中，第二刻蚀图形601为第二掩膜60上的凹孔，该凹孔需要对齐于沟槽13内剩余的第二介质墙12的方格孔，这样，则可以在剩余的第二介质墙12的位置形成第一接触孔14，如图4A所示。
S303、沿第二刻蚀图形进行刻蚀，去除第三阻挡层，将沟槽内剩余的第二介质墙刻蚀形成间隔设置的第一接触孔。
本公开实施例中，半导体设备可以沿第二刻蚀图形进行至少一次刻蚀，将第三阻挡层去除，并将沟槽内剩余的第二介质墙刻蚀形成间隔设置的第一接触孔。
在本公开实施例中，半导体设备可以先沿第二刻蚀图形601刻蚀第三阻挡层50，形成如图21A和图21B所示的第二中间结构501；第二刻蚀图形601被转移到了第二中间结构501上。而后，半导体设备能够以第二中间结构501为掩膜，刻蚀沟槽13内剩余的第二介质墙12，形成如图4A所示的第一接触孔14。
需要说明的是，第三阻挡层50中可以包括多种材料层，半导体设备可以根据不同材料选用不同的刻蚀速率比进行多次刻蚀，从而控制第二中间结构501上的第二刻蚀图形601的凹孔深度，进而可以控制所得到的第一接触孔14的深度。这样，可以使得在第一接触孔14的位置，有源区01被 暴露；而在其余位置，有源区01未被暴露。
可以理解的是，对应于沟槽内剩余的第二介质墙的位置，沿第二刻蚀图形刻蚀形成间隔设置的第一接触孔，将有源区暴露。这样，仅通过一次光罩，便为金属布线提供了与有源区的接触点。
在本公开的一些实施例中，可以通过S3031～S3032来实现图19示出的S303，将结合各步骤进行说明。
S3031、沿第二刻蚀图形刻蚀第三阻挡层，形成第二中间结构。
本公开实施例中，半导体设备可以先沿第二刻蚀图形601刻蚀第三阻挡层50，形成如图21A和图21B所示的第二中间结构501。
S3032、以第二中间结构为掩膜，刻蚀沟槽内剩余的第二介质墙，形成间隔设置的第一接触孔。
本公开实施例中，半导体设备能够以第二中间结构501为掩膜，刻蚀沟槽13内剩余的第二介质墙12，形成如图4A所示的第一接触孔14。
在本公开的一些实施例中，可以通过图22示出的S401～S403来实现图5示出的S105，将结合各步骤进行说明。
S401、在第一接触孔内沉积金属隔离层。
本公开实施例中，参考图4A，第一接触孔14暴露出了有源区01，可以作为金属层和有源区01的接触点。半导体设备在向第一接触孔内填充金属层前，需要先在第一接触孔内沉积金属隔离层。金属隔离层部分填充了第一接触孔14，且覆盖了所暴露出的有源区01。金属隔离层的材料可以是氮化钛(TiN)，其可以阻挡金属材料向有源区中扩散。
S402、沉积金属层；金属层覆盖金属隔离层，且填充第一接触孔和沟槽。
本公开实施例中，在沉积了金属隔离层后，半导体设备可以沉积金属层。图23为前视剖面图，如图23所示，金属层70覆盖了金属隔离层，且填充了第一接触孔14(因遮挡而未示出)和沟槽13。其中，金属层70的材料可以是钨(W)或铜(Cu)。
S403、研磨金属层，直到沟槽的顶部为止，从而形成第一导电层。
本公开实施例中，在沉积了金属层70后，半导体设备可以研磨金属层70，直到沟槽13的顶部为止，即采用大马士革工艺，将金属层70研磨形成如图24A和24B所示的第一导电层15。
在本公开实施例中，第一导电层15可以用于位线结构。
可以理解的是，在沟槽内形成第一导电层，通过第一接触孔与有源区接触，这样，形成埋入式的位线结构，降低了半导体结构的高度，有利于提高在垂直方向上的集成密度。
在本公开的一些实施例中，可以通过图25示出的S501～S502来实现图5示出的S106，将结合各步骤进行说明。
S501、在第一导电层上，形成第一隔离层；第一隔离层的材料和第一 介质墙的材料相同。
本公开实施例中，半导体设备可以先在第一导电层上，形成第一隔离层，其中，第一隔离层的材料和第一介质墙的材料相同。
在本公开实施例中，参考图24B和图26，半导体设备可以首先采用高选择比刻蚀速率对第一导电层15进行刻蚀，以降低第一导电层的高度。这里，高选择比是指第一导电层15的材料的刻蚀速率远大于其他材料的刻蚀速率。
而后，如图27所示，半导体设备可以在第一导电层15上，沉积第四阻挡层80。第四阻挡层80覆盖沟槽外剩余的第二介质墙12。
而后，如图28A和图28B所示，半导体设备可以研磨第四阻挡层80，直到暴露沟槽外剩余的第二介质墙12为止，剩余的第四阻挡层80形成第一隔离层16。
S502、以第一隔离层和沟槽外剩余的第一介质墙为掩膜，刻蚀沟槽外剩余的第二介质墙，形成第二接触孔。
在本公开实施例中，结合图28A、图28B、图29A和图29B，由于第一隔离层16和第一介质墙11的材料相同，半导体设备能够以第一隔离层16和沟槽外剩余的第一介质墙11为掩膜，刻蚀沟槽外剩余的第二介质墙12，在第二介质墙12的位置形成第二接触孔18。第二接触孔18暴露出有源区01。
可以理解的是，利用沟槽外剩余的第二介质墙作为光罩，在其对应位置刻蚀形成第二接触孔，并填入第二导电层。这样，不需要光罩，而利用半导体结构自身的图形刻蚀形成第二接触孔，达到了自对准的目的；同时，第二导电层为埋入式结构，降低了半导体结构的高度，有利于提高在垂直方向上的集成度。
在本公开的一些实施例中，可以通过S5011～S5013来实现图25示出的S501，将结合各步骤进行说明。
S5011、刻蚀第一导电层，降低第一导电层的高度。
在本公开实施例中，参考图24B和图26，半导体设备可以首先采用高选择比刻蚀速率对第一导电层15进行刻蚀，以降低第一导电层的高度。
S5012、在第一导电层上，沉积第四阻挡层；第四阻挡层覆盖沟槽外剩余的第二介质墙。
在本公开实施例中，如图27所示，半导体设备可以在第一导电层15上，沉积第四阻挡层80。第四阻挡层80覆盖沟槽外剩余的第二介质墙12。
S5013、研磨第四阻挡层，直到暴露沟槽外剩余的第二介质墙为止，剩余的第四阻挡层形成第一隔离层。
在本公开实施例中，如图28A和图28B所示，半导体设备可以研磨第四阻挡层80，直到暴露沟槽外剩余的第二介质墙12为止，剩余的第四阻挡层80形成第一隔离层16。
在本公开的一些实施例中，可以通过图30示出的S601～S603来实现图5示出的S107，将结合各步骤进行说明。
S601、在第二接触孔内，形成第二隔离层；第二隔离层覆盖第一导电层的侧面。
本公开实施例中，半导体设备可以在第二接触孔内，形成第二隔离层。图31B为前视剖面图，如图31B所示，第二隔离层17覆盖第一导电层15的侧面。其中，第二隔离层17的材料与第一介质墙11的材料相同。
S602、沉积导电介质；导电介质填满第二接触孔。
本公开实施例中，在形成第二隔离层后，半导体设备可以沉积导电介质。图31A和图31B分别为俯视图和前视剖面图，如图31A和图31B所示，导电介质90填满了第二接触孔18，并覆盖了第一导电层15；第二隔离层17将导电介质90和第一导电层15隔离开。其中，导电介质90的材料可以是多晶硅。
S603、高选择比刻蚀导电介质，直到导电介质的高度低于第二接触孔的顶部，剩余的导电介质形成第二导电层；第二隔离层隔离第一导电层和第二导电层。
本公开实施例中，图32A和图32B分别为俯视图和前视剖面图，结合图31A、图31B、图32A和图32B，在沉积了导电介质90后，半导体设备可以采用高选择比刻蚀导电介质90，即导电介质90的刻蚀速率高于其他材料的刻蚀速率；如此刻蚀，直到导电介质90的高度低于第二接触孔18的顶部，显露出沟槽外剩余的第一介质墙11和第一隔离层16，如图32A所示。这样，剩余的导电介质90形成了第二导电层19；而第二隔离层17则将第一导电层15和第二导电层19隔离开。
可以理解的是，选用与第一介质墙11相同的材料，在第一导电层15的侧面形成第二隔离层17。这样，可利用材料特性选择合适的刻蚀选择比刻蚀导电介质90，使得第一介质墙11和第二隔离层17得以保留；同时，第二隔离层17将第一导电层15和第二导电层19隔离开，避免了短路。
本公开实施例还提供了一种半导体结构08，半导体结构08由前述实施例提供的制备方法制备而成。
本公开实施例还提供了一种半导体存储器09，如图33所示，半导体存储器09至少包括半导体结构08。
在本公开的一些实施例中，图33示出的半导体存储器09至少包括动态随机存取存储器DRAM。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括 该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种半导体结构的制备方法、半导体结构和半导体存储器，能够在所提供的衬底上形成沿第一方向延伸的第一介质墙和第二介质墙，其中，第一介质墙和第二介质墙交替分布；而后，刻蚀第一介质墙和第二介质墙，形成沿第二方向延伸的沟槽，其中，沟槽内剩余的第一介质墙的高度大于剩余的第二介质墙的高度；而后，刻蚀沟槽内剩余的第二介质墙，在沟槽内形成间隔设置的第一接触孔，其中，第一接触孔暴露出衬底中的有源区。这样，沟槽提供了金属布线的埋入区域，第一接触孔则提供了金属布线与有源区的接触点，而两次刻蚀仅需要两次光罩；从而，以较少的光罩次数形成了可以进行金属布线的新颖半导体结构，为半导体工艺提供了新的选择。

Claims (16)

  1. 一种半导体结构的制备方法，所述方法包括：
    提供衬底；所述衬底内包括有源区；
    在所述衬底上形成沿第一方向延伸的第一介质墙和第二介质墙；所述第一介质墙和所述第二介质墙交替分布；
    刻蚀所述第一介质墙和所述第二介质墙，形成沿第二方向延伸的沟槽；其中，所述沟槽间隔设置；在所述沟槽内，剩余的所述第一介质墙的高度大于剩余的所述第二介质墙的高度；
    刻蚀所述沟槽内剩余的所述第二介质墙，在所述沟槽内形成间隔设置的第一接触孔；所述第一接触孔暴露所述有源区。
  2. 根据权利要求1所述的制备方法，其中，所述刻蚀所述沟槽内剩余的所述第二介质墙，在所述沟槽内形成间隔设置的接触孔之后，所述方法还包括：
    在所述沟槽内形成第一导电层；所述第一导电层填充所述第一接触孔，且填充至少部分所述沟槽；
    刻蚀所述沟槽外剩余的所述第二介质墙，形成第二接触孔；所述第二接触孔暴露所述有源区；
    在所述第二接触孔内形成第二导电层。
  3. 根据权利要求1所述的制备方法，其中，所述刻蚀所述第一介质墙和所述第二介质墙，形成沿第二方向延伸的沟槽，包括：
    在所述第一介质墙和所述第二介质墙上，依次沉积第一阻挡层和第二阻挡层；
    刻蚀所述第二阻挡层，形成沿所述第二方向延伸的心轴；所述心轴间隔设置；
    覆盖所述心轴的侧面形成侧墙；
    以所述侧墙为掩膜进行刻蚀，去除所述第一阻挡层，将所述第一介质墙和所述第二介质墙刻蚀形成所述沟槽。
  4. 根据权利要求3所述的制备方法，其中，所述刻蚀所述第二阻挡层，形成沿所述第二方向延伸的心轴，包括：
    在所述第二阻挡层上形成第一掩膜；所述第一掩膜包括沿所述第二方向延伸的第一刻蚀图形；
    沿所述第一刻蚀图形刻蚀所述第二阻挡层，形成沿所述第二方向延伸的所述心轴。
  5. 根据权利要求3所述的制备方法，其中，所述覆盖所述心轴侧面形成侧墙，包括：
    沉积硬掩膜层；所述硬掩膜层覆盖所述第一阻挡层及所述心轴；
    对所述硬掩膜层进行回刻，去除所述硬掩膜层的顶部直到暴露所述心轴，保留所述硬掩膜层的侧部作为所述侧墙。
  6. 根据权利要求3所述的制备方法，其中，所述以所述侧墙为掩膜进行刻蚀，去除所述第一阻挡层，将所述第一介质墙和所述第二介质墙刻蚀形成所述沟槽，包括：
    去除所述侧墙中间的所述心轴；
    以所述侧墙为掩膜，刻蚀所述第一阻挡层，形成第一中间结构；
    以所述第一中间结构为掩膜，按照刻蚀速率比刻蚀所述第一介质墙和所述第二介质墙，形成所述沟槽。
  7. 根据权利要求6所述的制备方法，其中，
    所述刻蚀速率比包括：所述第一介质墙的材料与所述第二介质墙的材料的刻蚀速率之比为1:4。
  8. 根据权利要求1所述的制备方法，其中，所述刻蚀所述沟槽内剩余的所述第二介质墙，在所述沟槽内形成间隔设置的第一接触孔，包括：
    在所述沟槽上沉积第三阻挡层；
    在所述第三阻挡层上形成第二掩膜；所述第二掩膜包括间隔设置的第二刻蚀图形；
    沿所述第二刻蚀图形进行刻蚀，去除所述第三阻挡层，将所述沟槽内剩余的所述第二介质墙刻蚀形成间隔设置的所述第一接触孔。
  9. 根据权利要求8所述的制备方法，其中，所述沿所述第二刻蚀图形进行刻蚀，去除所述第三阻挡层，将所述沟槽内剩余的所述第二介质墙刻蚀形成间隔设置的所述第一接触孔，包括：
    沿所述第二刻蚀图形刻蚀所述第三阻挡层，形成第二中间结构；
    以所述第二中间结构为掩膜，刻蚀所述沟槽内剩余的所述第二介质墙，形成间隔设置的所述第一接触孔。
  10. 根据权利要求2所述的制备方法，其中，所述第一导电层包括：金属隔离层和金属层；所述在所述沟槽内形成第一导电层，包括：
    在所述第一接触孔内沉积所述金属隔离层；
    沉积所述金属层；所述金属层覆盖所述金属隔离层，且填充所述第一接触孔和所述沟槽；
    研磨所述金属层，直到所述沟槽的顶部为止，从而形成所述第一导电层。
  11. 根据权利要求2所述的制备方法，其中，所述刻蚀所述沟槽外剩余的所述第二介质墙，形成第二接触孔，包括：
    在所述第一导电层上，形成第一隔离层；所述第一隔离层的材料和所述第一介质墙的材料相同；
    以所述第一隔离层和所述沟槽外剩余的所述第一介质墙为掩膜，刻蚀所述沟槽外剩余的所述第二介质墙，形成所述第二接触孔。
  12. 根据权利要求11所述的制备方法，其中，所述在所述第一导电层上，形成第一隔离层，包括：
    刻蚀所述第一导电层，降低所述第一导电层的高度；
    在所述第一导电层上，沉积第四阻挡层；所述第四阻挡层覆盖所述沟槽外剩余的所述第二介质墙；
    研磨所述第四阻挡层，直到暴露所述沟槽外剩余的所述第二介质墙为止，剩余的所述第四阻挡层形成所述第一隔离层。
  13. 根据权利要求2所述的制备方法，其中，所述在所述第二接触孔内形成第二导电层，包括：
    在所述第二接触孔内，形成第二隔离层；所述第二隔离层覆盖所述第一导电层的侧面；
    沉积导电介质；所述导电介质填满所述第二接触孔；
    高选择比刻蚀所述导电介质，直到所述导电介质的高度低于所述第二接触孔的顶部，剩余的所述导电介质形成所述第二导电层；所述第二隔离层隔离所述第一导电层和所述第二导电层。
  14. 一种半导体结构，所述半导体结构由权利要求1至13任一项所述的制备方法制备而成。
  15. 一种半导体存储器，包括如权利要求14所述的半导体结构。
  16. 根据权利要求15所述的半导体存储器，所述半导体存储器至少包括动态随机存取存储器DRAM。
PCT/CN2021/137551 2021-11-24 2021-12-13 一种半导体结构的制备方法、半导体结构和半导体存储器 WO2023092706A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/844,209 US20230164983A1 (en) 2021-11-24 2022-06-20 Method for preparing semiconductor structure, semiconductor structure and semiconductor memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111403797.6A CN116169091A (zh) 2021-11-24 2021-11-24 一种半导体结构的制备方法、半导体结构和半导体存储器
CN202111403797.6 2021-11-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/844,209 Continuation US20230164983A1 (en) 2021-11-24 2022-06-20 Method for preparing semiconductor structure, semiconductor structure and semiconductor memory

Publications (1)

Publication Number Publication Date
WO2023092706A1 true WO2023092706A1 (zh) 2023-06-01

Family

ID=86420500

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/137551 WO2023092706A1 (zh) 2021-11-24 2021-12-13 一种半导体结构的制备方法、半导体结构和半导体存储器

Country Status (2)

Country Link
CN (1) CN116169091A (zh)
WO (1) WO2023092706A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117545275A (zh) * 2024-01-08 2024-02-09 长鑫新桥存储技术有限公司 半导体结构的制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116364658B (zh) * 2023-05-31 2023-08-01 合肥晶合集成电路股份有限公司 半导体结构的制作方法以及半导体结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080057712A1 (en) * 2006-06-16 2008-03-06 Synopsys, Inc. Method For Achieving Uniform Etch Depth Using Ion Implantation And A timed Etch
CN111192875A (zh) * 2018-11-14 2020-05-22 长鑫存储技术有限公司 一种半导体结构及其制作方法
CN111627977A (zh) * 2019-02-28 2020-09-04 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、半导体器件
CN112951720A (zh) * 2019-11-26 2021-06-11 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法、半导体器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080057712A1 (en) * 2006-06-16 2008-03-06 Synopsys, Inc. Method For Achieving Uniform Etch Depth Using Ion Implantation And A timed Etch
CN111192875A (zh) * 2018-11-14 2020-05-22 长鑫存储技术有限公司 一种半导体结构及其制作方法
CN111627977A (zh) * 2019-02-28 2020-09-04 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、半导体器件
CN112951720A (zh) * 2019-11-26 2021-06-11 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法、半导体器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117545275A (zh) * 2024-01-08 2024-02-09 长鑫新桥存储技术有限公司 半导体结构的制作方法
CN117545275B (zh) * 2024-01-08 2024-05-14 长鑫新桥存储技术有限公司 半导体结构的制作方法

Also Published As

Publication number Publication date
CN116169091A (zh) 2023-05-26

Similar Documents

Publication Publication Date Title
CN102881658B (zh) 制作具有埋入式位线与埋入式字线的内存装置的方法
US9613967B1 (en) Memory device and method of fabricating the same
US8120103B2 (en) Semiconductor device with vertical gate and method for fabricating the same
US20070235801A1 (en) Self-aligned body contact for a semicondcutor-on-insulator trench device and method of fabricating same
WO2023092706A1 (zh) 一种半导体结构的制备方法、半导体结构和半导体存储器
KR20090085642A (ko) 패턴 층을 에칭하여 그 안에 스태거형 하이트들을 형성하는 방법 및 중간 반도체 디바이스 구조물
JP2002094027A (ja) 半導体記憶装置とその製造方法
KR20110030782A (ko) 반도체 소자의 제조 방법
US20130302968A1 (en) Memory device and method for manufacturing memory device
WO2014123170A1 (ja) 半導体装置及びその製造方法
US20220328494A1 (en) Memory forming method and memory
TWI490928B (zh) 埋入式字元線結構及其形成方法
WO2023070959A1 (zh) 一种有源区结构的制备方法、半导体结构和半导体存储器
WO2023000461A1 (zh) 存储器件及其形成方法
CN112071838A (zh) 存储器及其形成方法
CN112289800B (zh) 一种三维存储器件及其制造方法
KR20230094338A (ko) 반도체 소자의 제조 방법
JP2013201414A (ja) 半導体装置及びその製造方法
WO2023103139A1 (zh) 一种半导体结构的制备方法、半导体结构和半导体存储器
JP2014216409A (ja) 半導体装置の製造方法
US20230164983A1 (en) Method for preparing semiconductor structure, semiconductor structure and semiconductor memory
CN113517286B (zh) 一种半导体器件及其形成方法、电子设备
CN209785940U (zh) 存储器
WO2023035455A1 (zh) 半导体结构的形成方法及半导体结构
WO2023231196A1 (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21965428

Country of ref document: EP

Kind code of ref document: A1