WO2023168778A1 - 存储器及其形成方法 - Google Patents

存储器及其形成方法 Download PDF

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Publication number
WO2023168778A1
WO2023168778A1 PCT/CN2022/086255 CN2022086255W WO2023168778A1 WO 2023168778 A1 WO2023168778 A1 WO 2023168778A1 CN 2022086255 W CN2022086255 W CN 2022086255W WO 2023168778 A1 WO2023168778 A1 WO 2023168778A1
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Prior art keywords
layer
isolation
sub
etching
forming
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PCT/CN2022/086255
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English (en)
French (fr)
Inventor
肖德元
邵光速
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长鑫存储技术有限公司
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Priority to US17/805,966 priority Critical patent/US20230292485A1/en
Publication of WO2023168778A1 publication Critical patent/WO2023168778A1/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a memory and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • the memory and its forming method provided by some embodiments of the present disclosure are at least partially used to solve the problem of easy leakage at the bottom of the capacitor, thereby improving the electrical performance of the memory.
  • the present disclosure provides a memory forming method including the following steps:
  • a capacitor is formed in the capacitor hole.
  • the specific steps of forming a plurality of capacitor holes and a plurality of grooves connected one by one to the plurality of capacitor holes and located below the capacitor holes include:
  • the first direction and the second direction are both parallel to the top surface of the initial substrate, and the first direction and the second direction are orthogonal;
  • Etching the initial substrate to form a plurality of second etching grooves each of the second etching grooves extending along the second direction, and the plurality of second etching grooves are parallel to each other and at Arranged at intervals in the first direction, the initial substrate remaining at the bottom of the second etching groove and the bottom of the first etching groove serves as the substrate;
  • the first etching groove and the second etching groove are connected to form the capacitor hole.
  • the following steps are further included:
  • a first filling layer filling the first etching trench is formed.
  • the specific steps of forming the groove with a width greater than that of the second etching groove include:
  • the initial substrate at the bottom of the second etching groove is etched using a Bosch etching process to form the groove.
  • the first etching groove and the second etching groove are connected, and the specific steps of forming the capacitor hole include:
  • the mask layer including a plurality of openings exposing the overlapping areas of the first etching trench and the second etching trench;
  • the first filling layer and the second filling layer are removed along the opening to form the capacitor hole.
  • a patterned mask layer is formed over the initial substrate, and the mask layer includes a plurality of areas exposing the overlapping areas of the first etching trench and the second etching trench.
  • the specific steps for opening include:
  • a sub-opening is arranged at intervals along the second direction;
  • the third filling layer is removed along the opening to expose the overlapping area of the first etching groove and the second etching groove.
  • the initial substrate remaining between adjacent capacitor holes serves as a first isolation pillar, and the remaining initial substrate between adjacent grooves serves as a second isolation pillar.
  • the width of the second isolation column is 1/2 to 1/3 of the width of the first isolation column. In the second direction, the width of the second isolation column is It is equal to the width of the first isolation column.
  • the specific steps of forming an isolation layer that communicates with adjacent grooves and fills the grooves include:
  • the first isolation pillar and all the second isolation pillars along the oxidized part of the opening form isolation sidewalls on the side walls of the capacitor hole, and a first sub-section is formed between the adjacent grooves. Isolation layer;
  • a second sub-isolation layer is deposited in the groove along the opening to form the isolation layer including the first sub-isolation layer and the second sub-isolation layer.
  • the specific steps of depositing a second sub-isolation layer in the groove along the opening include:
  • the initial substrate is made of silicon
  • the first sub-isolation layer and the second sub-isolation layer are both made of silicon dioxide.
  • the specific steps of forming a capacitor in the capacitor hole include:
  • a second electrode is formed covering the dielectric layer to form the capacitor including the first electrode, the dielectric layer and the second electrode.
  • the following steps are further included:
  • a covering layer is formed to cover the exposed first isolation column.
  • the following steps are further included:
  • the first isolation pillar in the cover layer is doped to form an active region of the transistor.
  • the present disclosure also provides a memory, including:
  • a capacitor array located above the isolation layer, including a plurality of capacitors, each of the capacitors including a first electrode extending in a direction perpendicular to the top surface of the substrate, and a dielectric layer covering the surface of the first electrode , and a second electrode covering the surface of the dielectric layer.
  • it also includes:
  • a first isolation pillar is located between two adjacent capacitors
  • the isolation layer includes a first sub-isolation layer located between the first isolation pillar and the substrate, and a second sub-isolation layer located below the capacitor.
  • the first sub-isolation layer is made of the same material as the second sub-isolation layer.
  • the material of the substrate and the first isolation pillar are silicon
  • the material of the first sub-isolation layer and the second sub-isolation layer are silicon dioxide.
  • the first electrode covers the sidewall of the first isolation pillar
  • the dielectric layer covers the surface of the first electrode and the surface of the second sub-isolation layer.
  • the bottom surface of the first isolation pillar is located below the bottom surface of the first electrode.
  • it also includes:
  • a gate electrode is provided surrounding the channel region.
  • Some embodiments of the present disclosure provide a memory and a method for forming the same.
  • a groove is formed below the capacitor hole used to form the capacitor, and the groove is formed and filled until the groove is connected to the capacitor.
  • a capacitor is formed in the capacitor hole above the isolation layer to electrically isolate the bottom of the capacitor from the substrate through the isolation layer, thereby reducing or even avoiding the problem of leakage at the bottom of the capacitor. This improves the electrical performance of the memory.
  • the memory formation method compared with forming an isolation layer directly on a substrate through a deposition or oxidation process, integrates the formation process of the capacitor hole with the formation process of the isolation layer, so that it can be formed
  • the formation process of the isolation layer is carried out at the same time as the capacitor hole.
  • the isolation layer is formed directly under the capacitor to ensure that the isolation layer can be fully aligned with the bottom of the capacitor, which simplifies the manufacturing process of the memory and reduces the cost of the memory. While reducing process difficulty, the electrical isolation effect between the capacitor and the substrate can be further improved.
  • FIG. 1 is a flow chart of a memory forming method in a specific embodiment of the present disclosure
  • 2A-2Q are schematic diagrams of the main process structures in the process of forming a memory according to the specific embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a memory in a specific embodiment of the present disclosure.
  • FIG. 1 is a flow chart of the memory forming method in the specific embodiment of the present disclosure.
  • Figures 2A-2Q illustrate the main steps in the process of forming the memory in the specific embodiment of the present disclosure. Schematic diagram of the process structure.
  • the memory described in this specific embodiment may be, but is not limited to, a DRAM memory.
  • Figure 2A- Figure 2Q the memory forming method provided by this specific embodiment includes the following steps:
  • Step S11 providing an initial substrate 20.
  • the initial substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the initial substrate 20 as a silicon substrate as an example.
  • the initial substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • step S12 the initial substrate 20 is etched to form a plurality of capacitor holes 35 and a plurality of grooves 24 that are connected to the plurality of capacitor holes 35 one by one and located below the capacitor holes 35, remaining in the capacitor holes 35.
  • the portion of the initial substrate below the groove 24 serves as substrate 25 .
  • the specific steps of forming a plurality of capacitor holes 35 and a plurality of grooves 24 connected one by one with the plurality of capacitor holes 35 and located below the capacitor holes 35 include:
  • the initial substrate 20 is etched to form a plurality of first etching grooves 21 , each of the first etching grooves 21 extends along the first direction D1 , the plurality of first etching grooves 21 are parallel to each other, and Arranged at intervals in the second direction D2, the first direction D1 and the second direction D2 are both parallel to the top surface of the initial substrate 20, and the first direction D1 and the second direction D2 Orthogonal, as shown in Figure 2A;
  • the initial substrate 20 is etched to form a plurality of second etching grooves 23 , each second etching groove 23 extends along the second direction D2 , and the plurality of second etching grooves 23 are parallel to each other. , and arranged at intervals in the first direction D1;
  • the first etching groove 21 and the second etching groove 23 are connected to form the capacitor hole 35, as shown in FIG. 2J.
  • a dry etching process may be used to etch the initial substrate 20 in a direction perpendicular to the top surface of the initial substrate 20 (for example, the third direction D3 in FIG. 2A ) to form a plurality of The first etching grooves 21 each extend along the first direction D1, and a plurality of the first etching grooves 21 are parallel to each other and arranged at intervals along the second direction D2.
  • etching parameters such as the dose of the etching gas and/or the etching time, can be controlled so that along the vertical In the direction of the top surface of the original substrate 20 , the first etching groove 21 does not penetrate the original substrate 20 .
  • a first filling layer 22 filling the first etching trench 21 is formed, as shown in FIG. 2B .
  • the specific steps of forming the groove 24 with an inner diameter larger than that of the second etching groove 23 include:
  • the initial substrate 20 at the bottom of the second etching groove 23 is etched using a Bosch etching process to form the groove 24, as shown in FIG. 2C.
  • a chemical vapor deposition process may also be used before forming the second etching groove 23.
  • physical vapor deposition process or atomic layer deposition process deposits insulating materials such as silicon dioxide in the first etching trench 21 to form the first filling layer 22 that fills the first etching trench 21, as shown in Figure As shown in 2B.
  • a dry etching process may be used to etch the initial substrate 20 in a direction perpendicular to the top surface of the initial substrate 20 (for example, the third direction D3 in FIG. 2A ) to form a plurality of second etching processes.
  • each of the second etching grooves 23 extends along the second direction D2, and a plurality of the second etching grooves 23 are parallel to each other and arranged at intervals along the first direction D1, that is, the third etching groove 23 extends along the second direction D2.
  • the projection of the second etching trench 23 in the direction perpendicular to the top surface of the initial substrate 20 is orthogonal to the projection of the first etching trench 21 in the direction perpendicular to the top surface of the initial substrate 20 .
  • the Bosch etching process is used to continue etching the initial substrate 20 at the bottom of the second etching trench 23 along the first etching trench 21, thereby forming a connection with the bottom of the second etching trench 23.
  • the inner diameter is larger than the groove 24 of the second etching groove 23 . Since the inner diameter of the groove 24 is larger than the inner diameter of the second etching groove 23 , the initial lining remaining between the adjacent second etching grooves 23 along the first direction D1 The width of the bottom 20 (ie, the first isolation pillar 31) is greater than the width of the original substrate 20 (ie, the second isolation pillar 32) remaining between the adjacent grooves 24.
  • the Bosch etching process is then used to form the groove 24, so as to simplify the formation process of the memory.
  • those skilled in the art may also select other etching processes as needed to form the second etching groove 23 and the groove 24 connected with the second etching groove 23 .
  • the first etching groove 21 and the second etching groove 23 are connected, and the specific steps of forming the capacitor hole 35 include:
  • a patterned mask layer is formed above the initial substrate 20, and the mask layer includes a plurality of openings 45 exposing the overlapping areas of the first etching trench 21 and the second etching trench 23, As shown in Figure 2I;
  • the first filling layer 22 and the second filling layer 26 are removed along the opening 45 to form the capacitor hole 35, as shown in FIG. 2J.
  • the first filling layer 22 and the second filling layer 26 can be removed by selective etching.
  • Layer 26 connects the first etching groove 21 and the second etching groove 23 inside the initial substrate 20 .
  • a patterned mask layer is formed above the initial substrate 20 , and the mask layer includes a plurality of exposed intersections of the first etching trench 21 and the second etching trench 23 .
  • the specific steps of opening 45 in the stacking area include:
  • the first sub-mask layer 27 is etched to form a plurality of first sub-openings 28 exposing the first filling layer 22 , each of the first sub-openings 28 extends along the first direction D1, and The plurality of first sub-openings 28 are arranged in parallel along the second direction D2, as shown in Figure 2F;
  • the first sub-mask layer 27 and the third filling layer 39 are etched to form a plurality of second sub-openings 30 exposing the initial substrate 20 , and each of the second sub-openings 30 is along a line parallel to The direction of the second direction D2 extends, and the plurality of second sub-openings 30 are arranged in parallel along the first direction D1, as shown in Figure 2H;
  • the second sub-mask layer 33 is filled in the second sub-opening 30 to form the mask layer including the second sub-mask layer 33 and the remaining first sub-mask layer 27.
  • the mold layer includes a plurality of openings 45 exposing the third filling layer 39, as shown in Figure 2I;
  • the third filling layer 39 is removed along the opening 45 to expose the overlapping area of the first etching groove 21 and the second etching groove 23 .
  • a hard mask material such as silicon nitride or an organic mask material such as carbon is deposited on the second etching groove 23 and the groove 24.
  • the first sub-mask layer 27 is formed on the top surface of the initial substrate 20, as shown in FIG. 2E.
  • the first sub-mask layer 27 is used as a mask for subsequent removal of the first filling layer 22 and the second filling layer 26; on the other hand, it is also used to support the adjacent second etching groove.
  • the first isolation column 31 between 23 prevents tipping or collapse during subsequent removal of the first filling layer 22 and the second filling layer 26 .
  • the first sub-mask layer 27 may be etched using the same mask used to form the first etching trench 21 to form a plurality of first sub-openings 28 exposing the first filling layer 22.
  • Each of the first sub-openings 28 extends along the first direction D1, and a plurality of the first sub-openings 28 are arranged in parallel along the second direction D2, as shown in FIG. 2F.
  • the first sub-opening 28 is filled to form the third filling layer 39, as shown in FIG. 2G.
  • the first sub-mask layer 27 and the third filling layer 39 are etched to form a plurality of second sub-openings 30 exposing the initial substrate 20 , each of the second sub-openings 30 is along a Extending in a direction parallel to the second direction D2, the plurality of second sub-openings 30 are parallel to each other and arranged at intervals along the first direction D1, as shown in FIG. 2H.
  • the remaining first sub-mask layer 27 intersects the second sub-mask layer 33 , thereby forming a plurality of exposed third filling layers.
  • the opening 45 of layer 39 is shown in Figure 2I.
  • An etching process is used to remove the third filling layer 39 , the first filling layer 22 and the second filling layer 26 along the opening 45 , thereby connecting the first etching inside the initial substrate 20
  • the groove 21 and the second etching groove 23 form the capacitor hole 35, as shown in FIG. 2J.
  • the material of the first filling layer 22 , the material of the second filling layer 26 and the material of the third filling layer 39 are all the same.
  • the material of the first filling layer 22 , the material of the second filling layer 26 and the third filling layer 39 are all the same.
  • the material of the second filling layer 26 and the third filling layer 39 are both silicon dioxide, so that the first filling layer 22, the second filling layer 26 and all the materials can be removed simultaneously through a one-step etching process.
  • the third filling layer 39 is formed, thereby further simplifying the manufacturing process of the memory.
  • step S13 an isolation layer is formed that connects the adjacent grooves 24 and fills the grooves 24, and the original substrate 20 remaining under the isolation layer serves as the substrate 25, as shown in FIG. 2M.
  • the initial substrate 20 remaining between the adjacent capacitor holes 35 serves as the first isolation pillar 31 , and the initial substrate 20 remaining between the adjacent grooves 24 As the second isolation column 32, as shown in Figure 2J;
  • the width of the second isolation pillar 32 is 1/2 ⁇ 1/3 of the width of the first isolation pillar 31.
  • the width of the second isolation pillar 32 is 1/2 ⁇ 1/3 of the width of the first isolation pillar 31.
  • the width of the isolation pillar 32 is equal to the width of the first isolation pillar 31 .
  • the second isolation pillar 32 between the adjacent grooves 24 is in the first position.
  • the width in one direction D1 is smaller than the width of the first isolation pillar 31 between adjacent capacitor holes 35 in the first direction, so that the second isolation pillar 32 can be fully modified later. processing, so that the substrate 25 and the capacitor can be fully isolated later.
  • the width of the second isolation column 32 should not be too small, because if the width of the second isolation column 32 is too small, it cannot stably support the first isolation column 31 above the second isolation column 32.
  • the specific steps of forming an isolation layer that communicates with adjacent grooves 24 and fills the grooves 24 include:
  • first isolation pillar 31 and the entire second isolation pillar 32 along the opening 45 form isolation sidewalls 37 on the side walls of the capacitor hole 35 and the adjacent groove 24
  • a first sub-isolation layer 36 is formed therebetween, as shown in Figure 2K;
  • the initial substrate 20 is made of silicon, and the first sub-isolation layer 36 and the second sub-isolation layer 38 are both made of silicon dioxide.
  • the material of the initial substrate 20 is silicon
  • the materials of the first sub-isolation layer 36 and the second sub-isolation layer 38 are silicon dioxide.
  • the first isolation pillar 31, the second isolation pillar 32, and the portion of the initial substrate 20 at the bottom of the groove 24 are oxidized in situ (for example, water vapor is generated in situ).
  • the width of an isolation column 31 in the first direction D1 is greater than the width of the second isolation column 32 in the first direction D1.
  • the oxidation parameters (such as oxidation time, oxidant dosage, etc.) can be controlled so that The second isolation pillar 32 can be completely oxidized, and only the surface of the first isolation pillar 31 is oxidized, thereby forming the isolation sidewall 37 covering the side wall of the capacitor hole 35 and the adjacent groove. 24 and covering the bottom surface of the groove 24 , as shown in FIG. 2K .
  • silicon dioxide material is deposited along the opening 45 in the capacitor hole 35 and the groove 24 to form the second second layer filled with the opening 45 , the capacitor hole 35 and the groove 24 .
  • Sub-isolation layer 38 as shown in Figure 2L.
  • a portion of the second sub-isolation layer 38 is etched back, and a portion of the isolation sidewall 37 is removed to expose the first isolation pillar 31 and fill the remaining second sub-isolation layer 38
  • the groove 24 is as shown in Figure 2M.
  • the specific steps of depositing the second sub-isolation layer 38 in the groove 24 along the opening 45 include:
  • the parameter conditions of the etching back are controlled so that the top surface of the remaining second sub-isolation layer 38 is located on the first isolation pillar. 31 above the bottom surface, thereby fully isolating adjacent capacitors and avoiding leakage between adjacent capacitors.
  • This specific implementation method is explained by taking the second isolation pillar 32 to be oxidized to form the first sub-isolation layer 36 as an example.
  • other modification methods may also be used to process the second isolation pillar 32 to form the first sub-isolation layer 36 .
  • other modification methods may be but are not limited to doping methods.
  • step S14 a capacitor is formed in the capacitor hole 35, as shown in FIG. 2O.
  • specific steps of forming a capacitor in the capacitor hole 35 include:
  • a second electrode 42 is formed covering the dielectric layer 41 to form the capacitor including the first electrode 40, the dielectric layer 41 and the second electrode 42, as shown in FIG. 2O.
  • an atomic layer deposition process can be used to selectively deposit the first conductive material on the side walls of the capacitor hole 35 without depositing on the bottom surface of the capacitor hole 35 , thereby eliminating the need to deposit the first conductive material at the bottom of the capacitor hole 35
  • the removal step helps to further simplify the formation process of the memory.
  • an atomic layer deposition process is used to deposit the dielectric layer 41 on the surface of the first electrode 40 , the surface of the isolation layer and the bottom surface of the mask layer.
  • the second electrode 42 covering the dielectric layer 41 is formed.
  • the material of the first electrode 40 and the second electrode 42 may both be Ru, RuO 2 or TiN to enhance the conductive performance of the capacitor.
  • the material of the dielectric layer 41 may be one or a combination of two or more of STO (lithium titanate SrTiO 3 ), Al 2 O 3 , ZrO, and HfO 2 .
  • the following steps are further included:
  • Figure 2P is a schematic cross-sectional view of the plane where the first direction D1 and the second direction D3 in Figure 2O lie;
  • a covering layer 44 is formed to cover the exposed first isolation pillar 31, as shown in FIG. 2Q.
  • the following steps are further included:
  • the first isolation pillar 31 in the cover layer 44 is doped to form an active region of the transistor.
  • the mask layer is removed, and a portion of the capacitor is etched back to expose the upper portion of the first isolation pillar 31 with a preset height and the adjacent portion of the capacitor.
  • Spacing grooves 43 are formed between the first isolation pillars 31, as shown in FIG. 2P.
  • an insulating material such as silicon dioxide is deposited in the spacer grooves 43 to form the covering layer 44 that fills the spacer grooves 43, as shown in FIG. 2Q.
  • an active region is formed by doping the first isolation pillar 31 covered by the covering layer 44 to form a TOC (Transistor on Capacitor) structure.
  • TOC Transistor on Capacitor
  • the active area includes a channel area and source areas distributed on opposite sides of the channel area along a direction perpendicular to the top surface of the substrate 25 (for example, the third direction D3 in FIG. 2Q ). and a drain region, the drain region is electrically connected to the capacitor, and the source region is used to connect to a bit line, so that the bit line can be placed above the capacitor to reduce the bit line resistance. At the same time, it can reduce the difficulty of the memory manufacturing process, reduce the area occupied by a single memory, and improve the integration of the memory.
  • FIG. 3 is a schematic structural diagram of the memory in the embodiment of the disclosure.
  • the memory provided in this specific embodiment can be formed using the memory forming method as shown in FIG. 1 and FIG. 2A-FIG. 2Q.
  • the memory includes:
  • An isolation layer located above the substrate 25;
  • the capacitor array is located above the isolation layer and includes a plurality of capacitors.
  • Each capacitor includes a first electrode 40 extending in a direction perpendicular to the top surface of the substrate 25 and covering the surface of the first electrode 40 The dielectric layer 41 and the second electrode 42 covering the surface of the dielectric layer 41 .
  • the memory further includes:
  • the first isolation column 31 is located between the two adjacent capacitors
  • the isolation layer includes a first sub-isolation layer 36 located between the first isolation pillar 31 and the substrate 25 , and a second sub-isolation layer 38 located under the capacitor.
  • the first sub-isolation layer 36 is made of the same material as the second sub-isolation layer 38 .
  • the material of the substrate 25 and the first isolation pillar 31 are both silicon, and the material of the first sub-isolation layer 36 and the second sub-isolation layer 38 are both silicon.
  • Silica is
  • the first electrode 40 covers the sidewall of the first isolation pillar 31
  • the dielectric layer 41 covers the surface of the first electrode 40 and the surface of the second sub-isolation layer 38 .
  • the bottom surface of the first isolation pillar 31 is located below the bottom surface of the first electrode 40 .
  • the memory further includes:
  • the channel area is located above the first isolation pillar 31;
  • a gate electrode is provided surrounding the channel region.
  • Some embodiments of this embodiment provide a memory and a method for forming the memory.
  • a groove is formed below the capacitor hole used to form the capacitor, and the groove is formed and filled when the connected groove is formed.
  • a capacitor is formed in the capacitor hole above the isolation layer to electrically isolate the bottom of the capacitor from the substrate through the isolation layer, thereby reducing or even avoiding leakage at the bottom of the capacitor. problem, thereby improving the electrical performance of the memory.
  • the memory formation method compared with forming an isolation layer directly on a substrate through a deposition or oxidation process, integrates the formation process of the capacitor hole with the formation process of the isolation layer, so that it can be formed
  • the formation process of the isolation layer is carried out at the same time as the capacitor hole.
  • the isolation layer is formed directly under the capacitor to ensure that the isolation layer can be fully aligned with the bottom of the capacitor, which simplifies the manufacturing process of the memory and reduces the cost of the memory. While reducing process difficulty, the electrical isolation effect between the capacitor and the substrate can be further improved.

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Abstract

本公开涉及一种存储器及其形成方法。所述存储器的形成方法包括如下步骤:提供初始衬底;刻蚀所述初始衬底,形成多个电容孔、以及与多个所述电容孔一一连通且位于所述电容孔下方的多个凹槽;形成连通相邻的所述凹槽且填充满所述凹槽的隔离层,残留于所述隔离层下方的所述初始衬底作为衬底;形成电容器于所述电容孔内。本公开减少甚至是避免了电容器底部易发生漏电的问题,从而改善了存储器的电性能。

Description

存储器及其形成方法
相关申请引用说明
本申请要求于2022年03月10日递交的中国专利申请号202210237320.3、申请名为“存储器及其形成方法”的优先权,其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域,尤其涉及一种存储器及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory,DRAM)是计算机等电子设备中常用的半导体装置,其由多个存储单元构成,每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接,字线上的字线电压能够控制晶体管的开启和关闭,从而通过位线能够读取存储在电容器中的数据信息,或者将数据信息写入到电容器中。
但是,在现有的DRAM等存储器中,尤其是具有TOC(Transistor On Capacitor,电容器上晶体管)结构的存储器中,电容器底部易出现漏电的问题,从而降低了存储器的性能。
因此,如何减少电容器底部的漏电问题,从而改善存储器的电学性能,是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的存储器及其形成方法,至少部分用于解决电容器底部易发生漏电的问题,从而改善存储器的电学性能。
根据一些实施例,本公开提供了一种存储器的形成方法包括如下步骤:
提供初始衬底;
刻蚀所述初始衬底,形成多个电容孔、以及与多个所述电容孔一一连通且位于所述电容孔下方的多个凹槽;
形成连通相邻的所述凹槽且填充满所述凹槽的隔离层,残留于所述隔离层下方的所述初始衬底作为衬底;
形成电容器于所述电容孔内。
在一些实施例中,形成多个电容孔、以及与多个所述电容孔一一连通且位于所述电容孔下方的多个凹槽的具体步骤包括:
刻蚀所述初始衬底,形成多个第一刻蚀槽,每个所述第一刻蚀槽沿第一方向延伸,且多个所述第一刻蚀槽彼此平行、并在第二方向上间隔排布,所述第一方向与所述第二方向均平行于所述初始衬底的顶面、且所述第一方向与所述第二方向正交;
刻蚀所述初始衬底,形成多个第二刻蚀槽,每个所述第二刻蚀槽沿所述第二方向延伸,且多个所述第二刻蚀槽彼此平行、并在所述第一方向上间隔排布,所述第二刻蚀槽底部和所述第一刻蚀槽底部残留的部分所述初始衬底作为所述衬底;
刻蚀所述第二刻蚀槽底部的所述初始衬底,在第一方向上,形成宽度大于所述第二刻蚀槽的所述凹槽;
连通所述第一刻蚀槽和所述第二刻蚀槽,形成所述电容孔。
在一些实施例中,形成多个第二刻蚀槽之前,还包括如下步骤:
形成填充满所述第一刻蚀槽的第一填充层。
在一些实施例中,形成宽度大于所述第二刻蚀槽的所述凹槽的具体步骤包括:
采用博世刻蚀工艺刻蚀所述第二刻蚀槽底部的所述初始衬底,形成所述凹槽。
在一些实施例中,连通所述第一刻蚀槽和所述第二刻蚀槽,形成所述电容孔的具体步骤包括:
形成填充满所述第二刻蚀槽和所述凹槽的第二填充层;
形成图案化的掩模层于所述初始衬底上方,所述掩模层中包括多个暴露所述第一刻蚀槽与所述第二刻蚀槽交叠区域的开口;
沿所述开口去除所述第一填充层和所述第二填充层,形成所述电容孔。
在一些实施例中,形成图案化的掩模层于所述初始衬底上方,所述掩模层中包括多个暴露所述第一刻蚀槽与所述第二刻蚀槽交叠区域的开口的具体步骤包括:
形成第一子掩模层于所述初始衬底上方;
刻蚀所述第一子掩模层,形成多个暴露所述第一填充层的第一子开口,每个所述第一子开口均沿所述第一方向延伸、且多个所述第一子开口沿所述第二方向间隔排布;
形成填充满所述第一子开口的第三填充层;
刻蚀所述第一子掩模层和所述第三填充层,形成多个暴露所述初始衬底的第二子开口,每个所述第二子开口均沿平行于所述第二方向的方向延伸、且多个所述第二子开口沿所述第一方向间隔排布;
填充第二子掩模层于所述第二子开口,形成包括所述第二子掩模层和残留的所述第一子掩模层的所述掩模层,所述掩模层中包括多个暴露所述第三填充层的开口;
沿所述开口去除所述第三填充层,暴露所述第一刻蚀槽与所述第二刻蚀槽的交叠区域。
在一些实施例中,相邻的所述电容孔之间残留的所述初始衬底作为第一隔离柱,且相邻的所述凹槽之间残留的所述初始衬底作为第二隔离柱;
在所述第一方向上,所述第二隔离柱的宽度为所述第一隔离柱的的宽度1/2~1/3,在所述第二方向上,所述第二隔离柱的宽度与所述第一隔离柱的宽度相等。
在一些实施例中,形成连通相邻的所述凹槽且填充满所述凹槽的隔离层的具体步骤包括:
沿所述开口氧化部分的所述第一隔离柱和全部的所述第二隔离柱,于所述电容孔的侧壁形成隔离侧墙、且相邻的所述凹槽之间形成第一子隔离层;
沿所述开口沉积第二子隔离层于所述凹槽内,形成包括所述第一子隔离层和所述第二子隔离层的所述隔离层。
在一些实施例中,沿所述开口沉积第二子隔离层于所述凹槽内的具体步骤包括:
沿所述开口沉积第二子隔离层于所述凹槽内和所述电容孔的底部,使得所述第二子隔离层的顶面位于所述第一隔离柱的底面之上。
在一些实施例中,所述初始衬底的材料为硅,所述第一子隔离层和所述第二子隔离层的材料均为二氧化硅。
在一些实施例中,形成电容器于所述电容孔内的具体步骤包括:
去除所述隔离侧墙;
形成覆盖所述电容孔侧壁的第一电极;
形成覆盖所述第一电极的表面、所述隔离层的顶面和所述掩模层的底面的电介质层;
形成覆盖所述电介质层的第二电极,以形成包括所述第一电极、所述电介质层和所述第二电极的所述电容器。
在一些实施例中,形成覆盖所述电介质层的所述第二电极之后,还包括如下步骤:
去除所述掩模层、并回刻蚀部分的所述第一电极、所述电介质层和所述第二电极,暴露所述第一隔离柱的上部;
形成包覆暴露的所述第一隔离柱的覆盖层。
在一些实施例中,形成包覆暴露的所述第一隔离柱的覆盖层之后,还包括如下步骤:
掺杂所述覆盖层中的所述第一隔离柱,形成晶体管的有源区。
根据另一些实施例,本公开还提供了一种存储器,包括:
衬底;
隔离层,位于所述衬底上方;
电容阵列,位于所述隔离层上方,包括多个电容器,每个所述电容器包括沿垂直于所述衬底的顶面的方向延伸的第一电极、覆盖于所述第一电极表面的电介质层、以及覆盖于所述电介质层表面的第二电极。
在一些实施例中,还包括:
第一隔离柱,位于相邻的两个所述电容器之间;
所述隔离层包括位于所述第一隔离柱与所述衬底之间的第一子隔离层、以及位于所述电容器下方的第二子隔离层。
在一些实施例中,所述第一子隔离层的材料与所述第二子隔离层的材料相同。
在一些实施例中,所述衬底的材料和所述第一隔离柱的材料均为硅,所述第一子隔离层的材料和所述第二子隔离层的材料均为二氧化硅。
在一些实施例中,所述第一电极覆盖所述第一隔离柱的侧壁,所述电介质层覆盖所述第一电极的表面和所述第二子隔离层的表面。
在一些实施例中,所述第一隔离柱的底面位于所述第一电极的底面之下。
在一些实施例中,还包括:
沟道区域,位于所述第一隔离柱上方;
栅极,环绕所述沟道区域设置。
本公开一些实施例提供的存储器及其形成方法,在形成电容器之前,先于用于形成电容器的电容孔的下方形成凹槽,并在形成连通相连的所述凹槽且填充满所述凹槽的隔离层之后,再于所述隔离层上方的电容孔中形成电容器,以通过所述隔离层电性隔离所述电容器的底部与衬底,减少甚至是避免了电容器底部易发生漏电的问题,从而改善了存储器的电性能。另外,相较于直接在衬底上通过沉积或者氧化工艺形成隔离层的方式,本公开提供的所述存储器的形成方法,将电容孔的形成工艺与隔离层的形成工艺融合,使得能够在形成电容孔的同时进行所述隔离层的形成工艺,所述隔离层直接形成于所述电容器下方,确保所述隔离层能够充分与电容器底部对准,在简化所述存储器的制造工艺、降低存储器的工艺难度的同时,能够进一步提高所述电容器与衬底的电性隔离效果。
附图说明
附图1是本公开具体实施方式中存储器的形成方法流程图;
附图2A-2Q是本公开具体实施方式在形成存储器的过程中主要的工艺结构示意图;
附图3是本公开具体实施方式中存储器的结构示意图。
具体实施方式
下面结合附图对本公开提供的存储器及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种存储器的形成方法,附图1是本公开具体实施方式中存储器的形成方法流程图,附图2A-附图2Q是本公开具体实施方式在形成存储器的过程中主要的工艺结构示意图。本具体实施方式中所述的存储器可以是但不限于DRAM存储器。如图1、图2A-图2Q所示,本具体实施方式提供的存储器的形成方法,包括如下步骤:
步骤S11,提供初始衬底20。
具体来说,所述初始衬底20可以是但不限于硅衬底,本具体实施方式以所述初始衬底20为硅衬底为例进行说明。在其他示例中,所述初始衬底20可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。
步骤S12,刻蚀所述初始衬底20,形成多个电容孔35、以及与多个所述电容孔35一一连通且位于所述电容孔35下方的多个凹槽24,残留于所述凹槽24下方的部分所述初始衬底作为衬底25。
在一些实施例中,形成多个电容孔35、以及与多个所述电容孔35一一连通且位于所述电容孔35下方的多个凹槽24的具体步骤包括:
刻蚀所述初始衬底20,形成多个第一刻蚀槽21,每个所述第一刻蚀槽21沿第一方向D1延伸,多个所述第一刻蚀槽21彼此平行、且在第二方向D2上间隔排布,所述第一方向D1与所述第二方向D2均平行于所述初始衬底20的顶面、且所述第一方向D1与所述第二方向D2正交,如图2A所示;
刻蚀所述初始衬底20,形成多个第二刻蚀槽23,每个所述第二刻蚀槽23沿所述第二 方向D2延伸,多个所述第二刻蚀槽23彼此平行、且在所述第一方向D1上间隔排布;
刻蚀所述第二刻蚀槽23底部的所述初始衬底20,形成内径大于所述第二刻蚀槽23的所述凹槽24,如图2C所示;
连通所述第一刻蚀槽21和所述第二刻蚀槽23,形成所述电容孔35,如图2J所示。
具体来说,可以采用干法刻蚀工艺沿垂直于所述初始衬底20的顶面的方向(例如图2A中的第三方向D3)刻蚀所述初始衬底20,形成多个所述第一刻蚀槽21,每个所述第一刻蚀槽21沿第一方向D1延伸、且多个所述第一刻蚀槽21沿第二方向D2彼此平行并间隔排布。在刻蚀所述初始衬底20形成所述第一刻蚀槽21的过程中,可以通过控制刻蚀参数,例如刻蚀气体的剂量和/或刻蚀时间等刻蚀参数,使得在沿垂直于所述初始衬底20的顶面的方向上,所述第一刻蚀槽21未贯穿所述初始衬底20。
在一些实施例中,形成多个第二刻蚀槽23之前,还包括如下步骤:
形成填充满所述第一刻蚀槽21的第一填充层22,如图2B所示。
在一些实施例中,形成内径大于所述第二刻蚀槽23的所述凹槽24的具体步骤包括:
采用博世(Bosch)刻蚀工艺刻蚀所述第二刻蚀槽23底部的所述初始衬底20,形成所述凹槽24,如图2C所示。
具体来说,为了避免在刻蚀所述初始衬底20形成所述第二刻蚀槽23时出现坍塌或者倾倒现象,在形成所述第二刻蚀槽23之前,还可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积二氧化硅等绝缘材料于所述第一刻蚀槽21内,形成填充满所述第一刻蚀槽21的所述第一填充层22,如图2B所示。之后,可以采用干法刻蚀工艺沿垂直于所述初始衬底20的顶面的方向(例如图2A中的第三方向D3)刻蚀所述初始衬底20,形成多个第二刻蚀槽23,每个所述第二刻蚀槽23沿所述第二方向D2延伸,多个所述第二刻蚀槽23沿所述第一方向D1彼此平行并间隔排布,即所述第二刻蚀槽23在沿垂直于所述初始衬底20的顶面方向上的投影与所述第一刻蚀槽21在沿垂直于所述初始衬底20的顶面方向上的投影正交。之后,采用博世刻蚀工艺沿所述第一刻蚀槽21继续刻蚀所述第二刻蚀槽23底部的所述初始衬底20,从而形成与所述第二刻蚀槽23的底部连通、且内径大于所述第二刻蚀槽23的所述凹槽24。由于所述凹槽24的内径大于所述第二刻蚀槽23的内径,因此,在沿所述第一方向D1上,相邻所述第二刻蚀槽23之间残留的所述初始衬底20(即第一隔离柱31)的宽度大于相邻所述凹槽24之间残留的所述初始衬底20(即第二隔离柱32)的宽度。
本具体实施方式是以在形成所述第二刻蚀槽23之后、再采用博世刻蚀工艺来形成所述凹槽24,以简化所述存储器的形成工艺。在其他具体实施方式中,本领域技术人员也可以根据需要选择其他刻蚀工艺来形成所述第二刻蚀槽23、以及与所述第二刻蚀槽23连通的所述凹槽24。
在一些实施例中,连通所述第一刻蚀槽21和所述第二刻蚀槽23,形成所述电容孔35的具体步骤包括:
形成填充满所述第二刻蚀槽23和所述凹槽24的第二填充层26,如图2D所示;
形成图案化的掩模层于所述初始衬底20上方,所述掩模层中包括多个暴露所述第一刻蚀槽21与所述第二刻蚀槽23交叠区域的开口45,如图2I所示;
沿所述开口45去除所述第一填充层22和所述第二填充层26,形成所述电容孔35,如图2J所示。
具体来说,可以通过选择合适的所述第一填充层22的材料和所述第二填充层26的材料,从而可以通过选择性刻蚀去除所述第一填充层22和所述第二填充层26,在所述初始衬底20内部连通所述第一刻蚀槽21和所述第二刻蚀槽23。
在一些实施例中,形成图案化的掩模层于所述初始衬底20上方,所述掩模层中包括多个暴露所述第一刻蚀槽21与所述第二刻蚀槽23交叠区域的开口45的具体步骤包括:
形成第一子掩模层27于所述初始衬底20上方,如图2E所示;
刻蚀所述第一子掩模层27,形成多个暴露所述第一填充层22的第一子开口28,每个所述第一子开口28均沿所述第一方向D1延伸、且多个所述第一子开口28沿所述第二方向D2平行排布,如图2F所示;
形成填充满所述第一子开口28的第三填充层39,如图2G所示;
刻蚀所述第一子掩模层27和所述第三填充层39,形成多个暴露所述初始衬底20的第二子开口30,每个所述第二子开口30均沿平行于所述第二方向D2的方向延伸、且多个所述第二子开口30沿所述第一方向D1平行排布,如图2H所示;
填充第二子掩模层33于所述第二子开口30,形成包括所述第二子掩模层33和残留的所述第一子掩模层27的所述掩模层,所述掩模层中包括多个暴露所述第三填充层39的开口45,如图2I所示;
沿所述开口45去除所述第三填充层39,暴露所述第一刻蚀槽21与所述第二刻蚀槽23的交叠区域。
具体来说,在形成填充满所述第二刻蚀槽23和所述凹槽24的所述第二填充层26之后,沉积氮化硅等硬掩模材料或者碳等有机掩模材料于所述初始衬底20的顶面,形成所述第一子掩模层27,如图2E所示。所述第一子掩模层27一方面用作后续去除所述第一填充层22和所述第二填充层26的掩模;另一方面还用于支撑相邻所述第二刻蚀槽23之间的所述第一隔离柱31,避免后续在去除所述第一填充层22和所述第二填充层26的过程中出现倾倒或者坍塌。接着,可以采用刻蚀形成所述第一刻蚀槽21的同一掩模刻蚀所述第一子掩模层27,形成多个暴露所述第一填充层22的第一子开口28,每个所述第一子开口28均沿所述第一方向D1延伸、且多个所述第一子开口28沿所述第二方向D2平行排布,如图2F所示。之后,填充所述第一子开口28,形成所述第三填充层39,如图2G所示。然后,刻蚀所述第一子掩模层27和所述第三填充层39,形成多个暴露所述初始衬底20的第二子开口30,每个所述第二子开口30均沿平行于所述第二方向D2的方向延伸,多个所述第二子开口30沿所述第一方向D1彼此平行并间隔排布,如图2H所示。填充氮化物材料(例如氮化硅材料)的第二子掩模层33于所述第二子开口30,形成包括所述第二子掩模层33和残留的所述第一子掩模层27的所述掩模层。在沿平行于所述初始衬底20的顶面的方向上,残留的所述第一子掩模层27与所述第二子掩模层33相交,从而形成多个暴露所述第三填充层39的所述开口45,如图2I所示。采用刻蚀工艺沿所述开口45去除所述第三填充层39、所述第一填充层22和所述第二填充层26,从而连通所述初始衬底20内部的所述第一刻蚀槽21和所述第二刻蚀槽23,形成所述电容孔35,如图2J所示。
在一实施例中,所述第一填充层22的材料、所述第二填充层26的材料和所述第三填充层39的材料均相同,例如所述第一填充层22的材料、所述第二填充层26的材料和所述第三填充层39的材料均为二氧化硅,以便于通过一步刻蚀工艺同时去除所述第一填充层22、所述第二填充层26和所述第三填充层39,从而进一步简化存储器的制造工艺。
步骤S13,形成连通相邻的所述凹槽24且填充满所述凹槽24的隔离层,残留于所述隔离层下方的所述初始衬底20作为衬底25,如图2M所示。
在一些实施例中,相邻的所述电容孔35之间残留的所述初始衬底20作为第一隔离柱31,且相邻的所述凹槽24之间残留的所述初始衬底20作为第二隔离柱32,如图2J所示;
在所述第一方向D1上,所述第二隔离柱32的宽度为所述第一隔离柱31的宽度的1/2~1/3,在所述第二方向D2上,所述第二隔离柱32的宽度与所述第一隔离柱31的宽度相等。
具体来说,通过将所述凹槽24的内径设置为大于其上方的所述电容孔35的内径,从而使得相邻所述凹槽24之间的所述第二隔离柱32在所述第一方向D1上的宽度小于相邻所述电容孔35之间的所述第一隔离柱31在所述第一方向上的宽度,以便于后续能够充分对所述第二隔离柱32进行改性处理,以便于后续能够充分隔离所述衬底25与电容器。同时,所述第二隔离柱32的宽度也不宜过小,因为所述第二隔离柱32的宽度过小则不能稳定的 支撑所述第二隔离柱32上方的所述第一隔离柱31。
在一些实施例中,形成连通相邻的所述凹槽24且填充满所述凹槽24的隔离层的具体步骤包括:
沿所述开口45氧化部分的所述第一隔离柱31和全部的所述第二隔离柱32,于所述电容孔35的侧壁形成隔离侧墙37、且相邻的所述凹槽24之间形成第一子隔离层36,如图2K所示;
沿所述开口45沉积第二子隔离层38于所述凹槽24内,形成包括所述第一子隔离层36和所述第二子隔离层38的所述隔离层,如图2M所示。
在一些实施例中,所述初始衬底20的材料为硅,所述第一子隔离层36和所述第二子隔离层38的材料均为二氧化硅。
以下以所述初始衬底20的材料为硅、所述第一子隔离层36和所述第二子隔离层38的材料均为二氧化硅为例进行说明。举例来说,原位氧化(例如原位水汽生成)所述第一隔离柱31、所述第二隔离柱32、以及所述凹槽24底部的部分所述初始衬底20,由于所述第一隔离柱31在所述第一方向D1上的宽度大于所述第二隔离柱32在所述第一方向D1的宽度,因此,能够通过控制氧化参数(例如氧化时间、氧化剂用量等),使得所述第二隔离柱32能够完全氧化、所述第一隔离柱31仅表面被氧化,从而形成覆盖所述电容孔35侧壁的所述隔离侧墙37、以及位于相邻的所述凹槽24之间且覆盖所述凹槽24的底面的所述第一子隔离层36,如图2K所示。之后,沿所述开口45沉积二氧化硅材料于所述电容孔35和所述凹槽24内,形成填充满所述开口45、所述电容孔35和所述凹槽24的所述第二子隔离层38,如图2L所示。接着,回刻蚀部分的所述第二子隔离层38、并去除部分的所述隔离侧墙37,暴露所述第一隔离柱31,且使得残留的所述第二子隔离层38填充满所述凹槽24,如图2M所示。
在一些实施例中,沿所述开口45沉积第二子隔离层38于所述凹槽24内的具体步骤包括:
沿所述开口45沉积第二子隔离层38于所述凹槽24内和所述电容孔35的底部,使得所述第二子隔离层38的顶面位于所述第一隔离柱31的底面之上。
具体来说,在回刻蚀部分的所述第二子隔离层38时,通过控制回刻蚀的参数条件,使得残留的所述第二子隔离层38的顶面位于所述第一隔离柱31的底面之上,从而充分隔离相邻的电容器,避免相邻所述电容器之间的漏电。
本具体实施方式是以氧化所述第二隔离柱32来形成所述第一子隔离层36为例进行说明。在其他具体实施方式中,也可以采用其他改性方式来处理所述第二隔离柱32以形成所述第一子隔离层36。其中,其他改性方式可以是但不限于掺杂方式。
步骤S14,形成电容器于所述电容孔35内,如图2O所示。
在一些实施例中,形成电容器于所述电容孔35内的具体步骤包括:
去除所述隔离侧墙37;
形成覆盖所述电容孔35侧壁的第一电极40,如图2N所示;
形成覆盖所述第一电极40的表面、所述隔离层的顶面和所述掩模层的底面的电介质层41;
形成覆盖所述电介质层41的第二电极42,以形成包括所述第一电极40、所述电介质层41和所述第二电极42的所述电容器,如图2O所示。
具体来说,可以采用原子层沉积工艺选择性的沉积第一导电材料于所述电容孔35的侧壁、而不沉积于所述电容孔35的底面,从而无需进行电容孔底部第一导电材料的去除步骤,有助于进一步简化所述存储器的形成工艺。之后,采用原子层沉积工艺沉积所述电介质层41于所述第一电极40的表面、所述隔离层的表面和所述掩模层的底面。接着,形成覆盖所述电介质层41的第二电极42。其中,所述第一电极40的材料和所述第二电极42的材料可以均为Ru、RuO 2或者TiN,以增强所述电容器的导电性能。所述电介质层41的材料可以 为STO(钛酸锂SrTiO 3)、Al 2O 3、ZrO、HfO 2中的一种或者两种以上的组合。
在一些实施例中,形成覆盖所述电介质层41的所述第二电极42之后,还包括如下步骤:
去除所述掩模层、并回刻蚀部分的所述第一电极40、所述电介质层41和所述第二电极42,暴露所述第一隔离柱31的上部,如图2P所示,图2P是图2O中所述第一方向D1和所述第二方向D3所在平面的截面示意图;
形成包覆暴露的所述第一隔离柱31的覆盖层44,如图2Q所示。
在一些实施例中,形成包覆暴露的所述第一隔离柱31的覆盖层44之后,还包括如下步骤:
掺杂所述覆盖层44中的所述第一隔离柱31,形成晶体管的有源区。
具体来说,在形成所述电容器之后,去除所述掩模层,并回刻蚀部分的所述电容器,暴露预设高度的所述第一隔离柱31的上部,并于相邻的所述第一隔离柱31之间形成间隔槽43,如图2P所示。之后,沉积二氧化硅等绝缘材料于所述间隔槽43内,形成填充满所述间隔槽43的所述覆盖层44,如图2Q所示。之后,通过对被所述覆盖层44包覆的所述第一隔离柱31进行掺杂,形成有源区,以形成TOC(Transistor on Capacitor,晶体管上电容器)结构。所述有源区中包括沟道区域、以及沿垂直于所述衬底25的顶面的方向(例如图2Q中的第三方向D3)分布于所述沟道区域相对两侧的源极区和漏极区,所述漏极区与所述电容器电连接,所述源极区用于与位线连接,从而可以将所述位线设置在所述电容器的上方,在减小位线电阻的同时,能够减低存储器的制造工艺难度,并降低单个存储器的占用面积,提高存储器的集成度。
本具体实施方式还提供了一种存储器,附图3是本公开具体实施方式中存储器的结构示意图。本具体实施方式提供的所述存储器可以采用如图1、图2A-图2Q所示的存储器的形成方法形成。如图3所示,所述存储器包括:
衬底25;
隔离层,位于所述衬底25上方;
电容阵列,位于所述隔离层上方,包括多个电容器,每个所述电容器包括沿垂直于所述衬底25的顶面的方向延伸的第一电极40、覆盖于所述第一电极40表面的电介质层41、以及覆盖于所述电介质层41表面的第二电极42。
在一些实施例中,所述存储器还包括:
第一隔离柱31,位于相邻的两个所述电容器之间;
所述隔离层包括位于所述第一隔离柱31与所述衬底25之间的第一子隔离层36、以及位于所述电容器下方的第二子隔离层38。
在一些实施例中,所述第一子隔离层36的材料与所述第二子隔离层38的材料相同。
在一些实施例中,所述衬底25的材料和所述第一隔离柱31的材料均为硅,所述第一子隔离层36的材料和所述第二子隔离层38的材料均为二氧化硅。
在一些实施例中,所述第一电极40覆盖所述第一隔离柱31的侧壁,所述电介质层41覆盖所述第一电极40的表面和所述第二子隔离层38的表面。
在一些实施例中,所述第一隔离柱31的底面位于所述第一电极40的底面之下。
在一些实施例中,所述存储器还包括:
沟道区域,位于所述第一隔离柱31上方;
栅极,环绕所述沟道区域设置。
本具体实施方式一些实施例提供的存储器及其形成方法,在形成电容器之前,先于用于形成电容器的电容孔的下方形成凹槽,并在形成连通相连的所述凹槽且填充满所述凹槽的隔离层之后,再于所述隔离层上方的电容孔中形成电容器,以通过所述隔离层电性隔离所述电容器的底部与衬底,减少甚至是避免了电容器底部易发生漏电的问题,从而改善了存储器的电性能。另外,相较于直接在衬底上通过沉积或者氧化工艺形成隔离层的方式, 本公开提供的所述存储器的形成方法,将电容孔的形成工艺与隔离层的形成工艺融合,使得能够在形成电容孔的同时进行所述隔离层的形成工艺,所述隔离层直接形成于所述电容器下方,确保所述隔离层能够充分与电容器底部对准,在简化所述存储器的制造工艺、降低存储器的工艺难度的同时,能够进一步提高所述电容器与衬底的电性隔离效果。
以上所述仅是本公开的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本公开原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种存储器的形成方法,包括如下步骤:
    提供初始衬底;
    刻蚀所述初始衬底,形成多个电容孔、以及与多个所述电容孔一一连通且位于所述电容孔下方的多个凹槽;
    形成连通相邻的所述凹槽且填充满所述凹槽的隔离层,残留于所述隔离层下方的所述初始衬底作为衬底;
    形成电容器于所述电容孔内。
  2. 根据权利要求1所述的存储器的形成方法,其中,形成多个电容孔、以及与多个所述电容孔一一连通且位于所述电容孔下方的多个凹槽的具体步骤包括:
    刻蚀所述初始衬底,形成多个第一刻蚀槽,每个所述第一刻蚀槽沿第一方向延伸,且多个所述第一刻蚀槽彼此平行、并在第二方向上间隔排布,所述第一方向与所述第二方向均平行于所述初始衬底的顶面、且所述第一方向与所述第二方向正交;
    刻蚀所述初始衬底,形成多个第二刻蚀槽,每个所述第二刻蚀槽沿所述第二方向延伸,且多个所述第二刻蚀槽彼此平行、并在所述第一方向上间隔排布;
    刻蚀所述第二刻蚀槽底部的所述初始衬底,在第一方向上,形成宽度大于所述第二刻蚀槽的所述凹槽;
    连通所述第一刻蚀槽和所述第二刻蚀槽,形成所述电容孔。
  3. 根据权利要求2所述的存储器的形成方法,其中,形成多个第二刻蚀槽之前,还包括如下步骤:
    形成填充满所述第一刻蚀槽的第一填充层。
  4. 根据权利要求3所述的存储器的形成方法,其中,形成宽度大于所述第二刻蚀槽的所述凹槽的具体步骤包括:
    采用博世刻蚀工艺刻蚀所述第二刻蚀槽底部的所述初始衬底,形成所述凹槽。
  5. 根据权利要求3所述的存储器的形成方法,其中,连通所述第一刻蚀槽和所述第二刻蚀槽,形成所述电容孔的具体步骤包括:
    形成填充满所述第二刻蚀槽和所述凹槽的第二填充层;
    形成图案化的掩模层于所述初始衬底上方,所述掩模层中包括多个暴露所述第一刻蚀槽与所述第二刻蚀槽交叠区域的开口;
    沿所述开口去除所述第一填充层和所述第二填充层,形成所述电容孔。
  6. 根据权利要求5所述的存储器的形成方法,其中,形成图案化的掩模层于所述初始衬底上方,所述掩模层中包括多个暴露所述第一刻蚀槽与所述第二刻蚀槽交叠区域的开口的具体步骤包括:
    形成第一子掩模层于所述初始衬底上方;
    刻蚀所述第一子掩模层,形成多个暴露所述第一填充层的第一子开口,每个所述第一子开口均沿所述第一方向延伸、且多个所述第一子开口沿所述第二方向间隔排布;
    形成填充满所述第一子开口的第三填充层;
    刻蚀所述第一子掩模层和所述第三填充层,形成多个暴露所述初始衬底的第二子开口,每个所述第二子开口均沿平行于所述第二方向的方向延伸、且多个所述第二子开口沿所述第一方向间隔排布;
    填充第二子掩模层于所述第二子开口,形成包括所述第二子掩模层和残留的所述第一子掩模层的所述掩模层,所述掩模层中包括多个暴露所述第三填充层的开口;
    沿所述开口去除所述第三填充层,暴露所述第一刻蚀槽与所述第二刻蚀槽的交叠区域。
  7. 根据权利要求6所述的存储器的形成方法,其中,相邻的所述电容孔之间残留的所述初始衬底作为第一隔离柱,且相邻的所述凹槽之间残留的所述初始衬底作为第二隔离柱;
    在所述第一方向上,所述第二隔离柱的宽度为所述第一隔离柱的宽度的1/2~1/3,在所述第二方向上,所述第二隔离柱的宽度与所述第一隔离柱的宽度相等。
  8. 根据权利要求7所述的存储器的形成方法,其中,形成连通相邻的所述凹槽且填充满所述凹槽的隔离层的具体步骤包括:
    沿所述开口氧化部分的所述第一隔离柱和全部的所述第二隔离柱,于所述电容孔的侧壁形成隔离侧墙、且相邻的所述凹槽之间形成第一子隔离层;
    沿所述开口沉积第二子隔离层于所述凹槽内,形成包括所述第一子隔离层和所述第二子隔离层的所述隔离层。
  9. 根据权利要求8所述的存储器的形成方法,其中,沿所述开口沉积第二子隔离层于所述凹槽内的具体步骤包括:
    沿所述开口沉积第二子隔离层于所述凹槽内和所述电容孔的底部,使得所述第二子隔离层的顶面位于所述第一隔离柱的底面之上。
  10. 根据权利要求8所述的存储器的形成方法,其中,所述初始衬底的材料为硅,所述第一子隔离层和所述第二子隔离层的材料均为二氧化硅。
  11. 根据权利要求8所述的存储器的形成方法,其中,形成电容器于所述电容孔内的具体步骤包括:
    去除所述隔离侧墙;
    形成覆盖所述电容孔侧壁的第一电极;
    形成覆盖所述第一电极的表面、所述隔离层的顶面和所述掩模层的底面的电介质层;
    形成覆盖所述电介质层的第二电极,以形成包括所述第一电极、所述电介质层和所述第二电极的所述电容器。
  12. 根据权利要求11所述的存储器的形成方法,其中,形成覆盖所述电介质层的所述第二电极之后,还包括如下步骤:
    去除所述掩模层、并回刻蚀部分的所述第一电极、所述电介质层和所述第二电极,暴露所述第一隔离柱的上部;
    形成包覆暴露的所述第一隔离柱的覆盖层。
  13. 根据权利要求12所述的存储器的形成方法,其中,形成包覆暴露的所述第一隔离柱的覆盖层之后,还包括如下步骤:
    掺杂所述覆盖层中的所述第一隔离柱,形成晶体管的有源区。
  14. 一种存储器,包括:
    衬底;
    隔离层,位于所述衬底上方;
    电容阵列,位于所述隔离层上方,包括多个电容器,每个所述电容器包括沿垂直于所述衬底的顶面的方向延伸的第一电极、覆盖于所述第一电极表面的电介质层、以及覆盖于所述电介质层表面的第二电极。
  15. 根据权利要求14所述的存储器,还包括:
    第一隔离柱,位于相邻的两个所述电容器之间;
    所述隔离层包括位于所述第一隔离柱与所述衬底之间的第一子隔离层、以及位于所述电容器下方的第二子隔离层。
  16. 根据权利要求15所述的存储器,其中,所述第一子隔离层的材料与所述第二子隔离层的材料相同。
  17. 根据权利要求16所述的存储器,其中,所述衬底的材料和所述第一隔离柱的材料均为硅,所述第一子隔离层的材料和所述第二子隔离层的材料均为二氧化硅。
  18. 根据权利要求17所述的存储器,其中,所述第一电极覆盖所述第一隔离柱的侧壁,所述电介质层覆盖所述第一电极的表面和所述第二子隔离层的表面。
  19. 根据权利要求16所述的存储器,其中,所述第一隔离柱的底面位于所述第一电极的底面之下。
  20. 根据权利要求15所述的存储器,还包括:
    沟道区域,位于所述第一隔离柱上方;
    栅极,环绕所述沟道区域设置。
PCT/CN2022/086255 2022-03-10 2022-04-12 存储器及其形成方法 WO2023168778A1 (zh)

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