WO2023245788A1 - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
WO2023245788A1
WO2023245788A1 PCT/CN2022/106659 CN2022106659W WO2023245788A1 WO 2023245788 A1 WO2023245788 A1 WO 2023245788A1 CN 2022106659 W CN2022106659 W CN 2022106659W WO 2023245788 A1 WO2023245788 A1 WO 2023245788A1
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region
initial
along
doped
substrate
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PCT/CN2022/106659
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English (en)
French (fr)
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窦涛
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长鑫存储技术有限公司
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Priority to US17/908,467 priority Critical patent/US20240194731A1/en
Publication of WO2023245788A1 publication Critical patent/WO2023245788A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor device and a method for forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • the transistor of a semiconductor device such as a DRAM usually also includes a channel region, and a source region and a drain region located on opposite sides of the channel region and adjacent to the channel region.
  • BTBT Band to Band Tunneling
  • GIDL Gate-Induced Drain Leakage
  • the semiconductor device and its formation method provided by some embodiments of the present disclosure are used to reduce the GIDL effect inside the semiconductor device, thereby improving the electrical performance of the semiconductor device and increasing the yield of the semiconductor device.
  • the present disclosure provides a semiconductor device including:
  • a transistor, located on the substrate, includes an active pillar, the active pillar includes a channel region, a source region and a drain region distributed on opposite sides of the channel region, located between the source region and a first doped region between the channel regions, and a second doped region between the drain region and the channel region, the first doped region, the source region, Both the second doping region and the drain region include first type doping ions, and the doping concentration of the first doping region is smaller than the doping concentration of the source region, and the second doping region The doping concentration of the region is smaller than the doping concentration of the drain region.
  • the active pillar extends along a first direction, and the first direction is a direction parallel to the top surface of the substrate; the semiconductor device further includes:
  • a first isolation layer is located on the substrate, and the first isolation layer is distributed around the periphery of the first doped region, and the active pillar penetrates the first isolation layer along the first direction;
  • a second isolation layer is located on the substrate, and the second isolation layer is distributed around the periphery of the second doped region, and the active pillar penetrates the second isolation layer along the first direction.
  • a plurality of the active pillars are spaced apart along a second direction, the second direction is a direction parallel to the top surface of the substrate, and the first direction is consistent with the second direction. directions intersect;
  • the first isolation layer is continuously distributed around the periphery of a plurality of first doped regions spaced apart along the second direction;
  • the second isolation layer is continuously distributed around the periphery of a plurality of second doped regions spaced apart along the second direction.
  • it also includes:
  • a first air gap is located between adjacent first doped regions
  • the second air gap is located between adjacent second doped regions.
  • the active pillar extends along a first direction, and the first direction is a direction parallel to the top surface of the substrate; the semiconductor device further includes:
  • a first isolation layer is located on the substrate, and the first isolation layer covers the first doped region, and the active pillar penetrates the first isolation layer along the first direction;
  • a second isolation layer is located on the substrate, and the second isolation layer covers the second doped region, and the active pillar penetrates the second isolation layer along the first direction.
  • a plurality of the active pillars are spaced apart along a second direction, the second direction is a direction parallel to the top surface of the substrate, and the first direction is consistent with the second direction. directions intersect;
  • the first isolation layer continuously covers a plurality of first doped regions spaced apart along the second direction;
  • the second isolation layer continuously covers a plurality of second doped regions spaced apart along the second direction.
  • the channel region includes first type doping ions; or,
  • the channel region includes second type doping ions, and the first type doping ions have opposite conductivity types than the second type doping ions.
  • the active pillar extends along a first direction, the first direction being a direction parallel to the top surface of the substrate;
  • the length of the first doped region along the first direction is more than 2 times the thickness of the active pillar along a third direction, and the third direction is a direction perpendicular to the top surface of the substrate;
  • the length of the second doped region along the first direction is more than twice the thickness of the active pillar along the third direction.
  • the active pillar extends along a first direction, the first direction being a direction parallel to the top surface of the substrate;
  • the length of the first doped region along the first direction is greater than or equal to the length of the source region along the first direction
  • the length of the second doped region along the first direction is greater than or equal to the length of the drain region along the first direction.
  • the active pillars extend along a first direction, and a plurality of the active pillars are arranged in an array along a second direction and a third direction, and both the first direction and the second direction are A direction parallel to the top surface of the substrate, and the first direction intersects the second direction, and the third direction is a direction perpendicular to the top surface of the substrate;
  • the semiconductor device further includes :
  • a word line extends along the second direction and continuously covers the channel region in a plurality of active pillars spaced apart along the second direction;
  • a plurality of the word lines are arranged at intervals along the third direction, and among the two adjacent word lines along the third direction, the word line closer to the substrate is along the third direction. Two directions protrude from the other word line.
  • the present disclosure also provides a method for forming a semiconductor device, including the following steps:
  • a transistor is formed on the substrate, and the transistor includes an active pillar.
  • the active pillar includes a channel region, a source region and a drain region distributed on opposite sides of the channel region. a first doped region between the electrode region and the channel region, and a second doped region between the drain region and the channel region, the first doped region, the source The electrode region, the second doping region and the drain region all include first type doping ions, and the doping concentration of the first doping region is smaller than the doping concentration of the source region, and the The doping concentration of the second doped region is smaller than the doping concentration of the drain region.
  • specific steps of forming transistors on the substrate include:
  • an initial channel region in the semiconductor pillar an initial source region and an initial drain region distributed on opposite sides of the initial channel region, located between the initial source region and the initial channel region
  • an initial channel region is defined in the semiconductor pillar, an initial source region and an initial drain region distributed on opposite sides of the initial channel region, and the initial source region and the initial drain region are located between the initial source region and the initial drain region.
  • the specific steps of the initial first doped region between the initial channel regions and the initial second doped region between the initial drain region and the initial channel region include:
  • An initial channel region is defined in the semiconductor pillar, an initial source region and an initial drain region are distributed on opposite sides of the initial channel region along a first direction, and the initial source region is located along the first direction.
  • specific steps of forming semiconductor pillars over the substrate include:
  • the stacked layer including semiconductor layers and sacrificial layers alternately stacked along a third direction, the third direction being a direction perpendicular to the top surface of the substrate;
  • a plurality of the first trenches are spaced apart along the second direction.
  • the first trenches connect the
  • the semiconductor layer is divided into a plurality of semiconductor pillars arranged at intervals along the second direction.
  • the semiconductor pillars extend along the first direction. Both the first direction and the second direction are parallel to the substrate. The direction of the top surface, and the first direction intersects the second direction.
  • the method before injecting the first type doping ions into the initial source region, the initial drain region, the initial first doping region and the initial second doping region, the method further includes the following: step:
  • Part of the sacrificial layer in the stacked layer is removed to form a second trench and a third trench.
  • the second trench exposes all the areas between the initial first doped region and the initial channel region.
  • the semiconductor pillar, and the semiconductor pillar between the initial first doped region and the initial source region, the third trench exposes the initial second doped region and the initial channel region the semiconductor pillar between, and the semiconductor pillar between the initial second doped region and the initial drain region;
  • the method before injecting the first type doping ions into the initial source region, the initial drain region, the initial first doping region and the initial second doping region, the method further includes the following: step:
  • the specific steps of injecting first type doping ions into the initial source region, the initial drain region, the initial first doping region and the initial second doping region include:
  • the first type doping ions are implanted into the initial first doping region and the initial second doping region to form the first doping region and the second doping region.
  • it also includes:
  • the following steps are further included:
  • the interlayer isolation layer between adjacent first doped regions is removed, and the interlayer isolation layer between adjacent second doped regions is removed at the same time to form an adjacent first doped region.
  • a first air gap is formed between the doped regions, and a second air gap is formed between adjacent second doped regions.
  • the method further includes the following: step:
  • the semiconductor device and its formation method provided by some embodiments of the present disclosure provide a first doping region between the channel region and the source region, and a second doping region between the channel region and the drain region, Moreover, the ion doping type of the first doping region is the same as that of the source region, and the ion doping type of the second doping region is the same as that of the drain region.
  • the doping concentration of the first doping region is smaller than that of the source region and the second doping region.
  • the doping concentration of the impurity region is smaller than that of the drain region to reduce the band-to-band tunneling effect inside the transistor, thereby reducing the GIDL effect.
  • some embodiments of the present disclosure form a first isolation layer surrounding the first doping region and a second isolation layer surrounding the second doping region.
  • the first doping region and the second isolation layer can be avoided.
  • the second doped region affects other components in the semiconductor device; on the other hand, it also helps to further reduce the band-to-band tunneling effect inside the transistor, thereby further reducing the GIDL effect.
  • FIG. 1 is a schematic top structural view of a semiconductor device in an embodiment of the present disclosure
  • FIG. 2 is a schematic top structural view of a semiconductor device in another embodiment of the present disclosure.
  • FIG. 3 is a schematic three-dimensional structural diagram of a semiconductor device in another embodiment of the present disclosure.
  • 4-11 are schematic diagrams of the main process structures in the process of forming semiconductor devices according to specific embodiments of the present disclosure.
  • FIG. 1 is a schematic top structural view of a semiconductor device in an example of the specific implementation mode of this disclosure. As shown in Figure 1, the semiconductor device includes:
  • the active pillar includes a channel region 10, a source region 11 and a drain region 12 distributed on opposite sides of the channel region 10.
  • the doping region 13, the source region 11, the second doping region 14 and the drain region 12 all include first type doping ions, and the doping concentration of the first doping region 13 is less than
  • the doping concentration of the source region 11 and the doping concentration of the second doping region 14 are smaller than the doping concentration of the drain region 12 .
  • the substrate may be, but is not limited to, a silicon substrate.
  • the substrate is a silicon substrate as an example for description.
  • the substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate is used to support device structures above it.
  • the semiconductor device may be, but is not limited to, a DRAM. This specific embodiment will be described by taking the semiconductor device as a DRAM as an example.
  • the substrate includes a memory array composed of a plurality of memory cells arranged in an array.
  • the memory cells include transistors and capacitors 22 electrically connected to the transistors.
  • the active pillar in the transistor includes the channel region 10, the source region 11, the drain region 12, the first doped region 13 and the second doped region 14, Wherein, the channel region 10 and the source region 11 are distributed on opposite sides of the first doping region 13 along the extension direction of the active pillar.
  • the channel region 10 and the drain region Regions 12 are distributed on opposite sides of the second doped region 14 along the extending direction of the active pillar.
  • the semiconductor device also includes support pillars 17 distributed around the periphery of the memory array and penetrating the memory array in a direction perpendicular to the top surface of the substrate.
  • the support pillar 17 is used to support the memory array and isolate the memory array from other peripheral components.
  • the material of the support pillar 17 may be a nitride material (such as silicon nitride).
  • the plurality mentioned in this specific embodiment refers to two or more.
  • the types of doping ions in the first doping region 13, the source region 11, the second doping region 14 and the drain region 12 are the same (all are the first type doping ions). ), that is, the first doped region 13, the source region 11, the second doped region 14 and the drain region 12 are doped with the same type of ions.
  • the doping concentration of the first type doping ions in the first doping region 13 is smaller than the doping concentration of the first type doping ions in the source region 11 , and the second doping region 14
  • the doping concentration of the first type doping ions in the drain region 12 is smaller than the doping concentration of the first type doping ions in the drain region 12 , that is, the first doping region 13 and the second doping Region 14 is lightly doped, and the source region 11 and the drain region 12 are heavily doped.
  • the second doped region 14 which is lightly doped with the same type as the drain region 12 , is disposed between the channel regions 10 , thereby reducing the band-to-band tunneling effect inside the transistor, thereby reducing the GIDL effect.
  • the active pillar extends along a first direction D1, which is a direction parallel to the top surface of the substrate; the semiconductor device further includes:
  • the first isolation layer 15 is located on the substrate, and the first isolation layer 15 is distributed around the periphery of the first doped region 13 , and the active pillar penetrates the first direction D1 along the first direction D1 .
  • the second isolation layer 16 is located on the substrate, and the second isolation layer ring 16 is distributed around the periphery of the second doped region 14 , and the active pillar penetrates the first direction D1 second isolation layer 16.
  • a plurality of the active pillars are spaced apart along a second direction D2.
  • the second direction D2 is a direction parallel to the top surface of the substrate, and the first direction D1 is in contact with the top surface of the substrate.
  • the second direction D2 intersects;
  • the first isolation layer 15 is continuously distributed around the periphery of a plurality of first doped regions 13 spaced apart along the second direction D2;
  • the second isolation layer 16 is continuously distributed around the periphery of a plurality of second doped regions 14 spaced apart along the second direction D2.
  • it also includes:
  • a first air gap is located between adjacent first doped regions 13;
  • the second air gap is located between the adjacent second doped regions 14 .
  • the active pillars extend along the first direction D1, and a plurality of the active pillars extend along the second direction D2 and perpendicular to the top surface of the substrate.
  • the directions are arranged in an array.
  • the top surface of the substrate refers to the surface of the substrate facing the active pillar.
  • a plurality of the first doping regions 13 are arranged in an array along the second direction D2 and a direction perpendicular to the top surface of the substrate, and a plurality of the second doping regions 14 are also arranged along the second direction D2 and the direction perpendicular to the top surface of the substrate.
  • the second direction D2 and the direction perpendicular to the top surface of the substrate are arranged in an array.
  • the first isolation layer 15 is in the shape of a surrounding frame, extends in a direction perpendicular to the top surface of the substrate, and is continuously distributed around the periphery of the plurality of first doped regions 13 arranged in an array.
  • the second isolation layer 16 is also in the shape of a surrounding frame, extends in a direction perpendicular to the top surface of the substrate, and is continuously distributed around the periphery of the plurality of second doped regions 14 arranged in an array.
  • the first doping region 13 is isolated from signal lines such as word lines in the semiconductor device by the first isolation layer 15
  • the second doping region 14 is isolated from the signal lines by the second isolation layer 16 . signal lines such as word lines in the semiconductor device, thus helping to further reduce the GIDL effect.
  • the first isolation layer 15 and the second isolation layer 16 are made of the same material, for example, both are insulating dielectric materials such as nitride (eg, silicon nitride).
  • nitride eg, silicon nitride
  • the first isolation layer 15 and the second isolation layer 16 can be formed simultaneously with the support pillar 17 , thereby simplifying the manufacturing process of the semiconductor device and reducing the manufacturing cost of the semiconductor device.
  • the active pillar extends along a first direction D1, and the first direction D1 is a direction parallel to the top surface of the substrate; the semiconductor device further includes:
  • the first isolation layer 15 is located on the substrate, and the first isolation layer 15 covers the first doped region 13 , and the active pillar penetrates the first isolation along the first direction D1 layer 15;
  • the second isolation layer 16 is located on the substrate, and the second isolation layer 16 covers the second doping region 14 , and the active pillar penetrates the second isolation along the first direction D1 Layer 16.
  • a plurality of the active pillars are spaced apart along a second direction D2, the second direction D2 is a direction parallel to the top surface of the substrate, and the first direction D1 is The second direction D2 intersects;
  • the first isolation layer 15 continuously covers a plurality of the first doped regions 13 arranged at intervals along the second direction D2;
  • the second isolation layer 16 continuously covers a plurality of second doping regions 14 that are spaced apart along the second direction D2.
  • the active pillars extend along the first direction D1
  • a plurality of the active pillars extend along the second direction D2 and perpendicular to the top surface of the substrate.
  • the directions are arranged in an array.
  • the top surface of the substrate refers to the surface of the substrate facing the active pillar.
  • a plurality of the first doping regions 13 are arranged in an array along the second direction D2 and a direction perpendicular to the top surface of the substrate
  • a plurality of the second doping regions 14 are also arranged along the second direction D2 and the direction perpendicular to the top surface of the substrate.
  • the second direction D2 and the direction perpendicular to the top surface of the substrate are arranged in an array.
  • the first isolation layer 15 continuously covers the plurality of first doped regions 13 arranged in an array and fills the gaps between adjacent first doped regions 13.
  • the second isolation layer 16 continuously covers a plurality of second doped regions 14 arranged in an array and fills the gaps between adjacent second doped regions 14, thereby further reducing the band tunneling effect.
  • the channel region 10 includes first type doping ions; or,
  • the channel region 10 includes second type doping ions, and the conductivity types of the first type doping ions and the second type doping ions are opposite.
  • the channel region 10 , the first doped region 13 and the second doped region 14 are all lightly doped with N-type ions, and the source region 11 and the drain region 12 All are heavily doped with N-type ions.
  • the channel region 10, the first doped region 13 and the second doped region 14 are all lightly doped with P-type ions, and the source region 11 and the drain region 12 are all lightly doped.
  • P-type ions are heavily doped.
  • the channel region 10 is lightly doped with N-type ions
  • the first doped region 13 and the second doped region 14 are both lightly doped with P-type ions
  • the source region 11 and the The drain regions 12 are heavily doped with P-type ions.
  • the channel region 10 is lightly doped with P-type ions
  • the first doped region 13 and the second doped region 14 are both lightly doped with N-type ions
  • the source region 11 and the The drain regions 12 are heavily doped with N-type ions.
  • the active pillar extends along a first direction D1, and the first direction D1 is a direction parallel to the top surface of the substrate;
  • the length of the first doped region 13 along the first direction D1 is more than twice the thickness of the active pillar along the third direction, which is perpendicular to the top surface of the substrate. direction;
  • the length of the second doped region 14 along the first direction D1 is more than twice the thickness of the active pillar along the third direction.
  • the thickness of the active pillar along the third direction (ie, the diameter of the active pillar) may be greater than or equal to 5 nm, and the first doped region 13 and the second doped region 14
  • the length along the first direction D1 may be greater than or equal to 10 nm.
  • the lengths of the first doped region 13 and the second doped region 14 along the first direction D1 are both set to be more than twice the thickness of the active pillar along the third direction. , can better reduce or even eliminate the band tunneling effect, thereby reducing and completely avoiding the GIDL effect.
  • the active pillar extends along a first direction D1, and the first direction D1 is a direction parallel to the top surface of the substrate;
  • the length of the first doped region 13 along the first direction D1 is greater than or equal to the length of the source region 11 along the first direction D1;
  • the length of the second doped region 14 along the first direction D1 is greater than or equal to the length of the drain region 12 along the first direction D1.
  • the length of the first doped region 13 can be greater than the length of the source region 11 along the first direction D1, and the length of the second doped region can be The length of 14 is greater than the length of the drain region 12 .
  • the active pillars extend along the first direction D1, and a plurality of the active pillars are arranged in an array along the second direction D2 and the third direction.
  • the first direction D1 and the second direction D1 are arranged in an array.
  • the directions D2 are all directions parallel to the top surface of the substrate, and the first direction D1 intersects the second direction D2, and the third direction is a direction perpendicular to the top surface of the substrate;
  • the semiconductor device also includes:
  • the word line 18 extends along the second direction D2 and continuously covers the channel region 10 in the plurality of active columns spaced apart along the second direction D2;
  • a plurality of word lines 18 are arranged at intervals along the third direction, and among the two adjacent word lines 18 along the third direction, the word line 18 closer to the substrate is along the edge of the substrate.
  • the second direction D2 protrudes from the other word line 18 .
  • the capacitor 22 is electrically connected to the drain region 12 in the transistor.
  • the semiconductor device further includes bit lines 19 extending along the third direction. Each of the bit lines 19 is electrically connected to a plurality of source regions 11 spaced apart along the third direction. The bit lines 19 are arranged at intervals along the second direction D2. A bit line plug 21 is also provided on the top surface of the bit line 19 for electrically connecting the bit line 19 with a peripheral control circuit.
  • the semiconductor device further includes a plurality of word lines 18 extending along the second direction D2. The plurality of word lines 18 are arranged at intervals along the third direction, and each of the word lines 18 continuously covers Or cover a plurality of the channel regions 10 spaced apart along the second direction D2.
  • the end portions of the word lines 18 extend out of the memory array, and a plurality of the word lines 18 extend out of the end portions of the memory array to form a step-like structure to facilitate electrical connection of the word lines 18 through the word line plugs 20 .
  • the step-like structure means that among the two adjacent word lines 18 along the third direction, one of the word lines 18 closer to the substrate protrudes from the other along the second direction D2.
  • FIG. 3 is a schematic diagram of a three-dimensional structure of a semiconductor device in another embodiment of the disclosure.
  • FIGS. 4-11 are schematic diagrams of a method for forming a semiconductor device according to an embodiment of the disclosure.
  • a schematic diagram of the main process structure of the device in the process wherein Figure 4 is a top structural schematic diagram of the semiconductor device formed in this specific embodiment, Figures 5 to 11 are the positions a-a and b-b in Figure 4 during the formation process of the semiconductor device , c-c position, d-d position and e-e position schematic diagram of the main process to clearly show the formation process of the semiconductor device.
  • the structure of the semiconductor device formed in this specific embodiment can be seen in Figures 1 and 2.
  • the semiconductor device formed in this specific embodiment may be, but is not limited to, a DRAM.
  • the method for forming a semiconductor device includes the following steps:
  • step S31 a substrate 50 is provided, as shown in FIG. 5 .
  • the substrate 50 may be, but is not limited to, a silicon substrate.
  • the substrate 50 is a silicon substrate as an example for description.
  • the substrate 50 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the substrate 50 is used to support device structures above it.
  • Step S32 Form a transistor on the substrate.
  • the transistor includes an active pillar.
  • the active pillar includes a channel region 10, a source region 11 and a drain electrode distributed on opposite sides of the channel region 10.
  • the first doping region 13, the source region 11, the second doping region 14 and the drain region 12 all include first type doping ions, and the first doping region
  • the doping concentration of 13 is smaller than the doping concentration of the source region 11
  • the doping concentration of the second doped region 14 is smaller than the doping concentration of the drain region 12 , as shown in FIG. 11 and FIG. 4 .
  • specific steps of forming transistors on the substrate 50 include:
  • An initial channel region 90 is defined in the semiconductor pillar 76 , an initial source region 91 and an initial drain region 93 are distributed on opposite sides of the initial channel region 90 , and are located between the initial source region 91 and the initial drain region 93 .
  • an initial channel region 90 is defined in the semiconductor pillar 76 , and an initial source region 91 and an initial drain region 93 are distributed on opposite sides of the initial channel region 90 .
  • the initial first doped region 92 between the electrode region 91 and the initial channel region 90 and the initial second doped region 94 between the initial drain region 93 and the initial channel region 90 Specific steps include:
  • An initial channel region 90 is defined in the semiconductor pillar 76 .
  • An initial source region 91 and an initial drain region 93 are distributed on opposite sides of the initial channel region 90 along the first direction D1 .
  • D1 is located in the initial first doped region 92 between the initial source region 91 and the initial channel region 90 , and is located in the initial drain region 93 and the initial channel along the first direction D1
  • the initial second doped region 94 between the regions 90, the length of the initial first doped region 92 along the first direction D1 is more than twice the thickness of the semiconductor pillar 76 along the third direction D3, so The length of the initial second doped region 94 along the first direction D1 is more than twice the thickness of the semiconductor pillar 76 along the third direction D3.
  • the first direction D1 is parallel to the substrate 50
  • the third direction D3 is a direction perpendicular to the top surface of the substrate 50 .
  • specific steps of forming semiconductor pillars 76 over the substrate 50 include:
  • a stacked layer is formed on the substrate 50 .
  • the stacked layer includes semiconductor layers 52 and sacrificial layers 51 that are alternately stacked along a third direction D3 .
  • the third direction D3 is perpendicular to the top surface of the substrate 50 . direction;
  • the stacked layer is etched to form first trenches 60 penetrating the stacked layer along the third direction D3.
  • a plurality of the first trenches 60 are arranged at intervals along the second direction D2.
  • the groove 60 separates the semiconductor layer 52 into a plurality of semiconductor pillars 76 spaced apart along the second direction D2.
  • the semiconductor pillars 76 extend along the first direction D1.
  • the first direction D1 and the The second directions D2 are both directions parallel to the top surface of the substrate 50 , and the first direction D1 intersects the second direction D2.
  • epitaxial growth may be used to alternately form the semiconductor layer 52 and the sacrificial layer 51 on the top surface of the substrate 50 along the third direction D3 to form all the layers having a superlattice stack structure.
  • the stacked layers are shown in Figure 5. The more layers the semiconductor layer 52 and the sacrificial layer 51 are alternately stacked, the greater the storage capacity of the formed semiconductor device.
  • the material of the semiconductor layer 52 may be Si
  • the material of the sacrificial layer 51 may be SiGe.
  • a first dielectric layer 53 is formed on the top surface of the stacked layer, and a photolithography process is used to etch the stacked layer and the first dielectric layer 53 to form a plurality of layers penetrating the stacked layer along the third direction D3.
  • the first trench 60 separates the semiconductor layer 52 into a plurality of semiconductor pillars 76 spaced apart along the second direction D2.
  • the semiconductor pillars 76 extend along the first direction D1, as shown in FIG. 6 Show.
  • first type doping ions are injected into the initial source region 91 , the initial drain region 93 , the initial first doping region 92 and the initial second doping region 94 , also includes the following steps:
  • Part of the sacrificial layer 51 in the stacked layer is removed to form a second trench 73 and a third trench 74.
  • the second trench 73 exposes the initial first doped region 92 and the initial channel.
  • the semiconductor pillar 76 between the regions 90 and the semiconductor pillar 76 between the initial first doped region 92 and the initial source region 91, the third trench 74 exposes the initial third The semiconductor pillar 76 between the second doped region 94 and the initial channel region 90, and the semiconductor pillar 76 between the initial second doped region 94 and the initial drain region 93, such as As shown in Figure 7;
  • the second isolation layer 16 is shown in Figure 8 and Figure 4 .
  • an insulating dielectric material such as an oxide (such as silicon dioxide) may be deposited in the first trench 60 to form an insulating material that fills the first trench 60 and A filling layer 70 covering the top surface of the stacked layers is shown in Figure 7.
  • a photolithography process may be used to remove part of the sacrificial layer 51 to form the second trench 73 , the third trench 74 , and the support hole 71 that expose part of the semiconductor pillar 76 .
  • the second trench 73 is annular, and the projection of the second trench 73 on the top surface of the substrate 50 surrounds a plurality of the initial first doped regions 92 on the substrate. The peripheral distribution of the projection on the top surface of 50.
  • the third trench 74 is also annular, and the projection of the third trench 74 on the top surface of the substrate 50 surrounds a plurality of the initial second doped regions 74 on the substrate 50 The peripheral distribution of the projection on the top surface.
  • a first dielectric material such as nitride (such as silicon nitride) is filled into the second trench 73 , the third trench 74 and the support hole 71 , and the first isolation layer 15 is formed at the same time. , the second isolation layer 16 and the support column 17, as described in Figures 4 and 8.
  • first type doping ions are injected into the initial source region 91 , the initial drain region 93 , the initial first doping region 92 and the initial second doping region 94 , also includes the following steps:
  • the second dielectric material is filled in the fourth trench to form an interlayer isolation layer 100, as shown in FIG. 10 .
  • a wet etching process may be used to remove all the sacrificial layers 51 in the stacked layers, thereby forming a fourth trench exposing the semiconductor pillar 76 .
  • a second dielectric material such as oxide (such as silicon dioxide) is deposited in the fourth trench to form the interlayer isolation layer 100, as shown in FIG. 10 .
  • first type doping ions are implanted into the initial source region 91 , the initial drain region 93 , the initial first doped region 92 and the initial second doped region 94 Specific steps include:
  • the first type doping ions are implanted into the initial first doping region 92 and the initial second doping region 94 to form the first doping region 13 and the second doping region 14 .
  • the method of forming a semiconductor device further includes:
  • Second-type doping ions are implanted into the initial channel region 90 to form the channel region 10 , and the conductivity types of the first-type doping ions and the second-type doping ions are opposite.
  • multiple photomasks and multiple doping processes may be used to provide the initial source region 91 , the initial drain region 93 , the initial first doped region 92 and the initial second doped region 92 .
  • Doping ions are implanted into the doping region 94 and the initial channel region 90 respectively, and different types and/or different concentrations of doping are completed in each region.
  • first type doping ions are injected into the initial source region 91, the initial drain region 93, the initial first doping region 92 and the initial second doping region 94, and to the A specific method for doping the initial channel region 90 with the first type doping ions or the second type doping ions may be vapor phase diffusion, plasma doping or ion implantation.
  • the following steps are further included:
  • the interlayer isolation layer 100 between the adjacent first doped regions 13 is removed, and the interlayer isolation layer 100 between the adjacent second doped regions 14 is removed at the same time to form an adjacent The first air gap between the first doped regions 13 and the second air gap between the adjacent second doped regions 14 are simultaneously formed.
  • first air gap between the first doped regions 13 surrounded by the first isolation layer 15, so that the low dielectric constant of air is used to reduce the adjacent first doped regions.
  • second air gap between the second doped regions 14 surrounded by the second isolation layer 16, so that the low dielectric constant of air is used to reduce the density of the adjacent second doped regions. interference between 14.
  • the first dielectric material continuously covers a plurality of the first doped regions 13 arranged in an array and fills the gaps between adjacent first doped regions 13.
  • the two dielectric materials continuously cover the plurality of second doped regions 14 arranged in an array and fill the gaps between adjacent second doped regions 14, thereby further reducing the band tunneling effect.
  • a capacitor 22 electrically connected to the drain region 12 and The bit line 19 electrically connected to the source region 11 , the word line 18 covering the channel region 10 , the bit line plug 21 located on the top surface of the bit line 19 , and the bit line 18 located on the top surface of the word line 18
  • a plurality of the word lines 18 are arranged at intervals along the third direction, and each of the word lines 18 continuously covers or covers a plurality of the channel regions 10 arranged at intervals along the second direction D2.
  • the ends of the plurality of word lines 18 together form a step-like structure to facilitate electrical connection between the word lines 18 and peripheral control circuits through word line plugs 20 .
  • Some embodiments of this specific embodiment provide a semiconductor device and a method for forming the same, by arranging a first doping region between the channel region and the source region, and arranging a second doping region between the channel region and the drain region. region, and the ion doping type of the first doping region is the same as that of the source region, and the ion doping type of the second doping region is the same as that of the drain region.
  • the doping concentration of the first doping region is smaller than that of the source region and the third doping region.
  • the doping concentration of the second doped region is smaller than that of the drain region to reduce the band tunneling effect inside the transistor, thereby reducing the GIDL effect.
  • some embodiments of the present disclosure form a first isolation layer surrounding the first doping region and a second isolation layer surrounding the second doping region.
  • the first doping region and the second isolation layer can be avoided.
  • the second doped region affects other components in the semiconductor device; on the other hand, it also helps to further reduce the band-to-band tunneling effect inside the transistor, thereby further reducing the GIDL effect.

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Abstract

本公开涉及一种半导体器件及其形成方法。所述半导体器件包括：衬底；晶体管，位于所述衬底上，包括有源柱，所述有源柱包括沟道区、分布于所述沟道区相对两侧的源极区和漏极区、位于所述源极区与所述沟道区之间的第一掺杂区、以及位于所述漏极区与所述沟道区之间的第二掺杂区，所述第一掺杂区、所述源极区、所述第二掺杂区和所述漏极区均包括第一类型掺杂离子，且所述第一掺杂区掺杂浓度小于所述源极区的掺杂浓度，所述第二掺杂区的掺杂浓度小于所述漏极区的掺杂浓度。本公开减小了晶体管内部的带带隧穿效应，从而降低了GIDL效应。

Description

半导体器件及其形成方法
相关申请引用说明
本申请要求于2022年06月21日递交的中国专利申请号202210705481.0申请名为“半导体器件及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
DRAM等半导体器件的晶体管通常还包括沟道区、以及位于沟道区相对两侧、且与所述沟道区相邻的源极区和漏极区。随着DRAM尺寸的不断微缩，晶体管内部的BTBT(Band to Band Tunneling，带带隧穿)效应增强，从而引起半导体器件内部的GIDL(Gate-Induced Drain Leakage，栅极感应漏极漏电)效应增强，最终导致半导体器件电性能的降低。
因此，如何减少半导体器件内部的GIDL效应，改善半导体器件的性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体器件及其形成方法，用于降低半导体器件内部的GIDL效应，从而改善半导体器件的电性能，提高半导体器件的良率。
根据一些实施例，本公开提供了一种半导体器件，包括：
衬底；
晶体管，位于所述衬底上，包括有源柱，所述有源柱包括沟道区、分布于所述沟道区相对两侧的源极区和漏极区、位于所述源极区与所述沟道区之间的第一掺杂区、以及位于所述漏极区与所述沟道区之间的第二掺杂区，所述第一掺杂区、所述源极区、所述第二掺杂区和所述漏极区均包括第一类型掺杂离子，且所述第一掺杂区掺杂浓度小于所述源极区的掺杂浓度，所述第二掺杂区的掺杂浓度小于所述漏极区的掺杂浓度。
在一些实施例中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；所述半导体器件还包括：
第一隔离层，位于所述衬底上，且所述第一隔离层环绕所述第一掺杂区的外周分布，所述有源柱沿所述第一方向贯穿所述第一隔离层；
第二隔离层，位于所述衬底上，且所述第二隔离层环绕所述第二掺杂区的外周分布，所述有源柱沿所述第一方向贯穿所述第二隔离层。
在一些实施例中，多个所述有源柱沿第二方向间隔排布，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
所述第一隔离层连续环绕沿所述第二方向间隔排布的多个所述第一掺杂区的外周分布；
所述第二隔离层连续环绕沿所述第二方向间隔排布的多个所述第二掺杂区的外周分布。
在一些实施例中，还包括：
第一空气隙，位于相邻的所述第一掺杂区之间；
第二空气隙，位于相邻的所述第二掺杂区之间。
在一些实施例中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；所述半导体器件还包括：
第一隔离层，位于所述衬底上，且所述第一隔离层包覆所述第一掺杂区，所述有源柱 沿所述第一方向贯穿所述第一隔离层；
第二隔离层，位于所述衬底上，且所述第二隔离层包覆所述第二掺杂区，所述有源柱沿所述第一方向贯穿所述第二隔离层。
在一些实施例中，多个所述有源柱沿第二方向间隔排布，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
所述第一隔离层连续包覆沿所述第二方向间隔排布的多个所述第一掺杂区；
所述第二隔离层连续包覆沿所述第二方向间隔排布的多个所述第二掺杂区。
在一些实施例中，所述沟道区包括第一类型掺杂离子；或者，
所述沟道区包括第二类型掺杂离子，且所述第一类型掺杂离子与所述第二类型掺杂离子的导电类型相反。
在一些实施例中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；
所述第一掺杂区沿所述第一方向的长度为所述有源柱沿第三方向的厚度的2倍以上，所述第三方向为垂直于所述衬底的顶面的方向；
所述第二掺杂区沿所述第一方向的长度为所述有源柱沿所述第三方向厚度的2倍以上。
在一些实施例中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；
所述第一掺杂区沿所述第一方向的长度大于或者等于所述源极区沿所述第一方向的长度；
所述第二掺杂区沿所述第一方向的长度大于或者等于所述漏极区沿所述第一方向的长度。
在一些实施例中，所述有源柱沿第一方向延伸，多个所述有源柱沿第二方向和第三方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交，所述第三方向为垂直于所述衬底的顶面的方向；所述半导体器件还包括：
字线，沿所述第二方向延伸，且连续覆盖沿所述第二方向间隔排布的多个所述有源柱中的所述沟道区；
多条所述字线沿所述第三方向间隔排布，且沿所述第三方向相邻的两条所述字线中，较靠近所述衬底的一条所述字线沿所述第二方向突出于另一条所述字线。
根据另一些实施例，本公开还提供了一种半导体器件的形成方法，包括如下步骤：
提供衬底；
形成晶体管于所述衬底上，所述晶体管包括有源柱，所述有源柱包括沟道区、分布于所述沟道区相对两侧的源极区和漏极区、位于所述源极区与所述沟道区之间的第一掺杂区、以及位于所述漏极区与所述沟道区之间的第二掺杂区，所述第一掺杂区、所述源极区、所述第二掺杂区和所述漏极区均包括第一类型掺杂离子，且所述第一掺杂区的掺杂浓度小于所述源极区的掺杂浓度，所述第二掺杂区的掺杂浓度小于所述漏极区的掺杂浓度。
在一些实施例中，形成晶体管于所述衬底上的具体步骤包括：
于所述衬底上方形成半导体柱；
于所述半导体柱中定义初始沟道区、分布于所述初始沟道区相对两侧的初始源极区和初始漏极区、位于所述初始源极区与所述初始沟道区之间的初始第一掺杂区、以及位于所述初始漏极区与所述初始沟道区之间的初始第二掺杂区；
注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区，形成所述源极区、所述第一掺杂区、所述漏极区和所述第二掺杂区。
在一些实施例中，于所述半导体柱中定义初始沟道区、分布于所述初始沟道区相对两侧的初始源极区和初始漏极区、位于所述初始源极区与所述初始沟道区之间的初始第一掺杂区、以及位于所述初始漏极区与所述初始沟道区之间的初始第二掺杂区的具体步骤包括：
于所述半导体柱中定义初始沟道区、沿第一方向分布于所述初始沟道区相对两侧的初始源极区和初始漏极区、沿所述第一方向位于所述初始源极区与所述初始沟道区之间的初始第一掺杂区、以及沿所述第一方向位于所述初始漏极区与所述初始沟道区之间的初始第二掺杂区，所述初始第一掺杂区沿所述第一方向的长度为所述半导体柱沿第三方向的厚度的2倍以上，所述初始第二掺杂区沿所述第一方向的长度为所述半导体柱沿所述第三方向厚度的2倍以上，所述第一方向为平行于所述衬底的顶面的方向，所述第三方向为垂直于所述衬底的顶面的方向。
在一些实施例中，于所述衬底上方形成半导体柱的具体步骤包括：
形成堆叠层于所述衬底上，所述堆叠层包括沿第三方向交替堆叠的半导体层和牺牲层，所述第三方向为垂直于所述衬底的顶面的方向；
刻蚀所述堆叠层，形成沿所述第三方向贯穿所述堆叠层的第一沟槽，多个所述第一沟槽沿第二方向间隔排布，所述第一沟槽将所述半导体层分隔为沿所述第二方向间隔排布的多个所述半导体柱，所述半导体柱沿第一方向延伸，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交。
在一些实施例中，注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区之前，还包括如下步骤：
去除所述堆叠层中的部分所述牺牲层，形成第二沟槽和第三沟槽，所述第二沟槽暴露所述初始第一掺杂区和所述初始沟道区之间的所述半导体柱、以及所述初始第一掺杂区和所述初始源极区之间的所述半导体柱，所述第三沟槽暴露所述初始第二掺杂区和所述初始沟道区之间的所述半导体柱、以及所述初始第二掺杂区和所述初始漏极区之间的所述半导体柱；
沉积第一介质材料于所述第二沟槽和所述第三沟槽，于所述第二沟槽内形成第一隔离层、并同时于所述第三沟槽内形成第二隔离层。
在一些实施例中，注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区之前，还包括如下步骤：
去除所述堆叠层中的所述牺牲层，暴露所述半导体柱的第四沟槽；
填充第二介质材料于所述第四沟槽内，形成层间隔离层。
在一些实施例中，注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区的具体步骤包括：
注入第一类型掺杂离子至所述初始源极区和所述初始漏极区，形成所述源极区和所述漏极区；
注入所述第一类型掺杂离子至所述初始第一掺杂区和所述初始第二掺杂区，形成所述第一掺杂区和所述第二掺杂区。
在一些实施例中，还包括：
注入第一类型掺杂离子至所述初始沟道区，形成所述沟道区；或者，
注入第二类型掺杂离子至所述初始沟道区，形成所述沟道区，且述第一类型掺杂离子与所述第二类型掺杂离子的导电类型相反。
在一些实施例中，形成所述源极区、所述第一掺杂区、所述漏极区和所述第二掺杂区之后，还包括如下步骤：
去除相邻所述第一掺杂区之间的所述层间隔离层、并同时去除相邻所述第二掺杂区之间的所述层间隔离层，形成位于相邻所述第一掺杂区之间的第一空气隙、并同时形成位于相邻所述第二掺杂区之间的第二空气隙。
在一些实施例中，形成位于相邻所述第一掺杂区之间的第一空气隙、并同时形成位于相邻所述第二掺杂区之间的第二空气隙之后，还包括如下步骤：
沉积所述第一介质材料于所述第一空气隙和所述第二空气隙内。
本公开一些实施例提供的半导体器件及其形成方法，通过在沟道区与源极区之间设置 第一掺杂区、并在沟道区与漏极区之间设置第二掺杂区，且第一掺杂区的离子掺杂类型与源极区相同、第二掺杂区的离子掺杂类型与漏极区相同，第一掺杂区的掺杂浓度小于源极区、第二掺杂区的掺杂浓度小于漏极区，以减小晶体管内部的带带隧穿效应，从而降低GIDL效应。而且，本公开一些实施例形成包围所述第一掺杂区的第一隔离层、以及包围所述第二掺杂区的第二隔离层，一方面，可以避免所述第一掺杂区和所述第二掺杂区对所述半导体器件中的其他元器件造成影响；另一方面，还有助于进一步减小晶体管内部的带带隧穿效应，从而进一步降低GIDL效应。
附图说明
附图1是本公开具体实施方式一实施例中半导体器件的俯视结构示意图；
附图2是本公开具体实施方式另一实施例中半导体器件的俯视结构示意图；
附图3是本公开具体实施方式另一实施例中半导体器件的立体结构示意图；
附图4-11是本公开具体实施方式在形成半导体器件的过程中主要的工艺结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体器件及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体器件，附图1是本公开具体实施方式一实施例中半导体器件的俯视结构示意图。如图1所示，所述半导体器件，包括：
衬底；
晶体管，位于所述衬底上，包括有源柱，所述有源柱包括沟道区10、分布于所述沟道区10相对两侧的源极区11和漏极区12、位于所述源极区11与所述沟道区10之间的第一掺杂区13、以及位于所述漏极区12与所述沟道区10之间的第二掺杂区14，所述第一掺杂区13、所述源极区11、所述第二掺杂区14和所述漏极区12均包括第一类型掺杂离子，且所述第一掺杂区13的掺杂浓度小于所述源极区11的掺杂浓度，所述第二掺杂区14的掺杂浓度小于所述漏极区12的掺杂浓度。
具体来说，所述衬底可以是但不限于硅衬底，本具体实施方式以所述衬底为硅衬底为例进行说明。在其他实施例中，所述衬底还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底用于支撑在其上方的器件结构。所述半导体器件可以是但不限于DRAM，本具体实施方式以所述半导体器件为DRAM为例进行说明。举例来说，所述衬底上包括由多个存储单元呈阵列排布构成的存储阵列，所述存储单元包括晶体管、以及与所述晶体管电连接的电容器22。所述晶体管中的所述有源柱包括所述沟道区10、所述源极区11、所述漏极区12、所述第一掺杂区13和所述第二掺杂区14，其中，所述沟道区10和所述源极区11沿所述有源柱的延伸方向分布于所述第一掺杂区13的相对两侧，所述沟道区10和所述漏极区12沿所述有源柱的延伸方向分布于所述第二掺杂区14的相对两侧。所述半导体器件中还包括环绕所述存储阵列的外周分布、并沿垂直于所述衬底的顶面的方向贯穿所述存储阵列的支撑柱17。所述支撑柱17用于支撑所述存储阵列，并隔离所述存储阵列与其他外围元器件。在一实施例中，所述支撑柱17的材料可以为氮化物材料(例如氮化硅)。本具体实施方式中所述的多个是指两个以上。
所述第一掺杂区13、所述源极区11、所述第二掺杂区14和所述漏极区12中的掺杂离子的种类相同(均为所述第一类型掺杂离子)，即所述第一掺杂区13、所述源极区11、所述第二掺杂区14和所述漏极区12为同型离子掺杂。所述第一掺杂区13中所述第一类型掺杂离子的掺杂浓度小于所述源极区11中所述第一类型掺杂离子的掺杂浓度，所述第二掺杂区14中所述第一类型掺杂离子的掺杂浓度小于所述漏极区12中所述第一类型掺杂离子的掺杂浓度，即所述第一掺杂区13和所述第二掺杂区14为轻掺杂，所述源极区11和所述漏极区12为重掺杂。通过在所述源极区11与所述沟道区10之间设置与所述源极区11同型轻掺杂的所述第一掺杂区13、并在所述漏极区12与所述沟道区10之间设置与所述漏极区12同型轻掺杂的所述第二掺杂区14，减小了晶体管内部的带带隧穿效应，从而降低了GIDL效应。
在一些实施例中，所述有源柱沿第一方向D1延伸，所述第一方向D1为平行于所述衬底的顶面的方向；所述半导体器件还包括：
第一隔离层15，位于所述衬底上，且所述第一隔离层15环绕所述第一掺杂区13的外周分布，所述有源柱沿所述第一方向D1贯穿所述第一隔离层15；
第二隔离层16，位于所述衬底上，且所述第二隔离层环16绕所述第二掺杂区14的外周分布，所述有源柱沿所述第一方向D1贯穿所述第二隔离层16。
在一些实施例中，多个所述有源柱沿第二方向D2间隔排布，所述第二方向D2为平行于所述衬底的顶面的方向，且所述第一方向D1与所述第二方向D2相交；
所述第一隔离层15连续环绕沿所述第二方向D2间隔排布的多个所述第一掺杂区13的外周分布；
所述第二隔离层16连续环绕沿所述第二方向D2间隔排布的多个所述第二掺杂区14的外周分布。
在一些实施例中，还包括：
第一空气隙，位于相邻的所述第一掺杂区13之间；
第二空气隙，位于相邻的所述第二掺杂区14之间。
具体来说，如图1所示，所述有源柱沿所述第一方向D1延伸，且多个所述有源柱沿所述第二方向D2和垂直于所述衬底的顶面的方向呈阵列排布。所述衬底的顶面是指所述衬底朝向所述有源柱的表面。相应的，多个所述第一掺杂区13沿所述第二方向D2和所垂直于所述衬底的顶面的方向呈阵列排布，多个所述第二掺杂区14也沿所述第二方向D2和垂直于所述衬底的顶面的方向呈阵列排布。所述第一隔离层15呈围框状，且沿垂直于所述衬底的顶面的方向延伸，并连续环绕呈阵列排布的多个所述第一掺杂区13的外周分布。所述第二隔离层16也呈围框状，且沿垂直于所述衬底的顶面的方向延伸，并连续环绕呈阵列排布的多个所述第二掺杂区14的外周分布。通过所述第一隔离层15隔离所述第一掺杂区13与所述半导体器件中的字线等信号线，并通过所述第二隔离层16隔离所述第二掺杂区14与所述半导体器件中的字线等信号线，从而有助于进一步降低GIDL效应。在一实施例中，所述第一隔离层15和所述第二隔离层16的材料相同，例如均为氮化物(例如氮化硅)等绝缘介质材料。被所述第一隔离层15包围的所述第一掺杂区13之间具有所述第一空气隙，从而利用空气的低介电常数来降低相邻所述第一掺杂区13之间的干扰。相应的，被所述第二隔离层16包围的所述第二掺杂区14之间具有所述第二空气隙，从而利用空气的低介电常数来降低相邻所述第二掺杂区14之间的干扰。
在一实施例中，所述第一隔离层15和所述第二隔离层16可以与所述支撑柱17同步形成，从而简化所述半导体器件的制程工艺，减低所述半导体器件的制造成本。
在另一些实施例中，所述有源柱沿第一方向D1延伸，所述第一方向D1为平行于所述衬底的顶面的方向；所述半导体器件还包括：
第一隔离层15，位于所述衬底上，且所述第一隔离层15包覆所述第一掺杂区13，所述有源柱沿所述第一方向D1贯穿所述第一隔离层15；
第二隔离层16，位于所述衬底上，且所述第二隔离层16包覆所述第二掺杂区14，所述有源柱沿所述第一方向D1贯穿所述第二隔离层16。
在另一些实施例中，多个所述有源柱沿第二方向D2间隔排布，所述第二方向D2为平行于所述衬底的顶面的方向，且所述第一方向D1与所述第二方向D2相交；
所述第一隔离层15连续包覆沿所述第二方向D2间隔排布的多个所述第一掺杂区13；
所述第二隔离层16连续包覆沿所述第二方向D2间隔排布的多个所述第二掺杂区14。
具体来说，如图2所示，所述有源柱沿所述第一方向D1延伸，且多个所述有源柱沿所述第二方向D2和垂直于所述衬底的顶面的方向呈阵列排布。所述衬底的顶面是指所述衬底朝向所述有源柱的表面。相应的，多个所述第一掺杂区13沿所述第二方向D2和所垂直于所述衬底的顶面的方向呈阵列排布，多个所述第二掺杂区14也沿所述第二方向D2和垂直 于所述衬底的顶面的方向呈阵列排布。所述第一隔离层15连续包覆呈阵列排布的多个所述第一掺杂区13、且填充满相邻所述第一掺杂区13之间的间隙，所述第二隔离层16连续包覆呈阵列排布的多个所述第二掺杂区14、且填充满相邻所述第二掺杂区14之间的间隙，从而进一步降低带带隧穿效应。
为了满足所述半导体器件各种应用的需求，在一些实施例中，所述沟道区10包括第一类型掺杂离子；或者，
所述沟道区10包括第二类型掺杂离子，且所述第一类型掺杂离子与所述第二类型掺杂离子的导电类型相反。
举例来说，所述沟道区10、所述第一掺杂区13和所述第二掺杂区14均为N型离子轻掺杂，所述源极区11和所述漏极区12均为N型离子重掺杂。或者，所述沟道区10、所述第一掺杂区13和所述第二掺杂区14均为P型离子轻掺杂，所述源极区11和所述漏极区12均为P型离子重掺杂。或者，所述沟道区10为N型离子轻掺杂，所述第一掺杂区13和所述第二掺杂区14均为P型离子轻掺杂，所述源极区11和所述漏极区12均为P型离子重掺杂。或者，所述沟道区10为P型离子轻掺杂，所述第一掺杂区13和所述第二掺杂区14均为N型离子轻掺杂，所述源极区11和所述漏极区12均为N型离子重掺杂。
在一些实施例中，所述有源柱沿第一方向D1延伸，所述第一方向D1为平行于所述衬底的顶面的方向；
所述第一掺杂区13沿所述第一方向D1的长度为所述有源柱沿第三方向的厚度的2倍以上，所述第三方向为垂直于所述衬底的顶面的方向；
所述第二掺杂区14沿所述第一方向D1的长度为所述有源柱沿所述第三方向厚度的2倍以上。
举例来说，所述有源柱沿所述第三方向的厚度(即所述有源柱的直径)可以大于或者等于5nm，所述第一掺杂区13和所述第二掺杂区14沿所述第一方向D1的长度可以大于或者等于10nm。本具体实施方式通过将所述第一掺杂区13和所述第二掺杂区14沿所述第一方向D1的长度均设置为所述有源柱沿第三方向的厚度的2倍以上，可以更好的减少、甚至是消除带带隧穿效应，从而降低、设置是完全避免GIDL效应。
在一些实施例中，所述有源柱沿第一方向D1延伸，所述第一方向D1为平行于所述衬底的顶面的方向；
所述第一掺杂区13沿所述第一方向D1的长度大于或者等于所述源极区11沿所述第一方向D1的长度；
所述第二掺杂区14沿所述第一方向D1的长度大于或者等于所述漏极区12沿所述第一方向D1的长度。
具体来说，所述第一掺杂区13和所述第二掺杂区14的长度越长，降低GIDL的效应越显著。为了不增加所述半导体器件的尺寸，可以使得在沿所述第一方向D1上，所述第一掺杂区13的长度大于所述源极区11的长度、且所述第二掺杂区14的长度大于所述漏极区12的长度。
在一些实施例中，所述有源柱沿第一方向D1延伸，多个所述有源柱沿第二方向D2和第三方向呈阵列排布，所述第一方向D1和所述第二方向D2均为平行于所述衬底的顶面的方向，且所述第一方向D1与所述第二方向D2相交，所述第三方向为垂直于所述衬底的顶面的方向；所述半导体器件还包括：
字线18，沿所述第二方向D2延伸，且连续覆盖沿所述第二方向D2间隔排布的多个所述有源柱中的所述沟道区10；
多条所述字线18沿所述第三方向间隔排布，且沿所述第三方向相邻的两条所述字线18中，较靠近所述衬底的一条所述字线18沿所述第二方向D2突出于另一条所述字线18。
具体来说，如图1和图2所示，所述电容器22电连接所述晶体管中的所述漏极区12。所述半导体器件还包括沿所述第三方向延伸的位线19，每条所述位线19与沿所述第三方向 间隔排布的多个所述源极区11接触电连接，且多条所述位线19沿所述第二方向D2间隔排布。所述位线19的顶面还设置有位线插塞21，用于电连接所述位线19与外围控制电路。所述半导体器件还包括多条沿所述第二方向D2延伸的所述字线18，多条所述字线18沿所述第三方向间隔排布，且每条所述字线18连续覆盖或者包覆沿所述第二方向D2间隔排布的多个所述沟道区10。所述字线18的端部延伸出所述存储阵列，且多条所述字线18延伸出所述存储阵列的端部共同构成台阶状结构，以便于通过字线插塞20电连接所述字线18与外围控制电路。所述台阶状结构是指，沿所述第三方向相邻的两条所述字线18中，较靠近所述衬底的一条所述字线18沿所述第二方向D2突出于另一条所述字线18。
本具体实施方式还提供了一种半导体器件的形成方法，附图3是本公开具体实施方式另一实施例中半导体器件的立体结构示意图，附图4-11是本公开具体实施方式在形成半导体器件的过程中主要的工艺结构示意图，其中，图4是本具体实施方式形成的半导体器件的俯视结构示意图，图5-图11是所述半导体器件的形成过程中图4中a-a位置、b-b位置、c-c位置、d-d位置和e-e位置的主要工艺截面示意图，以清楚的表明所述半导体器件的形成过程。本具体实施方式形成的半导体器件的结构可以参见图1和图2。本具体实施方式形成的半导体器件可以是但不限于DRAM。如图1-图11所示，所述半导体器件的形成方法，包括如下步骤：
步骤S31，提供衬底50，如图5所示。
具体来说，所述衬底50可以是但不限于硅衬底，本具体实施方式以所述衬底50为硅衬底为例进行说明。在其他实施例中，所述衬底50还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底50用于支撑在其上方的器件结构。
步骤S32，形成晶体管于所述衬底上，所述晶体管包括有源柱，所述有源柱包括沟道区10、分布于所述沟道区10相对两侧的源极区11和漏极区12、位于所述源极区11与所述沟道区10之间的第一掺杂区13、以及位于所述漏极区12与所述沟道区10之间的第二掺杂区14，所述第一掺杂区13、所述源极区11、所述第二掺杂区14和所述漏极区12均包括第一类型掺杂离子，且所述第一掺杂区13的掺杂浓度小于所述源极区11的掺杂浓度，所述第二掺杂区14的掺杂浓度小于所述漏极区12的掺杂浓度，如图11和图4所示。
在一些实施例中，形成晶体管于所述衬底50上的具体步骤包括：
于所述衬底50上方形成半导体柱76，如图6所示；
于所述半导体柱76中定义初始沟道区90、分布于所述初始沟道区90相对两侧的初始源极区91和初始漏极区93、位于所述初始源极区91与所述初始沟道区90之间的初始第一掺杂区92、以及位于所述初始漏极区93与所述初始沟道区90之间的初始第二掺杂区94，如图9所示；
注入第一类型掺杂离子至所述初始源极区91、所述初始漏极区93、所述初始第一掺杂区92和所述初始第二掺杂区94，形成所述源极区11、所述第一掺杂区13、所述漏极区12和所述第二掺杂区14。
在一些实施例中，于所述半导体柱76中定义初始沟道区90、分布于所述初始沟道区90相对两侧的初始源极区91和初始漏极区93、位于所述初始源极区91与所述初始沟道区90之间的初始第一掺杂区92、以及位于所述初始漏极区93与所述初始沟道区90之间的初始第二掺杂区94的具体步骤包括：
于所述半导体柱76中定义初始沟道区90、沿第一方向D1分布于所述初始沟道区90相对两侧的初始源极区91和初始漏极区93、沿所述第一方向D1位于所述初始源极区91与所述初始沟道区90之间的初始第一掺杂区92、以及沿所述第一方向D1位于所述初始漏极区93与所述初始沟道区90之间的初始第二掺杂区94，所述初始第一掺杂区92沿所述第一方向D1的长度为所述半导体柱76沿第三方向D3的厚度的2倍以上，所述初始第二掺杂区94沿所述第一方向D1的长度为所述半导体柱76沿所述第三方向D3厚度的2倍以上，所述第一方向D1为平行于所述衬底50的顶面的方向，所述第三方向D3为垂直于所述衬 底50的顶面的方向。
在一些实施例中，于所述衬底50上方形成半导体柱76的具体步骤包括：
形成堆叠层于所述衬底50上，所述堆叠层包括沿第三方向D3交替堆叠的半导体层52和牺牲层51，所述第三方向D3为垂直于所述衬底50的顶面的方向；
刻蚀所述堆叠层，形成沿所述第三方向D3贯穿所述堆叠层的第一沟槽60，多个所述第一沟槽60沿第二方向D2间隔排布，所述第一沟槽60将所述半导体层52分隔为沿所述第二方向D2间隔排布的多个所述半导体柱76，所述半导体柱76沿第一方向D1延伸，所述第一方向D1和所述第二方向D2均为平行于所述衬底50的顶面的方向，且所述第一方向D1与所述第二方向D2相交。
具体来说，可以采用外延生长的方式、沿所述第三方向D3交替形成所述半导体层52和所述牺牲层51于所述衬底50的顶面，形成具有超晶格堆栈结构的所述堆叠层，如图5所示。所述半导体层52与所述牺牲层51交替堆叠的层数越多，形成的所述半导体器件的存储容量越大。在一实施例中，所述半导体层52的材料可以为Si，所述牺牲层51的材料可以为SiGe。之后，形成第一介质层53于所述堆叠层的顶面，并采用光刻工艺刻蚀所述堆叠层和所述第一介质层53，形成多个沿所述第三方向D3贯穿所述第一介质层53和所述堆叠层的所述第一沟槽60。所述第一沟槽60将所述半导体层52分隔为沿所述第二方向D2间隔排布的多个所述半导体柱76，所述半导体柱76沿第一方向D1延伸，如图6所示。
在一些实施例中，注入第一类型掺杂离子至所述初始源极区91、所述初始漏极区93、所述初始第一掺杂区92和所述初始第二掺杂区94之前，还包括如下步骤：
去除所述堆叠层中的部分所述牺牲层51，形成第二沟槽73和第三沟槽74，所述第二沟槽73暴露所述初始第一掺杂区92和所述初始沟道区90之间的所述半导体柱76、以及所述初始第一掺杂区92和所述初始源极区91之间的所述半导体柱76，所述第三沟槽74暴露所述初始第二掺杂区94和所述初始沟道区90之间的所述半导体柱76、以及所述初始第二掺杂区94和所述初始漏极区93之间的所述半导体柱76，如图7所示；
沉积第一介质材料于所述第二沟槽73和所述第三沟槽74，于所述第二沟槽73内形成第一隔离层15、并同时于所述第三沟槽74内形成第二隔离层16，如图8和图4所示。
具体来说，在形成所述第一沟槽60之后，可以沉积氧化物(例如二氧化硅)等绝缘介质材料于所述第一沟槽60内，形成填充满所述第一沟槽60并覆盖所述堆叠层的顶面的填充层70，如图7所示。之后，可以采用光刻工艺去除部分的所述牺牲层51，形成暴露部分所述半导体柱76的所述第二沟槽73、所述第三沟槽74、以及支撑孔71。其中，所述第二沟槽73呈环状，且所述第二沟槽73在所述衬底50的顶面上的投影环绕多个所述初始第一掺杂区92在所述衬底50的顶面上的投影的外周分布。所述第三沟槽74也呈环状，且所述第三沟槽74在所述衬底50的顶面上的投影环绕多个所述初始第二掺杂区74在所述衬底50的顶面上的投影的外周分布。同时填充氮化物(例如氮化硅)等第一介质材料于所述第二沟槽73内、所述第三沟槽74内和所述支撑孔71内，同时形成所述第一隔离层15、所述第二隔离层16和所述支撑柱17，如图4和图8所述。
在一些实施例中，注入第一类型掺杂离子至所述初始源极区91、所述初始漏极区93、所述初始第一掺杂区92和所述初始第二掺杂区94之前，还包括如下步骤：
去除所述堆叠层中的所述牺牲层51，暴露所述半导体柱76的第四沟槽，如图9所示；
填充第二介质材料于所述第四沟槽内，形成层间隔离层100，如图10所示。
具体来说，可以采用湿法刻蚀工艺去除所述堆叠层中所有的所述牺牲层51，从而形成暴露所述半导体柱76的第四沟槽。之后，沉积氧化物(例如二氧化硅)等第二介质材料于所述第四沟槽内，形成所述层间隔离层100，如图10所示。
在一些实施例中，注入第一类型掺杂离子至所述初始源极区91、所述初始漏极区93、所述初始第一掺杂区92和所述初始第二掺杂区94的具体步骤包括：
注入第一类型掺杂离子至所述初始源极区91和所述初始漏极区93，形成所述源极区 11和所述漏极区12；
注入所述第一类型掺杂离子至所述初始第一掺杂区92和所述初始第二掺杂区94，形成所述第一掺杂区13和所述第二掺杂区14。
在一些实施例中，所述半导体器件的形成方法还包括：
注入第一类型掺杂离子至所述初始沟道区90，形成所述沟道区10；或者，
注入第二类型掺杂离子至所述初始沟道区90，形成所述沟道区10，且所述第一类型掺杂离子与所述第二类型掺杂离子的导电类型相反。
具体来说，可以采用多次光罩、以及多次掺杂工艺来向所述初始源极区91、所述初始漏极区93、所述初始第一掺杂区92和所述初始第二掺杂区94、以及所述初始沟道区90分别注入掺杂离子，已完成各区域不同类型和/或不同浓度的掺杂。其中，注入第一类型掺杂离子至所述初始源极区91、所述初始漏极区93、所述初始第一掺杂区92和所述初始第二掺杂区94、以及对所述初始沟道区90掺杂所述第一类型掺杂离子或者所述第二类型掺杂离子的具体方法可以是气相扩散、等离子体掺杂或者离子注入。
在一些实施例中，形成所述源极区11、所述第一掺杂区13、所述漏极区12和所述第二掺杂区14之后，还包括如下步骤：
去除相邻所述第一掺杂区13之间的所述层间隔离层100、并同时去除相邻所述第二掺杂区14之间的所述层间隔离层100，形成位于相邻所述第一掺杂区13之间的第一空气隙、并同时形成位于相邻所述第二掺杂区14之间的第二空气隙。
具体来说，被所述第一隔离层15包围的所述第一掺杂区13之间具有所述第一空气隙，从而利用空气的低介电常数来降低相邻所述第一掺杂区13之间的干扰。相应的，被所述第二隔离层16包围的所述第二掺杂区14之间具有所述第二空气隙，从而利用空气的低介电常数来降低相邻所述第二掺杂区14之间的干扰。
在一些实施例中，形成位于相邻所述第一掺杂区13之间的第一空气隙、并同时形成位于相邻所述第二掺杂区14之间的第二空气隙之后，还包括如下步骤：
沉积所述第一介质材料于所述第一空气隙和所述第二空气隙内。
具体来说，所述第一介质材料连续包覆呈阵列排布的多个所述第一掺杂区13、且填充满相邻所述第一掺杂区13之间的间隙，所述第二介质材料连续包覆呈阵列排布的多个所述第二掺杂区14、且填充满相邻所述第二掺杂区14之间的间隙，从而进一步降低带带隧穿效应。
形成所述源极区11、所述第一掺杂区13、所述漏极区12和所述第二掺杂区14之后，再形成与所述漏极区12电连接的电容器22、与所述源极区11电连接的位线19、覆盖所述沟道区10的字线18、位于所述位线19顶面的位线插塞21、以及位于所述字线18顶面的字线插塞20，从而得到如图4所示的结构。多条所述字线18沿所述第三方向间隔排布，且每条所述字线18连续覆盖或者包覆沿所述第二方向D2间隔排布的多个所述沟道区10。多条所述字线18的端部共同构成台阶状结构，以便于通过字线插塞20电连接所述字线18与外围控制电路。
本具体实施方式一些实施例提供的半导体器件及其形成方法，通过在沟道区与源极区之间设置第一掺杂区、并在沟道区与漏极区之间设置第二掺杂区，且第一掺杂区的离子掺杂类型与源极区相同、第二掺杂区的离子掺杂类型与漏极区相同，第一掺杂区的掺杂浓度小于源极区、第二掺杂区的掺杂浓度小于漏极区，以减小晶体管内部的带带隧穿效应，从而降低GIDL效应。而且，本公开一些实施例形成包围所述第一掺杂区的第一隔离层、以及包围所述第二掺杂区的第二隔离层，一方面，可以避免所述第一掺杂区和所述第二掺杂区对所述半导体器件中的其他元器件造成影响；另一方面，还有助于进一步减小晶体管内部的带带隧穿效应，从而进一步降低GIDL效应。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员， 在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种半导体器件，包括：
    衬底；
    晶体管，位于所述衬底上，包括有源柱，所述有源柱包括沟道区、分布于所述沟道区相对两侧的源极区和漏极区、位于所述源极区与所述沟道区之间的第一掺杂区、以及位于所述漏极区与所述沟道区之间的第二掺杂区，所述第一掺杂区、所述源极区、所述第二掺杂区和所述漏极区均包括第一类型掺杂离子，且所述第一掺杂区的掺杂浓度小于所述源极区的掺杂浓度，所述第二掺杂区的掺杂浓度小于所述漏极区的掺杂浓度。
  2. 根据权利要求1所述的半导体器件，其中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；所述半导体器件还包括：
    第一隔离层，位于所述衬底上，且所述第一隔离层环绕所述第一掺杂区的外周分布，所述有源柱沿所述第一方向贯穿所述第一隔离层；
    第二隔离层，位于所述衬底上，且所述第二隔离层环绕所述第二掺杂区的外周分布，所述有源柱沿所述第一方向贯穿所述第二隔离层。
  3. 根据权利要求2所述的半导体器件，其中，多个所述有源柱沿第二方向间隔排布，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    所述第一隔离层连续环绕沿所述第二方向间隔排布的多个所述第一掺杂区的外周分布；
    所述第二隔离层连续环绕沿所述第二方向间隔排布的多个所述第二掺杂区的外周分布。
  4. 根据权利要求3所述的半导体器件，还包括：
    第一空气隙，位于相邻的所述第一掺杂区之间；
    第二空气隙，位于相邻的所述第二掺杂区之间。
  5. 根据权利要求1所述的半导体器件，其中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；所述半导体器件还包括：
    第一隔离层，位于所述衬底上，且所述第一隔离层包覆所述第一掺杂区，所述有源柱沿所述第一方向贯穿所述第一隔离层；
    第二隔离层，位于所述衬底上，且所述第二隔离层包覆所述第二掺杂区，所述有源柱沿所述第一方向贯穿所述第二隔离层。
  6. 根据权利要求5所述的半导体器件，其中，多个所述有源柱沿第二方向间隔排布，所述第二方向为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    所述第一隔离层连续包覆沿所述第二方向间隔排布的多个所述第一掺杂区；
    所述第二隔离层连续包覆沿所述第二方向间隔排布的多个所述第二掺杂区。
  7. 根据权利要求1所述的半导体器件，其中，所述沟道区包括第一类型掺杂离子；或者，所述沟道区包括第二类型掺杂离子，且所述第一类型掺杂离子与所述第二类型掺杂离子的导电类型相反。
  8. 根据权利要求1所述的半导体器件，其中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；
    所述第一掺杂区沿所述第一方向的长度为所述有源柱沿第三方向的厚度的2倍以上，所述第三方向为垂直于所述衬底的顶面的方向；
    所述第二掺杂区沿所述第一方向的长度为所述有源柱沿所述第三方向厚度的2倍以上。
  9. 根据权利要求1所述的半导体器件，其中，所述有源柱沿第一方向延伸，所述第一方向为平行于所述衬底的顶面的方向；
    所述第一掺杂区沿所述第一方向的长度大于或者等于所述源极区沿所述第一方向的长度；
    所述第二掺杂区沿所述第一方向的长度大于或者等于所述漏极区沿所述第一方向的长度。
  10. 根据权利要求1所述的半导体器件，其中，所述有源柱沿第一方向延伸，多个所述有源柱沿第二方向和第三方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬 底的顶面的方向，且所述第一方向与所述第二方向相交，所述第三方向为垂直于所述衬底的顶面的方向；所述半导体器件还包括：
    字线，沿所述第二方向延伸，且连续覆盖沿所述第二方向间隔排布的多个所述有源柱中的所述沟道区；
    多条所述字线沿所述第三方向间隔排布，且沿所述第三方向相邻的两条所述字线中，较靠近所述衬底的一条所述字线沿所述第二方向突出于另一条所述字线。
  11. 一种半导体器件的形成方法，包括如下步骤：
    提供衬底；
    形成晶体管于所述衬底上，所述晶体管包括有源柱，所述有源柱包括沟道区、分布于所述沟道区相对两侧的源极区和漏极区、位于所述源极区与所述沟道区之间的第一掺杂区、以及位于所述漏极区与所述沟道区之间的第二掺杂区，所述第一掺杂区、所述源极区、所述第二掺杂区和所述漏极区均包括第一类型掺杂离子，且所述第一掺杂区的掺杂浓度小于所述源极区的掺杂浓度，所述第二掺杂区的掺杂浓度小于所述漏极区的掺杂浓度。
  12. 根据权利要求11所述的半导体器件的形成方法，其中，形成晶体管于所述衬底上的具体步骤包括：
    于所述衬底上方形成半导体柱；
    于所述半导体柱中定义初始沟道区、分布于所述初始沟道区相对两侧的初始源极区和初始漏极区、位于所述初始源极区与所述初始沟道区之间的初始第一掺杂区、以及位于所述初始漏极区与所述初始沟道区之间的初始第二掺杂区；
    注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区，形成所述源极区、所述第一掺杂区、所述漏极区和所述第二掺杂区。
  13. 根据权利要求12所述的半导体器件的形成方法，其中，于所述半导体柱中定义初始沟道区、分布于所述初始沟道区相对两侧的初始源极区和初始漏极区、位于所述初始源极区与所述初始沟道区之间的初始第一掺杂区、以及位于所述初始漏极区与所述初始沟道区之间的初始第二掺杂区的具体步骤包括：
    于所述半导体柱中定义初始沟道区、沿第一方向分布于所述初始沟道区相对两侧的初始源极区和初始漏极区、沿所述第一方向位于所述初始源极区与所述初始沟道区之间的初始第一掺杂区、以及沿所述第一方向位于所述初始漏极区与所述初始沟道区之间的初始第二掺杂区，所述初始第一掺杂区沿所述第一方向的长度为所述半导体柱沿第三方向的厚度的2倍以上，所述初始第二掺杂区沿所述第一方向的长度为所述半导体柱沿所述第三方向厚度的2倍以上，所述第一方向为平行于所述衬底的顶面的方向，所述第三方向为垂直于所述衬底的顶面的方向。
  14. 根据权利要求12所述的半导体器件的形成方法，其中，于所述衬底上方形成半导体柱的具体步骤包括：
    形成堆叠层于所述衬底上，所述堆叠层包括沿第三方向交替堆叠的半导体层和牺牲层，所述第三方向为垂直于所述衬底的顶面的方向；
    刻蚀所述堆叠层，形成沿所述第三方向贯穿所述堆叠层的第一沟槽，多个所述第一沟槽沿第二方向间隔排布，所述第一沟槽将所述半导体层分隔为沿所述第二方向间隔排布的多个所述半导体柱，所述半导体柱沿第一方向延伸，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交。
  15. 根据权利要求14所述的半导体器件的形成方法，其中，注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区之前，还包括如下步骤：
    去除所述堆叠层中的部分所述牺牲层，形成第二沟槽和第三沟槽，所述第二沟槽暴露所述初始第一掺杂区和所述初始沟道区之间的所述半导体柱、以及所述初始第一掺杂区和 所述初始源极区之间的所述半导体柱，所述第三沟槽暴露所述初始第二掺杂区和所述初始沟道区之间的所述半导体柱、以及所述初始第二掺杂区和所述初始漏极区之间的所述半导体柱；
    沉积第一介质材料于所述第二沟槽和所述第三沟槽，于所述第二沟槽内形成第一隔离层、并同时于所述第三沟槽内形成第二隔离层。
  16. 根据权利要求15所述的半导体器件的形成方法，其中，注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区之前，还包括如下步骤：
    去除所述堆叠层中的所述牺牲层，暴露所述半导体柱的第四沟槽；
    填充第二介质材料于所述第四沟槽内，形成层间隔离层。
  17. 根据权利要求16所述的半导体器件的形成方法，其中，注入第一类型掺杂离子至所述初始源极区、所述初始漏极区、所述初始第一掺杂区和所述初始第二掺杂区的具体步骤包括：
    注入第一类型掺杂离子至所述初始源极区和所述初始漏极区，形成所述源极区和所述漏极区；
    注入所述第一类型掺杂离子至所述初始第一掺杂区和所述初始第二掺杂区，形成所述第一掺杂区和所述第二掺杂区。
  18. 根据权利要求12所述的半导体器件的形成方法，还包括：
    注入第一类型掺杂离子至所述初始沟道区，形成所述沟道区；或者，
    注入第二类型掺杂离子至所述初始沟道区，形成所述沟道区，且所述第一类型掺杂离子与所述第二类型掺杂离子的导电类型相反。
  19. 根据权利要求17所述的半导体器件的形成方法，其中，形成所述源极区、所述第一掺杂区、所述漏极区和所述第二掺杂区之后，还包括如下步骤：
    去除相邻所述第一掺杂区之间的所述层间隔离层、并同时去除相邻所述第二掺杂区之间的所述层间隔离层，形成位于相邻所述第一掺杂区之间的第一空气隙、并同时形成位于相邻所述第二掺杂区之间的第二空气隙。
  20. 根据权利要求19所述的半导体器件的形成方法，其中，形成位于相邻所述第一掺杂区之间的第一空气隙、并同时形成位于相邻所述第二掺杂区之间的第二空气隙之后，还包括如下步骤：
    沉积所述第一介质材料于所述第一空气隙和所述第二空气隙内。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210125989A1 (en) * 2019-10-29 2021-04-29 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device
US20210183862A1 (en) * 2019-12-16 2021-06-17 Samsung Electronics Co., Ltd. Semiconductor memory device and method for manufacturing the same
CN113644063A (zh) * 2020-04-27 2021-11-12 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
CN114582801A (zh) * 2022-05-05 2022-06-03 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN114639728A (zh) * 2022-05-05 2022-06-17 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210125989A1 (en) * 2019-10-29 2021-04-29 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device
US20210183862A1 (en) * 2019-12-16 2021-06-17 Samsung Electronics Co., Ltd. Semiconductor memory device and method for manufacturing the same
CN113644063A (zh) * 2020-04-27 2021-11-12 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
CN114582801A (zh) * 2022-05-05 2022-06-03 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN114639728A (zh) * 2022-05-05 2022-06-17 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法

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