WO2022116785A1 - 三维存储器及其制造方法 - Google Patents

三维存储器及其制造方法 Download PDF

Info

Publication number
WO2022116785A1
WO2022116785A1 PCT/CN2021/129763 CN2021129763W WO2022116785A1 WO 2022116785 A1 WO2022116785 A1 WO 2022116785A1 CN 2021129763 W CN2021129763 W CN 2021129763W WO 2022116785 A1 WO2022116785 A1 WO 2022116785A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
gate line
select gate
tangent
isolation region
Prior art date
Application number
PCT/CN2021/129763
Other languages
English (en)
French (fr)
Inventor
王清清
王健舻
徐伟
曾明
Original Assignee
长江存储科技有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to CN202180008042.8A priority Critical patent/CN116472788A/zh
Publication of WO2022116785A1 publication Critical patent/WO2022116785A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Definitions

  • the present disclosure relates to the field of manufacturing of integrated circuits, and in particular, to a three-dimensional memory with a widened and reinforced structure and a manufacturing method thereof.
  • the industry has developed memory devices with three-dimensional (3D) structures to improve integration by three-dimensionally arranging memory cells over a substrate.
  • the number of layers of the three-dimensional memory gradually increases from 32 to 128 or even more than 200 layers. The higher the number of layers, the greater the risk of collapse of the three-dimensional memory.
  • the stack structure in the 3D memory collapses, it will cause problems such as misalignment between the film layers and the inability of the conductive contacts to be accurately connected to the corresponding functional layers, resulting in a decline in device performance and serious damage to the 3D memory.
  • the technical problem to be solved by the present disclosure is to provide a three-dimensional memory with a widened reinforcement structure and a manufacturing method thereof.
  • a three-dimensional memory comprising: a substrate on which a stack structure in which gate layers and dielectric layers are alternately stacked; a plurality of channel structures, vertical passing through the stacked structure and reaching into the substrate; a first gate line spacer, extending along a first direction and dividing the plurality of channel structures into at least two memory blocks, the first gate line spacer
  • the trench includes a first isolation region, and the first isolation region isolates the first gate line isolation trench to form a plurality of first sub-gate line isolation trenches; a first connection structure is connected to the first gate line isolation trench along the first direction.
  • the adjacent first sub-gate line isolation trenches are separated by an isolation region.
  • it further includes: a second gate line spacer, located in the memory block, the second gate line spacer extending along the first direction and connecting all the space in the memory block.
  • the plurality of channel structures are divided into at least two finger storage regions, the second gate line isolation trench includes a second isolation region, and the second isolation region isolates the second gate line isolation trench to form a plurality of second gate line isolation regions. sub-gate line spacers; and a second connection structure connecting adjacent second sub-gate line spacers separated by the second isolation regions along the first direction.
  • a top portion of the stacked structure includes a top select gate and a top select gate tangent extending along the first direction, the top select gate tangent separating the top select gates.
  • the first isolation region includes a first cutout formed in a top select gate layer of the stacked structure, the first cutout having a depth similar to that of the top select gate The depth of the tangent is the same.
  • the second isolation region includes a second cutout formed in a top select gate layer of the stacked structure, the second cutout having a depth equal to a tangent of the top select gate line same depth.
  • the gate layer at the bottom of the stacked structure provides a bottom select gate;
  • the three-dimensional memory further includes: a bottom select gate tangent extending along a first direction and passing through the first Bottom select gates in an isolation region, the bottom select gates tangentially separating the bottom select gates of adjacent memory blocks.
  • the bottom select gate of the memory block is connected to a block select terminal for selecting the memory block.
  • the present disclosure also proposes a method for manufacturing a three-dimensional memory, including: providing a substrate, a stack structure alternately stacked by gate layers and dielectric layers; the stack structure includes a plurality of channel structures, the channel structure vertically passes through the stack structure and reaches the substrate; a first gate line spacer is formed in the stack structure, the first gate line spacer extends along a first direction and connects the A plurality of channel structures are divided into at least two memory blocks, the first gate line isolation trench includes a first isolation region, and the first isolation region isolates the first gate line isolation trench to form a plurality of first sub-gates A line separation groove; forming a first connection structure, the first connection structure connects the adjacent first sub-gate line separation grooves separated by the first isolation region along the first direction.
  • the method further includes: forming a second gate line spacer in the stacked structure, the second gate line spacer extending along the first direction and connecting all the memory blocks in the memory block.
  • the plurality of channel structures are divided into at least two finger storage regions, the second gate line isolation trench includes a plurality of second isolation regions, and the second isolation region isolates the second gate line isolation trench to form a plurality of second sub-gate line spacers; and forming a second connection structure connecting the adjacent second sub-gate line spacers separated by the second isolation regions along the first direction.
  • a gate layer located on top of the stacked structure provides a top select gate, forming a top select gate tangent extending along the first direction, the top select gate a tangent separating the top select gate; and forming a first cutout in the top select gate at the top of the stack structure of the first isolation region, the first cutout having a depth similar to that of the top select gate The depth of the gate tangent is the same.
  • a gate layer located on top of the stacked structure provides a top select gate, forming a top select gate tangent extending along the first direction, the top select gate a tangent separating the top select gate; and forming a second cutout in the top select gate at the top of the stacked structure of the second isolation region, the second cutout having a depth similar to the top select gate The depth of the tangent is the same.
  • the gate layer at the bottom of the stacked structure provides a bottom select gate; the method further includes:
  • a bottom select gate tangent is formed through the bottom select gate in the first isolation region, the bottom select gate tangent separating the bottom select gates of adjacent memory blocks.
  • the method further includes: connecting the bottom selection gate of the memory block to a block selection terminal for selecting the memory block.
  • the present disclosure increases reinforcement compared to only reinforcing inside one memory block by reinforcing the interface of two memory blocks with the first isolation region in the first gate line spacer and the first connecting structure.
  • the width can effectively prevent the collapse or tilt of the three-dimensional memory structure with more layers.
  • the three-dimensional memory of the present disclosure uses bottom select gate tangents to separate bottom select gates of adjacent memory blocks under the first isolation region of the first gate line spacer, so that different memory blocks can be controlled respectively.
  • FIG. 1 is a schematic structural diagram of a three-dimensional memory
  • FIG. 2 is an exemplary flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present disclosure
  • FIG. 4 is a schematic top-view structural diagram of a three-dimensional memory according to an embodiment of the present disclosure
  • Figure 5A is a schematic top view of the block portion in Figure 4.
  • FIG. 5B is a schematic three-dimensional structure diagram of the block part in FIG. 4;
  • 6A-6H are schematic diagrams of a process of forming a bottom select gate tangent in a manufacturing method of a three-dimensional memory according to an embodiment of the present disclosure.
  • spatially relative terms such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element shown in the figures or the relationship of a feature to other elements or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary words “below” and “below” can encompass both an orientation of above and below.
  • Devices may also have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
  • orientations rotated 90 degrees or at other orientations
  • spatially relative descriptors used herein should be interpreted accordingly.
  • a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • references where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, as well as further features formed on the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.
  • the term "three-dimensional (3D) memory device” refers to a string of memory cell transistors (referred to herein as “memory strings”, eg, NAND strings), having a vertical orientation on a laterally oriented substrate, thereby memory A string of semiconductor devices extending in a vertical direction relative to a substrate.
  • memory strings eg, NAND strings
  • vertical/vertically means a lateral surface that is nominally perpendicular to the substrate.
  • the term "substrate” refers to the material upon which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate may be patterned or may remain unpatterned.
  • the substrate may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like.
  • the substrate can be made of a non-conductive material such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of a material that includes a region of thickness.
  • a layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure.
  • a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes there.
  • the layers may extend horizontally, vertically and/or along a tapered surface.
  • the substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, over it, and/or under it. Layers may include multiple layers.
  • the interconnect layer may include one or more conductor and contact layers (with contacts, interconnect lines, and/or vias formed therein) and one or more dielectric layers.
  • FIG. 1 is a schematic structural diagram of a three-dimensional memory.
  • the three-dimensional memory includes a substrate 110 and a stack structure 120 formed on the substrate 110 .
  • the stacked structure 120 is originally formed by alternately stacking dummy gate layers and dielectric layers.
  • the stacked structure 120 includes a plurality of vertical channel structures 130 and gate line spacers 141 and 142 extending through the stacked structure 120 along a direction parallel to the word lines. These vertical channel structures 130 penetrate the stacked structure 120 and reach the substrate 110 middle.
  • the dummy gate layer in the stacked structure 120 is removed through the gate line spacers 141 and 142, and then the gate layer is formed at the position where the dummy gate layer is located.
  • FIG. 1 is a schematic structural diagram of a three-dimensional memory.
  • the three-dimensional memory includes a substrate 110 and a stack structure 120 formed on the substrate 110 .
  • the stacked structure 120 is originally formed by alternately stacking dummy gate layers and dielectric layers.
  • FIG. 1 shows a state after the dummy gate layer is removed, and the dummy gate layer adjacent to the dielectric layer 121 in the stack structure 120 has been removed.
  • the vertical channel structures 130 are originally perpendicular to the surface of the substrate 110 , however, in FIG. 1 , the vertical channel structures 130 are all inclined to the right.
  • the widths of the gate line spacers 141 and 142 parallel to each other are originally equal. Due to the inclination and deformation of the stacked structure 120 , the width W1 of the gate line spacers 141 is significantly larger than the width W2 of the gate line spacers 142 .
  • the array common source is formed in the gate line spacer.
  • the conductive contact portion connected to the array common source is formed, due to the change of the width and position of the gate line spacer, the conductive contact portion will not be effective.
  • the ground contacts the common source of the array, resulting in defects or even failure of the device.
  • FIG. 2 is an exemplary flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic top-view structural diagram of a three-dimensional memory according to an embodiment of the present disclosure.
  • the three-dimensional memory and the manufacturing method thereof of the present disclosure will be described below with reference to FIG. 2 , FIG. 3 and FIG. 4 .
  • the manufacturing method of the three-dimensional memory of this embodiment includes the following steps:
  • Step S210 providing a substrate, a stack structure in which gate layers and dielectric layers are alternately stacked, wherein the gate layer at the bottom of the stack structure provides a bottom selection gate; the stack structure includes a plurality of channel structures, and the channel structure vertically through the stack and into the substrate.
  • FIG. 3 shows a cross-sectional view of the three-dimensional memory of this embodiment.
  • FIG. 3 is a cross-sectional view along the AA′ tangent line perpendicular to the word line in FIG. 4 .
  • the three-dimensional memory includes a substrate 310 .
  • the substrate 310 may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanium substrate (SiGe), silicon on insulator (SOI, Silicon on Insulator) or germanium on insulator (GOI, Germanium on Insulator) Wait.
  • the substrate 310 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC.
  • the substrate 310 can also be a stacked structure, such as Si/SiGe and the like. Other epitaxial structures may also be included, such as silicon germanium on insulator (SGOI), and the like.
  • the substrate 310 may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer, among others.
  • the substrate 310 shown in FIG. 3 may have undergone some necessary processing, such as having formed a common active region, having undergone necessary cleaning, and the like.
  • a stack structure 320 is formed over the substrate 310 .
  • the stacked structure 320 may be a stack in which the first material layers and the second material layers are alternately stacked.
  • the first material layer and the second material layer may be selected from the following materials and include at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, etc., and combinations thereof .
  • the first material layer and the second material layer have different etch selectivities.
  • the first material layer may be a gate layer
  • the second material layer may be a dielectric layer.
  • the gate layer may be formed after removing the dummy gate layer.
  • the material as the gate sacrificial layer may be, for example, a silicon nitride layer.
  • the material used as the gate layer may be a conductive material such as metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon or any combination thereof.
  • As a material of the dielectric layer for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like may be used.
  • the material of the substrate 310 is, for example, silicon.
  • the first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods can be used to sequentially deposit silicon nitride and silicon oxide on the substrate 310 alternately to form a stack. Structure 320.
  • the substrate 310 may also be other silicon-containing substrates, such as SOI (silicon-on-insulator), SiGe, Si:C, and the like.
  • SOI silicon-on-insulator
  • the gate layer can also be other conductive layers, such as metal tungsten, cobalt, nickel, etc.
  • the second material layer may also be other dielectric materials, such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.
  • the present disclosure does not limit the number of layers of the stacked structure 320 .
  • the stack structure 320 is formed by stacking two sub-stack structures 321 and 322 .
  • the stack structure 320 may be formed by stacking a plurality of sub-stack structures.
  • the gate layer at the bottom provides the bottom select gate 311 for the three-dimensional memory of the present disclosure.
  • the upper and lower layers adjacent to the bottom select gate 311 are both dielectric layers.
  • a plurality of channel structures 330 are formed in the stack structure 320 of the three-dimensional memory.
  • a plurality of channel structures 330 are arranged in the three-dimensional memory according to a certain rule.
  • a plurality of channel structures 320 pass vertically through the stack structure 320 and into the substrate 310 .
  • the channel structure 330 may be formed in a channel hole vertically passing through the stack structure 320, and thus the channel structure 330 may be cylindrical.
  • the channel structure 330 may include a channel layer and a memory layer. As a whole, along the radial direction of the channel structure 330, the memory layer and the channel layer are sequentially arranged from the outside to the inside.
  • the memory layer may include a blocking layer, a charge trapping layer and a tunneling layer which are sequentially arranged from the outside to the inside along the radial direction of the channel structure 330 .
  • a filling layer may also be provided in the channel layer.
  • the filling layer can function as a support.
  • the material of the filling layer may be silicon oxide.
  • the filling layer can be solid or hollow without affecting the reliability of the device.
  • the formation of the channel structure 330 may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, etc., or any combination thereof.
  • the channel structure 330 is also composed of the sub-channel structure 331 in the stack structure 321 and the sub-channel structure 332 in the stack structure 322 .
  • the connection is formed, and there is an obvious boundary region at the position where the sub-channel structure 331 and the sub-channel structure 332 are connected.
  • Step S220 forming a first gate line spacer in the stacked structure, the first gate line spacer extending along the first direction and dividing the plurality of channel structures into at least two memory blocks, the first gate line spacer including the first gate line spacer.
  • the isolation region, the first isolation region isolates the first gate line isolation trench to form a plurality of first sub-gate line isolation trenches.
  • the three-dimensional memory generally includes several storage blocks (Block) and several finger storage areas (Finger) located in the storage block (Block), and between the storage blocks and the storage blocks and between the finger storage areas and the finger storage areas generally pass through in the vertical direction.
  • the gate spacers of the stacked structure are separated.
  • the first gate line spacer 340 is located in the middle part of the top layer of the three-dimensional memory.
  • the first gate line spacer 340 is a cutout extending downward from the top of the three-dimensional memory.
  • the first gate line spacer 340 is cut down one layer, indicating that the first gate line spacer 340 cuts off one gate layer.
  • the first gate line spacer 340 divides the plurality of channel structures 330 into two memory blocks, as shown by the dotted line in FIG. 3 , the first memory block 350 and The second memory block 360 on the right.
  • FIG. 4 shows the structure of the top of the three-dimensional memory shown in FIG. 3 , that is, the top layer of the stacked structure 320 .
  • the first gate line spacers 410 may correspond to the first gate line spacers 340 shown in FIG. 3 .
  • the first gate line spacer 410 extends along the first direction D1 and divides the plurality of channel structures into at least two memory blocks.
  • FIG. 4 shows two memory blocks divided by a first gate line spacer 410 , which are a first memory block 420 and a second memory block 430 respectively.
  • the first memory block 420 includes a plurality of channel structures 450 .
  • the column-shaped channel structures 450 are represented by a circular cross section.
  • FIG. 4 is not intended to limit the number and distribution of channel structures included in the memory block.
  • the first gate line spacer 410 is located between two adjacent memory blocks, at the junction of the first memory block 420 and the second memory block 430 .
  • the first gate line isolation trench 410 includes a plurality of first isolation regions, and the first gate line isolation trench 410 is isolated to form a plurality of first sub-gate line isolation trenches.
  • FIG. 4 shows three first isolation regions 441 , 442 , and 443 , and the first gate line isolation trench 410 is isolated to form four first sub-gate line isolation trenches 411 , 412 , 413 , and 414 .
  • the first isolation region 342 shown in FIG. 3 corresponds to the first isolation region 442 in FIG. 4 .
  • first gate line isolation trench 410 is isolated in the first isolation region, and in other parts, the first gate line isolation trench 410 is a trench that penetrates the stacked structure and reaches the substrate.
  • the first isolation region is a rectangular region extending along the first direction D1.
  • the first isolation region may also have other shapes, such as a square, a circle, and the like.
  • the three-dimensional memory may also be divided into a core array area 401 and a connection area 402 along the first direction D1.
  • the core array region 401 may include a plurality of channel structures serving as memory cells, and the connection region 402 may be a stepped region with a stepped structure.
  • the first gate line spacer 410 penetrates the core array region 401 and the connection region 402 along the first direction D1. As shown in FIG. 4 , the distribution and number of channel structures in the core array region 401 and the connection region 402 are different.
  • Step S230 forming a first connection structure, and the first connection structure connects adjacent first sub-gate line isolation trenches separated by the first isolation regions along a first direction.
  • FIG. 5A is a schematic top view of the block part in FIG. 4 , which shows the first isolation region 442 on the first gate line spacer 410 in FIG. 4 and the structures in the vicinity thereof.
  • the first isolation region 442 separates the first gate line isolation trench 410 to form the first sub-gate line isolation trenches 412 and 413 .
  • a first connection structure 510 is formed above the first isolation region 442, and the first connection structure 510 connects adjacent first sub-gate line spacers 412 and 413 along the first direction D1.
  • FIG. 5B is a schematic three-dimensional structure diagram of the block part in FIG. 4 .
  • the first direction D1 is the same as the extending direction of the first gate line spacer 410
  • a first isolation region 442 is located between the first sub-gate line spacer 412 and the first sub-gate line spacer 413 .
  • the first isolation region 442 includes a stack structure 522 and a first cutout 521 located above the stack structure 522 with a filling material in the first cutout 521 .
  • the stacked structure 522 is a part of the stacked structure 320 in FIG. 3 , and the gate layers in the same layer in the stacked structure 522 and the stacked structure 320 in FIG. 3 are communicated with each other.
  • the first isolation region 442 isolates the first gate line isolation trench 410 and is divided into a first sub-gate line isolation trench 412 and a first sub-gate line isolation trench 413 . Filling material is provided in the first sub-gate line spacers 412 and 413 .
  • the first connection structure 510 is formed above the first isolation region 442 to connect the first sub-gate line spacer 412 and the first sub-gate line spacer 413 .
  • the first gate line spacer 410 is filled with polysilicon, which can be used as the source structure of the three-dimensional memory.
  • the first cutout 521 includes one or more of silicon oxide, silicon nitride and/or silicon oxynitride.
  • the first connection structure 510 includes a conductive material, such as tungsten.
  • the first gate line spacer 410 filled with polysilicon is used as the source structure of the three-dimensional memory, and the first sub-gate line spacers 412 and 413 filled with polysilicon can be respectively used as source contacts of the three-dimensional memory. Adjacent first sub-gate line spacers 412 and 413 are in contact and conductively connected together through the first connection structure 510 . According to such a structure, the source voltage can be applied to the source contact through the first connection structure 510, reducing or eliminating the use of contact plugs.
  • the first isolation region 442 is insulated from the first sub-gate line isolation trenches 412 and 413 separated therefrom.
  • the portion of the stacked structure 522 in contact with the first sub-gate line spacers 412 and 413 further includes a spacer layer 523 .
  • the spacer layer 523 may provide further insulation between the stack structure 522 and the adjacent first sub-gate line spacers 412, 413 serving as source contacts.
  • Step S240 Forming a bottom select gate tangent through the bottom select gate in the first isolation region, the bottom select gate tangent separating the bottom select gates of adjacent memory blocks.
  • the bottom select gate tangent 341 is located between the first memory block 350 and the second memory block 360, extends upward from the substrate, and passes through the bottom select gate 311, so that the different memory blocks 350, The bottom select gate 311 of 360 is spaced apart.
  • the bottom select gate tangent 341 is not shown in FIG. 4 , it can be understood that the bottom select gate tangent 341 is located at the bottom of the first gate line spacer 410 , and is different from the first gate line spacer 410 parallel.
  • the gate layer at the bottom of the stack structure 522 is the bottom select gate 531, and the bottom select gate 531 is cut by the bottom select gate tangent 530 through it.
  • the first gate layer above the substrate 310 serves as the bottom select gate 311 .
  • several gate layers above the substrate 310 can be used as the bottom select gate 311 , and the bottom select gate tangent 341 passes through the bottom select gates 311 of the several layers.
  • connecting a bottom select gate at the bottom of each memory block to a block select terminal can be used to select that memory block. Voltages can be applied to the block select terminals to select the corresponding memory block through the bottom select gate connected thereto.
  • the three-dimensional memory formed through steps S210-S240 includes at least two memory blocks, and at the junction of the two memory blocks, the junction is reinforced with the first gate line spacer, the first isolation region and the first connection structure, and the junction is reinforced with the first gate line spacer, the first isolation region and the first connection structure.
  • the three-dimensional memory formed according to the above method includes a plurality of memory blocks, and the bottom select gates of adjacent memory blocks are separated by bottom select gate tangent lines, so that different memory blocks can be controlled respectively.
  • the manufacturing method of the present disclosure further comprises:
  • Step S250 forming a second gate line spacer in the stacked structure, the second gate line spacer extending along the first direction and dividing the plurality of channel structures in the memory block into at least two finger storage regions, the second gate line spacer extending along the first direction
  • the line isolation trench includes a plurality of second isolation regions, and the second isolation regions isolate the second gate line isolation trench to form a plurality of second sub-gate line isolation trenches.
  • Step S260 forming a second connection structure, and the second connection structure connects the adjacent second sub-gate line isolation trenches separated by the second isolation regions along the first direction.
  • two second gate line spacers 462 and 463 are formed in the first memory block 420 , and the two second gate line spacers 462 and 463
  • the multiple channel structures in the first memory block 420 are divided into three finger storage areas, and one finger storage area 421 is indicated in FIG. 4 .
  • a gate line spacer 461 is further included at the boundary of the first memory block 420 .
  • the second gate line spacers 462 and 463 each include three second isolation regions, wherein the second isolation regions 444 , 445 , 446 and the second gate line spacers 462 are marked.
  • the second isolation region 447 on the gate line spacer 463 FIG. 3 shows the second isolation regions 445 on the second gate line spacing trenches 462 and the second isolation regions 447 on the second gate line spacing trenches 463 cut by the AA′ line.
  • the structure of the second isolation region is the same as that of the first isolation region, and the foregoing description about the first isolation region can be used to describe the second isolation region.
  • the finger storage area 421 indicated in FIG. 4 corresponds to the finger storage area 371 indicated in FIG. 3 . 3 and 4, the number of channel structures included in each finger storage region may be the same.
  • forming the second isolation region and the second connection structure on the second gate line spacers 462 and 463 can have the effect of strengthening the three-dimensional memory structure inside the memory block.
  • the second connection structure is not formed on the gate line spacer 461 .
  • the second connection structure is similar to the first connection structure, except that the second connection structure is located in the second isolation region in the second gate line spacer.
  • the second isolation region and the second connection structure are formed in the second gate line spacers in each memory block, and the structure can be reinforced inside the memory block.
  • a reinforcement structure can be formed inside each storage block and between multiple storage blocks at the same time, which can meet the structural stability requirements of a three-dimensional memory with more layers.
  • the method for manufacturing a three-dimensional memory of the present disclosure further includes:
  • Step S262 the gate layer at the top of the stack structure provides a top select gate, forming a top select gate tangent extending along the first direction, the top select gate tangent separating the top select gate;
  • Step S264 forming a first cutout in the top select gate at the top of the stack structure of the first isolation region, and the depth of the first cutout is the same as the depth of the top select gate tangent.
  • the gate layer on the top of the stacked structure 320 is used as the top select gate 312 of the three-dimensional memory, and three top select gate tangent lines 351 , 352 , and 353 are formed in step S262 , corresponding to those shown in FIG. 4 .
  • the top select gate tangents 451, 452, 453 are shown.
  • the top select gate tangent line is located in the finger storage region separated by the second gate line spacer.
  • the present disclosure does not limit the number of layers of the gate layer serving as the top select gate in the stacked structure.
  • a gate layer is used as the top select gate 312 .
  • 2-6 layers of gate layers at the top of the stacked structure can be used as the top select gate, and the top select gate tangent cuts off the 2-6 layers of gate layers.
  • the first cutout 521 is formed in the top select gate of the stacked structure of the first isolation regions 442 .
  • the top select gate tangent and the first cutout are formed in the same process step to the same depth.
  • the method for manufacturing a three-dimensional memory of the present disclosure further includes:
  • Step S266 the gate layer at the top of the stacked structure provides a top select gate, forming a top select gate tangent extending along the first direction, the top select gate tangent separating the top select gates;
  • Step S268 forming a second cutout in the top select gate at the top of the stack structure of the second isolation region, and the depth of the second cutout is the same as the depth of the top select gate tangent.
  • These embodiments include a second gate line spacer inside the memory block, and the second cutout is formed in the second isolation region in the same way as the first cutout is formed in the first isolation region. Therefore, the content of the description about the first cutout can be used to describe the second cutout.
  • the structure of the second cutout is similar to that of the first cutout 521 and can be filled with the same material.
  • Figure 5B can be used to simultaneously represent the second cut.
  • the top select gate tangent and the second cutout are formed in the same process step to the same depth.
  • the top select gate tangent, the first cutout, and the second cutout are formed in the same process step, all having the same depth.
  • 6A-6H are schematic diagrams of a process of forming a bottom select gate tangent in a manufacturing method of a three-dimensional memory according to an embodiment of the present disclosure.
  • a substrate 610 is provided, and a high temperature oxide (HTO, High Temperature Oxide) layer 621 is formed on the substrate 610 .
  • HTO High Temperature Oxide
  • a gate layer 631 is deposited over the high temperature oxide layer 621 as a bottom select gate.
  • a dielectric layer 622 , a gate layer 632 and a dielectric layer 623 are also formed above the gate layer 631 .
  • the high temperature oxide layer 621 , the gate layer 631 , the dielectric layer 622 , the gate layer 632 , and the dielectric layer 623 form a stacked structure on the substrate 610 in sequence. It can be understood that the gate layer 632 can serve as an etch stop layer to protect the gate layer 631 .
  • a photoresist layer 640 having a pattern 641 is formed over the dielectric layer 623 at the top.
  • the location of the pattern 641 corresponds to the location where the top select gate tangent needs to be formed.
  • the stacked structure above the substrate is etched according to the photoresist layer 640 to form the cutout 642 shown in FIG. 6D .
  • the gate layer 631 is cut off.
  • a dielectric material 624 is deposited over the structure shown in Figure 6D such that the cutouts 642 are filled. This step can be performed by atomic layer deposition.
  • the top of the semiconductor structure shown in FIG. 6E is ground flat to expose the upper surface of the gate layer 632 .
  • a chemical mechanical polishing method can be used.
  • a cut 643 is formed in the gate layer 632 by wet etching, and the depth of the cut 643 is the same as the thickness of the gate layer 632, so that the dielectric layer 622 under the gate layer 632 is in the gate layer 632. Cut 643 is exposed.
  • gate layer 632 is removed.
  • bottom select gate cutouts 643 are formed on bottom select gate 631.
  • the stacked structure of the three-dimensional memory may continue to be formed over the semiconductor structure shown in FIG. 6H.
  • two or more memory blocks can be reinforced at the same time, thereby increasing the width of the reinforcement; the bottom select gate cutout is formed in the bottom select gate, and different memory blocks can be selected .
  • FIG. 3 and FIG. 4 For the structure of the three-dimensional memory of the present disclosure, reference may be made to FIG. 3 and FIG. 4 .
  • the three-dimensional memory of the present disclosure can be manufactured by the above-mentioned manufacturing method, so FIG. 2 and related description contents can be used to describe the three-dimensional memory of the embodiment of the present disclosure.
  • the three-dimensional memory of this embodiment includes a substrate 310 , a plurality of channel structures 330 , a first gate line spacer 340 , a first connection structure and a bottom select gate tangent 341 .
  • a stack structure 320 in which gate layers and dielectric layers are alternately stacked is formed on the substrate 310 , wherein the gate layer at the bottom of the stack structure 320 provides the bottom select gate 311 .
  • a plurality of channel structures 330 pass vertically through the stack structure 320 and into the substrate 310 .
  • Bottom select gate tangent lines 341 separate the bottom select gates 311 of adjacent memory blocks.
  • the first gate line spacer 410 extends along the first direction D1 and divides the plurality of channel structures into at least two memory blocks 420 and 430 , and the first gate line spacer 410 includes a first isolation region 441 , 442 , 443 , the first isolation regions 441 , 442 , and 443 isolate the first gate line isolation trench 410 to form a plurality of first sub-gate line isolation trenches 411 , 412 , 413 , and 414 .
  • the first connection structure 510 is located above the first isolation region 442 and connects adjacent first sub-gate line isolation trenches 412 and 413 separated by the first isolation region 442 along the first direction D1 .
  • the three-dimensional memory of the present disclosure further includes a second gate line spacer and a second connection structure.
  • the second gate line spacers 461 , 462 and 463 are located in the memory block 420 , and the second gate line spacers 461 , 462 and 463 extend along the first direction D1 and connect a plurality of trenches in the memory block 420
  • the track structure is divided into at least two finger storage areas.
  • the storage block 420 includes three finger storage areas.
  • the second gate line spacer includes a plurality of second isolation regions, and the second isolation regions separate the second gate line spacer to form a plurality of second sub-gateline spacers.
  • the second connection structure is located above the second isolation region, and connects adjacent second sub-gate line isolation trenches separated by the second isolation region along the first direction D1.
  • the top of the stack structure of the three-dimensional memory of the present disclosure further includes a top select gate tangent and a top select gate tangent extending along the first direction, the top select gate tangent separating the top select gates.
  • the top select gate tangents 451 , 452 and 453 are respectively located in the three finger storage regions of the memory block 420 , corresponding to the top select gate tangents 351 , 352 and 353 shown in FIG. 3 .
  • the first isolation region includes a first cutout formed in the top select gate layer of the stacked structure, the first cutout having the same depth as the top select gate tangent.
  • the second isolation region includes a second cutout formed in the top select gate layer of the stack, the second cutout having the same depth as the top select gate tangent.
  • the bottom select gate of the memory block is connected to the block select terminal for selecting the memory block.
  • the three-dimensional memory of the present disclosure includes 2 memory blocks, each memory block includes 2 second gate line spacers and 3 finger storage areas, and the area of each finger storage area is equal.
  • the area of the finger storage area refers to the area of the top surface of the finger storage area shown in the top view.
  • the memory block 420 includes two second gate line spacers 462 and 463 , and the two second gate line spacers 462 and 463 together with the gate line spacer 461 serving as the boundary of the memory block 420 will store the The block 420 is divided into 3 finger storage areas, and each finger storage area is of equal size.
  • the gate line spacer 461 serves as the space between the two memory blocks.
  • the gate line spacer can also form a second isolation region thereon.
  • the number of rows of channel structures between the top select gate tangents and the adjacent second gate line spacers of the three-dimensional memory of the present disclosure is the same.
  • the rows here extend in the first direction D1.
  • the top select gate tangent lines 352 and 353 of the three-dimensional memory of this embodiment all include two rows of channel structures between the adjacent second gate line spacers 363 , and the top select gate tangent line is located where the top select gate tangent lines are located.
  • the middle position of the finger storage area makes the channel structure in the finger storage area symmetrically distributed with the top select gate tangent. As shown in FIG.
  • the first gate line spacer 340 , the second gate line spacer and the gate line spacer 361 together divide the channel structure into three parts in each memory block, and each part includes 4 rows of channel structures .
  • the top select gate tangent lines 351, 352, 353 further divide each part into two symmetrical parts, each part including 2 rows of channel structures.
  • a memory block is composed of 3 finger memory areas, and the width of a memory block along the second direction D2 perpendicular to the first direction D1 is 4.5 ⁇ m, then the width of the three-dimensional memory formed by the 2 memory blocks is 4.5 ⁇ m. is 9 microns. In this way, the width of the reinforced three-dimensional memory is widened, and it can be used for a three-dimensional memory structure with more than 200 layers, which can prevent the structure from tilting or collapsing.

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本公开涉及一种三维存储器及其制造方法，该三维存储器包括：衬底，所述衬底上形成有栅极层和介电层交替堆叠的堆叠结构，其中，位于所述堆叠结构底部的栅极层提供底部选择栅极；多个沟道结构，垂直穿过所述堆叠结构并到达所述衬底内；第一栅线隔槽，沿第一方向延伸并将所述多个沟道结构划分成至少两个存储块，所述第一栅线隔槽包括第一隔离区，所述第一隔离区将所述第一栅线隔槽隔断形成多个第一子栅线隔槽；第一连接结构，沿所述第一方向连接被所述第一隔离区隔断的相邻的所述第一子栅线隔槽；以及底部选择栅极切线，沿第一方向延伸并穿过所述第一隔离区中的底部选择栅极，所述底部选择栅极切线将相邻的存储块的底部选择栅极隔开。

Description

三维存储器及其制造方法
相关申请的交叉引用
本申请基于申请号为202011412875.4，申请日为2020年12月04日，申请名称为“三维存储器及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及集成电路的制造领域，尤其涉及一种具有加宽加固结构的三维存储器及其制造方法。
背景技术
为了克服二维存储器件的限制，业界已经研发了具有三维(3D)结构的存储器件，通过将存储器单元三维地布置在衬底之上来提高集成度。三维存储器的层数从32层到128层乃至200层以上逐渐增加，层数越高，三维存储器发生倒塌的风险就越大。当三维存储器中的堆叠结构发生倒塌会导致膜层之间对不准、导电接触部不能准确连接到相应功能层等问题，造成器件性能的下降，严重地会造成三维存储器的损坏。
发明内容
本公开所要解决的技术问题是提供一种具有加宽加固结构的三维存储器及其制造方法。
本公开为解决上述技术问题而采用的技术方案是一种三维存储器，包括：衬底，所述衬底上形成有栅极层和介电层交替堆叠的堆叠结构；多个沟道结构，垂直穿过所述堆叠结构并到达所述衬底内；第一栅线隔槽，沿第一方向延伸并将所述多个沟道结构划分成至少两个存储块，所述第一栅线隔槽包括第一隔离区，所述第一隔离区将所述第一栅线隔槽隔断形成多个第一子栅线隔槽；第一连接结构，沿所述第一方向连接被所述第一隔离区隔断的相邻的所述第一子栅线隔槽。
在本公开的一实施例中，还包括：第二栅线隔槽，位于所述存储块中，所述第二栅线隔槽沿所述第一方向延伸并将所述存储块中的所述多个沟道结构划分成至少两个指存储区，所述第二栅线隔槽包括第二隔离区，所述第二隔离区将所述第二栅线隔槽隔断形成多个第二子栅线隔槽；以及第二连接结构，沿所述第一方向连接被所述第二隔离区隔断的相邻的所述第二子栅线隔槽。
在本公开的一实施例中，所述堆叠结构的顶部包括顶部选择栅极和沿第一方向延伸 的顶部选择栅极切线，所述顶部选择栅极切线将所述顶部选择栅极隔开。
在本公开的一实施例中，所述第一隔离区包括形成在所述堆叠结构的顶部选择栅极层中的第一切口，所述第一切口的深度与所述顶部选择栅极切线的深度相同。
在本公开的一实施例中，所述第二隔离区包括形成在所述堆叠结构的顶部选择栅极层中的第二切口，所述第二切口的深度与所述顶部选择栅极切线的深度相同。
在本公开的一实施例中，位于所述堆叠结构底部的栅极层提供底部选择栅极；所述三维存储器，还包括：底部选择栅极切线，沿第一方向延伸并穿过所述第一隔离区中的底部选择栅极，所述底部选择栅极切线将相邻的存储块的所述底部选择栅极隔开。
在本公开的一实施例中，所述存储块的所述底部选择栅极与块选择端连接，用于选择所述存储块。
本公开为解决上述技术问题还提出一种三维存储器的制造方法，包括：提供衬底、由栅极层和介电层交替堆叠的堆叠结构；所述堆叠结构中包含多个沟道结构，所述沟道结构垂直穿过所述堆叠结构并到达所述衬底内；在所述堆叠结构中形成第一栅线隔槽，所述第一栅线隔槽沿第一方向延伸并将所述多个沟道结构划分成至少两个存储块，所述第一栅线隔槽包括第一隔离区，所述第一隔离区将所述第一栅线隔槽隔断形成多个第一子栅线隔槽；形成第一连接结构，所述第一连接结构沿所述第一方向连接被所述第一隔离区隔断的相邻地所述第一子栅线隔槽。
在本公开的一实施例中，还包括：在所述堆叠结构中形成第二栅线隔槽，所述第二栅线隔槽沿所述第一方向延伸并将所述存储块中的所述多个沟道结构划分成至少两个指存储区，所述第二栅线隔槽包括多个第二隔离区，所述第二隔离区将所述第二栅线隔槽隔断形成多个第二子栅线隔槽；以及形成第二连接结构，所述第二连接结构沿所述第一方向连接被所述第二隔离区隔断的相邻地所述第二子栅线隔槽。
在本公开的一实施例中，还包括：位于所述堆叠结构的顶部的栅极层提供顶部选择栅极，形成沿所述第一方向延伸的顶部选择栅极切线，所述顶部选择栅极切线将所述顶部选择栅极隔开；以及在所述第一隔离区的所述堆叠结构顶部的顶部选择栅极中形成第一切口，所述第一切口的深度与所述顶部选择栅极切线的深度相同。
在本公开的一实施例中，还包括：位于所述堆叠结构的顶部的栅极层提供顶部选择栅极，形成沿所述第一方向延伸的顶部选择栅极切线，所述顶部选择栅极切线将所述顶部选择栅极隔开；以及在所述第二隔离区的所述堆叠结构顶部的顶部选择栅极中形成第二切口，所述第二切口的深度与所述顶部选择栅极切线的深度相同。
在本公开的一实施例中，位于所述堆叠结构底部的栅极层提供底部选择栅极；所述方法还包括：
形成穿过所述第一隔离区中的底部选择栅极的底部选择栅极切线，所述底部选择栅极切线将相邻的存储块的底部选择栅极隔开。
在本公开的一实施例中，还包括：将所述存储块的底部选择栅极与块选择端连接，用于选择所述存储块。
本公开通过在两个存储块交界处用第一栅线隔槽中的第一隔离区和第一连接结构对该交界处进行加固，与仅在一个存储块内部进行加固相比增加了加固宽度，可以有效地防止更多层的三维存储器结构的倒塌或倾斜。同时，本公开的三维存储器在第一栅线隔槽的第一隔离区下方，采用底部选择栅极切线将相邻的存储块的底部选择栅极隔开，从而可以分别控制不同的存储块。
附图说明
为让本公开的上述目的、特征和优点能更明显易懂，以下结合附图对本公开的具体实施方式作详细说明，其中：
图1是一种三维存储器的结构示意图；
图2是本公开一实施例的三维存储器的制造方法的示例性流程图；
图3是本公开一实施例的三维存储器的截面示意图；
图4是本公开一实施例的三维存储器的俯视结构示意图；
图5A是图4中的方框部分的俯视示意图；
图5B是图4中的方框部分的立体结构示意图；
图6A-6H是本公开一实施例的三维存储器的制造方法中形成底部选择栅极切线的过程示意图。
具体实施方式
为让本公开的上述目的、特征和优点能更明显易懂，以下结合附图对本公开的具体实施方式作详细说明。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是本公开还可以采用其它不同于在此描述的其它方式来实施，因此本公开不受下面公开的具体实施例的限制。
如本申请和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、 “一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
在详述本公开实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。例如，如果翻转附图中的器件，则被描述为在其他元件或特征“下方”或“之下”或“下面”的元件的方向将改为在所述其他元件或特征的“上方”。因而，示例性的词语“下方”和“下面”能够包含上和下两个方向。器件也可能具有其他朝向(旋转90度或处于其他方向)，因此应相应地解释此处使用的空间关系描述词。此外，还将理解，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
在本申请的上下文中，所描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
此外，需要说明的是，使用“第一”、“第二”等词语来限定零部件，仅仅是为了便于对相应零部件进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本申请保护范围的限制。
在本文中所使用的术语“三维(3D)存储器件”是指在横向取向的衬底上具有竖直取向的存储单元晶体管串(在文中被称为“存储器串”，例如NAND串)从而存储器串相对于衬底在竖直方向上延伸的半导体器件。如在本文中所使用的，术语“竖直/竖直地”表示标称垂直于衬底的横向表面。
在本文中所使用的属于“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。添加在衬底的顶部上的材料可以被图案化或可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、锗、砷化镓、磷化铟等。或者，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本申请中所使用的术语“层”是指包括具有厚度的区域的材料部分。层可以在整 个下层或上层结构上延伸，或者可以具有小于下层或上层结构范围的范围。此外，层可以是厚度小于连续结构的厚度的均匀或不均匀连续结构的区域。例如，层可以位于连续结构的顶表面和底表面之间或其处的任何一对水平平面之间。层可以水平地、垂直地和/或沿着锥形表面延伸。衬底可以是层，其中可以包括一层或多层，和/或可以在其上、其上方和/或其下方具有一层或多层。层可以包括多个层。例如，互连层可以包括一个或多个导体和触点层(其中形成有触点、互连线和/或通孔)以及一个或多个电介质层。
本申请中使用了流程图用来说明根据本申请的实施例的系统所执行的操作。应当理解的是，前面或下面操作不一定按照顺序来精确地执行。相反，可以按照倒序或同时处理各种步骤。同时，或将其他操作添加到这些过程中，或从这些过程移除某一步或数步操作。
图1是一种三维存储器的结构示意图。该三维存储器包括衬底110和形成在衬底110上的堆叠结构120。该堆叠结构120本来由伪栅极层和介电层交替堆叠而成。在该堆叠结构120中包括多个垂直沟道结构130以及沿平行于字线方向贯穿该堆叠结构120的栅线隔槽141、142，这些垂直沟道结构130贯穿堆叠结构120并到达衬底110中。在形成三维存储器的过程中，通过栅线隔槽141、142去掉堆叠结构120中的伪栅极层，再在伪栅极层所在的位置形成栅极层。图1所示为伪栅极层被去掉之后的状态，在堆叠结构120中与介电层121相邻的伪栅极层已经被去除。随着堆叠结构120中层数的增多，失去伪栅极层的支撑之后，该堆叠结构120发生了倾斜。垂直沟道结构130本来垂直于衬底110的表面，然而在图1中，垂直沟道结构130都向右倾斜。相互平行的栅线隔槽141和142的宽度本来是相等的，由于堆叠结构120的倾斜和变形，导致栅线隔槽141的宽度W1明显大于栅线隔槽142的宽度W2。在后续的工艺中，在栅线隔槽中形成阵列共源极，在形成与阵列共源极相连接的导电接触部时，由于栅线隔槽宽度和位置的改变会导致导电接触部不能有效地接触阵列共源极，从而导致器件发生缺陷甚至失效。
图2是本公开一实施例的三维存储器的制造方法的示例性流程图。图3是本公开一实施例的三维存储器的截面示意图。图4是本公开一实施例的三维存储器的俯视结构示意图。以下结合图2、图3和图4对本公开的三维存储器及其制造方法进行说明。参考图2所示，该实施例的三维存储器的制造方法包括以下步骤：
步骤S210：提供衬底、由栅极层和介电层交替堆叠的堆叠结构，其中，位于堆叠结构底部的栅极层提供底部选择栅极；堆叠结构中包含多个沟道结构，沟道结构垂直穿过堆叠结构并到达衬底内。
图3示出了该实施例的三维存储器的剖视图，结合图4，图3是沿图4中垂直于字线的AA'切线的剖视图。参考图3所示，该三维存储器包括衬底310。该衬底310可以是硅衬底(Si)、锗衬底(Ge)、锗化硅衬底(SiGe)、绝缘体上硅(SOI，Silicon on Insulator)或绝缘体上锗(GOI，Germanium on Insulator)等。在一些实施例中，该衬底310还可以为包括其他元素半导体或化合物半导体的衬底，如GaAs、InP或SiC等。还可以是叠层结构，例如Si/SiGe等。还可以包括其他外延结构，例如绝缘体上锗硅(SGOI)等。在一些实施例中，衬底310可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆等。图3中所示的衬底310可以已经经过了一些必要的处理，例如已形成公共有源区以及已经经过了必要的清洗等。
参考图3所示，在衬底310上方形成有堆叠结构320。堆叠结构320可为第一材料层和第二材料层交替层叠的叠层。第一材料层和第二材料层可以是选自以下材料并且至少包括一种绝缘介质，例如氮化硅、氧化硅、非晶碳、类金刚石无定形碳、氧化锗、氧化铝等及其组合。第一材料层和第二材料层具有不同的刻蚀选择性。例如可以是氮化硅和氧化硅的组合、氧化硅与未掺杂的多晶硅或非晶硅的组合、氧化硅或氮化硅与非晶碳的组合等。堆栈结构的第一材料层和第二材料层的沉积方法可以包括化学气相沉积(CVD、PECVD、LPCVD、HDPCVD)、原子层沉积(ALD)，或物理气相沉积方法如分子束外延(MBE)、热氧化、蒸发、溅射等其各种方法。在本公开的实施例中，第一材料层可为栅极层，第二材料层为介电层。栅极层可以在去除伪栅极层之后形成。作为栅极牺牲层的材料可以是例如氮化硅层。作为栅极层的材料可以是导电材料例如金属钨、钴、铜、镍等，也可以是多晶硅、掺杂硅或其任何组合。作为介电层的材料可以是例如氧化硅、氧化铝、氧化铪、氧化钽等。
在本公开的实施例中，衬底310的材料例如是硅。第一材料层和第二材料层例如是氮化硅和氧化硅的组合。以氮化硅和氧化硅的组合为例，可以采用化学气相沉积(CVD)、原子层沉积(ALD)或其他合适的沉积方法，依次在衬底310上交替沉积氮化硅和氧化硅形成堆叠结构320。
尽管在此描述了初始的半导体结构的示例性构成，但可以理解，一个或多个特征可以从这一半导体结构中被省略、替代或者增加到这一半导体结构中。例如，衬底中可根据需要形成各种阱区。此外，所举例的各层的材料仅仅是示例性的，例如衬底310还可以是其他含硅的衬底，例如SOI(绝缘体上硅)、SiGe、Si:C等。栅极层还可以是其它导电层，例如金属钨，钴，镍等。第二材料层还可以是其它介电材料，例如氧化铝，氧 化铪，氧化钽等。
本公开对堆叠结构320的层数不做限制。如图3所示，该堆叠结构320是由两个子堆叠结构321、322叠加构成的。在其他的实施例中，堆叠结构320可以是由多个子堆叠结构叠加构成。
参考图3所示，在堆叠结构320中，位于底部的栅极层为本公开的三维存储器提供底部选择栅极311。与底部选择栅极311相邻的上下两层均为介电层。
参考图3所示，在该三维存储器的堆叠结构320中形成了多个沟道结构330。多个沟道结构330按照一定的规律排列在三维存储器中。多个沟道结构320垂直穿过堆叠结构320并到达衬底310内。
沟道结构330可以形成在垂直穿过堆叠结构320的沟道孔中，因此沟道结构330可以是圆柱状。沟道结构330可以包括沟道层和存储器层。整体来看，沿沟道结构330的径向从外向内依次设置的是存储器层和沟道层。存储器层可以包括沿沟道结构330的径向从外向内依次设置的阻挡层、电荷捕获层和隧穿层。沟道层内还可设有填充层。填充层可以起到支撑物的作用。填充层的材料可以是氧化硅。填充层可以是实心的，在不影响器件可靠性的前提下也可以是中空的。沟道结构330的形成可以采用一个或多个薄膜沉积工艺来实现，例如ALD、CVD、PVD等或其任意组合。
如图3所示，由于堆叠结构320是由两个子堆叠结构321、322叠加构成的，沟道结构330也是由堆叠结构321中的子沟道结构331和堆叠结构322中的子沟道结构332连通构成，在子沟道结构331和子沟道结构332相连接的位置具有明显的交界区。
步骤S220：在堆叠结构中形成第一栅线隔槽，第一栅线隔槽沿第一方向延伸并将多个沟道结构划分成至少两个存储块，第一栅线隔槽包括第一隔离区，第一隔离区将第一栅线隔槽隔断形成多个第一子栅线隔槽。
三维存储器一般包括若干存储块(Block)以及位于存储块(Block)中的若干指存储区(Finger)，存储块与存储块之间以及指存储区与指存储区之间一般通过沿垂直方向贯穿堆叠结构的栅极隔槽隔开。
在图3所示的堆叠结构320中，第一栅线隔槽340位于该三维存储器顶层的中间部位。该第一栅线隔槽340是一种从三维存储器的顶部向下延伸的切口。第一栅线隔槽340向下切一层表示该第一栅线隔槽340将一层栅极层切断。该第一栅线隔槽340将多个沟道结构330划分成两个存储块，如图3中的虚直线所示，分别是位于第一栅线隔槽340左边的第一存储块350和右边的第二存储块360。
图4所示为图3中所示的三维存储器的顶部，也就是堆叠结构320的顶层的结构。参考图4所示，第一栅线隔槽410可以对应于图3中所示的第一栅线隔槽340。第一栅线隔槽410沿第一方向D1延伸，并将多个沟道结构划分成至少两个存储块。图4中示出了由一个第一栅线隔槽410所划分出的两个存储块，分别是第一存储块420和第二存储块430。
以第一存储块420为例，参考图4所示，其中包括多个沟道结构450，在图4所示的角度，用圆形截面表示柱状的沟道结构450。
图4不用于限制存储块中所包括的沟道结构的数量和分布情况。第一栅线隔槽410位于相邻的两个存储块之间，处于第一存储块420和第二存储块430的交界处。
参考图4所示，该第一栅线隔槽410上包括多个第一隔离区，将第一栅线隔槽410隔断形成了多个第一子栅线隔槽。图4中示出了3个第一隔离区441、442、443，将第一栅线隔槽410隔断形成了4个第一子栅线隔槽411、412、413、414。图3中示出的第一隔离区342对应于图4中的第一隔离区442。
需要说明，第一栅线隔槽410在第一隔离区被隔断，在其他的部分，第一栅线隔槽410是贯穿堆叠结构并到达衬底的沟槽。
图4所示仅为示例，不用于限制第一隔离区的具体数量、相邻的第一隔离区之间的间距、第一子栅线隔槽沿第一方向D1的长度等。
在图4所示的实施例中，第一隔离区为沿第一方向D1延伸的长方形区域。在其他的实施例中，第一隔离区也可以是其他的形状，例如正方形、圆形等。
参考图4所示，该三维存储器还可以沿第一方向D1被划分为核心阵列区401和连接区402。其中，核心阵列区401中可以包括多个作为存储单元的沟道结构，连接区402中可以是具有台阶结构的台阶区。第一栅线隔槽410沿第一方向D1贯穿核心阵列区401和连接区402。如图4所示，核心阵列区401和连接区402中的沟道结构的分布及数量都不同。
步骤S230：形成第一连接结构，该第一连接结构沿第一方向连接被第一隔离区隔断的相邻地第一子栅线隔槽。
图5A是图4中的方框部分的俯视示意图，其中示出了图4中第一栅线隔槽410上的第一隔离区442及其附近的结构。参考图5A所示，第一隔离区442将第一栅线隔槽410隔断，形成了第一子栅线隔槽412、413。在步骤S230，在该第一隔离区442的上方形成第一连接结构510，该第一连接结构510沿第一方向D1将相邻的第一子栅线隔 槽412、413连接起来。通过在相邻的存储块之间设置第一栅线隔槽，并在该第一栅线隔槽中设置第一隔离区和第一连接结构可以起到对三维堆叠结构加固的作用，减少堆叠结构因应力变形的情况。
图5B是图4中的方框部分的立体结构示意图。参考图5B所示，第一方向D1与第一栅线隔槽410的延伸方向相同，第一子栅线隔槽412和第一子栅线隔槽413之间是第一隔离区442。该第一隔离区442包括堆叠结构522和位于该堆叠结构522上方的第一切口521，在第一切口521中具有填充材料。该堆叠结构522是图3中的堆叠结构320的一部分，堆叠结构522和图3中的堆叠结构320中处于同一层的栅极层相互连通。第一隔离区442将第一栅线隔槽410隔断，分为第一子栅线隔槽412和第一子栅线隔槽413。在第一子栅线隔槽412、413中具有填充材料。第一连接结构510形成在第一隔离区442上方，将第一子栅线隔槽412和第一子栅线隔槽413连接起来。
在一些实施例中，第一栅线隔槽410中填充多晶硅，可以作为三维存储器的源极结构。第一切口521中包括氧化硅、氮化硅和/或氮氧化硅中的一种或多种。第一连接结构510包括导电材料，例如钨。
经过填充的第一切口521和堆叠结构320一起在第一栅线隔槽410中起到支撑作用。填充有多晶硅的第一栅线隔槽410作为三维存储器的源极结构，填充有多晶硅的第一子栅线隔槽412、413可以分别作为三维存储器的源极接触部。相邻的第一子栅线隔槽412、413通过第一连接结构510相接触并且导电地连接在一起。根据这样的结构，可以使源极电压通过第一连接结构510被施加在源极接触部上，减少或消除对接触插塞的使用。
在一些实施例中，第一隔离区442与被其隔断的第一子栅线隔槽412、413都绝缘。参考图5B所示，堆叠结构522与第一子栅线隔槽412、413接触的部分还包括间隔体层523。间隔体层523可以提供在堆叠结构522与邻近的作为源极接触部的第一子栅线隔槽412、413之间的进一步的绝缘。
步骤S240：形成穿过在第一隔离区中的底部选择栅极的底部选择栅极切线，该底部选择栅极切线将相邻的存储块的底部选择栅极隔开。
参考图3所示，底部选择栅极切线341位于第一存储块350和第二存储块360之间，从衬底上方向上延伸，穿过底部选择栅极311，从而使不同存储块350、360的底部选择栅极311隔开。结合图4所示，尽管图4中未示出底部选择栅极切线341，可以理解，该底部选择栅极切线341位于第一栅线隔槽410的底部，与该第一栅线隔槽410平行。再结合图5B所示，位于堆叠结构522底部的栅极层是底部选择栅极531，底部选择栅 极切线530穿过该底部选择栅极531将其切断。
在图3所示的实施例中，衬底310上方的第一个栅极层作为底部选择栅极311。在其他的实施例中，可以将衬底310上方的若干栅极层作为底部选择栅极311，则底部选择栅极切线341穿过该若干层底部选择栅极311。
在一些实施例中，将每个存储块底部的底部选择栅极与块选择端连接，可用于选择该存储块。电压可以施加块选择端上，以通过与之相连的底部选择栅极来选择相应的存储块。
经过步骤S210-S240所形成的三维存储器中至少包括两个存储块，在两个存储块交界处用第一栅线隔槽、第一隔离区和第一连接结构对该交界处进行加固，与仅在一个存储块内部进行加固相比增加了加固宽度，可以有效地防止更多层的三维存储器结构的倒塌或倾斜。根据上述方法形成的三维存储器中包括多个存储块，通过底部选择栅极切线将相邻的存储块的底部选择栅极隔开，从而可以分别控制不同的存储块。
在一些实施例中，本公开的制造方法还包括：
步骤S250：在堆叠结构的中形成第二栅线隔槽，第二栅线隔槽沿第一方向延伸并将存储块中的多个沟道结构划分成至少两个指存储区，第二栅线隔槽包括多个第二隔离区，第二隔离区将第二栅线隔槽隔断形成多个第二子栅线隔槽。
步骤S260：形成第二连接结构，第二连接结构沿第一方向连接被第二隔离区隔断的相邻第二子栅线隔槽。
参考图4所示，以第一存储块420为例，在该第一存储块420中形成有2个第二栅线隔槽462、463，该2个第二栅线隔槽462、463将第一存储块420中的多个沟道结构划分成3个指存储区，图4中标示出了一个指存储区421。在第一存储块420的边界处还包括一个栅线隔槽461。
参考图4所示，第二栅线隔槽462、463上都包括3个第二隔离区，其中标示出了第二栅线隔槽462上的第二隔离区444、445、446和第二栅线隔槽463上的第二隔离区447。图3中标示出了AA'线所切开的第二栅线隔槽462上的第二隔离区445和第二栅线隔槽463上的第二隔离区447。
第二隔离区与第一隔离区的结构相同，前文关于第一隔离区的说明可以用于说明第二隔离区。
图4中所标示的指存储区421对应于图3中所标示的指存储区371。结合图3和图4，每个指存储区中所包括的沟道结构数量可以是相同的。
参考图4所示，在第二栅线隔槽462、463上形成第二隔离区和第二连接结构可以起到在存储块内部加固三维存储器结构的效果。在栅线隔槽461上没有形成第二连接结构。
第二连接结构与第一连接结构类似，所不同的是第二连接结构位于第二栅线隔槽中的第二隔离区中。
根据上述的步骤，在每个存储块中的第二栅线隔槽中形成了第二隔离区和第二连接结构，可以在存储块内部进行结构的加固。结合第一连接结构，可以同时在每个存储块内部和多个存储块之间都形成加固结构，可以满足更多层的三维存储器的结构稳定性要求。
在一些实施例中，本公开的三维存储器的制造方法在形成了第一栅线隔槽和第一隔离区之后，还包括：
步骤S262：位于堆叠结构的顶部的栅极层提供顶部选择栅极，形成沿第一方向延伸的顶部选择栅极切线，该顶部选择栅极切线将所述顶部选择栅极隔开；
步骤S264：在第一隔离区的堆叠结构顶部的顶部选择栅极中形成第一切口，第一切口的深度与顶部选择栅极切线的深度相同。
参考图3所示，位于堆叠结构320顶部的栅极层作为该三维存储器的顶部选择栅极312，在步骤S262形成了3个顶部选择栅极切线351、352、353，对应于图4中所示的顶部选择栅极切线451、452、453。结合图3和图4所示，顶部选择栅极切线位于由第二栅线隔槽隔开的指存储区中。
本公开对堆叠结构中作为顶部选择栅极的栅极层的层数不做限制。如图3所示，其中以一层栅极层作为顶部选择栅极312。在其他的实施例中，可以采用堆叠结构顶部的2-6层栅极层作为顶部选择栅极，则顶部选择栅极切线切断该2-6层栅极层。
参考图5B所示，第一切口521形成在第一隔离区442的堆叠结构的顶部选择栅极中。
在一些实施例中，在同一工艺步骤中形成顶部选择栅极切线和第一切口，二者的深度相同。
在一些实施例中，本公开的三维存储器的制造方法在形成了第二栅线隔槽和第二隔离区之后，还包括：
步骤S266：位于堆叠结构的顶部的栅极层提供顶部选择栅极，形成沿第一方向延伸的顶部选择栅极切线，顶部选择栅极切线将顶部选择栅极隔开；以及
步骤S268：在第二隔离区的堆叠结构顶部的顶部选择栅极中形成第二切口，第二切口的深度与顶部选择栅极切线的深度相同。
这些实施例包括在存储块内部的第二栅线隔槽，在第二隔离区中形成第二切口的方法与在第一隔离区中形成第一切口的方法相同。因此，关于第一切口的说明内容可以用于说明第二切口。第二切口的结构与第一切口521类似，可以填充相同的材料。图5B可以用于同时表示第二切口。
在一些实施例中，在同一工艺步骤中形成顶部选择栅极切线和第二切口，二者的深度相同。
在一些实施例中，在同一工艺步骤中形成顶部选择栅极切线、第一切口和第二切口，三者的深度相同。
图6A-6H是本公开一实施例的三维存储器的制造方法中形成底部选择栅极切线的过程示意图。
参考图6A所示，提供衬底610，并在衬底610上形成一层高温氧化物(HTO，High Temperature Oxide)层621。
参考图6B所示，在该高温氧化物层621上方沉积作为底部选择栅极的栅极层631。在栅极层631的上方还形成了介电层622，以及栅极层632、介电层623。高温氧化物层621、栅极层631、介电层622、栅极层632、介电层623依次在衬底610上方形成了堆叠结构。可以理解，栅极层632可以作为刻蚀阻挡层，起到保护栅极层631的作用。
参考图6C所示，在位于顶部的介电层623的上方形成具有图案641的光刻胶层640。该图案641的位置对应于需要形成顶部选择栅极切线的位置。
参考图6D所示，根据光刻胶层640对衬底上方的堆叠结构进行刻蚀，形成图6D中所示的切口642。经过图6D所示的步骤，栅极层631被切断。
参考图6E所示，在图6D所示的结构上沉积介电材料624，使切口642被填满。本步骤可以采用原子层沉积法来执行。
参考图6F所示，将图6E所示的半导体结构的顶部磨平，使栅极层632的上表面暴露。本步骤可以采用化学机械磨平方法。
参考图6G所示，采用湿法刻蚀在栅极层632中形成切口643，该切口643的深度与该栅极层632的厚度相同，使位于栅极层632下方的介电层622在该切口643处暴露出来。
参考图6H所示，去除栅极层632。
经过图6A-6H之后，在底部选择栅极631形成了底部选择栅极切口643。可以继续在图6H所示的半导体结构上方形成三维存储器的堆叠结构。
根据本公开的三维存储器的制造方法，可以同时对两个及以上的存储块进行加固，增加了加固的宽度；在底部选择栅极中形成底部选择栅极切口，可以对不同的存储块进行选择。
本公开的三维存储器的结构可以参考图3和图4。本公开的三维存储器可以由前文所述的制造方法制造而成，因此图2以及相关的说明内容都可以用于说明本公开实施例的三维存储器。
参考图3所示，该实施例的三维存储器包括衬底310、多个沟道结构330、第一栅线隔槽340、第一连接结构和底部选择栅极切线341。其中，衬底310上形成有栅极层和介电层交替堆叠的堆叠结构320，其中，位于堆叠结构320底部的栅极层提供底部选择栅极311。多个沟道结构330垂直穿过堆叠结构320并到达衬底310内。底部选择栅极切线341将相邻的存储块的底部选择栅极311隔开。
参考图4所示，第一栅线隔槽410沿第一方向D1延伸并将多个沟道结构划分成至少两个存储块420、430，第一栅线隔槽410包括第一隔离区441、442、443，第一隔离区441、442、443将第一栅线隔槽410隔断形成多个第一子栅线隔槽411、412、413、414。
参考图4、5A和5B所示，第一连接结构510位于第一隔离区442上方，沿第一方向D1连接被第一隔离区442隔断的相邻地第一子栅线隔槽412和413。
在一些实施例中，本公开的三维存储器还包括第二栅线隔槽和第二连接结构。参考图4所示，第二栅线隔槽461、462、463位于存储块420中，第二栅线隔槽461、462、463沿第一方向D1延伸并将存储块420中的多个沟道结构划分成至少两个指存储区。在图4所示的实施例中，存储块420中包括3个指存储区。与第一栅线隔槽类似地，第二栅线隔槽中包括多个第二隔离区，第二隔离区将第二栅线隔槽隔断形成多个第二子栅线隔槽。第二连接结构位于第二隔离区上方，沿第一方向D1连接被第二隔离区隔断的相邻第二子栅线隔槽。
在一些实施例中，本公开的三维存储器的堆叠结构的顶部还包括顶部选择栅极切线和沿第一方向延伸的顶部选择栅极切线，该顶部选择栅极切线将顶部选择栅极隔开。
参考图4所示，顶部选择栅极切线451、452、453分别位于存储块420的三个指存储区中，对应于图3中所示的顶部选择栅极切线351、352、353。
在一些实施例中，第一隔离区包括形成在堆叠结构的顶部选择栅极层中的第一切口，第一切口的深度与顶部选择栅极切线的深度相同。
在一些实施例中，第二隔离区包括形成在堆叠结构的顶部选择栅极层中的第二切口，第二切口的深度与顶部选择栅极切线的深度相同。
在一些实施例中，存储块的底部选择栅极与块选择端连接，用于选择存储块。
优选地，本公开的三维存储器中包括2个存储块，每个存储块中包括2个第二栅线隔槽和3个指存储区，并且每一个指存储区的面积相等。参考图4所示，指存储区的面积指在俯视图中所示的该指存储区的顶面的面积。参考图4所示，存储块420中包括2个第二栅线隔槽462、463，该2个第二栅线隔槽462、463和作为存储块420边界的栅线隔槽461一起将存储块420分为了3个指存储区，并且每个指存储区的面积都相等。
在其他的实施例中，当该三维存储器包括大于2个存储块时，例如在图4中所示的存储块420上方再增加一个存储块，则栅线隔槽461作为两个存储块之间的栅线隔槽，也可以在其上形成第二隔离区。
在一些实施例中，本公开的三维存储器的顶部选择栅极切线与相邻的第二栅线隔槽之间的沟道结构的行数相同。这里的行沿第一方向D1延伸。参考图3所示，该实施例的三维存储器的顶部选择栅极切线352、353与相邻的第二栅线隔槽363之间都包括2行沟道结构，顶部选择栅极切线位于其所在的指存储区的中间位置，使该指存储区中的沟道结构以该顶部选择栅极切线为对称分布。如图3所示，第一栅线隔槽340、第二栅线隔槽以及栅线隔槽361一起在每个存储块中将沟道结构分成了三部分，每部分包括4行沟道结构。顶部选择栅极切线351、352、353再将每部分分成对称的两部分，每部分包括2行沟道结构。
图3和图4并不用于限制沟道结构的具体数量。参考图4所示，由3个指存储区构成一个存储块，一个存储块沿垂直于第一方向D1的第二方向D2的宽度是4.5微米，则由2个存储块形成的三维存储器的宽度是9微米。这样经过加固的三维存储器的宽度变宽，用于大于200层的三维存储器结构，可以防止结构的倾斜或倒塌。
虽然本公开已参照当前的具体实施例来描述，但是本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来说明本公开，在没有脱离本公开精神的情况下还可作出各种等效的变化或替换，因此，只要在本公开的实质精神范围内对上述实施例的变化、变型都将落在本申请的权利要求书的范围内。

Claims (13)

  1. 一种三维存储器，包括：
    衬底，所述衬底上形成有栅极层和介电层交替堆叠的堆叠结构；
    多个沟道结构，垂直穿过所述堆叠结构并到达所述衬底内；
    第一栅线隔槽，沿第一方向延伸并将所述多个沟道结构划分成至少两个存储块，所述第一栅线隔槽包括第一隔离区，所述第一隔离区将所述第一栅线隔槽隔断形成多个第一子栅线隔槽；
    第一连接结构，沿所述第一方向连接被所述第一隔离区隔断的相邻的所述第一子栅线隔槽。
  2. 如权利要求1所述的三维存储器，还包括：
    第二栅线隔槽，位于所述存储块中，所述第二栅线隔槽沿所述第一方向延伸并将所述存储块中的所述多个沟道结构划分成至少两个指存储区，所述第二栅线隔槽包括第二隔离区，所述第二隔离区将所述第二栅线隔槽隔断形成多个第二子栅线隔槽；以及
    第二连接结构，沿所述第一方向连接被所述第二隔离区隔断的相邻的所述第二子栅线隔槽。
  3. 如权利要求1所述的三维存储器，其中，所述堆叠结构的顶部包括顶部选择栅极和沿第一方向延伸的顶部选择栅极切线，所述顶部选择栅极切线将所述顶部选择栅极隔开。
  4. 如权利要求3所述的三维存储器，其中，所述第一隔离区包括形成在所述堆叠结构的顶部选择栅极层中的第一切口，所述第一切口的深度与所述顶部选择栅极切线的深度相同。
  5. 如权利要求4所述的三维存储器，其中，所述第二隔离区包括形成在所述堆叠结构的顶部选择栅极层中的第二切口，所述第二切口的深度与所述顶部选择栅极切线的深度相同。
  6. 如权利要求1所述的三维存储器，其中，位于所述堆叠结构底部的栅极层提供底部选择栅极；所述三维存储器，还包括：
    底部选择栅极切线，沿第一方向延伸并穿过所述第一隔离区中的底部选择栅极，所述底部选择栅极切线将相邻的存储块的所述底部选择栅极隔开。
  7. 如权利要求6所述的三维存储器，其中，所述存储块的所述底部选择栅极与块选择端连接，用于选择所述存储块。
  8. 一种三维存储器的制造方法，包括：
    提供衬底、由栅极层和介电层交替堆叠的堆叠结构；所述堆叠结构中包含多个沟道结构，所述沟道结构垂直穿过所述堆叠结构并到达所述衬底内；
    在所述堆叠结构中形成第一栅线隔槽，所述第一栅线隔槽沿第一方向延伸并将所述多个沟道结构划分成至少两个存储块，所述第一栅线隔槽包括第一隔离区，所述第一隔离区将所述第一栅线隔槽隔断形成多个第一子栅线隔槽；
    形成第一连接结构，所述第一连接结构沿所述第一方向连接被所述第一隔离区隔断的相邻地所述第一子栅线隔槽。
  9. 如权利要求8所述的制造方法，还包括：
    在所述堆叠结构中形成第二栅线隔槽，所述第二栅线隔槽沿所述第一方向延伸并将所述存储块中的所述多个沟道结构划分成至少两个指存储区，所述第二栅线隔槽包括多个第二隔离区，所述第二隔离区将所述第二栅线隔槽隔断形成多个第二子栅线隔槽；以及
    形成第二连接结构，所述第二连接结构沿所述第一方向连接被所述第二隔离区隔断的相邻地所述第二子栅线隔槽。
  10. 如权利要求8所述的制造方法，还包括：
    位于所述堆叠结构的顶部的栅极层提供顶部选择栅极，形成沿所述第一方向延伸的顶部选择栅极切线，所述顶部选择栅极切线将所述顶部选择栅极隔开；以及
    在所述第一隔离区的所述堆叠结构顶部的顶部选择栅极中形成第一切口，所述第一切口的深度与所述顶部选择栅极切线的深度相同。
  11. 如权利要求10所述的制造方法，还包括：
    位于所述堆叠结构的顶部的栅极层提供顶部选择栅极，形成沿所述第一方向延伸的顶部选择栅极切线，所述顶部选择栅极切线将所述顶部选择栅极隔开；以及
    在所述第二隔离区的所述堆叠结构顶部的顶部选择栅极中形成第二切口，所述第二切口的深度与所述顶部选择栅极切线的深度相同。
  12. 如权利要求8所述的制造方法，其中，位于所述堆叠结构底部的栅极层提供底部选择栅极；所述方法还包括：
    形成穿过所述第一隔离区中的底部选择栅极的底部选择栅极切线，所述底部选择栅极切线将相邻的存储块的底部选择栅极隔开。
  13. 如权利要求12所述的制造方法，其中，还包括：将所述存储块的底部选择栅极与块选择端连接，用于选择所述存储块。
PCT/CN2021/129763 2020-12-04 2021-11-10 三维存储器及其制造方法 WO2022116785A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202180008042.8A CN116472788A (zh) 2020-12-04 2021-11-10 三维存储器及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011412875.4A CN112530966B (zh) 2020-12-04 2020-12-04 三维存储器及其制造方法
CN202011412875.4 2020-12-04

Publications (1)

Publication Number Publication Date
WO2022116785A1 true WO2022116785A1 (zh) 2022-06-09

Family

ID=74997751

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/129763 WO2022116785A1 (zh) 2020-12-04 2021-11-10 三维存储器及其制造方法

Country Status (2)

Country Link
CN (2) CN112530966B (zh)
WO (1) WO2022116785A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530966B (zh) * 2020-12-04 2021-07-16 长江存储科技有限责任公司 三维存储器及其制造方法
CN113078164B (zh) * 2021-03-26 2022-04-15 长江存储科技有限责任公司 一种半导体器件

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107810554A (zh) * 2015-08-11 2018-03-16 桑迪士克科技有限责任公司 含有存储器区块电桥的三维存储器器件
US20180366482A1 (en) * 2017-06-20 2018-12-20 Sandisk Technologies Llc Three-dimensional memory device including vertically offset drain select level layers and method of making thereof
CN110622309A (zh) * 2019-08-13 2019-12-27 长江存储科技有限责任公司 具有源极结构的三维存储设备和用于形成其的方法
CN111052381A (zh) * 2019-11-28 2020-04-21 长江存储科技有限责任公司 三维存储器件及其制作方法
CN111668228A (zh) * 2020-06-03 2020-09-15 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN111819691A (zh) * 2020-05-25 2020-10-23 长江存储科技有限责任公司 存储器件及其形成方法
CN112289799A (zh) * 2020-10-29 2021-01-29 长江存储科技有限责任公司 三维存储器及其制造方法
CN112530966A (zh) * 2020-12-04 2021-03-19 长江存储科技有限责任公司 三维存储器及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101175885B1 (ko) * 2011-02-17 2012-08-21 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 제조 방법
US10580791B1 (en) * 2018-08-21 2020-03-03 Micron Technology, Inc. Semiconductor device structures, semiconductor devices, and electronic systems
SG11202104885PA (en) * 2018-12-07 2021-06-29 Yangtze Memory Technologies Co Ltd Novel 3d nand memory device and method of forming the same
CN110211964B (zh) * 2019-06-17 2022-03-18 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN110914989B (zh) * 2019-06-17 2021-09-14 长江存储科技有限责任公司 不具有栅极线缝隙的三维存储器件及用于形成其的方法
CN110176461B (zh) * 2019-06-17 2020-04-10 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN111146209A (zh) * 2019-12-25 2020-05-12 长江存储科技有限责任公司 3d存储器件及其制造方法
CN111211134B (zh) * 2020-01-14 2023-02-03 长江存储科技有限责任公司 一种3d存储器及其制造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107810554A (zh) * 2015-08-11 2018-03-16 桑迪士克科技有限责任公司 含有存储器区块电桥的三维存储器器件
US20180366482A1 (en) * 2017-06-20 2018-12-20 Sandisk Technologies Llc Three-dimensional memory device including vertically offset drain select level layers and method of making thereof
CN110622309A (zh) * 2019-08-13 2019-12-27 长江存储科技有限责任公司 具有源极结构的三维存储设备和用于形成其的方法
CN111052381A (zh) * 2019-11-28 2020-04-21 长江存储科技有限责任公司 三维存储器件及其制作方法
CN111819691A (zh) * 2020-05-25 2020-10-23 长江存储科技有限责任公司 存储器件及其形成方法
CN111668228A (zh) * 2020-06-03 2020-09-15 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN112289799A (zh) * 2020-10-29 2021-01-29 长江存储科技有限责任公司 三维存储器及其制造方法
CN112530966A (zh) * 2020-12-04 2021-03-19 长江存储科技有限责任公司 三维存储器及其制造方法

Also Published As

Publication number Publication date
CN116472788A (zh) 2023-07-21
CN112530966A (zh) 2021-03-19
CN112530966B (zh) 2021-07-16

Similar Documents

Publication Publication Date Title
US11289508B2 (en) Three-dimensional memory device and method for forming the same
US10269620B2 (en) Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
US11600636B2 (en) Stacked connections in 3D memory and methods of making the same
CN108565266B (zh) 形成三维存储器的方法以及三维存储器
TWI757626B (zh) 三維記憶體元件及其形成方法
CN106024794B (zh) 半导体器件及其制造方法
US10991717B2 (en) Vertical memory devices
JP2022533896A (ja) バックサイドソースコンタクトを備える３次元メモリデバイス
JP2023514283A (ja) バックサイドソースコンタクトを備える３次元メモリデバイスを形成するための方法
TWI715423B (zh) 具有位於記憶體串中的口袋結構的立體記憶體元件及其形成方法
JP7279202B2 (ja) ゲート線スリットがない３次元メモリデバイスおよびそれを形成するための方法
WO2022116785A1 (zh) 三维存储器及其制造方法
CN110233152B (zh) 一种形成三维存储器的方法及三维存储器
WO2023216396A1 (zh) 半导体结构及其形成方法
TWI772958B (zh) 立體記憶體元件及其製作方法
KR20190123880A (ko) 수직형 메모리
US20230018927A1 (en) Three-dimensional storage and method for manufacturing same
CN112909005B (zh) 一种三维存储器及其制备方法
CN114388519A (zh) 三维存储器及其制备方法
TWI776230B (zh) 兩步l形選擇性磊晶生長
WO2024027333A1 (zh) 半导体结构及其形成方法
CN112331672B (zh) 三维存储器及其制造方法
CN113571523A (zh) 三维存储器及其制备方法
CN112289799A (zh) 三维存储器及其制造方法
US20230140992A1 (en) Three-dimensional memory and manufacturing method thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180008042.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21899819

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21899819

Country of ref document: EP

Kind code of ref document: A1