WO2022198950A1 - 半导体结构的制备方法和半导体结构 - Google Patents

半导体结构的制备方法和半导体结构 Download PDF

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WO2022198950A1
WO2022198950A1 PCT/CN2021/120339 CN2021120339W WO2022198950A1 WO 2022198950 A1 WO2022198950 A1 WO 2022198950A1 CN 2021120339 W CN2021120339 W CN 2021120339W WO 2022198950 A1 WO2022198950 A1 WO 2022198950A1
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layer
dielectric layer
bit line
trench
conductive
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PCT/CN2021/120339
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English (en)
French (fr)
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卢经文
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长鑫存储技术有限公司
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Priority claimed from CN202110302133.4A external-priority patent/CN115116962B/zh
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/651,089 priority Critical patent/US20220302128A1/en
Publication of WO2022198950A1 publication Critical patent/WO2022198950A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the technical field of semiconductor preparation, and in particular, to a preparation method of a semiconductor structure and a semiconductor structure.
  • Dynamic random access memory is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices.
  • Dynamic random access memory includes a plurality of repeated memory cells, each memory cell usually includes a capacitor and a transistor, the gate of the transistor is connected to the word line (Word line, referred to as WL), the drain is connected to the bit line (Bit line, referred to as WL) It is connected to BL), and the source is connected to the capacitor.
  • the voltage signal on the bit line can read the data information stored in the capacitor, or write the data information into the capacitor for storage.
  • the current bit lines are prepared by etching. Parts between adjacent bit lines in the composite deposition layer are removed by etching, and the remaining composite deposition layer forms the bit lines.
  • the surface structure of the bit line is easily damaged, resulting in tilt or collapse of the bit line, which reduces the structural stability and signal transmission performance of the bit line, and affects the storage performance of the semiconductor memory at the same time.
  • the present application provides a method for preparing a semiconductor structure, comprising:
  • the substrate includes an active region and an isolation region
  • bit line structure on the first conductive layer, the bit line structure covers the surface of the first conductive layer, and the top surface of the bit line structure is lower than the top surface of the first dielectric layer;
  • the third dielectric layer fills the first trench, and the top surface of the third dielectric layer is flush with the top surface of the second dielectric layer;
  • the fourth dielectric layer and part of the first dielectric layer covering the bottom of the second trench are removed to form a third trench that exposes the substrate.
  • the present application also provides a semiconductor structure, comprising:
  • the substrate includes an active region and an isolation region;
  • the first conductive layer is located on the substrate, and the top surface of the first conductive layer is concave;
  • the bit line structure includes a barrier layer and a second conductive layer stacked on the first conductive layer; the bit line structure is electrically connected to the active region through the first conductive layer;
  • bit line protection layer covers at least the top surface and sidewalls of the bit line structure, and a third trench is arranged between adjacent bit line protection layers.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art
  • FIG. 2 is a schematic structural diagram of a bit line of a semiconductor structure in the related art
  • FIG. 3 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of forming a first trench in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 5 is a schematic flowchart of forming a first conductive layer of a method for preparing a semiconductor structure provided by an embodiment of the present application
  • FIG. 6 is a schematic flowchart of forming a bit line structure in a method for preparing a semiconductor structure provided by an embodiment of the present application
  • FIG. 7 is a schematic structural diagram of a substrate, a first dielectric layer and a second dielectric layer of a semiconductor structure provided by an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of forming a mask layer on the top surface of the second dielectric layer of the semiconductor structure provided by the embodiment of the present application;
  • FIG. 9 is a schematic structural diagram of forming a first trench of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a top view of forming a first trench of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of forming a first conductive material layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of forming a first conductive layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 13 is a top view of forming a first conductive layer of the semiconductor structure provided by the embodiment of the application;
  • FIG. 14 is a schematic structural diagram of forming a recessed first conductive layer of a semiconductor structure provided by an embodiment of the present application.
  • 15 is a schematic structural diagram of forming a barrier material layer and a second conductive layer material layer of a semiconductor structure provided in an embodiment of the present application;
  • 16 is a schematic structural diagram of forming a barrier layer and a second conductive layer of a semiconductor structure provided by an embodiment of the present application;
  • FIG. 17 is a schematic structural diagram of forming a third dielectric layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of forming a second trench of a semiconductor structure provided by an embodiment of the present application.
  • 19 is a schematic structural diagram of forming a fourth dielectric layer of the semiconductor structure provided by the embodiment of the application.
  • FIG. 20 is a schematic structural diagram of forming a third trench of a semiconductor structure provided by an embodiment of the present application.
  • 21 is a schematic structural diagram of forming a bit line protection layer of a semiconductor structure provided by an embodiment of the present application.
  • 22 is a schematic structural diagram of forming an isolation layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 23 is a schematic partial structure diagram of part I in FIG. 22 according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art.
  • FIG. 2 is a schematic structural diagram of a bit line of a semiconductor structure in the related art. Referring to FIG. 1 and FIG. 2 , the current bit lines are prepared by etching. First, a substrate 1 having an active region 2 and an isolation region 3 can be formed, a titanium nitride layer 4 and a metal tungsten layer 5 are sequentially formed on the substrate 1 , and a silicon nitride layer is formed on the top surface of the metal tungsten layer 5 6.
  • a bit line mask layer 7 is formed on the top surface of the silicon nitride layer 6, and the titanium nitride layer 4 and the metal tungsten layer 5 are etched using the bit line mask layer 7, thereby forming bit lines.
  • the etching depth cannot be precisely controlled, which leads to the phenomenon of structural damage, such as necking, easily occurring in the formed bit line.
  • the structure of the titanium nitride layer 4 close to the substrate 1 is damaged by excessive etching, and here Defective regions A are formed.
  • the metal tungsten layer 5 on the side far from the substrate 1 in the bit line b is first affected by the etching medium, so that over-etching occurs, resulting in uneven structure size of the bit line b, and a defect region can also be formed here.
  • the above-mentioned bit line structures all lead to the collapse of the bit line, which affects the structural stability of the bit line, and causes signal transmission in the bit line to be blocked, which affects the storage performance of the DRAM device.
  • the method for preparing a semiconductor structure and the semiconductor structure provided by the embodiments of the present application, by forming a first dielectric layer and a second dielectric layer on a substrate, and forming a first trench, and using the first trench to form a first Conductive layer and bit line structure.
  • the top surface of the first conductive layer is recessed, and the first conductive layer is used as the setting base of the bit line structure.
  • the bit line structure is formed by depositing a barrier layer and a second conductive layer on the first conductive layer, which can effectively avoid the problem of inclination or collapse caused by damage to the bit line structure.
  • the bit line protection layer By forming the bit line protection layer on the top surface and sidewalls of the bit line structure, the protection effect on the bit line structure is improved.
  • the isolation layer on the sidewall of the bit line protection layer, the influence of external oxygen elements or impurities on the bit line structure can be effectively avoided, the stability of the bit line structure and signal transmission can be improved, and the storage of the semiconductor structure can be optimized. performance.
  • FIG. 3 is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of forming a first trench in a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of forming a first conductive layer of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic flow chart of forming a bit line structure in a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a substrate, a first dielectric layer, and a second dielectric layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of forming a mask layer on the top surface of the second dielectric layer of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of forming a first trench of a semiconductor structure according to an embodiment of the present application.
  • FIG. 10 is a top view of forming a first trench in a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of forming a first conductive material layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of forming a first conductive layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 13 is a top view of forming a first conductive layer of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of forming a recessed first conductive layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of forming a barrier material layer and a second conductive layer material layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of forming a barrier layer and a second conductive layer of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of forming a third dielectric layer of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of forming a second trench of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of forming a fourth dielectric layer of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of forming a third trench of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of forming a bit line protection layer of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of forming an isolation layer of a semiconductor structure according to an embodiment of the present application.
  • FIG. 23 is a schematic partial structure diagram of part I in FIG. 22 according to an embodiment of the present application.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including:
  • S1 Provide a substrate, the substrate includes an active region and an isolation region.
  • the material of the substrate 10 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon-on-insulator (SOI for short), etc., or known to those skilled in the art Other materials, the substrate 10 can provide a support base for the structural layers on the substrate 10 .
  • the substrate 10 is a Si substrate.
  • the substrate 10 may have a semiconductor layer therein, and the semiconductor layer forms an active region 11 of the substrate 10 , the active region 11 includes a source region and a drain region, and an isolation region 12 is formed between the source region and the drain region .
  • a Shallow Trench Isolation (STI for short) may be disposed in the isolation region 12 .
  • first dielectric layer 20 and the second dielectric layer 30 can be prepared by chemical deposition, the first dielectric layer 20 can be a silicon nitride layer, and the second dielectric layer 30 can be a silicon oxide layer.
  • the structures of the substrate 10 , the first dielectric layer 20 and the second dielectric layer 30 can be referred to as shown in FIG. 7 , and the active regions 11 and the isolation regions 12 can be staggered and spaced in the substrate 10 .
  • S3 removing part of the first dielectric layer and part of the second dielectric layer to form a first trench. It should be noted that, in this step 3, it may specifically include:
  • the mask layer 102 may be a photoresist layer, and a position where the bit line structure 50 needs to be formed is reserved on the mask layer 102, thereby forming the mask opening 102a.
  • the structure of the mask layer 102 may be as shown in FIG. 8 .
  • first dielectric layer 20 and the second dielectric layer 30 at the mask opening 102a may be removed by an etching process to form the first trench 101 .
  • the bit line structure 50 formed in the first trench 101 can be electrically connected to the source region or the drain region in the active region 11 , and the structure of the first trench 101 formed can be referred to as shown in FIG. 9 .
  • the semiconductor structure may include a word line 105 structure disposed in the substrate 10 , the word line 105 structure may be disposed in the form of a buried word line 105 , and a plurality of word lines 105 are spaced along the first direction set up.
  • the plurality of first trenches 101 on the substrate 10 are arranged at intervals along the second direction, the second direction intersects with the first direction or are perpendicular to each other, and the first trenches 101 are used to form the bit line structure 50 .
  • S4 a first conductive layer is formed in the first trench, and the top surface of the first conductive layer is concave.
  • this step 4 it can specifically include:
  • the first conductive material layer 41 may be formed by deposition, and the structure may be shown in FIG. 11 .
  • the gap 42 is inevitably generated due to structural defects, in order to reduce the influence of the gap 42 on the first conductive material layer 41 .
  • the slit opening of the slit 42 can be exposed, and the subsequent recessed structure of the first conductive layer 40 can be formed by using the slit 42 .
  • the remaining first conductive material layer 41 forms a first conductive layer 40 .
  • the material for forming the first conductive material layer 41 is polysilicon doped with phosphorus element. Based on the high solid solubility between phosphorus element and silicon, doping with phosphorus element can increase the doping amount, which is helpful to improve the Conductivity of polysilicon.
  • the step of forming the first conductive material layer 41 includes: at 480-520° C., feeding a mixed gas of SiH 4 and PH 3 into the first trench 101 , and using a low-pressure chemical deposition method The first conductive material layer 41 is prepared.
  • the low pressure chemical deposition method can improve the structure uniformity during the deposition process of the first conductive material layer 41 and reduce the structural defects generated during the preparation process.
  • the first conductive layer 40 is continuously etched along the position of the slit opening, and the slit opening is enlarged, so that a V-shaped or arc-shaped structure is formed on the top surface of the first conductive layer 40, and the V-shaped or arc-shaped structure is formed.
  • the shape of the structure constitutes the concave shape of the top surface of the first conductive layer 40 .
  • the structure can be shown with reference to FIG. 14 .
  • the first conductive layer 40 fills part of the first trench 101 , because the first trench 101 corresponds to the active region 11 of the substrate 10 .
  • the first conductive layer 40 covers the first trench 101 , it can be in electrical contact with the active region 11 of the substrate 10 , thereby forming a structural relationship of electrical connection, so that the subsequent bit line structure 50 can be electrically connected through the first conductive layer 40 .
  • the active region 11 is electrically connected, and the first conductive layer 40 constitutes a bit line contact structure (Bit Line Contact, BLC for short).
  • S5 forming the bit line structure 50 on the first conductive layer 40 , the bit line structure 50 covers the surface of the first conductive layer 40 , and the top surface of the bit line structure 50 is lower than the first medium The top surface of layer 20.
  • it can specifically include:
  • the structures of the barrier material layer 51a and the second conductive material layer 52a can be referred to as shown in FIG. 15 , and the barrier material layer 51a can cover the surface of the first conductive layer 40 , the sidewall surface of the first trench 101 and the first conductive material layer 51a. The surfaces of the two dielectric layers 30 .
  • the second conductive material layer 52a covers the surface of the barrier material layer 51a.
  • the barrier material layer 51a may be a titanium nitride layer, and the second conductive material layer 52a may be a metal tungsten layer.
  • the formed bit line structure 50 may be the bit line structure 50 formed by the barrier layer 51 and the second conductive layer 52 as shown in FIG. 16 .
  • the top surface of the second conductive layer 52 Located in the first trench 101 , but not filling the first trench 101 , that is, the top surface of the second conductive layer 52 has a certain distance from the position of the notch of the first trench 101 .
  • the top surface of the first conductive layer 40 is concave, then at least part of the barrier layer 51 and the second conductive layer 52 formed on the first conductive layer 40 are concave, which can increase the contact between the two area, thereby improving the conductivity of the bit line structure 50 .
  • the top surfaces of the barrier layer 51 and the second conductive layer 52 are flush, and this arrangement can improve the flatness of the top surface of the bit line structure 50 , which is beneficial for the subsequent arrangement of the third dielectric layer 60 .
  • a third dielectric layer is formed, the third dielectric layer fills the first trench, and the top surface of the third dielectric layer is flush with the top surface of the second dielectric layer. It should be noted that the third dielectric layer 60 covers the top surface of the bit line structure 50 and can protect the bit line structure 50 .
  • the material for forming the first dielectric layer 20 is the same as the material for forming the third dielectric layer 60 , both of which are silicon nitride.
  • Such an arrangement can reduce the difficulty of preparation, that is, during the preparation process, the same material and the same preparation process can be used to form the first dielectric layer 20 and the third dielectric layer 60, thereby reducing the complexity of the process and helping to reduce the difficulty of preparation .
  • the materials are the same, which can improve the material compatibility between the first dielectric layer 20 and the third dielectric layer 60, avoid structural defects at the junction of the first dielectric layer 20 and the third dielectric layer 60, thereby ensuring the stability of the semiconductor structure sex.
  • the second dielectric layer is removed to form a second trench.
  • the second dielectric layer 30 may be removed by an etching process.
  • a fourth dielectric layer is formed, and the fourth dielectric layer covers at least the bottom and sidewalls of the second trench.
  • the fourth dielectric layer 70 may be a silicon oxide layer.
  • the thickness of the fourth dielectric layer 70 ranges from 8 to 15 mm. Based on the following step 9, the fourth dielectric layer 70 covering the bottom of the second trench 103 and part of the first dielectric layer 20 need to be removed by vertical etching, so the fourth dielectric layer on the sidewall of the second trench 103 The thickness of 70 determines the thickness of the first dielectric layer 20 remaining on the sidewall of the bit line structure 50 after the etching in step 9 is completed. Therefore, when the thickness of the fourth dielectric layer 70 is too small, the thickness of the first dielectric layer 20 remaining on the sidewall of the subsequent bit line structure 50 is too small, so that the first dielectric layer 20 cannot protect the bit line structure 50 Effect.
  • the semiconductor structure needs to be provided with other structural layers, such as a capacitive contact structure, when the thickness of the fourth dielectric layer 70 is too large, it will increase the difficulty of depositing the capacitive contact structure subsequently. Therefore, in the actual preparation process, the user can select the specific thickness value of the fourth dielectric layer 70 within the above range according to needs, for example, it can be 9 mm, 10 mm or 13 mm, preferably 12 mm in this embodiment.
  • the process for forming the fourth dielectric layer 70 is atomic layer deposition, and the gas of the precursor selected in the deposition process may be a mixed gas of C 6 H 17 NSi and O 2 .
  • the fourth dielectric layer 70 on the sidewall of the second trench 103 is etched vertically, thereby removing the fourth dielectric layer 70 and part of the first dielectric layer 20 covering the bottom of the second trench 103 ,
  • the thickness of the remaining first dielectric layer 20 is the thickness of the fourth dielectric layer 70 on the sidewall of the second trench 103 .
  • step 9 it may also include:
  • the fourth dielectric layer 70 and part of the third dielectric layer 60 are removed to expose the top surface of the first dielectric layer 20 , which is flush with the top surface of the remaining third dielectric layer 60 .
  • the first dielectric layer 20 and the remaining third dielectric layer 60 form a bit line protection layer 80 .
  • the top surface of the first dielectric layer 20 and the top surface of the third dielectric layer 60 are flush, which can improve the structural flatness of the bit line protection layer 80 and facilitate the setting of subsequent capacitive contact structures in the semiconductor structure.
  • the above-mentioned preparation method can not only avoid the problem of damage to the bit line caused by the formation of the bit line by etching in the related art, but also can avoid the problem of damage to the bit line caused by the formation of the bit line in the related art.
  • the bit line protection layer 80 formed by the first dielectric layer 20 and the third dielectric layer 60 is formed on the top surface to improve the protection effect on the bit line structure 50 .
  • the top surface of the first dielectric layer 20 after removing the fourth dielectric layer 70 and part of the third dielectric layer 60 , the top surface of the first dielectric layer 20 , the top surface of the first dielectric layer 20 and the remaining third dielectric layer 60 are exposed. After the step of flushing the top surface, you can also include:
  • the isolation layer 100 is formed on the sidewall of the first dielectric layer 20 .
  • the isolation layer 100 includes a first isolation layer 100 a , a second isolation layer 100 b and a third isolation layer 100 c which are stacked.
  • the material of the first isolation layer 100a is the same as the material of the third isolation layer 100c, and is different from the material of the second isolation layer 100b.
  • the first isolation layer 100a and the third isolation layer 100c may be silicon nitride
  • the second isolation layer 100b may be silicon oxide.
  • chemical etching can be selected as the etching method of silicon nitride, silicon oxide and polysilicon, and the etching gas can be selected from SF 6 , CF 4 , CHF 3 , O 2 , Ar or any mixture thereof.
  • the ratio of the mixed gas to achieve a certain selectivity ratio of the etching gas, selective etching is achieved.
  • an embodiment of the present application also provides a semiconductor structure, including:
  • the substrate 10 includes an active region 11 and an isolation region 12 .
  • the first conductive layer 40 is disposed on the substrate 10, and the top surface of the first conductive layer 40 is recessed.
  • the bit line structure 50 includes a barrier layer 51 and a second conductive layer 52 stacked on the first conductive layer 40 ; the bit line structure 50 is electrically connected to the active region 11 through the first conductive layer 40 .
  • the bit line protection layer 80 covers at least the top surface and sidewalls of the bit line structure 50 , and a third trench 104 is formed between adjacent bit line protection layers 80 .
  • isolation layer 100 is also included, and the isolation layer 100 covers the sidewalls of the bit line protection layer 80 .
  • the isolation layer 100 includes a first isolation layer 100a, a second isolation layer 100b and a third isolation layer 100c which are stacked.
  • the material of the first isolation layer 100a is the same as that of the third isolation layer 100c, and is different from the material of the second isolation layer 100b.
  • the semiconductor structure may be a DRAM device, and the above-mentioned substrate 10 , the first conductive layer 40 , the bit line structure 50 , the bit line protection layer 80 and the isolation layer 100 are part of the layer structure in the DRAM device. And the technical effects thereof have been stated above, and will not be repeated here.
  • the material of the first isolation layer 100a and the material of the third isolation layer 100c may be silicon nitride, and the material of the second isolation layer 100b may be silicon oxide. Covering the isolation layer 100 with the sidewall surface of the bit line protection layer 80 can effectively isolate external oxygen elements and impurities from entering the bit line structure 50 to prevent them from affecting the performance of the device. Further, the isolation layer 100 can also reduce the parasitic capacitance of the device as much as possible.
  • the DRAM device may also include transistor structures, capacitor structures, and word lines 105 .
  • the DRAM device may also include an array of multiple memory cells formed on the substrate 10, each memory cell including a capacitor structure and a transistor structure.
  • the capacitor structure is used for storing data, and the transistor structure can control access to data by the capacitor structure, and the gate of the transistor structure is connected to the word line 105 .
  • the drain region in the substrate 10 is connected to the bit line structure 50, and the source region is connected to the capacitor structure.
  • the voltage signal on the word line 105 can control the opening or closing of the transistor structure, and then read the data information stored in the capacitor structure through the bit line structure 50, or write data information into the capacitor structure through the bit line structure 50 for storage , to realize the data access of the DRAM device, so when the above-mentioned semiconductor structure of this embodiment is applied to the DRAM device, the access performance of the DRAM device can be improved.

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Abstract

本申请提供一种半导体结构的制备方法和半导体结构，涉及半导体技术领域，旨在解决位线制备过程中，位线结构受损的问题。该半导体结构的制备方法包括于衬底的第一沟槽内形成第一导电层，第一导电层的顶表面为凹陷状。于第一导电层上形成位线结构。形成第三介质层和第四介质层，第四介质层至少覆盖第二沟槽的底部及侧壁。去除覆盖第二沟槽的底部的第四介质层及部分第一介质层，以形成第三沟槽，第三沟槽暴露衬底。该半导体结构采用上述的制备方法制备。

Description

半导体结构的制备方法和半导体结构
本申请要求于2021年3月22日提交中国专利局、申请号为202110302133.4、申请名称为“半导体结构的制备方法和半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制备技术领域，尤其涉及一种半导体结构的制备方法和半导体结构。
背景技术
动态随机存取存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
动态随机存取存储器包括多个重复的存储单元，每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线(Word line，简称为WL)相连、漏极与位线(Bit line，简称为BL)相连、源极与电容器相连。位线上的电压信号能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中进行存储。随着DRAM器件的特征尺寸不断微缩，位线的特征尺寸以及相邻位线之间的间距不断减小。目前的位线采用刻蚀的方式制备，通过刻蚀将复合沉积层中相邻位线之间的部分刻蚀去除，剩余的复合沉积层则形成位线。
然而，上述的刻蚀过程中，容易引起位线表面结构受损，导致位线发生倾斜或坍塌，降低了位线的结构稳定性和信号传输性能，同时影响半导体存储器的存储性能。
发明内容
第一方面，本申请提供一种半导体结构的制备方法，包括：
提供衬底，衬底包括有源区和隔离区；
于衬底上依次形成第一介质层和第二介质层；
去除部分第一介质层和部分第二介质层，以形成第一沟槽；
于第一沟槽内形成第一导电层，第一导电层的顶表面为凹陷状；
于第一导电层上形成位线结构，位线结构覆盖第一导电层的表面，且位线结构的顶表面低于第一介质层的顶表面；
形成第三介质层，第三介质层填充满第一沟槽，且第三介质层的顶表面与第二介质层的顶表面齐平；
去除第二介质层，形成第二沟槽；
形成第四介质层，第四介质层至少覆盖第二沟槽的底部及侧壁；
去除覆盖第二沟槽的底部的第四介质层及部分第一介质层，以形成第三沟槽，第三沟槽暴露衬底。
第二方面，本申请还提供一种半导体结构，包括：
衬底，衬底包括有源区和隔离区；
第一导电层，位于衬底上，第一导电层的顶表面为凹陷状；
位线结构，位线结构包括层叠设置在第一导电层上的阻挡层和第二导电层；位线结构通过第一导电层与有源区电性连接；
位线保护层，位线保护层至少覆盖位线结构的顶表面和侧壁，相邻的位线保护层之间具有第三沟槽。
本申请的构造以及它的发明目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作以简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中半导体结构的结构示意图；
图2为相关技术中半导体结构的位线的结构示意图；
图3为本申请实施例提供的半导体结构的制备方法的流程示意图；
图4为本申请实施例提供的半导体结构的制备方法的形成第一沟槽的流程示意图；
图5为本申请实施例提供的半导体结构的制备方法的形成第一导电层的流程示意图；
图6为本申请实施例提供的半导体结构的制备方法的形成位线结构的流程示意图；
图7为本申请实施例提供的半导体结构的衬底、第一介质层和第二介质层的结构示意图；
图8为本申请实施例提供的半导体结构的第二介质层的顶表面形成掩膜层的结构示意图；
图9为本申请实施例提供的半导体结构的形成第一沟槽的结构示意图；
图10为本申请实施例提供的半导体结构的形成第一沟槽的俯视图；
图11为本申请实施例提供的半导体结构的形成第一导电材料层的结构示意图；
图12为本申请实施例提供的半导体结构的形成第一导电层的结构示意图；
图13为本申请实施例提供的半导体结构的形成第一导电层的俯视图；
图14为本申请实施例提供的半导体结构的形成凹陷状的第一导电层的结构示意图；
图15为本申请实施例提供的半导体结构的形成阻挡材料层和第二导电层材料层的结构示意图；
图16为本申请实施例提供的半导体结构的形成阻挡层和第二导电层的结构示意图；
图17为本申请实施例提供的半导体结构的形成第三介质层的结构示意图；
图18为本申请实施例提供的半导体结构的形成第二沟槽的结构示意图；
图19为本申请实施例提供的半导体结构的形成第四介质层的结构示意图；
图20为本申请实施例提供的半导体结构的形成第三沟槽的结构示意图；
图21为本申请实施例提供的半导体结构的形成位线保护层的结构示意图；
图22为本申请实施例提供的半导体结构的形成隔离层的结构示意图；
图23为本申请实施例提供的图22中I部分的局部结构示意图。
附图标记说明：
10、1-衬底；11、2-有源区；12、3-隔离区；20-第一介质层；30-第二介质层；40-第一导电层；41-第一导电材料层；42-缝隙；50-位线结构；51-阻挡层；51a-阻挡材料层；52-第二导电层；52a-第二导电材料层；60-第三介质层；70-第四介质层；80-位线保护层；100-隔离层；100a-第一隔离层；100b-第二隔离层；100c-第三隔离层；101-第一沟槽；102-掩膜层；102a-掩膜开口；103-第二沟槽；104-第三沟槽；105-字线；4-氮化钛层；5-金属钨层；6-氮化硅层；7-位线掩膜层；A-缺陷区域；a、b、c、d-位线。
具体实施方式
本申请的发明人在实际研究过程中发现，随着DRAM器件的特征尺寸不断微缩，DRAM器件中位线的特征尺寸以及相邻位线之间的间距不断减小。图1为相关技术中半导体结构的结构示意图。图2为相关技术中半导体结构的位线的结构示意图。参照图1和图2所示，目前的位线采用刻蚀的方式制备。首先可以形成具有有源区2和隔离区3的衬底1，在衬底1上依次形成氮化钛层4和金属钨层5，并且在金属钨层5的顶表面上形成氮化硅层6。氮化硅层6的顶表面上形成位线掩膜层7，利用位线掩膜层7刻蚀氮化钛层4和金属钨层5，从而形成位线。在刻蚀过程中，由于刻蚀工艺的限制，刻蚀深度无法精确控制，导致所形成的位线中容易出现结构受损的现象，例如颈缩(necking)。
参照图2中，最左侧的氮化钛层4和金属钨层5所形成的位线a中，靠近衬底1的氮化钛层4被过度刻蚀产生的结构受损，在此处形成缺陷区域A。或者，位线b中远离衬底1一侧的金属钨层5最先受到刻蚀介质的影响，从而发生过度刻蚀，导致位线b的结构尺寸不均匀，同样在此处可以形成缺陷区域A。亦或者，位线c和位线d发生倾斜的问题。上述的位线结构均会导致位线坍塌，影响位线的结构稳定性，并且导致位线中信号传输受阻，影响DRAM器件的存储性能。
有鉴于此，本申请实施例提供的半导体结构的制备方法和半导体结构，通过在衬底上形成第一介质层和第二介质层，并且形成第一沟槽，利用第一沟槽形成第一导电层和位线结构。通过在第一导电层的顶表面为凹陷状，利用第一导电层作为位线结构的设置基础。通过在第一导电层上设置位线结构，位线结构的阻挡层和第二导电层之间的接触面积增加，有助于提高位线结构的导电性能。位线结构是通过在第一导电层上沉积阻挡层和第二导电层形成的，可以有效避免位线结构受损而发生倾斜或坍塌的问题。通过在位线结构的顶表面和侧壁上形成位线保护层，提高了对位线结构的保护效果。并且通过在位线保护层的侧壁设置隔离层，可以有效避免外部的氧元素或杂质对位线结构的影响， 提高位线结构和信号传输的稳定性，有助于优化该半导体结构的存储性能。
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请的优选实施例中的附图，对本申请实施例中的技术方案进行更加详细的描述。在附图中，自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。所描述的实施例是本申请一部分实施例，而不是全部的实施例。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。下面结合附图对本申请的实施例进行详细说明。
图3为本申请实施例提供的半导体结构的制备方法的流程示意图。图4为本申请实施例提供的半导体结构的制备方法的形成第一沟槽的流程示意图。图5为本申请实施例提供的半导体结构的制备方法的形成第一导电层的流程示意图。图6为本申请实施例提供的半导体结构的制备方法的形成位线结构的流程示意图。图7为本申请实施例提供的半导体结构的衬底、第一介质层和第二介质层的结构示意图。图8为本申请实施例提供的半导体结构的第二介质层的顶表面形成掩膜层的结构示意图。图9为本申请实施例提供的半导体结构的形成第一沟槽的结构示意图。图10为本申请实施例提供的半导体结构的形成第一沟槽的俯视图。图11为本申请实施例提供的半导体结构的形成第一导电材料层的结构示意图。图12为本申请实施例提供的半导体结构的形成第一导电层的结构示意图。图13为本申请实施例提供的半导体结构的形成第一导电层的俯视图。图14为本申请实施例提供的半导体结构的形成凹陷状的第一导电层的结构示意图。图15为本申请实施例提供的半导体结构的形成阻挡材料层和第二导电层材料层的结构示意图。图16为本申请实施例提供的半导体结构的形成阻挡层和第二导电层的结构示意图。图17为本申请实施例提供的半导体结构的形成第三介质层的结构示意图。图18为本申请实施例提供的半导体结构的形成第二沟槽的结构示意图。图19为本申请实施例提供的半导体结构的形成第四介质层的结构示意图。图20为本申请实施例提供的半导体结构的形成第三沟槽的结构示意图。图21为本申请实施例提供的半导体结构的形成位线保护层的结构示意图。图22为本申请实施例提供的半导体结构的形成隔离层的结构示意图。图23为本申请实施例提供的图22中I部分的局部结构示意图。
参照图3至图6所示，同时结合图7至图23所示，本申请的一个实施例提供一种半导体结构的制备方法，包括：
S1：提供衬底，衬底包括有源区和隔离区。
需要说明的是，衬底10的材料可以是单晶硅、多晶硅、无定型硅、硅锗化合物或绝缘体上硅(silicon-on-insulator，简称为SOI)等，或者本领域技术人员已知的其他材料，该衬底10可以为衬底10上的结构层提供支撑基础。在本实施例中，衬底10为Si衬底。衬底10中可以具有半导体层，该半导体层形成衬底10的有源区11，有源区11包括源极区和漏极区，并且源极区和漏极区之间形成有隔离区12。该隔离区12内可以设置浅沟道隔离结构(Shallow Trench Isolation，简称为STI)。
S2：于衬底上依次形成第一介质层和第二介质层。
需要说明的是，第一介质层20和第二介质层30可以通过化学沉积的方式制备，第一介质层20可以为氮化硅层，第二介质层30可以为氧化硅层。
其中，衬底10、第一介质层20和第二介质层30的结构可以参照图7所示，有源区11和隔离区12可以在衬底10中交错间隔设置。
参照图3和图4所示，S3：去除部分第一介质层和部分第二介质层，以形成第一沟槽。需要说明的是，在该步骤3中，可以具体包括：
S31：于第二介质层的顶表面形成掩膜层，掩膜层上具有多个间隔设置的掩膜开口。该掩膜层102可以是光刻胶层，掩膜层102上预留出需要形成位线结构50的位置，从而形成掩膜开口102a。其中，掩膜层102的结构可以如图8所示。
S32：沿掩膜开口刻蚀第一介质层和第二介质层，形成第一沟槽。
S33：去除掩膜层。
其中，掩膜开口102a处的第一介质层20和第二介质层30可以通过刻蚀工艺去除，以形成第一沟槽101。第一沟槽101中形成的位线结构50可以与有源区11中的源极区或漏极区电性连接，所形成的第一沟槽101的结构可以参照图9所示。
结合图10所示，该半导体结构可以包括设置在衬底10中的字线105结构，该字线105结构可以采用埋入式字线105的方式设置，多条字线105沿第一方向间隔设置。衬底10上的多条第一沟槽101沿第二方向间隔设置，第二方向与第一方向相交或者相互垂直，第一沟槽101用于形成位线结构50。
参照图3和图5所示，S4：于第一沟槽内形成第一导电层，第一导电层的顶表面为凹陷状。在该步骤4中，可以具体包括：
S41：形成第一导电材料层，第一导电材料层填充第一沟槽且第一导电材料层具有缝隙。
S42：利用刻蚀工艺去除部分第一导电材料层，剩余的第一导电材料层构成第一导电层。
需要说明的是，第一导电材料层41可以是通过沉积的方式形成，该结构可以参照图11所示。在沉积过程中，由于结构的缺陷会不可避免的产生缝隙42，为了减少该缝隙42对第一导电材料层41的影响。本实施例可以在刻蚀去除部分第一导电材料层41后，暴露出该缝隙42的缝隙开口，利用该缝隙42形成后续的第一导电层40的凹陷状结构。参照图12所示，剩余的第一导电材料层41形成了第一导电层40。
其中，形成第一导电材料层41的材料为掺杂有磷元素的多晶硅，基于磷元素与硅之间具有较高的固熔度，因此掺杂磷元素可以提高掺杂量，有助于提高多晶硅的导电性能。
作为一种可实现的实施方式，形成第一导电材料层41的步骤中包括：在480-520℃下，向第一沟槽101中通入SiH 4和PH 3混合气体，采用低压化学沉积法制备第一导电材料层41。低压化学沉积法可以提高第一导电材料层41沉积过程中的结构均匀性，减少制备过程中所产生的结构缺陷。
进一步地，沿着缝隙开口的位置继续刻蚀第一导电层40，将缝隙开口扩大，从而在第一导电层40的顶表面上形成V字型或弧形的结构，该V字型或弧形的结构即构成了第一导电层40的顶表面的凹陷状。该结构可以参照图14所示。
结合图13所示，沉积了第一导电层40的半导体结构中，第一导电层40填充部分第一沟槽101，基于第一沟槽101与衬底10的有源区11相对应。第一导电层40覆盖第一沟槽101后，可以与衬底10的有源区11电接触，从而形成电性连接的结构关系，便于 后续的位线结构50通过该第一导电层40电性连接有源区11，第一导电层40则构成了位线接触结构(Bit Line Contact，简称为BLC)。
参照图3和图6所示，S5：于第一导电层40上形成位线结构50，位线结构50覆盖第一导电层40的表面，且位线结构50的顶表面低于第一介质层20的顶表面。在该步骤5中，可以具体包括：
S51：形成阻挡材料层，阻挡材料层至少覆盖第一导电层的表面。
S52：形成第二导电材料层，第二导电材料层覆盖阻挡材料层的表面。
需要说明的是，该阻挡材料层51a和第二导电材料层52a的结构可以参照图15所示，阻挡材料层51a可以覆盖第一导电层40的表面，第一沟槽101的侧壁面以及第二介质层30的表面。第二导电材料层52a覆盖阻挡材料层51a的表面。该阻挡材料层51a可以为氮化钛层，第二导电材料层52a可以为金属钨层。
S53：利用刻蚀工艺去除部分阻挡材料层和部分第二导电材料层，剩余的阻挡材料层构成阻挡层，剩余的第二导电材料层构成第二导电层，阻挡层和第二导电层构成位线结构。
需要说明的是，去除部分的阻挡材料层51a和部分第二导电材料层52a，所形成的位线结构50可以是图16所示，阻挡层51和第二导电层52构成的位线结构50位于该第一沟槽101中，但并未填充满该第一沟槽101，即第二导电层52的顶表面与第一沟槽101的槽口位置具有一定的间距。
其中，基于第一导电层40的顶表面为凹陷状，那么形成在第一导电层40上的阻挡层51以及第二导电层52的至少部分为凹陷状，这样可以增加两者之间的接触面积，从而提高位线结构50的导电性能。
进一步地，参照图16所示，阻挡层51和第二导电层52的顶表面齐平，这样的设置可以提高位线结构50顶表面的平整度，有利于设置后续的第三介质层60。
结合图17所示，在S6中：形成第三介质层，第三介质层填充满第一沟槽，且第三介质层的顶表面与第二介质层的顶表面齐平。需要说明的是，该第三介质层60覆盖位线结构50的顶表面，可以对位线结构50起到保护的效果。
同时，形成第一介质层20的材料与形成第三介质层60的材料相同，均为氮化硅。这样的设置可以减小制备难度，即在制备过程中，可以使用同一材料，同一制备工艺形成该第一介质层20和第三介质层60，从而减少工艺的复杂度，有助于降低制备难度。并且材料相同，可以提高第一介质层20和第三介质层60之间材料相容性，避免第一介质层20和第三介质层60的接合处出现结构缺陷，从而保证该半导体结构的稳定性。
结合图18所示，在S7中：去除第二介质层，形成第二沟槽。该步骤中，可以通过刻蚀工艺去除第二介质层30。
参照图19所示，在S8中：形成第四介质层，第四介质层至少覆盖第二沟槽的底部及侧壁。该第四介质层70可以为氧化硅层。
此处，需要强调的是，第四介质层70厚度范围为8-15mm。基于后续步骤9中，需要通过垂直刻蚀的方式去除覆盖第二沟槽103的底部的第四介质层70及部分第一介质层20，因此第二沟槽103侧壁处的第四介质层70的厚度决定了步骤9刻蚀完成后，位线结构50侧壁保留的第一介质层20的厚度。因此当该第四介质层70的厚度过小时，导致后 续位线结构50的侧壁保留的第一介质层20的厚度过小，无法通过第一介质层20起到对位线结构50的保护效果。
进一步地，由于该半导体结构后续需要设置其余结构层，例如电容接触结构，当该第四介质层70的厚度过大时，导致后续沉积电容接触结构的难度增加。因此在实际制备过程中，用户可以根据需要上述范围内选定第四介质层70的具体厚度值，例如可以为9mm、10mm或者13mm，本实施例中优选为12mm。
其中，形成第四介质层70的工艺为原子层沉积法，沉积过程中选用的前驱体的气体可以为C 6H 17NSi和O 2混合气体。
参照图20所示，在S9中：去除覆盖第二沟槽的底部的第四介质层及部分第一介质层，以形成第三沟槽，第三沟槽暴露衬底。
需要说明的是，沿着第二沟槽103的侧壁上的第四介质层70垂直刻蚀，从而去除覆盖第二沟槽103的底部的第四介质层70及部分第一介质层20，保留的第一介质层20的厚度即为第二沟槽103的侧壁上的第四介质层70的厚度。通过上述的刻蚀，可以形成多个相互独立的位线结构50。
参照图21所示，在该步骤9之后，还可以包括：
去除第四介质层70和部分第三介质层60，暴露第一介质层20的顶表面，第一介质层20的顶表面和剩余的第三介质层60的顶表面齐平。
其中，第一介质层20和剩余的第三介质层60形成位线保护层80。
需要说明的是，第一介质层20的顶表面和第三介质层60的顶表面齐平可以提高位线保护层80的结构平整度，有助于半导体结构中后续电容接触结构的设置。在本实施例中，通过上述的制备方式，不仅可以避免相关技术中，通过刻蚀的方式形成位线，所造成的位线受损的问题，而且还可以在位线结构50的侧壁和顶表面上形成第一介质层20和第三介质层60所形成的位线保护层80，提高了对位线结构50的保护效果。
参照图22和图23所示，在去除第四介质层70和部分第三介质层60，暴露第一介质层20的顶表面，第一介质层20的顶表面和剩余的第三介质层60的顶表面齐平的步骤之后，还可以包括：
于第一介质层20的侧壁上形成隔离层100，隔离层100包括层叠设置的第一隔离层100a、第二隔离层100b和第三隔离层100c。其中，第一隔离层100a的材料和第三隔离层100c材料相同，且与第二隔离层100b的材料不同。
需要说明的是，第一隔离层100a和第三隔离层100c可以为氮化硅，第二隔离层100b可以为氧化硅。通过设置层叠的氮化硅-氧化硅-氮化硅结构，既可以有效隔离外部的氧元素和杂质进入位线结构50中，影响器件性能，也可以尽可能的减小器件的寄生电容。
需要指出的是，在该半导体的制备方法中，刻蚀氮化硅、氧化硅以及多晶硅的方式可以选用化学刻蚀法，刻蚀气体可以选用SF 6、CF 4、CHF 3、O 2、Ar或其任意多个的混合气体。在刻蚀过程中，通过调整混合气体的比例，以达到该刻蚀气体具有一定的选择比，从而实现选择性刻蚀。
在上述的基础上，本申请实施例还提供一种半导体结构，包括：
衬底10，衬底包括有源区11和隔离区12。
第一导电层40，第一导电层40设置在衬底10上，第一导电层40的顶表面为凹陷 状。
位线结构50，位线结构50包括层叠设置在第一导电层40上的阻挡层51和第二导电层52；位线结构50通过第一导电层40与有源区11电性连接。
位线保护层80，位线保护层80至少覆盖位线结构50的顶表面和侧壁，相邻的位线保护层80间具有第三沟槽104。
进一步地，还包括隔离层100，隔离层100覆盖位线保护层80的侧壁。
隔离层100包括层叠设置的第一隔离层100a、第二隔离层100b和第三隔离层100c。
第一隔离层100a的材料和第三隔离层100c的材料相同，且与第二隔离层100b的材料不同。
需要说明的是，该半导体结构可以为DRAM器件，上述衬底10、第一导电层40、位线结构50、位线保护层80以及隔离层100是DRAM器件中的部分层结构，这些层结构以及其技术效果已在上述陈述，此处不再一一赘述。
其中，第一隔离层100a的材料和第三隔离层100c的材料可以为氮化硅，第二隔离层100b的材料可以为氧化硅。位线保护层80的侧壁面覆盖该隔离层100可以有效隔离外部的氧元素和杂质进入位线结构50中，以防止其影响器件的性能。进一步地，该隔离层100还可以尽可能地减小器件的寄生电容。
除上述的层结构之外，该DRAM器件中的还可以包括晶体管结构、电容结构以及字线105。DRAM器件还可以包括形成在衬底10上的多个存储单元的阵列，每个存储单元均包括电容结构和晶体管结构。
其中，电容结构用于存储数据，而晶体管结构可以控制电容结构对数据的存取，晶体管结构的栅极与字线105相连。衬底10中的漏极区与位线结构50相连，源极区与电容结构相连。字线105上的电压信号能够控制晶体管结构的打开或关闭，进而通过位线结构50读取存储在电容器结构中的数据信息，或者通过位线结构50将数据信息写入到电容器结构中进行存储，实现该DRAM器件的数据存取，因此当本实施例的上述半导体结构应用在该DRAM器件中，可以提升DRAM器件的存取性能。
在上述描述中，需要理解的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以使固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。术语“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或者暗示所指的装置或者元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。在本申请的描述中，“多个”的含义是两个或两个以上，除非是另有精确具体地规定。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单 元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，其中，包括：
    提供衬底，所述衬底包括有源区和隔离区；
    于所述衬底上依次形成第一介质层和第二介质层；
    去除部分所述第一介质层和部分所述第二介质层，以形成第一沟槽；
    于所述第一沟槽内形成第一导电层，所述第一导电层的顶表面为凹陷状；
    于所述第一导电层上形成位线结构，所述位线结构覆盖所述第一导电层的表面，且所述位线结构的顶表面低于所述第一介质层的顶表面；
    形成第三介质层，所述第三介质层填充满所述第一沟槽，且所述第三介质层的顶表面与所述第二介质层的顶表面齐平；
    去除所述第二介质层，形成第二沟槽；
    形成第四介质层，所述第四介质层至少覆盖所述第二沟槽的底部及侧壁；
    去除覆盖所述第二沟槽的底部的所述第四介质层及部分所述第一介质层，以形成第三沟槽，所述第三沟槽暴露所述衬底。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述于所述第一沟槽内形成第一导电层，所述第一导电层的顶表面为凹陷状的步骤中包括：
    形成第一导电材料层，所述第一导电材料层填充所述第一沟槽且所述第一导电材料层具有缝隙；
    利用刻蚀工艺去除部分所述第一导电材料层，剩余的所述第一导电材料层构成所述第一导电层。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，包括：
    形成所述第一导电材料层的材料为掺杂有磷元素的多晶硅。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，所述形成第一导电材料层的步骤中包括：
    在480-520℃下，向所述第一沟槽中通入SiH 4和PH 3混合气体，采用低压化学沉积法制备所述第一导电材料层。
  5. 根据权利要求1所述的半导体结构的制备方法，其中，所述于所述第一导电层上形成位线结构，所述位线结构覆盖所述第一导电层的表面，且所述位线结构的顶表面低于所述第一介质层的顶表面的步骤中包括：
    形成阻挡材料层，所述阻挡材料层至少覆盖所述第一导电层的表面；
    形成第二导电材料层，所述第二导电材料层覆盖所述阻挡材料层的表面；
    利用刻蚀工艺去除部分所述阻挡材料层和部分所述第二导电材料层，剩余的所述阻挡材料层构成阻挡层，剩余的所述第二导电材料层构成第二导电层，所述阻挡层和所述第二导电层构成所述位线结构。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，包括：
    所述阻挡层和所述第二导电层的顶表面齐平。
  7. 根据权利要求1所述的半导体结构的制备方法，其中，包括：
    形成所述第一介质层的材料与形成所述第三介质层的材料相同。
  8. 根据权利要求1所述的半导体结构的制备方法，其中，包括：
    形成所述第四介质层的工艺为原子层沉积法。
  9. 根据权利要求1所述的半导体结构的制备方法，其中，包括：
    所述第四介质层厚度范围为8-15mm。
  10. 根据权利要求1所述的半导体结构的制备方法，其中，所述去除部分所述第一介质层和部分所述第二介质层，以形成第一沟槽的步骤中包括：
    于所述第二介质层的顶表面形成掩膜层，所述掩膜层上具有多个间隔设置的掩膜开口；
    沿所述掩膜开口刻蚀所述第一介质层和所述第二介质层，形成所述第一沟槽；
    去除所述掩膜层。
  11. 根据权利要求1所述的半导体结构的制备方法，其中，在所述去除覆盖所述第二沟槽的底部的所述第四介质层及部分所述第一介质层，以形成第三沟槽，所述第三沟槽暴露所述衬底的步骤之后，还包括：
    去除所述第四介质层和部分第三介质层，暴露所述第一介质层的顶表面，所述第一介质层的顶表面和剩余的所述第三介质层的顶表面齐平；
    其中，所述第一介质层和剩余的所述第三介质层形成位线保护层。
  12. 根据权利要求11所述的半导体结构的制备方法，其中，所述去除所述第四介质层和部分第三介质层，暴露所述第一介质层的顶表面，所述第一介质层的顶表面和剩余的所述第三介质层的顶表面齐平的步骤之后，还包括：
    于所述第一介质层的侧壁上形成隔离层，所述隔离层包括层叠设置的第一隔离层、第二隔离层和第三隔离层；
    其中，所述第一隔离层的材料和所述第三隔离层材料相同，且与所述第二隔离层的材料不同。
  13. 根据权利要求12所述的半导体结构的制备方法，其中，包括：
    形成所述第一隔离层和所述第三隔离层的材料为氮化硅，形成所述第二隔离层的材料为氧化硅。
  14. 一种半导体结构，其中，包括：
    衬底，所述衬底包括有源区和隔离区；
    第一导电层，位于所述衬底上，所述第一导电层的顶表面为凹陷状；
    位线结构，所述位线结构包括层叠设置在所述第一导电层上的阻挡层和第二导电层；所述位线结构通过所述第一导电层与所述有源区电性连接；
    位线保护层，所述位线保护层至少覆盖所述位线结构的顶表面和侧壁，相邻所述位线保护层之间具有第三沟槽。
  15. 根据权利要求14所述的半导体结构，其中，还包括隔离层，所述隔离层覆盖所述位线保护层的侧壁；
    所述隔离层包括层叠设置的第一隔离层、第二隔离层和第三隔离层；
    所述第一隔离层的材料和所述第三隔离层的材料相同，且与所述第二隔离层的材料不同。
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CN111710679A (zh) * 2020-06-24 2020-09-25 福建省晋华集成电路有限公司 存储器及其形成方法

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