WO2022052593A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2022052593A1
WO2022052593A1 PCT/CN2021/103751 CN2021103751W WO2022052593A1 WO 2022052593 A1 WO2022052593 A1 WO 2022052593A1 CN 2021103751 W CN2021103751 W CN 2021103751W WO 2022052593 A1 WO2022052593 A1 WO 2022052593A1
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Prior art keywords
bit line
layer
trench
conductive layer
conductive
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PCT/CN2021/103751
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English (en)
French (fr)
Inventor
赵忠强
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长鑫存储技术有限公司
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Priority to US17/442,428 priority Critical patent/US11495603B1/en
Publication of WO2022052593A1 publication Critical patent/WO2022052593A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a preparation method thereof.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a commonly used memory. With the shrinking of the storage capacitor area on the DRAM cell array, the preparation of DRAM requires higher and higher precision of the lithography process. The impact of the etching process on the bit mismatch on DRAM is also increasing.
  • the electrical connection between the capacitor and the capacitive contact is achieved through a conductive layer.
  • the conductive layer needs to be patterned.
  • the resistance value of the conductive layer increases, and even breaks in severe cases, which eventually reduces the contact area between the storage capacitor and the capacitor contact, increases the contact resistance, and reduces the transmission efficiency of the dynamic random access memory cell array.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a semiconductor device and a preparation method thereof.
  • a method for fabricating a semiconductor device comprising:
  • a substrate is provided on which a plurality of access units are formed, the access units include a bit line unit and a capacitive contact; each bit line unit and each capacitive contact of the plurality of access units Alternately arranged and insulated from each other, the height of the bit line unit is higher than the height of the capacitive contact, so that a groove is formed between two adjacent bit line units; the substrate is also formed with a conductive layer covering each of the access cells, the conductive layer filling each of the grooves;
  • the conductive layer above the bit line unit is the first conductive portion
  • the conductive layer covering the sidewall of the bit line unit and connected to the first conductive portion is the second conductive portion, covering the groove
  • the conductive layer at the bottom and connected to the second conductive portion is the third conductive portion
  • a storage capacitor is formed on a side of the first conductive portion away from the substrate, and the storage capacitor is in contact with the first conductive portion.
  • the forming a first trench in the conductive layer corresponding to each of the access cells includes:
  • the first etching is performed on the portion of the conductive layer corresponding to each of the grooves to form a plurality of initial trenches, so that in each of the access cells, the initial trenches are close to the side of the bit line unit
  • the wall is farther from the bit line cell than the sidewall of the same side of the groove;
  • the initial trench is etched downward again, so that the newly etched trench is close to the sidewall of the bit line unit to form an arc surface in the depth direction of the trench, and the arc surface is facing the trench.
  • the direction of the bottom of the groove is gradually approached to the opposite side wall to obtain the first groove.
  • forming a protective layer on the sidewall of the first trench of the conductive layer includes:
  • the protective material covering the upper surface of the conductive layer and the bottom surface of the first trench is etched away, and the protective material covering the sidewall of the first trench is retained to form the protective layer.
  • the bit line unit includes a bit line structure layer formed on a substrate and a bit line protection layer on a side of the bit line structure layer away from the substrate, so The bottom surface of the bit line protection layer is not higher than the bottom surface of the groove;
  • bit line protection layer is also etched away while the second trench is formed by etching a portion of the conductive layer located in the groove.
  • the protective material is one or a mixture of any of silicon nitride, silicon dioxide, silicon oxynitride, titanium nitride, titanium dioxide, zirconium dioxide, and polysilicon .
  • the thickness of the protective layer is 5-10 nm.
  • the etching gas for forming the first trench is a mixed gas of sulfur hexafluoride, chlorine gas, nitrogen gas and oxygen gas.
  • the etching gas for forming the second trench and the etching gas for etching the protective layer is a mixed gas of tetrafluoroethane, argon and oxygen.
  • the forming the storage capacitor includes:
  • a lower electrode, a dielectric layer and an upper electrode of the capacitor are sequentially formed in the capacitor hole, and the lower electrode is in contact with the first conductive portion.
  • a step-by-step etching method is adopted, and parameters such as the composition of the etching gas, the etching time, and the rate of each step can be flexibly adjusted , so that the conductive layer can be etched into an ideal shape.
  • this step of etching will not affect the second wire portion, so that the second wire portion is thicker, so that the conductive layer is not easily broken here. , and it is not easy to increase the resistance because of the narrowness, ensuring sufficient contact area and low contact resistance, and at the same time, the requirements for the alignment accuracy of the lithography process during the preparation process are reduced, thereby improving the yield.
  • FIG. 1 is a top view of a semiconductor device according to an embodiment of the disclosure
  • Fig. 2 is the cross-sectional schematic diagram of A-A in Fig. 1;
  • FIG. 3 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the disclosure
  • FIG. 4 is a schematic structural diagram of forming a bit line unit and a capacitor contact according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of forming a conductive layer according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of forming an initial trench according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of forming a first trench according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of depositing a protective material according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of forming a protective layer according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a second trench according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of removing a protective layer according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of forming an insulating layer according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of forming a capacitor hole according to an embodiment of the disclosure.
  • FIG. 14 is a schematic structural diagram of forming a storage capacitor according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a top view of the structure of a semiconductor device, showing part of the capacitance distribution structure
  • FIG. 2 is a schematic cross-sectional view along the AA direction in FIG. 1 , showing a schematic cross-sectional view including two capacitors.
  • the semiconductor device is provided with a plurality of bit line units 2 and a plurality of capacitive contacts 3 on a substrate 1, and the plurality of bit line units 2 and the plurality of capacitive contacts 3 are alternately arranged one by one and insulated from each other.
  • the film layer of the bit line unit 2 is usually more than that of the capacitor contact 3 and its thickness is thicker, that is to say, the height of the bit line unit 2 is higher than that of the capacitor contact 3, so the adjacent two bit line units 2 Grooves are formed in between.
  • the height of the bit line unit refers to the distance from the upper surface of the bit line unit to the substrate; similarly, the height of the capacitor contact refers to the distance from the upper surface of the capacitor contact to the substrate.
  • a conductive layer 4 and an insulating layer 5 are provided above the capacitive contact 3, and the insulating layer 5 is used to The conductive layers 4 of two adjacent access cells are isolated from each other.
  • a support layer 10 is disposed above the conductive layer 4 and the insulating layer 5 , and the support layer 10 is provided with a capacitor hole penetrating up and down, and the capacitor hole exposes the conductive layer 4 .
  • a storage capacitor 6 is arranged in the capacitor hole, and the storage capacitor 6 is electrically connected to the capacitor contact 3 through the conductive layer 4 . In order to form the hexagonal closest packing of the storage capacitors 6 as shown in FIG.
  • the storage capacitors 6 need to be arranged staggered from the capacitor contacts 3 , that is, the storage capacitors 6 are not located directly above the capacitor contacts 3 , but are facing the
  • the bit line cells are offset, as shown in FIG. 1 , the circles represent the storage capacitors 6 and the dashed boxes represent the locations of the lower capacitor contacts 3 .
  • the conductive layer 4 also needs to be offset toward the bit line unit. Therefore, the conductive layer 4 needs to be designed into the shape shown in the dotted frame in FIG.
  • the first conductive portion 41 is located above the bit line unit 2
  • the second conductive portion 42 covers the left side wall of the groove
  • the third conductive portion 43 covers the bottom of the groove.
  • the capacitor is located above the first conductive portion 41, so that the three conductive portions are electrically connected to the capacitive contact.
  • the rest of the groove is filled with insulating layer 5 .
  • the conductive layer 4 When preparing the semiconductor device with the above structure, in order to form the shape of the conductive layer 4, the conductive layer 4 needs to be continuously patterned. During the patterning process, the photolithography process is usually used for preparation. When the quasi-deviation occurs, the second conductive portion 42 is made thinner, which leads to an increase in the contact resistance between the storage capacitor 6 and the capacitor contact 3, which reduces the data transmission efficiency of the access unit. In severe cases, the second conductive portion 42 may even be broken, and the storage capacitor 6 and the capacitor contact 3 cannot be in contact with each other, which ultimately causes the access unit to be unable to access data.
  • the fabrication method includes the following steps:
  • Step S100 a substrate 1 is provided, and a plurality of access units are formed on the substrate 1, and the access unit includes a bit line unit 2 and a capacitor contact 3; each bit line unit 2 of the plurality of access units and each capacitor
  • the contacts 3 are alternately arranged one by one and are insulated from each other, and the height of the bit line unit 2 is higher than that of the capacitive contact 3, so that a groove is formed between two adjacent bit line units 2; a cover is also formed on the substrate 1
  • the conductive layer 4 of each access cell, the conductive layer 4 fills the groove.
  • Step S200 etching the portion of the conductive layer 4 corresponding to the groove to form a first trench 92 corresponding to each access unit in the conductive layer 4.
  • the first trench 92 is close to The side wall of the bit line unit is farther from the bit line unit 2 than the side wall of the same side of the groove.
  • Step S300 forming the protective layer 8 on the sidewall of the first trench 92 .
  • Step S400 continue to etch down the first trench 92, etch away part of the conductive layer 4 located in the groove, and retain the conductive layer 4 covering the sidewall of the bit line unit 2 and the bottom of the groove to form a second groove Slot 93.
  • the conductive layer above the bit line unit is the first conductive portion
  • the conductive layer covering the sidewall of the bit line unit and connected to the first conductive portion is the second conductive portion
  • the conductive layer is the third conductive portion.
  • step S500 the protective layer 8 is removed.
  • step S600 a storage capacitor 6 is formed on the side of the first conductive portion 42 away from the substrate 1 , so that the storage capacitor 6 is in contact with the first conductive portion 42 .
  • the conductive layer 4 on the substrate 1 is patterned, the conductive layer 4 is first etched to form the first trench 92 by means of step-by-step etching, and the unetched part at the top is used as the capacitor 6
  • the connected first conductive portion 41 then protect the sidewall of the first trench 92, and then continue to etch the conductive layer 4 downward to form a second trench 93, after removing the protective layer 8, form the vertical second conductive portion 42 and the third conductive portion 43 at the bottom, and finally the conductive layer 4 is obtained.
  • the step-by-step etching method Due to the step-by-step etching method, parameters such as the composition of the etching gas, the etching time, and the rate of each step can be flexibly adjusted, so that the three parts of the conductive layer 4 can be etched into an ideal shape. Especially during the second step of etching, since the protective layer 8 is provided, this step of etching will not affect the sidewall of the conductive layer 4, so that the final vertical second conductive portion 42 has a thicker thickness. In this way, the conductive layer 4 is not easy to break here, and it is not easy to increase the resistance because the second conductive portion 42 is too narrow, so as to ensure that the storage capacitor 6 and the capacitor contact 3 can form a good electrical contact, ensuring sufficient high contact area and low contact resistance. The requirements on the alignment accuracy of the photolithography process during the preparation process are reduced, thereby increasing the yield.
  • a substrate 1 is provided. As shown in FIG. 4, a plurality of access units are formed on the substrate 1, and the access units include a bit line unit 2 and a capacitor contact 3; each bit line in the plurality of access units The units 2 and the capacitor contacts 3 are alternately arranged one by one and insulated from each other. The height of the bit line unit 2 is greater than that of the capacitor contact 3 , so that a groove 94 is formed between two adjacent bit line units 2 .
  • a conductive layer 4 covering each access unit is also formed on the substrate 1, and the conductive layer 4 fills each groove 94;
  • the substrate 1 is a semiconductor substrate, and the formation material of the substrate 1 includes but is not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate.
  • the substrate 1 is a single crystal substrate When the substrate or polycrystalline substrate is used, it may also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it may be an N-type polysilicon substrate or a P-type polysilicon substrate.
  • the substrate 1 is provided with a shallow trench isolation structure, the shallow trench isolation structure defines a plurality of active regions, the active region is provided with a transistor, and the transistor includes a gate electrode, a source electrode and a drain electrode.
  • the gate is used for connecting with the word line
  • the source is used for connecting with the capacitor
  • the drain is used for connecting with the bit line.
  • the specific structures of the transistors and the word lines may adopt existing conventional structures, which will not be described here.
  • the bit line unit 2 and the capacitor contact 3 can be of various existing structures.
  • FIG. 4 which is a schematic structural diagram of a bit line unit 2 in an embodiment, the bit line unit 2 includes a bit line contact layer 21 , a first barrier layer 22 , a bit line contact layer 21 , a first barrier layer 22 , The bit line metal layer 23 , the bit line insulating layer 24 and the second barrier layer 25 .
  • the bit line contact layer 21, the first barrier layer 22, and the bit line metal layer 23 constitute the bit line structure layer
  • the bit line insulating layer 24 and the second barrier layer 25 constitute the bit line protection layer, that is, the bit line protection layer It is located on the side of the bit line structure layer away from the substrate.
  • the bit line contact layer 21 is used to connect the bit line metal layer 23 and the drain of the transistor.
  • the material of the bit line contact layer 21 may be polysilicon or the like.
  • the first blocking layer 22 is used to prevent metal ions from diffusing into the substrate 1 when the bit line metal layer 23 is prepared, so as to protect the substrate 1 .
  • voids may be generated, and the first barrier layer 22 can also be used as an adhesion layer to reduce the generation of voids and defects.
  • the material of the first barrier layer 22 may be titanium nitride or the like.
  • the bit line metal layer 23 is the bit line, and its material can be a metal material with good conductivity, such as tungsten.
  • the bit line insulating layer 24 plays an insulating and protective role on the bit line metal layer 23 to prevent short circuit between the bit line unit 2 and the upper conductive layer 4 .
  • the material of the bit line insulating layer 24 may be silicon nitride or the like.
  • the function of the second barrier layer 25 is similar to that of the first barrier layer 22. On the one hand, it can prevent metal ions from diffusing into the substrate 1 when the upper conductive layer 4 is prepared, and on the other hand, it can also serve as an adhesion layer for the upper and lower layers.
  • the material of the first barrier layer 22 may be the same or different.
  • the capacitive contact 3 includes a capacitive contact layer 31 , a metal conductive layer 32 and a first layer formed on the substrate 1 in sequence from bottom to top. Three barrier layers 33 .
  • the capacitive contact layer 31 is used to connect the storage capacitor 6 and the source of the transistor.
  • the material of the capacitive contact layer 31 may be polysilicon or the like.
  • the metal conductive layer 32 acts as an ohmic contact between the conductive layer 4 and the capacitive contact layer 31 for reducing the contact resistance.
  • the material of the metal conductive layer 32 may be cobalt silicide (CoSix).
  • the third barrier layer 33 has the same function as the second barrier layer 25, except that the third barrier layer 33 should have conductivity, so that the upper conductive layer 4 can be electrically connected to the lower film layer.
  • the material thereof is preferably titanium nitride.
  • the material of the third barrier layer 33 and the second barrier layer 25 are the same, they can be formed in the same process and can be connected as a whole film layer as shown in the figure.
  • the part of the bit line unit 2 higher than the capacitor contact 3 is the bit line protection layer, and the bottom surface of the bit line protection layer is not higher than the bottom surface of the groove 94 .
  • one bit line unit 2 and one capacitive contact 3 belong to the same access unit, and of course, the access unit also includes structures such as transistors, word lines and the like connected to them. As shown in the figure, adjacent bit line units 2 and capacitor contacts 3 are insulated from each other, so insulating sidewalls 7 may be formed therebetween, and the material of the insulating sidewalls 7 may be silicon nitride or the like.
  • the above-mentioned film layer can be formed by chemical deposition, physical deposition, atomic deposition, liquid epitaxy and other methods, which will not be repeated here.
  • bit line unit 2 since the bit line unit 2 has more film layers than the capacitor contact 3 and has a higher height, the capacitor contact 3 between two adjacent bit line units 2 will be formed above the capacitor contact 3 as shown in FIG. 4 . groove 94.
  • the conductive layer 4 fills the groove 94 .
  • the conductive layer 4 is used to connect the storage capacitor 6 and the capacitor contact 3, and its material is preferably metal tungsten.
  • the metal tungsten has good step coverage and gap filling properties, and can form a film layer with good electrical connection characteristics.
  • the film layer can be formed by chemical deposition, physical deposition and other methods. In the process of depositing metal tungsten, the precursor WCl 6 dissociates to generate Cl ⁇ , and the third barrier layer 33 provided in the capacitive contact 3 can prevent Cl ⁇ from diffusing into the silicon substrate 1 and causing damage to the silicon substrate 1 .
  • Step S200 etching the portion of the conductive layer 4 corresponding to the groove to form a first trench 92 corresponding to each access unit in the conductive layer 4.
  • the first trench 92 is close to The sidewalls of the bitline cells are farther from the bitline cells 2 than the same sidewalls of the grooves 94 .
  • FIG. 7 which is a schematic cross-sectional structure of the first trench, in an access cell, the sidewall of the first trench 92 close to the bit line cell is farther from the bit line cell than the sidewall of the same side of the groove. 2, it means that the left side wall of the first groove 92 in the figure is located on the right side of the left side wall of the groove.
  • a conductive layer of a certain thickness can be reserved on the left side of the groove during subsequent downward etching, so as to form
  • the second conductive portion 42 can make the first conductive portion 41 further to the right in the horizontal direction, which can help to form the closest hexagonal stacking of the capacitors 6 above.
  • the unetched portion above the bit line unit 2 is the first conductive portion 41 .
  • this application only defines the position of the left side wall of the first groove, and the position of the right side wall is not limited.
  • the left side wall of the first groove 92 is located in the concave Above the groove, the right side wall is located above the adjacent bit line unit 2.
  • the position of the side wall of the first trench 92 in the figure is only an example. In other embodiments, the position of the right side wall can also be moved to the left. to be flush with the left side wall of the right adjacent bit line cell.
  • the width of the first trench 92 needs to be controlled to not only ensure that the first conductive part 41 has a sufficient contact area, but also have a sufficient insulation distance from the first conductive part 41 of the adjacent access cells ; At the same time, a sufficient thickness of the second conductive layer 42 can be retained.
  • step S200 further include:
  • Step S210 as shown in FIG. 6 , the first etching is performed on the portion of the conductive layer 4 corresponding to the groove to form an initial trench 91 corresponding to each access unit.
  • the sidewalls are farther from the bit line cell 2 than the sidewalls on the same side of the groove.
  • the shape of the initial trench 91 formed in this step is a trench with a uniform width as shown in the figure.
  • the trench formed in this step is higher than the bit line unit 2 .
  • step S220 the initial trench 91 etched for the first time is etched downward again.
  • parameters such as the angle of etching are adjusted so that the newly etched trench is close to the sidewall of the bit line unit (ie The left side wall in the figure) forms an arc surface in the groove depth direction (vertical direction), and the arc surface gradually approaches the opposite side wall in the direction toward the bottom of the trench, that is, the left side of the newly etched trench.
  • the lower the side wall is, the closer to the right side wall, that is to say, the width of the trench etched in this step is narrower as it goes down.
  • the final complete first trench 92 is formed after two etchings. groove shape.
  • the present application only defines the lower part of the left side wall of the first groove as an arc surface, and the shape of the right side wall is not limited, which may be a vertical surface as shown in the figure, or may also have a certain arc .
  • the formation of the first trench by two-step etching can enable a smooth transition between the second conductive portion 42 and the first conductive portion 41 formed subsequently.
  • the bottom of the first trench 92 finally formed in this step is already lower than the upper surface of the bit line unit 2. Since the etching gas is for the conductive layer 4, the bit line unit 2 on the right will not be A part of the sidewall of the first trench 92 formed by etching is the conductive layer 4 , and the other part is the bit line unit 2 .
  • dry etching is used when etching the first trench 92, and the etching gas is preferably a mixed gas of sulfur hexafluoride, chlorine, nitrogen and oxygen, which has an ideal etching effect on metal tungsten.
  • wet etching can also be used in other embodiments.
  • Step S300 forming the protective layer 8 on the sidewall of the first trench 92 .
  • the method of forming the protective layer 8 on the first trench 92 is to deposit a protective material 81 on the conductive layer 4 first, and the protective material 81 will cover the first conductive portion 41 and the first trench 92 . sidewall and bottom surface, as shown in Figure 8. Then, the protective material 81 covering the first conductive portion 41 and the bottom surface of the first trench 92 is etched away, and the protective material 81 covering the sidewall of the first trench 92 remains to form the protective layer 8 . As shown in FIG. 9 , the shape of the protective layer 8 is consistent with the shape of the sidewall of the first trench 92 and can protect the vertical surface and the arc surface of the first trench.
  • the thickness of the protective layer 8 is preferably 5-10 nm, and the protective layer 8 of this thickness can play an ideal protective effect on the sidewall of the first trench 92, and at the same time, it is not easy to affect the subsequent etching.
  • the material of the protective layer 8 formed on the sidewall of the first trench 92 includes, but is not limited to, silicon nitride, silicon dioxide, silicon oxynitride, titanium nitride, titanium dioxide, zirconium dioxide, polysilicon, etc., and can be any of the above materials It can also be a mixture of any of them.
  • the protective layer 8 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDCVD), metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition deposition (PECVD) and other deposition processes.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • HDCVD high density plasma chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition deposition
  • the etching gas is preferably a mixed gas of tetrafluoroethane, argon and oxygen, which has an ideal etching effect on the protective layer 8 of the above materials.
  • the ratio of tetrafluoroethane, argon and oxygen is 5:1:1, which has an ideal etching effect on the protective layer 8 .
  • Step S400 continue to etch the first trench 92 downward, etch away part of the conductive layer 4 located in the groove, and retain the second conductive portion 42 and the concave portion covering the sidewall of the bit line unit 2 .
  • the third conductive portion 43 at the bottom of the groove forms the second groove 93 .
  • the conductive layer covering the sidewall of the bit line unit and connected to the first conductive portion 41 is the second conductive portion 42
  • the conductive layer covering the bottom of the groove and connected to the second conductive portion 42 is the third conductive portion 43 .
  • the second conductive portion 42 and the third conductive portion 43 are divided as shown by the dotted frame in FIG. 10 .
  • the right side wall of the first trench 92 is located on the adjacent bit line unit, part of the structure of the bit line unit 2 will also be etched away when the downward etching is continued.
  • the etched part of the bit line unit 2 is a part of the bit line protection layer. Specifically, a part of the silicon nitride layer and the titanium nitride layer in the bit line protection layer are both etched away. Since the bottom surface of the bit line protection layer is not higher than the bottom surface of the groove, a certain thickness of silicon nitride and titanium nitride are still reserved at the bottom of the bit line protection layer to protect the underlying bit line structure layer.
  • the bit line unit is etched to a certain extent, so that the width of the second trench is larger, and the subsequently formed insulating layer has a larger area and good insulating effect. Since the widths of the first trenches 92 and the second trenches 93 will affect the width of the upper surface of the adjacent bit line unit, and then affect the area of the adjacent first conductive portion 41, the first trench should be well controlled during etching. 92 and the width of the second trench 93 to take into account the area of the insulating layer and the area of the first conductive portion.
  • the etching process in this step due to the protection of the protective layer 8, the sidewalls of the first trench 92 will not be affected. Therefore, when etching downwards, the etching will be performed along the bottom of the protective layer 8. , that is, the etching is performed downward according to the minimum width of the first trench 92, so that the width of the formed second trench 93 is narrower, and the thickness of the remaining conductive layer on the sidewall of the corresponding groove is thicker, that is, the second trench 93 has a narrower width.
  • the conductive portion 42 is thicker, so cracking is less likely to occur here.
  • the contact area between the bottom of the second conductive part 42 and the third conductive part 43 is obviously larger, so it is no longer sensitive to the influence factors of the alignment process offset of the photolithography process during etching, and a wider process can be obtained. alignment process space.
  • the bottom of the first groove 92 is in a constricted shape, the second conductive portion 42 and the first conductive portion 41 can form a smooth transition.
  • the shape of the second trench 93 is shown in FIG. 10 , a part of the sidewall is the conductive layer 4 , and the other part of the sidewall is the bit line unit 2 .
  • etching dry etching is preferably used, which can achieve the purpose of ideal selective etching.
  • the conductive layer 4 and the bit line unit 2 that is, various materials such as metal tungsten, silicon nitride, titanium nitride, etc.
  • the etching gas is preferably a mixture of tetrafluoroethane, argon and oxygen Among them, tetrafluoroethane has a good etching effect on the silicon nitride, titanium nitride and other materials of the bit line unit 2, and argon and oxygen have a good etching effect on the metal tungsten of the conductive layer 4,
  • the content of different etching gases can be adjusted according to the material to be etched to meet the etching requirements for forming the structure in the figure, preferably the ratio of tetrafluoroethane, argon and oxygen is (3-5): 1: 1, Within this range, it is more favorable to obtain the shape of the second trench 93 shown in the figure if the above-mentioned film layers have a similar etching rate.
  • Step S500 as shown in FIG. 11 , the protective layer 8 is removed.
  • the protective layer 8 may be removed by etching.
  • the etching gas is preferably a mixed gas of tetrafluoroethane, argon and oxygen in a ratio of 5:1:1. In other embodiments, other removal processes such as wet etching may also be used. Since the material targeted by the etching gas is the protective layer 8, the conductive layer material will not be erroneously etched when the protective layer 8 is removed, and the thickness of the second conductive portion 42 will not be thinned or even broken.
  • step S600 a storage capacitor 6 is formed on the side of the conductive layer 4 away from the substrate 1 , so that the storage capacitor 6 is in contact with the conductive layer 4 .
  • this step may further include the following steps:
  • step S610 an insulating layer is deposited in the second trench.
  • the material of the insulating layer may be the same as the material of the insulating sidewall 7, which will not be repeated here.
  • the upper surface of the insulating layer 5 may be flush with the upper surface of the first conductive part 41 .
  • Step S620 referring to FIG. 13 , a support layer 10 is formed over the conductive layer and the insulating layer 5 .
  • the support layer 10 covers the first conductive portion 41 and the insulating layer 5, and is used to form a support structure for the storage capacitor formed subsequently.
  • Step S630 etching the through capacitor hole 101 at the position of the support layer 10 corresponding to the first conductive portion 41 to expose the first conductive portion 41 , as shown in FIG. 13 .
  • a storage capacitor 6 is formed in the capacitor hole 101.
  • the storage capacitor 6 includes a lower electrode 61, a dielectric layer 62, and an upper electrode 63.
  • the lower electrode 61 is in contact with the first conductive portion 41, and is then electrically connected to the capacitor contact 3. , as shown in Figure 14.
  • the structure of the storage capacitor 6 in the figure is only an example, and it may also have other structures, which will not be listed one by one here.
  • the conductive layer formed by the above method can form a thick second conductive portion 42, and the thickness can reach 20-30 nm.
  • the thickness of the second conductive portion is only about 15 nm.
  • the second conductive portion 42 formed by the method of the present application is not prone to breakage, which can ensure that the storage capacitor 6 and the capacitive contact 3 can form a good electrical contact, thereby realizing data access. There is a lower contact resistance between the capacitive contacts, thereby improving the data transmission efficiency of the access unit.
  • the contact area between the bottom of the second conductive part 42 and the third conductive part 43 formed by the above method is obviously larger, so it is no longer sensitive to the influence factors of the alignment process offset of the photolithography process during etching. A wider alignment process space can be obtained. Therefore, the method can take into account both the size requirements of semiconductor devices gradually shrinking and the high requirements of storage performance.
  • Embodiments of the present disclosure also provide a semiconductor device, which is fabricated by the above method.
  • the semiconductor device prepared by the above method includes a substrate 1 on which a plurality of bit line units 2 and a plurality of capacitive contacts 3 are arranged; a plurality of bit line units 2 and a plurality of capacitive contacts 3 are alternately arranged one by one and are insulated from each other by insulating sidewalls 7, the height of the bit line unit 2 is higher than the height of the capacitive contact 3, and there is a groove between two adjacent bit line units 2; the substrate 1 is also provided with The conductive layer 4 covering the bit line unit 2 and the capacitive contact 3, the conductive layer 4 includes a first conductive part 41 located on the bit line unit 2, a second conductive part 42 covering one of the side walls of the groove, and covering the bottom surface of the groove In the third conductive part 43, the three conductive parts are connected as a whole, and the division of the three conductive parts may refer to the dotted frame in
  • the remaining part of the groove is filled with an insulating layer 5, a support layer 10 is provided on the insulating layer 5 and the conductive layer, and a capacitor hole 101 is opened in the support layer 10 at the position of the first conductive portion 41, and a capacitor 6 is arranged in the capacitor hole 101,
  • the lower electrode 61 of the capacitor 6 is in contact with the first conductive portion 41 and is further electrically connected to the capacitor contact 3 .
  • the thickness of the second conductive portion 42 of the semiconductor device is relatively thick, which can reach 20-30 nm, is not easy to break, and has a low contact resistance, which can ensure that the storage capacitor 6 and the capacitor contact 3 can form a good electrical contact, thereby improving the storage capacity.
  • the data transfer efficiency of the fetch unit can also form the closest hexagonal stacking of the storage capacitors 6, which is beneficial to further reduce the size of the semiconductor device.

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Abstract

本公开提供一种半导体器件及其制备方法，该制备方法包括，提供一衬底，在衬底上形成位线单元、电容触点和导电层，采用分步刻蚀的方式对衬底上的导电层进行图案化处理，先刻蚀第一沟槽形成位于位线单元上方的第一导电部，对第一沟槽侧壁进行保护后再刻蚀第二沟槽，形成覆盖位线单元侧壁的第二导电部和覆盖电容触点的第三导电部，该方法形成的导电层第二导电部处较厚，不容易发生断裂，可以保证电容和电容触点能形成良好的电接触。

Description

半导体器件及其制备方法
交叉引用
本公开要求于2020年9月14日提交的申请号为202010962471.6名称为“半导体器件及其制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件及其制备方法。
背景技术
动态随机存取存储器((Dynamic Random Access Memory，DRAM)是一种常用的存储器，随着DRAM单元数组上的存储电容区域的微缩，DRAM的制备对光刻工艺的精度要求越来越高，光刻工艺对位不匹配对DRAM的影响也越来越大。
电容与电容触点之间通过导电层实现电连接。在制备过程中，需要对导电层进行图案化处理，利用光刻工艺进行图案化时，如果出现对准偏差，会造成存储电容的下电极层与电容触点发生相对的移动，则会导致导电层图案变形，导电层阻值变大，严重的时候甚至断裂，最终导致存储电容和电容触点的接触面积缩小，接触电阻变大，降低了动态随机存取存储器单元数组的传输效率。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种半导体器件及其制备方法。
根据本公开的一个方面，提供一种半导体器件的制备方法，包括：
提供一衬底，所述衬底上形成有多个存取单元，所述存取单元包括一个位线单元和一个电容触点；所述多个存取单元的各位线单元和各电容触点一一交替设置且相互绝缘，所述位线单元的高度高于所述电容触点的高度，以使相邻两个所述位线单元之间形成凹槽；所述衬底上还形成有覆盖各所述存取单元的导电层，所述导电层填充各所述凹槽；
对所述导电层对应于所述凹槽的部分进行刻蚀，以在所述导电层内形成对应于各所述存取单元的第一沟槽；所述存取单元内，所述第一沟槽靠近所述位线单元的侧壁相比所述凹槽的同一侧侧壁远离所述位线单元；
在所述第一沟槽侧壁上形成保护层，
对所述第一沟槽继续向下刻蚀，刻蚀掉位于所述凹槽内的部分导电层，保留覆盖所述位线单元侧壁和凹槽底部的导电层，以形成第二沟槽；其中，位于所述位线单元上方的导电层为第一导电部，覆盖所述位线单元侧壁且与所述第一导电部连接的导电层为第二导电部，覆盖所述凹槽底部且与所述第二导电部连接的导电层为第三导电部；
去除所述保护层；
在所述第一导电部背离所述衬底的一侧形成存储电容，使所述存储电容与所述第一导电部接触。
在本公开的一种示例性实施方式中，所述在所述导电层内形成对应于各所述存取单元的第一沟槽包括：
对所述导电层对应于各所述凹槽的部分进行第一次刻蚀，形成多个初始沟槽，使各所述存取单元内，所述初始沟槽靠近所述位线单元的侧壁相比所述凹槽的同一侧侧壁远离所述位线单元；
对所述初始沟槽再次向下刻蚀，使新刻蚀的沟槽靠近所述位线单元的侧壁在所述沟槽深度方向上形成一弧面，所述弧面在朝向所述沟槽底部的方向上逐渐靠近相对的另一个侧壁，得到所述第一沟槽。
在本公开的一种示例性实施方式中，在所述导电层的第一沟槽侧壁上形成保护层包括：
在所述导电层上沉积保护材料，使所述保护材料覆盖所述导电层上表面以及第一沟槽的侧壁和底面；
刻蚀掉覆盖在所述导电层上表面和所述第一沟槽底面的保护材料，保留覆盖在所述第一沟槽侧壁的保护材料，形成所述保护层。
在本公开的一种示例性实施方式中，所述位线单元包括在衬底上形成的位线结构层和位于所述位线结构层背离所述衬底一侧的位线保护层，所述位线保护层的底面不高于所述凹槽底面；
刻蚀位于所述凹槽内的部分导电层形成所述第二沟槽的同时，还刻蚀掉所述位线保护层的一部分。
在本公开的一种示例性实施方式中，所述保护材料为氮化硅、二氧化硅、氮氧化硅、氮化钛、二氧化钛、二氧化锆、多晶硅中的一种或任意多种的混合物。
在本公开的一种示例性实施方式中，所述保护层的厚度为5-10nm。
在本公开的一种示例性实施方式中，形成所述第一沟槽的刻蚀气体为六氟化硫、氯气、氮气和氧气的混合气体。
在本公开的一种示例性实施方式中，形成所述第二沟槽的刻蚀气体和刻蚀所述保护层的刻蚀气体为四氟乙烷、氩气和氧气的混合气体。
在本公开的一种示例性实施方式中，所述形成存储电容包括：
在所述第二沟槽内填充绝缘层；
在所述导电层和所述绝缘层上方形成支撑层；
在所述支撑层对应于所述第一导电部的位置处形成贯穿的电容孔，所述电容孔暴露出所述第一导电部；
在电容孔内依次形成电容的下电极、介质层和上电极，所述下电极与所述第一导电部接触。
根据本公开的另一个方面，提供一种半导体器件，由以上所述的制备方法得到。
本公开的半导体器件的制备方法中，在对衬底上的导电层进行图案化处理时，采用分步刻蚀的方式，可以灵活调整每一步刻蚀气体的成分、刻蚀时间、速率等参数，使得导电层可以刻蚀出理想的形状。在形成竖向的第二导线部时，由于设置有保护层，该步刻蚀不会对第二导线部造成影响，从而使第二导线部较粗，这样导电层不容易在此处发生断裂，也不容易因此处过窄而使得电阻增大，保证足够的接触面积和较低的接 触电阻，同时制备过程中对光刻工艺对准精度的要求得以降低，从而提高了良品率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施方式的一种半导体器件的俯视图；
图2为图1中A-A向的截面示意图；
图3为本公开实施方式半导体器件的制备方法流程图；
图4为本公开实施方式形成位线单元和电容触点的结构示意图；
图5为本公开实施方式形成导电层的结构示意图；
图6为本公开实施方式形成初始沟槽的结构示意图；
图7为本公开实施方式形成第一沟槽的结构示意图；
图8为本公开实施方式沉积保护材料的结构示意图；
图9为本公开实施方式形成保护层的结构示意图；
图10为本公开实施方式形成第二沟槽的结构示意图；
图11为本公开实施方式去除保护层的结构示意图；
图12为本公开实施方式形成绝缘层的结构示意图；
图13为本公开实施方式形成电容孔的结构示意图；
图14为本公开实施方式形成存储电容的结构示意图。
图中：1、衬底；2、位线单元；3、电容触点；4、导电层；5、绝缘层；6、存储电容；10、支撑层；21、位线接触层；22、第一阻隔层；23、位线金属层；24、位线绝缘层；25、第二阻隔层；31、电容接触层32、金属导电层；33、第三阻隔层；41、第一导电部；42、第二导电部；43、第三导电部；101、电容孔；61、下电极；62、介电层；63、上电极；7、 绝缘侧壁；8、保护层；81、保护材料；91、初始沟槽；92、第一沟槽；93、第二沟槽；94、凹槽。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
相关技术中，图1所示，为一种半导体器件的结构俯视图，图中示出了部分电容分布结构，图2为图1中A-A向的截面示意图，示出了包含两个电容的截面示意图。该半导体器件在衬底1上设有多个位线单元2和多个电容触点3，多个位线单元2和多个电容触点3一一交替设置且相互绝缘。由于位线单元2的膜层通常比电容触点3的膜层多，厚度更厚，也就是说位线单元2的高度高于电容触点3的高度，因此相邻两个位线单元2之间会形成凹槽。需要说明的是，位线单元高度是指，位线单元上表面到衬底的距离；同理，电容触点高度是指，电容触点上表面到衬底的距离。
以其中一个存储电容6及其对应的位线单元2和电容触点3所在的存取单元为例进行说明，电容触点3上方设有导电层4和绝缘层5，绝缘层5用于将相邻两个存取单元的导电层4隔绝。导电层4和绝缘层5上方设置支撑层10，支撑层10内开设有上下贯穿的电容孔，电容孔暴露出导电层4。电容孔内设置存储电容6，存储电容6通过导电层4与电容触点3形成电连接。为了使存储电容6形成如图1所示的六方最密堆积，存储电容6需要和电容触点3错开排布，也就是说，存储电容6不位于电容触点3的正上方，而是朝向位线单元偏移，如图1中所示，圆圈代表存储电容6，虚线框代表下方电容触点3的位置。对应的，导电层4也需要朝向位线单元偏移，因此，导电层4需设计成如图2中虚线框所示的形状，即包括依次连接的第一导电部41、第二导电部42和第三导电部43，第一导电部41位于位线单元2的上方，第二导电部42覆盖凹槽 的左侧壁，第三导电部43覆盖凹槽的底部。电容位于第一导电部41的上方，从而通过三个导电部与电容触点实现电连接。凹槽内其余部分由绝缘层5填充。
在制备上述结构的半导体器件时，为了形成上述导电层4的形状，需要对导电层4进行连续的图案化处理，在图案化过程中，通常利用光刻工艺进行制备，当光刻工艺出现对准偏差时，会使得第二导电部42较细，导致存储电容6和电容触点3的接触电阻变大，降低了该存取单元的数据传输效率。严重的时候第二导电部42甚至会断裂，存储电容6和电容触点3无法接触，最终导致该存取单元无法存取数据。
为解决上述问题，本公开实施方式提供了一种半导体器件的制备方法，参照图3，该制备方法包括以下步骤：
步骤S100，提供一衬底1，衬底1上形成有多个存取单元，存取单元包括一个位线单元2和一个电容触点3；多个存取单元的各位线单元2和各电容触点3一一交替设置且相互绝缘，位线单元2的高度高于电容触点3的高度，以使相邻两个位线单元2之间形成凹槽；衬底1上还形成有覆盖各存取单元的导电层4，导电层4填充凹槽。
步骤S200，对导电层4对应于凹槽的部分进行刻蚀，以在导电层4内形成对应于各存取单元的第一沟槽92，任一存取单元内，第一沟槽92靠近位线单元的侧壁相比所述凹槽的同一侧侧壁远离所述位线单元2。
步骤S300，在第一沟槽92侧壁上形成保护层8。
步骤S400，对第一沟槽92继续向下刻蚀，刻蚀掉位于凹槽内的部分导电层4，保留覆盖位线单元2侧壁和凹槽底部的导电层4，以形成第二沟槽93。其中，位于位线单元上方的导电层为第一导电部，覆盖位线单元侧壁且与第一导电部连接的导电层为第二导电部，覆盖凹槽底部且与第二导电部连接的导电层为第三导电部。
步骤S500，去除保护层8。
步骤S600，在第一导电部42背离衬底1的一侧形成存储电容6，使存储电容6与第一导电部42接触。
本公开的方法在对衬底1上的导电层4进行图案化处理时，采用分步刻蚀的方式，先刻蚀导电层4形成第一沟槽92，顶部未刻蚀的部分作 为与电容6相连的第一导电部41；然后对第一沟槽92侧壁进行保护，再继续向下刻蚀导电层4形成第二沟槽93，去掉保护层8后，形成竖向第二导电部42和底部的第三导电部43，最终得到导电层4。由于采用了分步刻蚀的方法，可以灵活调整每一步刻蚀气体的成分、刻蚀时间、速率等参数，使得导电层4的三部分都可以刻蚀出理想的形状。尤其是在进行第二步刻蚀时，由于设置有保护层8，该步刻蚀不会对导电层4侧壁造成影响，从而使得最终形成的竖向的第二导电部42的厚度较厚，这样导电层4不容易在此处发生断裂，也不容易因第二导电部42过窄而使得电阻增大，从而可以保证存储电容6和电容触点3能形成良好的电接触，保证足够的接触面积和较低的接触电阻。制备过程中对光刻工艺对准精度的要求得以降低，从而提高了良品率。
下面参照图4-图14，对本公开实施方式的半导体器件的制备方法逐步进行详细说明：
步骤S100，提供一衬底1，如图4所示，衬底1上形成有多个存取单元，存取单元包括位线单元2和电容触点3；多个存取单元中的各位线单元2和各电容触点3一一交替设置且相互绝缘，位线单元2的高度大于电容触点3的高度，以使相邻两个位线单元2之间形成凹槽94。衬底1上还形成有覆盖各存取单元的导电层4，导电层4填充各凹槽94；
本步骤中，衬底1为半导体衬底，衬底1的形成材料包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，衬底1为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。
衬底1上设置有浅沟槽隔离结构，浅沟槽隔离结构定义出多个有源区，有源区设置有晶体管，晶体管包括栅极、源极和漏极。其中，栅极用于与字线连接，源极用于与电容连接，漏极用于与位线连接。晶体管与字线的具体结构可采用现有的常规结构，此处不再介绍。
位线单元2和电容触点3可以为现有的各种结构。如图4所示，为实施例中的一种位线单元2的结构示意图，该位线单元2包括在衬底1上由下至上依次形成的位线接触层21、第一阻隔层22、位线金属层23、位线绝缘层24和第二阻隔层25。其中，位线接触层21、第一阻隔层22、 位线金属层23组成位线结构层，位线绝缘层24和第二阻隔层25组成位线保护层，也就是说，位线保护层位于位线结构层背离衬底的一侧。位线接触层21用于将位线金属层23和晶体管的漏极连接。位线接触层21的材料可以是多晶硅等。第一阻隔层22用于防止制备位线金属层23时金属离子扩散至衬底1中，对衬底1起到保护作用。另外，由于上方位线金属层23附着能力差，会产生空隙，第一阻隔层22还可以作为黏附层减少空隙的产生，减少缺陷。第一阻隔层22的材料可以是氮化钛等。位线金属层23即为位线，其材料可以为导电性较好的金属材料，例如钨。位线绝缘层24对位线金属层23起绝缘保护作用，防止位线单元2与上方的导电层4形成短路。位线绝缘层24的材料可以是氮化硅等。第二阻隔层25与第一阻隔层22的作用相似，一方面可以防止制备上方导电层4时金属离子扩散至衬底1中，另一方面还可以作为上下两层的黏附层。其材料可以与第一阻隔层22相同，也可以不同。
如图4所示，为实施例中的一种电容触点3的截面结构示意图，该电容触点3包括在衬底1上由下至上依次形成的电容接触层31、金属导电层32和第三阻隔层33。电容接触层31用于将存储电容6和晶体管的源极连接。电容接触层31的材料可以是多晶硅等。金属导电层32在导电层4和电容接触层31之间起到欧姆接触的作用，用于降低接触电阻。金属导电层32的材料可以是硅化钴(CoSix)。第三阻隔层33与第二阻隔层25的作用相同，除此之外，第三阻隔层33应当具有导电性，以使上方导电层4能与下方膜层电连接。其材料优选氮化钛。当第三阻隔层33与第二阻隔层25材料相同时，可以在同一步工艺中形成且可以连接为如图所示的一整面膜层。本实施方式中，位线单元2高出电容触点3的部分为位线保护层，位线保护层的底面不高于凹槽94的底面。
需要说明的是，一个位线单元2和一个电容触点3属于同一个存取单元，当然该存取单元还包括与其对应连接的晶体管、字线等结构。如图所示，相邻的位线单元2和电容触点3之间相互绝缘，因此在二者之间可以形成绝缘侧壁7，绝缘侧壁7的材料可以是氮化硅等。
上述膜层可采用化学沉积、物理沉积、原子沉积和液向外延法等多种方法形成，此处不再赘述。
在本实施例中，由于位线单元2的膜层比电容触点3多，高度更高，因此两个相邻的位线单元2之间的电容触点3上方会形成如图4所示的凹槽94。
如图5所示，在衬底1上形成有覆盖位线单元2和电容触点3的导电层4时，使导电层4填充凹槽94。导电层4用于连接存储电容6和电容触点3，其材料优选为金属钨，金属钨具有良好的阶梯覆盖和缝隙填充性能，能够形成具有良好电连接特性的膜层。该膜层可以采用化学沉积、物理沉积等方法形成。在沉积金属钨的过程中，前驱体WCl 6解离会产生Cl -，电容触点3中设置的第三阻隔层33能够防止Cl -扩散到硅衬底1中对硅衬底1造成损伤。
步骤S200，对导电层4对应于凹槽的部分进行刻蚀，以在导电层4内形成对应于各存取单元的第一沟槽92，任一存取单元内，第一沟槽92靠近位线单元的侧壁相比凹槽94的同一侧侧壁远离位线单元2。
如图7所示，为第一沟槽的一种截面结构示意图，在一存取单元内，第一沟槽92靠近位线单元的侧壁相比凹槽的同一侧侧壁远离位线单元2，是指图中第一沟槽92的左侧壁位于凹槽左侧壁的右侧，一方面可以在后续向下刻蚀时凹槽内左侧能够保留一定厚度的导电层，以便形成第二导电部42，另一方面可以使第一导电部41在水平方向上更靠右侧，如此可以有助于使上方的电容6形成最密六方堆积。本步骤中，参考图中虚线框所示，位线单元2上方未被刻蚀的部分为第一导电部41。需要说明的是，本申请仅限定第一沟槽左侧壁的位置，而右侧壁的位置未进行限定，在图中所示的实施方式中，第一沟槽92的左侧壁位于凹槽上方，右侧壁位于相邻的位线单元2上方，该图中第一沟槽92的侧壁位置仅为一种示例，在其他实施例中，其右侧壁位置也可以向左移动至与右侧相邻位线单元的左侧壁平齐。需要注意的是，第一沟槽92的宽度需要控制在既能保证第一导电部41具有足够的接触面积，又能够与相邻存取单元的第一导电部41之间具有足够的绝缘距离；同时还能保留足够厚度的第二导电层42。
在本实施例中，为了使后续形成的第二导电部42更厚，在导电层4内形成对应于各存取单元的第一沟槽92时分为两步进行刻蚀，因此，步 骤S200进一步包括：
步骤S210，如图6所示，对导电层4对应于凹槽的部分进行第一次刻蚀，形成对应于各存取单元的初始沟槽91，各存取单元内，初始沟槽91的侧壁相比凹槽的同一侧侧壁远离位线单元2。该步骤形成的初始沟槽91形状如图所示为宽度一致的沟槽。本步骤形成的沟槽高于位线单元2。
步骤S220，对第一次刻蚀的初始沟槽91再次向下刻蚀，本次刻蚀时，调整刻蚀的角度等参数，使新刻蚀的沟槽靠近位线单元的侧壁(即图中左侧壁)在沟槽深度方向(竖直方向)上形成一弧面，该弧面在朝向沟槽底部的方向上逐渐靠近相对的另一个侧壁，即新刻蚀的沟槽左侧壁越向下越靠近右侧壁，也就是说，本步骤刻蚀的沟槽宽度越向下越窄，如图7所示，最终形成的完整的第一沟槽92为两次刻蚀后形成的沟槽形状。需要说明的是，本申请仅限定第一沟槽左侧壁下部分为弧面，而右侧壁的形状未进行限定，其可以为如图所示的竖直面，也可以也具有一定弧度。本步骤通过两步刻蚀形成第一沟槽可以使后续形成的第二导电部42和第一导电部41之间能够光滑过渡。如图所示，本步骤最终形成的第一沟槽92底部已经低于位线单元2的上表面，由于刻蚀气体是针对导电层4的气体，因此右侧的位线单元2不会被刻蚀，形成的第一沟槽92的侧壁一部分为导电层4，另一部分为位线单元2。
本实施方式刻蚀第一沟槽92时采用干法刻蚀，刻蚀气体优选为六氟化硫、氯气、氮气和氧气的混合气体，该混合气体对金属钨具有理想的刻蚀效果。当然在其他实施方式中也可以采用湿法刻蚀。
步骤S300，在第一沟槽92侧壁上形成保护层8。
本实施例中，在第一沟槽92上形成保护层8的方法为，先在导电层4上沉积保护材料81，保护材料81会覆盖在第一导电部41上以及第一沟槽92的侧壁和底面上，如图8所示。然后刻蚀掉覆盖在第一导电部41上和第一沟槽92底面的保护材料81，保留覆盖在第一沟槽92侧壁的保护材料81，形成保护层8。保护层8的形状如图9所示，与第一沟槽92的侧壁形状吻合，能够保护住第一沟槽的竖直面和弧面。保护层8的厚度优选5-10nm，该厚度的保护层8能对第一沟槽92侧壁起到理想的 保护作用，同时又不易影响后续刻蚀。
在第一沟槽92侧壁上形成的保护层8的材料包括但不限于氮化硅、二氧化硅、氮氧化硅、氮化钛、二氧化钛、二氧化锆、多晶硅中等，可以是上述材料中的一种，也可以是其中任意多种的混合物。保护层8可以通过化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度等离子化学气相沉积(HDCVD)、金属有机化学气相沉积(MOCVD)、等离子体增强化学气相沉积(PECVD)等沉积工艺形成。
该步刻蚀优选采用干法刻蚀，可以达到理想的选择性刻蚀的目的。由于需要刻蚀掉的材料是保护层8，因此刻蚀气体优选为四氟乙烷、氩气和氧气的混合气体，该混合气体对上述材料的保护层8都具有理想的刻蚀效果。优选四氟乙烷、氩气和氧气的比例为5：1：1，该比例对保护层8具有理想的刻蚀效果。
步骤S400，如图10所示，对第一沟槽92继续向下刻蚀，刻蚀掉位于凹槽内的部分导电层4，保留覆盖位线单元2侧壁的第二导电部42和凹槽底部的第三导电部43，以形成第二沟槽93。其中，覆盖位线单元侧壁且与第一导电部41连接的导电层为第二导电部42，覆盖凹槽底部且与第二导电部42连接的导电层为第三导电部43。第二导电部42和第三导电部43见图10中虚线框所示的划分。
本步骤中，由于第一沟槽92的右侧壁位于相邻的位线单元上，因此在继续向下刻蚀时，还会刻蚀掉位线单元2的部分结构。位线单元2被刻蚀掉的部分为位线保护层中的一部分，具体而言，位线保护层中的氮化硅层和氮化钛层都各刻蚀掉一部分。由于位线保护层的底面不高于凹槽的底面，因此位线保护层底部仍然保留一定厚度的氮化硅和氮化钛，以对下方的位线结构层进行保护。对位线单元进行一定的刻蚀，使得第二沟槽宽度更大，后续形成的绝缘层面积更大绝缘效果良好。由于第一沟槽92和第二沟槽93的宽度会影响相邻位线单元上表面的宽度，进而影响相邻第一导电部41的面积，因此刻蚀时，应当控制好第一沟槽92和第二沟槽93的宽度，以兼顾绝缘层面积和第一导电部面积。
本步骤在进行刻蚀时，由于有保护层8的保护，第一沟槽92的侧壁不会受到影响，由此再向下刻蚀时，会沿着保护层8最下方向下刻蚀， 即按照第一沟槽92的最小宽度向下刻蚀，由此使得形成的第二沟槽93的宽度较窄，相应的凹槽侧壁剩余的导电层的厚度则更厚，即第二导电部42更厚，因此此处不容易发生断裂。同时，第二导电部42底部与第三导电部43的接触面积显然更大，因此在刻蚀时对光刻工艺的对准工艺偏移的影响因素不再敏感，在制程上可以获得更宽广的对准工艺空间。而且由于第一沟槽92下方呈收口状，第二导电部42和第一导电部41能形成光滑过渡。第二沟槽93的形状如图10所示，其一部分侧壁为导电层4，另一部分侧壁为位线单元2。
该步刻蚀优选采用干法刻蚀，可以达到理想的选择性刻蚀的目的。本步骤需要刻蚀的是导电层4和位线单元2，即例如金属钨、氮化硅、氮化钛等多种材料，因此刻蚀气体优选为四氟乙烷、氩气和氧气的混合气体，其中，四氟乙烷对位线单元2的氮化硅、氮化钛等材料具有较好的刻蚀效果，氩气和氧气对导电层4的金属钨具有较好的刻蚀效果，不同刻蚀气体的含量可以根据待刻蚀的材料进行调整以满足达到形成图中结构的刻蚀需求，优选四氟乙烷、氩气和氧气的比例为(3-5)：1：1，在该范围内，对上述膜层的具有相近的刻蚀速率，更利于得到图中所示的第二沟槽93形状。
步骤S500，如图11所示，去除保护层8。
在本步骤中，保护层8可以通过刻蚀去除。如前所述，采用干法刻蚀时，当保护层8材料为氮化硅时，刻蚀气体优选比例为5：1：1的四氟乙烷、氩气和氧气的混合气体。在其他实施例中，也可以采用湿法刻蚀等其他去除工艺。由于刻蚀气体针对的材料是保护层8，因此不会在去除保护层8时对导电层材料造成误刻蚀，保证第二导电部42的厚度不会减薄甚至断裂。
步骤S600，在导电层4背离衬底1的一侧形成存储电容6，使存储电容6与导电层4接触。
本步骤中，首先在第二沟槽内填充绝缘层，然后在上方形成具有电容孔101的支撑层10，然后在电容孔101内制作电容6。因此，本步骤可进一步包括以下步骤：
步骤S610，在第二沟槽内沉积绝缘层，如图12所示，绝缘层的材 料可以与绝缘侧壁7的材料相同，此处不再赘述。绝缘层5的上表面可以与第一导电部41的上表面平齐。
步骤S620，参考图13，在导电层和绝缘层5上方形成支撑层10。支撑层10覆盖在第一导电部41和绝缘层5上，用于对后续形成的存储电容构成支撑结构。
步骤S630，在支撑层10对应于第一导电部41的位置处刻蚀贯穿的电容孔101，暴露出第一导电部41，如图13所示。
步骤S640，在电容孔101内形成存储电容6，存储电容6包括下电极61、介电层62和上电极63，下电极61与第一导电部41接触，进而与电容触点3实现电连接，如图14所示。图中存储电容6的结构仅为一种示例，其还可以具有其他结构，此处不再一一列举。
采用上述方法形成的导电层能够形成较厚的第二导电部42，厚度可以达到20-30nm。而现有方法所形成的导电层结构中，第二导电部的厚度仅有15nm左右。本申请方法形成的第二导电部42不易发生断裂，可以保证存储电容6和电容触点3能形成良好的电接触，从而实现数据存取，同时较厚的第二导电部42能保证电容和电容触点之间具有较低的接触电阻，从而提高存取单元的数据传输效率。同时，上述方法形成的第二导电部42底部与第三导电部43的接触面积显然更大，因此在刻蚀时对光刻工艺的对准工艺偏移的影响因素不再敏感，在制程上可以获得更宽广的对准工艺空间。因此该方法能够兼顾半导体器件逐渐微缩的尺寸要求和存储性能的高要求。
本公开实施方式还提供一种半导体器件，采用上述方法制备而成。如图14所示，由上述方法制备的半导体器件包括衬底1，衬底1上设有多个位线单元2和多个电容触点3；多个位线单元2和多个电容触点3一一交替设置且通过绝缘侧壁7相互绝缘，位线单元2的高度高于电容触点3的高度，相邻两个位线单元2之间具有凹槽；衬底1上还设有覆盖位线单元2和电容触点3的导电层4，导电层4包括位于位线单元2上的第一导电部41、覆盖凹槽其中一个侧壁的第二导电部42、覆盖凹槽底面的第三导电部43，三个导电部连接成一个整体，三个导电部的划分具体可参照图10或图11中虚线框。凹槽内其余部分填充有绝缘层5， 绝缘层5和导电层上设有支撑层10，支撑层10位于第一导电部41的位置开设有电容孔101，电容孔101内设有电容6，电容6的下电极61与第一导电部41接触，进而与电容触点3电连接。
该半导体器件的第二导电部42厚度较厚，可以达到20-30nm，不易发生断裂，具有较低的接触电阻，可以保证存储电容6和电容触点3能形成良好的电接触，从而提高存取单元的数据传输效率。同时，该结构还能够使存储电容6形成最密六方堆积，有利于进一步降低半导体器件的尺寸。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (10)

  1. 一种半导体器件的制备方法，其中，包括：
    提供一衬底，所述衬底上形成有多个存取单元，所述存取单元包括一个位线单元和一个电容触点；所述多个存取单元的各位线单元和各电容触点一一交替设置且相互绝缘，所述位线单元的高度高于所述电容触点的高度，以使相邻两个所述位线单元之间形成凹槽；所述衬底上还形成有覆盖各所述存取单元的导电层，所述导电层填充各所述凹槽；
    对所述导电层对应于所述凹槽的部分进行刻蚀，以在所述导电层内形成对应于各所述存取单元的第一沟槽；所述存取单元内，所述第一沟槽靠近所述位线单元的侧壁相比所述凹槽的同一侧侧壁远离所述位线单元；
    在所述第一沟槽侧壁上形成保护层，
    对所述第一沟槽继续向下刻蚀，刻蚀掉位于所述凹槽内的部分导电层，保留覆盖所述位线单元侧壁和凹槽底部的导电层，以形成第二沟槽；其中，位于所述位线单元上方的导电层为第一导电部，覆盖所述位线单元侧壁且与所述第一导电部连接的导电层为第二导电部，覆盖所述凹槽底部且与所述第二导电部连接的导电层为第三导电部；
    去除所述保护层；
    在所述第一导电部背离所述衬底的一侧形成存储电容，使所述存储电容与所述第一导电部接触。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，所述在所述导电层内形成对应于各所述存取单元的第一沟槽包括：
    对所述导电层对应于各所述凹槽的部分进行第一次刻蚀，形成多个初始沟槽，使各所述存取单元内，所述初始沟槽靠近所述位线单元的侧壁相比所述凹槽的同一侧侧壁远离所述位线单元；
    对所述初始沟槽再次向下刻蚀，使新刻蚀的沟槽靠近所述位线单元的侧壁在所述沟槽深度方向上形成一弧面，所述弧面在朝向所述沟槽底部的方向上逐渐靠近相对的另一个侧壁，得到所述第一沟槽。
  3. 根据权利要求2所述的半导体器件的制备方法，其中，在所述导电层的第一沟槽侧壁上形成保护层包括：
    在所述导电层上沉积保护材料，使所述保护材料覆盖所述导电层上表面以及第一沟槽的侧壁和底面；
    刻蚀掉覆盖在所述导电层上表面和所述第一沟槽底面的保护材料，保留覆盖在所述第一沟槽侧壁的保护材料，形成所述保护层。
  4. 根据权利要求1所述的半导体器件的制备方法，其中，所述位线单元包括在衬底上形成的位线结构层和位于所述位线结构层背离所述衬底一侧的位线保护层，所述位线保护层的底面不高于所述凹槽底面；
    刻蚀位于所述凹槽内的部分导电层形成所述第二沟槽的同时，还刻蚀掉所述位线保护层的一部分。
  5. 根据权利要求3所述的半导体器件的制备方法，其中，所述保护材料为氮化硅、二氧化硅、氮氧化硅、氮化钛、二氧化钛、二氧化锆、多晶硅中的一种或任意多种的混合物。
  6. 根据权利要求5所述的半导体器件的制备方法，其中，所述保护层的厚度为5-10nm。
  7. 根据权利要求1所述的半导体器件的制备方法，其中，形成所述第一沟槽的刻蚀气体为六氟化硫、氯气、氮气和氧气的混合气体。
  8. 根据权利要求1所述的半导体器件的制备方法，其中，形成所述第二沟槽的刻蚀气体和刻蚀所述保护层的刻蚀气体为四氟乙烷、氩气和氧气的混合气体。
  9. 根据权利要求1所述的半导体器件的制备方法，其中，所述形成存储电容包括：
    在所述第二沟槽内填充绝缘层；
    在所述导电层和所述绝缘层上方形成支撑层；
    在所述支撑层对应于所述第一导电部的位置处形成贯穿的电容孔，所述电容孔暴露出所述第一导电部；
    在电容孔内依次形成电容的下电极、介质层和上电极，所述下电极与所述第一导电部接触。
  10. 一种半导体器件，其中，由权利要求1-9中任一项所述的制备方法得到。
PCT/CN2021/103751 2020-09-14 2021-06-30 半导体器件及其制备方法 WO2022052593A1 (zh)

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