WO2022151697A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022151697A1
WO2022151697A1 PCT/CN2021/107898 CN2021107898W WO2022151697A1 WO 2022151697 A1 WO2022151697 A1 WO 2022151697A1 CN 2021107898 W CN2021107898 W CN 2021107898W WO 2022151697 A1 WO2022151697 A1 WO 2022151697A1
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Prior art keywords
filling layer
layer
filling
substrate
semiconductor structure
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PCT/CN2021/107898
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English (en)
French (fr)
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巩金峰
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长鑫存储技术有限公司
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Priority to US17/456,850 priority Critical patent/US20220223597A1/en
Publication of WO2022151697A1 publication Critical patent/WO2022151697A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a fabrication method thereof.
  • DRAM Dynamic Random Access Memory
  • the spacing between adjacent bit line structures becomes smaller and smaller.
  • the smaller the spacing between adjacent bit line structures the larger the aspect ratio of the capacitor contact holes between the adjacent bit line structures. Therefore, when the capacitor contact plugs are subsequently formed in the capacitor contact holes, it is difficult to control the capacitance contact. Top topography of the plug, making it difficult to ensure good yield of semiconductor structures
  • the technical problem solved by the embodiments of the present application is to provide a semiconductor structure and a manufacturing method thereof, which are beneficial to form a capacitor contact plug with a relatively flat top shape when the depth-width ratio of the capacitor contact hole is large, thereby helping to improve the Yield of semiconductor structures.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate with a plurality of mutually discrete bit lines on the substrate, and capacitor contact holes between adjacent bit lines; forming Filling the filling film of the capacitor contact hole, and the filling film has a gap area; using the first etching process, the filling film is etched to open the gap area, and the remaining filling film is used as a first filling layer, the remaining gap area is used as a first gap in the first filling layer, and the first filling layer has a top surface connecting the first gap and the sidewall of the capacitor contact hole, In a direction parallel to the substrate and pointing to the sidewall of the capacitor contact hole along the first gap, the distance between the top surface and the substrate gradually increases; stacking to form at least two basic filling layers, and the basic filling layer farthest from the substrate fills the remaining capacitor contact holes; in a direction perpendicular to the substrate and pointing to the bit line along the substrate, The do
  • an embodiment of the present application further provides a semiconductor structure, comprising: a substrate having a plurality of mutually discrete bit lines on the substrate, and capacitor contact holes between adjacent bit lines; and a capacitor contact plug, so The capacitive contact plug is located at the bottom of the capacitive contact hole, and the capacitive contact plug is formed by a first filling layer or the capacitive contact plug is formed by a first filling layer and a basic filling layer.
  • a filling film is first formed in the capacitor contact hole, the filling film is etched by a first etching process to form a first filling layer, and then at least two basic filling layers are formed on the surface of the first filling layer, and the basic filling layer is formed.
  • the layer fills the first gap in the first filling layer, which is beneficial to avoid voids in the subsequently formed capacitor contact plug and to avoid reducing the conductivity of the capacitor contact plug.
  • the first filling layer has a first gap
  • the first filling layer has a top surface connecting the first gap and the sidewall of the capacitor contact hole, the direction parallel to the substrate and pointing to the sidewall of the capacitor contact hole along the first gap
  • the distance between the top surface and the substrate gradually increases.
  • the doping concentration of the basic filling layer decreases layer by layer in the direction perpendicular to the substrate and pointing to the bit line along the substrate.
  • the basic filling layer near the sidewall of the capacitor contact hole is etched more in the same etching time, while the basic filling layer near the middle area of the capacitor contact hole is etched
  • the etching is less, so by controlling the difference in doping concentration between the adjacent basic filling layers, the top shape of the finally formed capacitor contact plug is relatively flat, which is beneficial to reduce the capacitance contact plug and other conductive plugs.
  • Contact resistance between structures is beneficial to improve the yield of semiconductor structures.
  • the first filling layer is only located on the bottom and part of the sidewall of the capacitor contact hole, so the size of the first gap in the first filling layer away from the opening of the substrate is larger, which is conducive to filling the first gap with the subsequent basic filling layer.
  • there is no void in the basic filling layer located in the first gap which is beneficial to ensure that there is no void in the capacitor contact plug formed subsequently, so as to ensure good conductivity of the capacitor contact plug.
  • 1 to 9 are schematic cross-sectional structural diagrams corresponding to each step of the manufacturing method of the semiconductor structure provided by the first embodiment of the present application;
  • 10 to 13 are schematic cross-sectional structural diagrams corresponding to each step of the method for fabricating a semiconductor structure provided by the second embodiment of the present application.
  • the spacing between adjacent bit lines becomes smaller and smaller, and the aspect ratio of the capacitor contact hole is also larger and larger, so the conductive material is filled in the capacitor contact hole to form a filling layer, the top of the capacitor contact holes between adjacent bit lines will be sealed by the conductive material in advance, then there will be gaps in the filling layer, and the surface of the filling layer above the capacitor contact holes has grooves, the gaps and grooves make the subsequent
  • the filling layer is etched to form the capacitive contact plug, the capacitive contact plug with a relatively flat top shape cannot be formed, which is not conducive to ensuring a small contact resistance between the capacitive contact plug and other conductive structures.
  • the present application provides a method for fabricating a semiconductor structure, wherein a filling film is first formed in the capacitor contact hole, the filling film is etched by a first etching process to form a first filling layer, and then a filling layer is formed in the first filling layer. At least two basic filling layers are formed on the surface. Because the first filling layer has a first gap, and the first filling layer has a top surface connecting the first gap and the side wall of the capacitor contact hole, in a direction parallel to the substrate and pointing to the side wall of the capacitor contact hole along the first gap, The distance between the top surface and the substrate gradually increases.
  • the etching rate of the base filling layer close to the sidewall of the capacitor contact hole by the subsequent second etching process is the first etching rate
  • the second etching process The etching rate of the basic filling layer in the middle area of the capacitor contact hole is the second etching rate.
  • the first The etching rate is higher than the second etching rate, so by controlling the difference in doping concentration between the adjacent base filling layers, the top shape of the finally formed capacitor contact plug is relatively flat, which is beneficial to reduce the capacitance
  • the contact resistance between the contact plug and other conductive structures is beneficial to improve the yield of the semiconductor structure.
  • 1 to 9 are schematic cross-sectional structural diagrams corresponding to each step of the manufacturing method of the semiconductor structure provided by the first embodiment of the present application.
  • a substrate 100 is provided.
  • the substrate 100 has a plurality of mutually discrete bit lines 101 , and capacitor contact holes 11 are formed between adjacent bit lines 101 .
  • the substrate 100 includes structures such as buried word lines, shallow trench isolation structures, and active regions.
  • the bit line 101 includes a bit line contact layer 111 , a bottom dielectric layer 121 , a metal layer 131 and a top dielectric layer 141 which are stacked in sequence.
  • the material of the bit line contact layer 111 includes tungsten or polysilicon
  • the material of the bottom dielectric layer 121 and the top dielectric layer 141 includes silicon nitride, silicon dioxide or silicon oxynitride
  • the metal layer 131 can be made of one conductive material or a variety of conductive materials. Materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and tungsten composites, etc.
  • the top and sidewalls of the bit lines 101 are also covered with an insulating layer 102 , and the insulating layer 102 is used to protect and isolate the adjacent bit lines 101 .
  • the insulating layer 102 is formed by an atomic layer deposition process.
  • the atomic layer deposition process has the characteristics of slow deposition rate, high density of the deposited film, and good step coverage. In this way, the insulating layer 102 can be made thinner in thickness.
  • the adjacent bit lines 101 are effectively isolated and protected under the same conditions, so as to prevent the insulating layer 102 from occupying a large space between the adjacent bit lines 101, which is beneficial to the subsequent filling of the basic filling layer.
  • the material of the insulating layer 102 includes silicon nitride or silicon oxynitride.
  • the insulating layer 102 on top of the bit line 101 may be removed in a subsequent process step.
  • a filling film 103 filling the capacitor contact hole 11 (refer to FIG. 1 ) is formed, and the filling film 103 has a gap region 12 therein.
  • the process of forming the filling film 103 includes a chemical vapor deposition process or an atomic layer deposition process, and the filling film 103 not only fills the capacitor contact hole 11 , but also is located on the top of the bit line 101 .
  • the filling film 103 due to the continuous shrinking of the process, in the direction perpendicular to the surface of the substrate 100 , when the height of the bit lines 101 remains unchanged, the distance between adjacent bit lines 101 tends to become smaller, so the capacitor contact holes 11 The aspect ratio of , tends to be larger, the gap region 12 is likely to exist in the filling film 103 , and the surface of the filling film 103 located above the capacitor contact hole 11 has the first groove 13 .
  • the top of the filling film 103 is higher than the top of the bit line 101 .
  • the thickness of the filling film 103 is relatively large in the direction perpendicular to the surface of the substrate 100. Therefore, chemical vapor deposition with a faster deposition rate is adopted.
  • the process of forming the filling film 103 is beneficial to shorten the cycle of the semiconductor structure manufacturing process.
  • the filling film 103 is a silicon material layer with a doping element, wherein the material of the silicon material layer includes monocrystalline silicon, polycrystalline silicon or amorphous silicon; the doping element is boron element or phosphorus element. It should be noted that the introduction of the silicon material layer and the doping element in this embodiment is for those skilled in the art to understand the implementation details of this solution, and does not constitute a limitation to this solution.
  • the filling film 103 may also be a silicon material layer without doping elements; in addition, the filling film 103 may be formed only in the capacitor contact hole 11 and does not need to cover the top of the bit line 101 .
  • the doping concentration of the doping element in the filling film 103 is greater than the doping concentration of the doping element in the subsequently formed basic filling layer.
  • a gas with doping elements is introduced during the deposition process, and the gas flow rate of the gas used to form the filling film 103 is the first gas flow rate; the subsequent deposition process is used to form the basic filling layer
  • the gas with doping element is introduced, and the gas flow rate of the gas is the second gas flow rate when used to form the basic filling layer, the first gas flow rate is greater than the second gas flow rate.
  • the gas flow rate of the gas containing the doping element is fixed.
  • the gas flow rate of the gas with the doping element can be gradually increased with the deposition time.
  • the minimum gas flow rate of the gas in the process of forming the filling film 103 is the third The gas flow rate.
  • the maximum gas flow rate of the gas with doping elements in the subsequent formation of the basic filling layer is the fourth gas flow rate, and the third gas flow rate is greater than the fourth gas flow rate.
  • the filling film 103 ( FIG. 2 ) is etched to open the gap region 12 (refer to FIG. 2 ) using a first etching process, the remaining filling film 103 is used as the first filling layer 113 , and the remaining gap region 12 As the first gap 14 in the first filling layer 113, the first filling layer 113 has a top surface a connecting the first gap 14 and the sidewall of the capacitor contact hole 11 (refer to FIG. 1).
  • the filling film 103 is etched by the first etching process to form
  • the distance between the top surface a of the first filling layer 113 and the substrate 100 gradually increases in the direction parallel to the substrate 100 and pointing to the sidewall of the capacitor contact hole 11 along the first gap 14 .
  • the first filling layer 113 is only located on the bottom and part of the sidewall of the capacitor contact hole 11 , which is beneficial to ensure that the size of the first gap 14 away from the opening of the substrate 100 is large.
  • the width of the opening of the first slit 14 away from the substrate 100 may be the maximum width of the slit area 12, that is, the opening of the slit area 12 by the first etching process is relatively large, which is conducive to the subsequent filling of the base filling layer.
  • Filling the first gap 14 and having no gaps in the basic filling layer in the first gap 14 is beneficial to ensure that there are no gaps in the capacitor contact plugs formed subsequently, so as to ensure good conductivity of the capacitor contact plugs.
  • the filling film 103 is a silicon material layer with doping elements
  • the first filling layer 113 is also a silicon material layer with doping elements, and the doping concentration of the doping elements in the first filling layer 113 is greater than the basis for subsequent formation Doping concentration of doping elements in the filling layer. Therefore, when the second etching process is subsequently used to etch the first filling layer 113 and at least part of the basic filling layer, in order to obtain a capacitor contact plug with a flat top shape, as the etching time increases, a second etching time is required. A filling layer 113 is etched in a relatively large amount.
  • the first filling layer 113 can be etched within the same etching time.
  • a filling layer 113 is etched more than the base filling layer, so it is more favorable to form a capacitor contact plug with a flat top shape.
  • At least two basic filling layers are sequentially stacked on the surface of the first filling layer 113 , and the basic filling layer farthest from the substrate 100 is filled with the remaining capacitor contact holes 11 ;
  • the doping concentration of the base filling layer decreases layer by layer. Therefore, in the direction perpendicular to the substrate 100 and pointing to the bit line 101 along the substrate 100 , the etching rate of the base filling layer by the subsequent second etching process decreases layer by layer.
  • the base filling layer is a silicon material layer with doping elements, and the difference between the doping concentrations of the doping elements in the adjacent base filling layers is not higher than 200 atoms/cm 3 .
  • the process steps of sequentially stacking and forming two basic filling layers on the surface of the first filling layer 113 include:
  • an underfill layer 104 is formed, the underfill layer 104 fills the first gap 14 (refer to FIG. 3 ), and the underfill layer 104 located in the capacitor contact hole 11 (refer to FIG. 1 ) forms a concave hole 15 .
  • the process of forming the underfill layer 104 includes a chemical vapor deposition process or an atomic layer deposition process, and the underfill layer 104 is also located over the top of the bit line 101 .
  • the ratio between the thickness of the underfill layer 104 and the width of the capacitor contact hole 11 ranges from 10% to 40%.
  • the ratio between the widths of the capacitor contact holes 11 is 20%.
  • the aspect ratio of the capacitor contact holes 11 is large, it is easy to form the underfill layer 104 of this thickness through the deposition process; It is beneficial to etch the underfill layer 104 of this thickness through the second etching process, so as to form a capacitor contact plug with a relatively flat top shape.
  • a top filling layer 105 is formed, the top filling layer 105 fills the concave hole 15 (refer to FIG. 4 ), and the top filling layer 105 has a second gap 16 , and the surface of the top filling layer 105 corresponds to the central axis of the concave hole 15
  • the place also has a second groove 17.
  • the process of forming the top fill layer 105 may be the same as the process of forming the bottom fill layer 104 , and the top fill layer 105 is also located over the top of the bit line 101 . It should be noted that, in other embodiments, the bottom filling layer 104 and the top filling layer 105 may be formed only on the capacitor contact hole 11 , and do not need to cover the top of the bit line 101 .
  • the base filling layer is formed by a deposition process
  • a gas with doping elements is introduced, and the gas is used to form the base filling in the direction perpendicular to the substrate 100 and along the direction of the base 100 to the bit line 101 .
  • the gas flow of the gas in the layers decreases layer by layer.
  • the gas flow rate of the gas used to form the underfill layer 104 is greater than the gas flow rate of the gas used to form the top fill layer 105
  • the gas flow rate of the gas used to form the fill film 103 is greater than the gas flow rate of the gas used to form the underfill layer 104 Gas flow of gas.
  • the doping concentration of the doping element in the first filling layer 113, the doping concentration of the doping element in the bottom filling layer 104, and the doping concentration of the doping element in the top filling layer 105 decrease in sequence, and then the second etching In the process, the etching rate of the first filling layer 113 , the etching rate of the bottom filling layer 104 and the etching rate of the top filling layer 105 are successively decreased.
  • the filling layer 113 and the underfill layer 104 are etched in a larger amount, and the top filling layer 105 and the underfill layer 104 near the central axis of the first gap 14 are etched in a smaller amount, which is beneficial to slow down the capacitance formed subsequently
  • the difference in the distance between the top surface of the contact plug and the substrate 100 is used to obtain a capacitive contact plug with a relatively flat top shape.
  • the base filling layer is also located on top of the bit line 101; after at least two base filling layers are sequentially stacked on the surface of the first filling layer 113, the first filling layer 104 and at least two base filling layers are formed by using a second etching process. Before etching the part of the base filling layer, the method further includes: using a third etching process to etch the base filling layer to expose the insulating layer 102 on the top of the bit line 101 .
  • the method before using the third etching process to etch the base filling layer, the method further includes: planarizing the base filling layer, and the remaining base filling layer is located on the top of the bit line 101 .
  • the surface of the top filling layer 105 has a second groove 17 at the position corresponding to the central axis of the concave hole 15, and the top filling layer 105 is planarized to remove the second groove 17.
  • the groove 17 makes the surface of the remaining top filling layer 105 relatively flat.
  • the base filling layer is subsequently etched to the top of the exposed bit line 101 by the third etching process, it is beneficial to make the remaining top filling layer
  • the top surface c formed by 105 and the remaining underfill layer 104 is relatively flat, that is, the difference in the distance between the top surface c and the substrate 100 is reduced.
  • the top filling layer 105 may not be planarized, and the top filling layer 105 and the bottom filling layer 104 may be directly etched by the third etching process until the top of the bit line 101 is exposed.
  • the top filling layer The difference between the doping concentrations of the doping elements in the layer 105 and the underfill layer 104 is used to obtain a capacitor contact plug with a flat top shape.
  • the remaining top filling layer 105 and bottom filling layer 104 are etched by the third etching process to expose the insulating layer 102 on the top of the bit line 101 , wherein the insulating layer 102 on the top of the bit line 101 is Etch stop point.
  • the top of the bit line 101 is the etching stop point of the third etching process.
  • the thicknesses of the first filling layer 113 and the basic filling layer formed on different substrates 100 are different, that is, the thickness of each substrate 100 is higher than the bit line 101
  • the total thickness of the top first filling layer 113 and the base filling layer is different.
  • the thicknesses of the bit line 101 formed on each substrate 100 and the insulating layer 102 located on the bit line 101 are strictly uniform, so when the third etching process is performed, the insulating layer 102 located on the top of the bit line 101 is used as the etching At the stop point of etching, the total thickness of the remaining underfill layer 104 and the remaining top filling layer 105 on each substrate 100 may be the same. Therefore, when the second etching process is performed subsequently, the etching time is controlled to be the same, and a capacitor contact plug with a flat top shape can be obtained in different substrates 100 .
  • both the top filling layer 105 and the bottom filling layer 104 may be planarized to ensure that the remaining bottom filling layer 104 is located on the top of the bit line 101, so that the third etching process is performed on the bit line
  • the insulating layer 102 on the top of the 101 or the top of the bit line 101 can be used as an etch stop point.
  • the second gap 16 (refer to FIG. 5 ) is removed, which is beneficial to ensure the subsequent formation of There is no void in the capacitive contact plug, which is beneficial to ensure that the capacitive contact plug has good electrical conductivity.
  • the first filling layer 113 , the remaining top filling layer 105 and the remaining bottom filling layer 104 are etched by using the second etching process.
  • the first filling layer 113 , the top filling layer 105 and the bottom filling layer 104 may be etched directly by a second etching process.
  • the etching rate of the base filling layer by the second etching process decreases layer by layer, that is, the second etching process is used for the remaining underfill layer.
  • the etch rate for 104 is greater than the rate for the remaining top fill layer 105 .
  • the process parameters of the third etching process and the second etching process are the same. In other embodiments, the process parameters of the third etching process and the second etching process may also be different.
  • the capacitor contact holes 11 in the process of etching the first filling layer 113 , the remaining top filling layer 105 and the remaining bottom filling layer 104 by using the second etching process, the capacitor contact holes 11 (refer to FIG. 1 ), an etched curved surface is formed, wherein, in the direction parallel to the substrate 100 and along the first slit 12 (refer to FIG. 2 ) to the side wall of the capacitor contact hole 11 , the etched surfaces at each point on the curved surface are etched. The slope gradually increases.
  • the etched curved surface is the surface where the etched substance is in contact with the first filling layer 113 and at least part of the basic filling layer in the second etching process. Because in the direction perpendicular to the substrate 100 and pointing to the bit line 101 along the substrate 100, the etching rate of the base filling layer by the second etching process decreases layer by layer. On the substrate 100 and along the direction of the first slit 12 toward the side wall of the capacitor contact hole 11 , the slope of each point on the etched curved surface gradually increases, which is beneficial to finally obtain the capacitor contact plug 106 with a flat top shape. .
  • point E is the junction point of the remaining underfill layer 104 and the remaining top filling layer 105 on the etched curved surface at this time; referring to the etching time shown in FIG. 8 , point F
  • the junction point between the remaining bottom filling layer 104 and the remaining top filling layer 105 on the etched curved surface is etched.
  • points E and F are points corresponding to similar positions at different etching times on the etched curved surface. Referring to FIG. 7 and FIG. 8 , it can be seen that the slope of point F is smaller than that of point E, and as the second etching process proceeds, the slope of each point on the etched curved surface gradually increases.
  • the second etching process is used to etch the first filling layer 113 , the remaining top filling layer 105 and at least part of the remaining bottom filling layer 104 , so as to form capacitor contact plugs in the capacitor contact holes 11 106.
  • the remaining first filling layer 113 and the remaining underfill layer 104 together constitute the capacitive contact plug 106 .
  • the top surface of the capacitive contact plug 106 away from the substrate 100 is parallel to the surface of the substrate 100 , which facilitates the subsequent formation of other conductive structures on the capacitive contact plug 106 and helps to reduce the contact between the capacitive contact plug 106 and other conductive structures. resistance, and help improve the yield of semiconductor structures.
  • the capacitive contact plug 106 can also be composed of only the remaining first filling layer 113 , or the capacitor The contact plug 106 may also be composed of the remaining first filling layer 113 , the remaining bottom filling layer 104 and the remaining top filling layer 105 .
  • the ratio of the thickness of the capacitive contact plug 106 to the height of the bit line 101 ranges from 10% to 80%. In one example, the ratio of the thickness of the capacitive contact plug 106 to the height of the bit line 101 is 30%.
  • the capacitive contact plug 106 by controlling the doping concentration of the doping elements in the first filling layer 113 , the bottom filling layer 104 and the top filling layer 105 to decrease layer by layer, when the capacitor contact plug 106 is formed by the subsequent etching process, The capacitive contact plug 106 with a flat top shape and no voids inside can be obtained, which is beneficial to improve the conductivity of the capacitive contact plug 106 itself and reduce the contact resistance between the capacitive contact plug 106 and other conductive structures. It is beneficial to improve the yield of the semiconductor structure.
  • the second embodiment of the present application also provides a method for fabricating a semiconductor structure.
  • This embodiment is substantially the same as the previous embodiment, and the main difference is that the number of layers of the formed basic filling layer is different.
  • the fabrication method of the semiconductor structure provided by the second embodiment of the present application will be described in detail below with reference to FIG. 5 . It should be noted that, for the same or corresponding parts as those in the previous embodiment, reference may be made to the detailed description of the previous embodiment, which is not described here. Repeat.
  • 10 to 13 are schematic cross-sectional structural diagrams corresponding to each step of the method for fabricating a semiconductor structure provided in this embodiment.
  • three basic filling layers are sequentially stacked on the surface of the first filling layer 113 , and the basic filling layer farthest from the substrate 100 fills the remaining capacitor contact holes 11 .
  • the three basic filling layers are an underfill layer 204 , a middle filling layer 205 and a top filling layer 206 in sequence.
  • the doping concentration of the doping elements in the bottom filling layer 204 , the middle filling layer 205 and the top filling layer 206 decreases layer by layer.
  • the deposition process when used to form the three-layer base filling layer, during the deposition process, a gas with doping elements is introduced, and in the direction perpendicular to the substrate 200 and along the direction of the substrate 200 to the bit line 201, use The gas flow rate of the gas for forming the base filling layer decreases layer by layer.
  • the underfill layer 204 located in the capacitor contact hole 11 encloses the first concave hole
  • part of the intermediate filling layer 205 is located in the first concave hole
  • the intermediate filling layer 205 located in the first concave hole encloses the first concave hole
  • Two concave holes The top filling layer 206 fills the second concave holes
  • the top filling layer 206 has a second gap 26
  • the surface of the top filling layer 206 also has a second groove 27 corresponding to the center axis of the second gap 26 .
  • the process of forming the bottom filling layer 204, the middle filling layer 205 and the top filling layer 206 includes a chemical vapor deposition process or an atomic layer deposition process.
  • the second gap 26 is removed, which is beneficial to ensure the subsequent formation of capacitive contact plugs There is no void in the 207, which is beneficial to ensure that the capacitive contact plug 207 has good electrical conductivity.
  • the second etching process proceeds to the first moment, at which time the remaining bottom filling layer 204 , the remaining intermediate filling layer 205 and the remaining top filling layer 206 together form the first top surface d; with reference to FIG. 12 , Correspondingly, the second etching process is carried out to the second moment, at which time the remaining bottom filling layer 204 , the remaining middle filling layer 205 and the remaining top filling layer 206 together form the second top surface e.
  • the concave degree of the first top surface d is greater than that of the second top surface e.
  • the etched curved surface is the surface where the etched substance is in contact with the first filling layer 213 and at least part of the basic filling layer in the second etching process. Because in the direction perpendicular to the substrate 200 and pointing to the bit line 201 along the substrate 200, the etching rate of the base filling layer by the second etching process decreases layer by layer. On the substrate 200 and along the direction of the first slit toward the sidewall of the capacitor contact hole, the slope of each point on the etched curved surface gradually increases, which is beneficial to finally obtain the capacitor contact plug 207 with a flat top shape.
  • the remaining first filling layer 213 and the remaining third underfill layer 204 together constitute the capacitive contact plug 207 .
  • the top surface of the capacitor contact plug 207 away from the substrate 200 is parallel to the surface of the substrate 200, which facilitates the subsequent formation of other conductive structures on the capacitor contact plug 207, and helps to reduce the contact resistance between the capacitor contact plug 207 and other conductive structures , and is beneficial to improve the yield of the semiconductor structure.
  • the capacitive contact plug 207 can also be made of only the remaining first filling layer 213 .
  • the capacitive contact plug 207 may also be composed of the remaining first filling layer 213, the remaining underfill layer 204 and the remaining intermediate filling layer 205; The filling layer 213 , the remaining bottom filling layer 204 , the remaining middle filling layer 205 and the remaining top filling layer 206 are formed together.
  • the third embodiment of the present application further provides a semiconductor structure, and the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure provided in any of the above-mentioned embodiments.
  • the semiconductor structure includes: a substrate 100 with a plurality of discrete bit lines 101 on the substrate 100 , and capacitor contact holes between adjacent bit lines 101 ; capacitor contact plugs 106 , and the capacitor contact plugs 106 are located in the capacitor contacts At the bottom of the hole, the capacitive contact plug 106 is composed of the first filling layer 113 and the base filling layer.
  • the base filling layer is the underfill layer 104 in the above-mentioned embodiment.
  • the base filling layer may also be a laminated structure of at least two layers.
  • the capacitive contact plug 106 may be composed of only the first filling layer 113 .
  • the top surface of the capacitive contact plug 106 away from the base 100 is parallel to the surface of the base 100 , which facilitates the subsequent formation of other conductive structures on the capacitive contact plug 106 and helps to reduce the contact between the capacitive contact plug 106 and other conductive structures. Contact resistance, and help improve the yield of semiconductor structures.
  • first filling layer 113 and the underfill layer 104 are both silicon material layers with doping elements, and the doping concentration of the doping elements in the first filling layer 113 is greater than the doping concentration of the doping elements in the underfill layer 104 .

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Abstract

本申请实施例提供一种半导体结构及其制作方法，半导体结构的制作方法包括：提供基底，基底上具有多个相互分立的位线，相邻位线之间具有电容接触孔；形成填充满电容接触孔的填充膜，且填充膜内具有缝隙区域；采用第一刻蚀工艺，对填充膜进行刻蚀以打开缝隙区域，剩余填充膜作为第一填充层；在第一填充层表面依次堆叠形成至少两层基础填充层，距离基底最远的基础填充层填充满剩余电容接触孔；在垂直于基底且沿基底指向位线的方向上，基础填充层的掺杂浓度逐层减小；采用第二刻蚀工艺，对第一填充层和至少部分基础填充层进行刻蚀，以形成电容接触插塞。本申请实施例有利于在电容接触孔的深宽比较大的情况下，形成顶部形貌较为平坦的电容接触插塞。

Description

半导体结构及其制作方法
交叉引用
本申请基于申请号为202110049125.3、申请日为2021年01月14日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
随着动态随机存取存储器(DRAM，DynamicRandomAccessMemory)制程的不断微缩，相邻位线结构之间间距变得越来越小。而相邻位线结构之间间距变小，会导致相邻位线结构之间的电容接触孔的深宽比变大，因而后续在电容接触孔中形成电容接触插塞时，难以控制电容接触插塞的顶部形貌，从而难以保证半导体结构具有较好的良率
在电容接触孔的深宽比较大的情况下，如何形成顶部形貌较好的电容接触插塞，是当前亟待解决的问题。
发明内容
本申请实施例解决的技术问题为提供一种半导体结构及其制作方法，有利于在电容接触孔的深宽比较大的情况下，形成顶部形貌较为平坦的电容接触插塞，从而有利于提高半导体结构的良率。
为解决上述问题，本申请实施例提供一种半导体结构的制作方法，包括：提供基底，所述基底上具有多个相互分立的位线，相邻所 述位线之间具有电容接触孔；形成填充满所述电容接触孔的填充膜，且所述填充膜内具有缝隙区域；采用第一刻蚀工艺，对所述填充膜进行刻蚀以打开所述缝隙区域，剩余的所述填充膜作为第一填充层，剩余的所述缝隙区域作为位于所述第一填充层内的第一缝隙，所述第一填充层具有连接所述第一缝隙以及所述电容接触孔侧壁的顶面，在平行于所述基底且沿所述第一缝隙指向所述电容接触孔侧壁的方向上，所述顶面与所述基底之间的距离逐渐增大；在所述第一填充层表面依次堆叠形成至少两层基础填充层，距离所述基底最远的所述基础填充层填充满剩余所述电容接触孔；在垂直于所述基底且沿所述基底指向所述位线的方向上，所述基础填充层的掺杂浓度逐层减小；采用第二刻蚀工艺，对所述第一填充层和至少部分所述基础填充层进行刻蚀，以形成电容接触插塞。
相应地，本申请实施例还提供一种半导体结构，包括：基底，所述基底上具有多条相互分立的位线，相邻所述位线之间具有电容接触孔；电容接触插塞，所述电容接触插塞位于所述电容接触孔底部，所述电容接触插塞由第一填充层构成或者所述电容接触插塞由第一填充层和基础填充层构成。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
上述技术方案中，在电容接触孔中先形成填充膜，采用第一刻蚀工艺对填充膜进行刻蚀以形成第一填充层，然后在第一填充层表面形成至少两层基础填充层，且基础填充层填充满第一填充层内的第一缝隙，有利于避免后续形成的电容接触插塞中具有空隙，避免降低电容 接触插塞的导电性能。此外，因为第一填充层内具有第一缝隙，且第一填充层具有连接第一缝隙以及电容接触孔侧壁的顶面，在平行于基底且沿第一缝隙指向电容接触孔侧壁的方向上，顶面与基底之间的距离逐渐增大，在此基础上，使得在垂直于基底且沿基底指向位线的方向上，基础填充层的掺杂浓度逐层减小，则后续对第一填充层和至少部分基础填充层进行刻蚀时，相同刻蚀时间内，靠近电容接触孔侧壁的基础填充层被刻蚀得多一些，而靠近电容接触孔中间区域的基础填充层被刻蚀得少一些，因而能通过控制相邻基础填充层之间的掺杂浓度的差异，使得最终形成的电容接触插塞的顶部形貌较为平坦，从而有利于减小电容接触插塞与其他导电结构之间的接触电阻，并有利于提高半导体结构的良率。
另外，第一填充层仅位于电容接触孔的底部和部分侧壁上，则第一填充层内的第一缝隙远离基底的开口的尺寸较大，有利于后续基础填充层填充满第一缝隙，且位于第一缝隙中的基础填充层内没有空隙，有利于保证后续形成的电容接触插塞中没有空隙，以保证电容接触插塞良好的导电性。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1至图9为本申请第一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图；
图10至图13为本申请第二实施例提供的半导体结构的制作方 法各步骤对应的剖面结构示意图。
具体实施方式
由背景技术可知，现有技术中在电容接触孔的深宽比较大的情况下，如何形成顶部形貌较好的电容接触插塞，是当前亟待解决的问题。
经分析可知，为满足DRAM的小型化，相邻位线之间的间距变得越来越小，电容接触孔的深宽比也越来越大，因此在电容接触孔中填充导电材料形成填充层时，相邻位线之间的电容接触孔顶部会提前被导电材料封口，则填充层中会存在空隙，且位于电容接触孔上方的填充层表面具有凹槽，该空隙和凹槽使得后续对填充层进行刻蚀形成电容接触插塞时，无法形成顶部形貌较为平坦的电容接触插塞，从而不利于保证电容接触插塞与其他导电结构之间较小的接触电阻。
为解决上述问题，本申请实施提供一种半导体结构的制作方法，在电容接触孔中先形成填充膜，采用第一刻蚀工艺对填充膜进行刻蚀以形成第一填充层，然后在第一填充层表面形成至少两层基础填充层。因为第一填充层内具有第一缝隙，且第一填充层具有连接第一缝隙以及电容接触孔侧壁的顶面，在平行于基底且沿第一缝隙指向电容接触孔侧壁的方向上，顶面与基底之间的距离逐渐增大，在此基础上，后续第二刻蚀工艺对靠近电容接触孔侧壁的基础填充层的刻蚀速率为第一刻蚀速率，第二刻蚀工艺对电容接触孔中间区域的基础填充层的刻蚀速率为第二刻蚀速率，由于在垂直于基 底且沿基底指向位线的方向上，基础填充层的掺杂浓度逐层减小，则第一刻蚀速率大于第二刻蚀速率，因而能通过控制相邻基础填充层之间的掺杂浓度的差异，使得最终形成的电容接触插塞的顶部形貌较为平坦，从而有利于减小电容接触插塞与其他导电结构之间的接触电阻，和有利于提高半导体结构的良率。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图9为本申请第一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图1，提供基底100，基底100上具有多个相互分立的位线101，相邻位线101之间具有电容接触孔11。本实施例中，基底100内包括埋入式字线、浅沟槽隔离结构、有源区等结构。位线101包括依次堆叠设置的位线接触层111、底层介质层121、金属层131以及顶层介质层141。位线接触层111的材料包括钨或多晶硅，底层介质层121和顶层介质层141的材料包括氮化硅、二氧化硅或氮氧化硅，金属层131可以由一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
此外，位线101的顶部和侧壁还覆盖有绝缘层102，绝缘层102 用于保护并隔离相邻的位线101。具体地，绝缘层102采用原子层沉积工艺形成，原子层沉积工艺具有沉积速率慢，沉积形成的膜层致密性高和阶梯覆盖率好等特点，如此，能够使得绝缘层102能够在厚度较薄的条件下对相邻位线101进行有效地隔离保护，避免绝缘层102占据相邻位线101之间较大的空间，有利于后续实现基础填充层的填充。其中，绝缘层102的材料包括氮化硅或氮氧化硅。
在其他实施例中，在后续工艺步骤中，可以去除位于位线101顶部的绝缘层102。
参考图2，形成填充满电容接触孔11(参考图1)的填充膜103，且填充膜103内具有缝隙区域12。
本实施例中，形成填充膜103的工艺包括化学气相沉积工艺或原子层沉积工艺，且填充膜103不仅填充满电容接触孔11，且还位于位线101顶部。具体地，由于工艺制程的不断微缩，在垂直于基底100表面的方向上，在位线101高度不变的情况下，相邻位线101之间的距离趋向于变小，则电容接触孔11的深宽比趋向于变大，则填充膜103中容易存在缝隙区域12，且位于电容接触孔11上方的填充膜103表面具有第一凹槽13。此外，填充膜103的顶部高于位线101顶部。
此外，由于需要形成的填充膜103的顶部需要高于位线101的顶部，则在垂直于基底100表面的方向上，填充膜103的厚度较大，因此，采用沉积速率较快的化学气相沉积工艺形成填充膜103有利于缩短半导体结构制程工艺的周期。
具体地，填充膜103为具有掺杂元素的硅材料层，其中硅材料层的材料包括单晶硅、多晶硅或者非晶硅；掺杂元素为硼元素或者磷元素。需要说明的是，本实施例中对硅材料层和掺杂元素的介绍是为了让本领域技术人员理解本方案的实现细节，并不构成对本方案的限定。在其他实施例中，填充膜103也可以为不具有掺杂元素的硅材料层；另外，填充膜103可以仅在电容接触孔11中形成，并不需要覆盖位线101的顶部。
进一步地，填充膜103中掺杂元素的掺杂浓度大于后续形成的基础填充层中掺杂元素的掺杂浓度。采用沉积工艺形成填充膜103时，在沉积过程中，通入具有掺杂元素的气体，且用于形成填充膜103时该气体的气体流量为第一气体流量；后续采用沉积工艺形成基础填充层时，通入具有掺杂元素的气体，且用于形成基础填充层时该气体的气体流量为第二气体流量，则第一气体流量要大于第二气体流量。
本实施例中，在形成填充膜103的过程中，具有掺杂元素的气体的气体流量固定不变。在其他实施例，在形成填充膜103的过程中，具有掺杂元素的气体的气体流量可以随沉积时间逐渐变大，此外，在形成填充膜103的过程中该气体的最小气体流量为第三气体流量，后续形成基础填充层的过程中具有掺杂元素的气体的最大气体流量为第四气体流量，且第三气体流量大于第四气体流量。
参考图3，采用第一刻蚀工艺，对填充膜103(图2)进行刻蚀以打开缝隙区域12(参考图2)，剩余的填充膜103作为第一填充 层113，剩余的缝隙区域12作为位于第一填充层113内的第一缝隙14，第一填充层113具有连接第一缝隙14以及电容接触孔11(参考图1)侧壁的顶面a。
由上述描述可知，填充膜103中存在缝隙区域12，且位于电容接触孔11上方的填充膜103表面具有第一凹槽13，则采用第一刻蚀工艺对填充膜103进行刻蚀，以形成第一填充层113时，在平行于基底100且沿第一缝隙14指向电容接触孔11侧壁的方向上，第一填充层113的顶面a与基底100之间的距离逐渐增大。
本实施例中，第一填充层113仅位于电容接触孔11的底部和部分侧壁上，有利于保证第一缝隙14远离基底100的开口的尺寸较大，进一步地，在垂直于电容接触孔11侧壁方向I上，第一缝隙14远离基底100的开口的宽度可以为缝隙区域12的最大宽度，即第一刻蚀工艺对缝隙区域12的打开程度较大，有利于后续基础填充层填充满第一缝隙14，且位于第一缝隙14中的基础填充层内没有空隙，有利于保证后续形成的电容接触插塞中没有空隙，以保证电容接触插塞良好的导电性。
由于填充膜103为具有掺杂元素的硅材料层，则第一填充层113也为具有掺杂元素的硅材料层，且第一填充层113中掺杂元素的掺杂浓度大于后续形成的基础填充层中掺杂元素的掺杂浓度。因而，后续采用第二刻蚀工艺，对第一填充层113和至少部分基础填充层进行刻蚀时，为获得顶部形貌较平坦的电容接触插塞，随着刻蚀时间的增加，需要第一填充层113被刻蚀的量较大，当第一填充层113 中掺杂元素的掺杂浓度大于基础填充层中掺杂元素的掺杂浓度时，可以使得相同的刻蚀时间内，第一填充层113被刻蚀的量多于基础填充层被刻蚀的量，因而更有利于形成顶部形貌较平坦的电容接触插塞。
参考图4和图5，在第一填充层113表面依次堆叠形成至少两层基础填充层，距离基底100最远的基础填充层填充满剩余电容接触孔11；在垂直于基底100且沿基底100指向位线101的方向II上，基础填充层的掺杂浓度逐层减小。因而，在垂直于基底100且沿基底100指向位线101的方向上，后续第二刻蚀工艺对基础填充层的刻蚀速率逐层减小。
本实施例中，在第一填充层113表面依次堆叠形成两层基础填充层。具体地，基础填充层为具有掺杂元素的硅材料层，相邻基础填充层中掺杂元素的掺杂浓度的差值不高于200atom/cm3。
本实施例中，在第一填充层113表面依次堆叠形成两层基础填充层的工艺步骤包括：
参考图4，形成底层填充层104，底层填充层104填充满第一缝隙14(参考图3)，位于电容接触孔11(参考图1)中的底层填充层104围成凹孔15。
具体地，形成底层填充层104的工艺包括化学气相沉积工艺或原子层沉积工艺，且底层填充层104也位于位线101顶部的上方。在沿垂直于电容接触孔11侧壁的方向I上，底层填充层104的厚度与电容接触孔11的宽度之间的比值范围为10％～40％，优选地，底 层填充层104的厚度与电容接触孔11的宽度之间的比值为20％，一方面，在电容接触孔11的深宽比较大的情况下，容易通过沉积工艺形成该厚度的底层填充层104；另一方面，在后续有利于通过第二刻蚀工艺刻蚀该厚度的底层填充层104，以形成顶部形貌较平坦的电容接触插塞。
参考图5，形成顶层填充层105，顶层填充层105填充满凹孔15(参考图4)，且顶层填充层105内具有第二缝隙16，且顶层填充层105表面与凹孔15中心轴线对应的地方还具有第二凹槽17。
具体地，形成顶层填充层105的工艺可以与形成底层填充层104的工艺相同，且顶层填充层105也位于位线101顶部的上方。需要说明的是，在其他实施例中，底层填充层104和顶层填充层105可以仅在电容接触孔11形成，并不需要覆盖位线101顶部的上方。
本实施例中，采用沉积工艺形成基础填充层时，在沉积过程中，通入具有掺杂元素的气体，在垂直于基底100且沿基底100指向位线101的方向上，用于形成基础填充层的气体的气体流量逐层减小。
具体地，用于形成底层填充层104的气体的气体流量大于用于形成顶层填充层105的气体的气体流量，且用于形成填充膜103的气体的气体流量大于用于形成底层填充层104的气体的气体流量。则第一填充层113中掺杂元素的掺杂浓度、底层填充层104中掺杂元素的掺杂浓度和顶层填充层105中掺杂元素的掺杂浓度依次减小，则后续第二刻蚀工艺对第一填充层113的刻蚀速率、底层填充层104的刻蚀速率和顶层填充层105进行刻蚀的刻蚀速率依次减 小。
本实施例中，参考图3至图5，在平行于基底100且沿第一缝隙14指向电容接触孔11侧壁的方向上，由于第一填充层113的顶面a与基底100之间的距离逐渐增大，则位于第一填充层113顶面a上的底层填充层104的顶面b与基底100之间的距离也逐渐增大。后续进行第二刻蚀工艺时，由于第二刻蚀工艺对第一填充层113、底层填充层104和顶层填充层105的刻蚀速率依次减小，使得靠近电容接触孔11侧壁的第一填充层113和底层填充层104被刻蚀的量较大，靠近第一缝隙14的中心轴线的顶层填充层105和底层填充层104被刻蚀的量较少，从而有利于减缓后续形成的电容接触插塞顶面上各处与基底100之间的距离的差异，以获得顶部形貌较为平坦的电容接触插塞。
参考图5至图7，基础填充层还位于位线101顶部；在第一填充层113表面依次堆叠形成至少两层基础填充层之后，在采用第二刻蚀工艺对第一填充层104和至少部分基础填充层进行刻蚀之前，还包括：采用第三刻蚀工艺，对基础填充层进行刻蚀至露出位于位线101顶部的绝缘层102。
此外，本实施例中，参考图6，在采用第三刻蚀工艺对基础填充层进行刻蚀之前，还包括：对基础填充层进行平坦化处理，且剩余的基础填充层位于位线101顶部。
具体地，由于采用沉积工艺形成顶层填充层105时，顶层填充层105表面与凹孔15中心轴线对应的地方具有第二凹槽17，通过 对顶层填充层105进行平坦化处理，以去除第二凹槽17，使得剩余的顶层填充层105表面较为平坦，参考图7，在后续采用第三刻蚀工艺对基础填充层进行刻蚀至露出位线101顶部时，有利于使得剩余的顶层填充层105和剩余的底层填充层104共同组成的顶面c较为平坦，即减缓顶面c上各处与基底100之间的距离的差异。
在其他实施例中，也可以不对顶层填充层105进行平坦化处理，直接采用第三刻蚀工艺对顶层填充层105和底层填充层104进行刻蚀至露出为位线101顶部，通过调节顶层填充层105和底层填充层104中掺杂元素的掺杂浓度的差值，以获得最终顶部形貌较为平坦的电容接触插塞。
本实施例中，采用第三刻蚀工艺对剩余的顶层填充层105和底层填充层104进行刻蚀至露出位于位线101顶部的绝缘层102，其中，位于位线101顶部的绝缘层102为刻蚀停止点。在其他实施例中，当位于位线101顶部的绝缘层102被去除时，位线101顶部为第三刻蚀工艺的刻蚀停止点。
由于沉积工艺引起的工艺误差，在垂直于基底100表面的方向上，在不同基底100上形成的第一填充层113和基础填充层的厚度有差异，即每个基底100上高于位线101顶部的第一填充层113和基础填充层的总厚度不一样。但每个基底100上形成的位线101和位于位线101上的绝缘层102的厚度是严格规定一致的，因而进行第三刻蚀工艺时，以位于位线101顶部的绝缘层102为刻蚀停止点时，可以使得每个基底100上剩余的底层填充层104和剩余的顶层 填充层105的总厚度一样。因而，后续进行第二刻蚀工艺时，控制刻蚀时间相同，不同基底100中均能获得顶部形貌较平坦的电容接触插塞。
此外，在其他实施例中，可以对顶层填充层105和底层填充层104均进行平坦化处理，保证剩余的底层填充层104位于位线101顶部，使得进行第三刻蚀工艺时，处于位线101顶部的绝缘层102或位线101顶部可以作为刻蚀停止点即可。
参考图7至图9，采用第二刻蚀工艺对第一填充层113和至少部分基础填充层进行刻蚀的过程中，第二缝隙16(参考图5)被去除，有利于保证后续形成的电容接触插塞中没有空隙，从而有利于保证电容接触插塞具有良好的导电性。
具体地，本实施例中，采用第二刻蚀工艺对第一填充层113、剩余的顶层填充层105和剩余的底层填充层104进行刻蚀。在其他实施例中，在形成顶层填充层105之后，可以直接采用第二刻蚀工艺对第一填充层113、顶层填充层105和底层填充层104进行刻蚀。
进一步地，在垂直于基底100且沿基底100指向位线101的方向上，第二刻蚀工艺对基础填充层的刻蚀速率逐层减小，即第二刻蚀工艺对剩余的底层填充层104的刻蚀速率大于对剩余的顶层填充层105的速率。此外，本实施例中，第三刻蚀工艺与第二刻蚀工艺的工艺参数相同。在其他实施例中，第三刻蚀工艺与第二刻蚀工艺的工艺参数也可以不同。
继续参考图7至图9，本实施例中，采用第二刻蚀工艺对第一 填充层113、剩余的顶层填充层105和剩余的底层填充层104进行刻蚀的过程中，在电容接触孔11(参考图1)中会形成刻蚀曲面，其中，在平行于基底100且沿第一缝隙12(参考图2)指向电容接触孔11侧壁的方向上，刻蚀曲面上各点处的斜率逐渐增大。
具体地，刻蚀曲面为第二刻蚀工艺中刻蚀物质与第一填充层113和至少部分基础填充层相接触的表面。因为在垂直于基底100且沿基底100指向位线101的方向上，第二刻蚀工艺对基础填充层的刻蚀速率逐层减小，所以，随着第二刻蚀工艺的进行，在平行于基底100且沿第一缝隙12指向电容接触孔11侧壁的方向上，刻蚀曲面上各点的斜率逐渐增大的趋势减缓，有利于最终获得顶部形貌较为平坦的电容接触插塞106。
进一步地，参考图7所示的刻蚀时刻，点E为此时刻蚀曲面上剩余的底层填充层104与剩余的顶层填充层105的交界点；参考图8所示的刻蚀时刻，点F为此时刻蚀曲面上剩余的底层填充层104与剩余的顶层填充层105的交界点，需要说明的是，点E和点F为刻蚀曲面上不同刻蚀时刻相似位置所对应的点。结合参考图7和图8可知，点F的斜率小于点E的斜率，则随着第二刻蚀工艺的进行，刻蚀曲面上各点的斜率逐渐增大的趋势减缓。
本实施例中，采用第二刻蚀工艺对第一填充层113、剩余的顶层填充层105和至少部分剩余的底层填充层104进行刻蚀，目的是在电容接触孔11中形成电容接触插塞106。
具体地，剩余的第一填充层113和剩余的底层填充层104共同 组成电容接触插塞106。此外，电容接触插塞106远离基底100的顶面与基底100表面平行，便于后续在电容接触插塞106上形成其他导电结构，且有利于降低电容接触插塞106与其他导电结构之间的接触电阻，并有利于提高半导体结构的良率。在其他实施例中，通过调节底层填充层104和顶层填充层105中掺杂元素的掺杂浓度的差值，电容接触插塞106也可以只由剩余的第一填充层113构成，或者，电容接触插塞106也可以由剩余的第一填充层113、剩余的底层填充层104和剩余的顶层填充层105共同构成。
进一步地，在垂直于基底100表面的方向上，电容接触插塞106的厚度与位线101的高度的比值范围为10％～80％。在一个例子中，电容接触插塞106的厚度与位线101的高度的比值为30％。
本实施例中，通过控制第一填充层113、底层填充层104和顶层填充层105中的掺杂元素的掺杂浓度逐层减小，使得后续通过刻蚀工艺形成电容接触插塞106时，可以获得顶部形貌较为平坦且内部没有空隙的电容接触插塞106，从而有利于提高电容接触插塞106自身的导电性和降低电容接触插塞106与其他导电结构之间的接触电阻，从而有利于提高半导体结构的良率。
本申请第二实施例还提供一种半导体结构的制作方法，该实施例与前述实施例大致相同，主要区别在于形成的基础填充层的层数不同。以下将结合附图5对本申请第二实施例提供的半导体结构的制作方法进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细描述，在此不再赘述。
图10至图13为本实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图10，在第一填充层113表面依次堆叠形成三层基础填充层，距离基底100最远的基础填充层填充满剩余的电容接触孔11。
具体地，在垂直于基底200且沿基底200指向位线201的方向上，三层基础填充层依次为底层填充层204、中间填充层205和顶层填充层206。其中，底层填充层204、中间填充层205和顶层填充层206中掺杂元素的掺杂浓度逐层减小。因而，本实施例中，采用沉积工艺形成三层基础填充层时，在沉积过程中，通入具有掺杂元素的气体，在垂直于基底200且沿基底200指向位线201的方向上，用于形成基础填充层的气体的气体流量逐层减小。
本实施例中，位于电容接触孔11中的底层填充层204围成第一凹孔，部分中间填充层205位于第一凹孔中，且位于第一凹孔中的中间填充层205围成第二凹孔。顶层填充层206填充满第二凹孔，且顶层填充层206内具有第二缝隙26，且顶层填充层206表面与第二缝隙26中心轴线对应的地方还具有第二凹槽27。
其中，形成底层填充层204、中间填充层205和顶层填充层206的工艺包括化学气相沉积工艺或原子层沉积工艺。
参考图10至图13，采用第二刻蚀工艺，对第一填充层213和至少部分基础填充层进行刻蚀的过程中，第二缝隙26被去除，有利于保证后续形成的电容接触插塞207中没有空隙，从而有利于保证电容接触插塞207具有良好的导电性。
参考图11，对应第二刻蚀工艺进行至第一时刻，此时剩余的底层填充层204、剩余的中间填充层205和剩余的顶层填充层206共同构成第一顶面d；参考图12，对应第二刻蚀工艺进行至第二时刻，此时剩余的底层填充层204、剩余的中间填充层205和剩余的顶层填充层206共同构成第二顶面e。结合参考图11和图12，第一顶面d的凹陷程度大于第二顶面e的凹陷程度。
可见，采用第二刻蚀工艺对第一填充层213、底层填充层204、中间填充层205和顶层填充层206进行刻蚀的过程中，在电容接触孔中会形成刻蚀曲面。具体地，刻蚀曲面为第二刻蚀工艺中刻蚀物质与第一填充层213和至少部分基础填充层相接触的表面。因为在垂直于基底200且沿基底200指向位线201的方向上，第二刻蚀工艺对基础填充层的刻蚀速率逐层减小，所以，随着第二刻蚀工艺的进行，在平行于基底200且沿第一缝隙指向电容接触孔侧壁的方向上，刻蚀曲面上各点的斜率逐渐增大的趋势减缓，有利于最终获得顶部形貌较为平坦的电容接触插塞207。
参考图13，剩余的第一填充层213和剩余的第三底层填充层204共同组成电容接触插塞207。此外，电容接触插207远离基底200的顶面与基底200表面平行，便于后续在电容接触插塞207上形成其他导电结构，且有利于降低电容接触插塞207与其他导电结构之间的接触电阻，且有利于提高半导体结构的良率。
在其他实施例中，通过调节底层填充层204、中间填充层205和顶层填充层206中掺杂元素的掺杂浓度的差值，电容接触插塞207 也可以只由剩余的第一填充层213构成；或者，电容接触插塞207也可以由剩余的第一填充层213、剩余的底层填充层204和剩余的中间填充层205共同构成；或者，电容接触插塞207也可以由剩余的第一填充层213、剩余的底层填充层204、剩余的中间填充层205和剩余的顶层填充层206共同构成。
相应地，本申请第三实施例还提供一种半导体结构，该半导体结构由上述任一实施例提供的半导体结构的制作方法制成。
参考图9，半导体结构包括：基底100，基底100上具有多条相互分立的位线101，相邻位线101之间具有电容接触孔；电容接触插塞106，电容接触插塞106位于电容接触孔底部，电容接触插塞106由第一填充层113和基础填充层构成。本实施例中，基础填充层为上述实施例中的底层填充层104，在其他实施例中，基础填充层也可以为至少两层的叠层结构。
具体地，第一填充层113顶部表面存在孔洞，底层填充层104填充第一填充层113顶部表面的孔洞，有利于保证电容接触插塞106中没有空隙，且电容接触插塞106的顶部形貌较为平坦。在其他实施例中，电容接触插塞106可以只由第一填充层113构成。
进一步地，电容接触插塞106远离基底100的顶面与基底100表面平行，便于后续在电容接触插塞106上形成其他导电结构，且有利于降低电容接触插塞106与其他导电结构之间的接触电阻，并有利于提高半导体结构的良率。
此外，第一填充层113和底层填充层104均为具有掺杂元素的 硅材料层，且第一填充层113中掺杂元素的掺杂浓度大于底层填充层104中掺杂元素的掺杂浓度。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (17)

  1. 一种半导体结构的制作方法，其中，包括：
    提供基底，所述基底上具有多个相互分立的位线，相邻所述位线之间具有电容接触孔；
    形成填充满所述电容接触孔的填充膜，且所述填充膜内具有缝隙区域；
    采用第一刻蚀工艺，对所述填充膜进行刻蚀以打开所述缝隙区域，剩余的所述填充膜作为第一填充层，剩余的所述缝隙区域作为位于所述第一填充层内的第一缝隙，所述第一填充层具有连接所述第一缝隙以及所述电容接触孔侧壁的顶面，且在沿所述第一缝隙指向所述电容接触孔侧壁的方向上，所述顶面与所述基底之间的距离逐渐增大；
    在所述第一填充层表面依次堆叠形成至少两层基础填充层，距离所述基底最远的所述基础填充层填充满剩余所述电容接触孔；
    在垂直于所述基底且沿所述基底指向所述位线的方向上，所述基础填充层的掺杂浓度逐层减小；
    采用第二刻蚀工艺，对所述第一填充层和至少部分所述基础填充层进行刻蚀，以形成电容接触插塞。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述电容接触插塞远离所述基底的顶面与所述基底表面平行。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，所 述第一填充层仅位于所述电容接触孔的底部和部分侧壁上。
  4. 根据权利要求1所述的半导体结构的制作方法，其中，在所述第一填充层表面依次堆叠形成至少两层基础填充层的工艺步骤包括：形成底层填充层，所述底层填充层填充满所述第一缝隙，位于所述电容接触孔中的所述底层填充层围成凹孔；形成顶层填充层，所述顶层填充层填充满所述凹孔，且所述顶层填充层内具有第二缝隙。
  5. 根据权利要求1所述的半导体结构的制作方法，其中，所述基础填充层为具有掺杂元素的硅材料层，相邻所述基础填充层中所述掺杂元素的掺杂浓度的差值不高于200atom/cm3。
  6. 根据权利要求1所述的半导体结构的制作方法，其中，采用沉积工艺形成所述基础填充层，且在沉积过程中，通入具有所述掺杂元素的气体，在垂直于所述基底且沿所述基底指向所述位线的方向上，用于形成所述基础填充层的所述气体的气体流量逐层减小。
  7. 根据权利要求4所述的半导体结构的制作方法，其中，采用所述第二刻蚀工艺对所述第一填充层和至少部分所述基础填充层进行刻蚀的过程中，所述第二缝隙被去除。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，采用所述第二刻蚀工艺对所述第一填充层和至少部分所述基础填充层进行刻蚀的过程中，在垂直于所述基底且沿所述基底指向所述位线的方向上，所述第二刻蚀工艺对所述基础填充层的刻蚀速率 逐层减小。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，采用所述第二刻蚀工艺，对所述第一填充层、所述顶层填充层和至少部分所述底层填充层进行刻蚀，以形成所述电容接触插塞。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，所述基础填充层还位于所述位线顶部；在所述第一填充层表面依次堆叠形成至少两层基础填充层之后，在采用所述第二刻蚀工艺对所述第一填充层和至少部分所述基础填充层进行刻蚀之前，还包括：
    采用第三刻蚀工艺，对所述基础填充层进行刻蚀至露出所述位线顶部。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，在采用所述第三刻蚀工艺对所述基础填充层进行刻蚀之前，还包括：
    对所述基础填充层进行平坦化处理，且剩余的所述基础填充层位于所述位线顶部。
  12. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一填充层为具有掺杂元素的硅材料层，且所述第一填充层中所述掺杂元素的掺杂浓度大于所述基础填充层中所述掺杂元素的掺杂浓度。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，采用沉积工艺形成所述填充膜和所述基础填充层，且在沉积过程 中，通入具有所述掺杂元素的气体，用于形成所述填充膜时的所述气体的气体流量为第一气体流量，用于形成所述基础填充层时的所述气体的气体流量为第二气体流量，所述第一气体流量大于所述第二气体流量。
  14. 一种半导体结构，其中，包括：
    基底，所述基底上具有多条相互分立的位线，相邻所述位线之间具有电容接触孔；
    电容接触插塞，所述电容接触插塞位于所述电容接触孔底部，所述电容接触插塞由第一填充层构成或者所述电容接触插塞由第一填充层和基础填充层构成。
  15. 根据权利要求14所述的半导体结构，其中，所述电容接触插塞远离所述基底的顶面与所述基底表面平行。
  16. 根据权利要求14所述的半导体结构，其中，所述电容接触插塞由所述第一填充层和所述基础填充层构成，所述第一填充层顶部表面存在孔洞，所述基础填充层填充所述第一填充层顶部表面的孔洞。
  17. 根据权利要求16所述的半导体结构，其中，所述第一填充层和所述基础填充层均为具有掺杂元素的硅材料层，且所述第一填充层中所述掺杂元素的掺杂浓度大于所述础填充层中所述掺杂元素的掺杂浓度。
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