WO2023133993A1 - 半导体结构及半导体结构的制备方法 - Google Patents

半导体结构及半导体结构的制备方法 Download PDF

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Publication number
WO2023133993A1
WO2023133993A1 PCT/CN2022/079804 CN2022079804W WO2023133993A1 WO 2023133993 A1 WO2023133993 A1 WO 2023133993A1 CN 2022079804 W CN2022079804 W CN 2022079804W WO 2023133993 A1 WO2023133993 A1 WO 2023133993A1
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semiconductor structure
layer
inversion region
isolation
bit line
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PCT/CN2022/079804
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Publication of WO2023133993A1 publication Critical patent/WO2023133993A1/zh
Priority to US18/446,514 priority Critical patent/US20230389271A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a method for preparing the semiconductor structure.
  • MOSFET Metal-oxide-semiconductor field-effect transistors
  • MOSFET Metal-oxide-semiconductor field-effect transistors
  • GAA Gate-All-Around
  • an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, including: providing a substrate; forming a bit line extending along a first direction in the substrate; forming an active pillar on the bit line, having The bottom surface of the source pillar is in contact with the bit line and the active pillar is doped with N-type elements; an inversion region is formed on the side of the active pillar, and the inversion region is doped with P-type elements; a dielectric layer is formed in sequence and along the The word line extending in the second direction covers part of the inversion area, and the dielectric layer is located between the word line and the inversion area.
  • a selective epitaxial growth process is used to form an inversion region.
  • P-type elements are doped in situ.
  • the inversion region before forming the inversion region, it also includes: thinning the sidewall of the active column with a partial thickness.
  • a wet etching process is adopted for thinning treatment, and the etching liquid used in the wet etching process is an alkaline liquid.
  • the thinning process before performing the thinning process, it includes: sequentially forming a stacked first isolation layer, a sacrificial layer, and a second isolation layer on the substrate and the top surface of the bit line, and the second isolation layer has a through hole penetrating through the thickness of the second isolation layer. , and the sacrificial layer is exposed at the bottom of the through hole; the sacrificial layer is removed to expose the side of the active column.
  • the material of the sacrificial layer includes silicon nitride, and the sacrificial layer is removed by hot phosphoric acid etching solution.
  • the process step of sequentially forming a stacked first isolation layer, a sacrificial layer, and a second isolation layer on the substrate includes: sequentially forming a stacked first isolation film, a sacrificial layer, and a second isolation film on the substrate and the top surface of the bit line and a first mask layer having a first opening; using the first mask layer as a mask, sequentially etching the first mask layer, the second isolation film, the sacrificial layer and the first isolation film along the first opening to form a trench Groove, the bit line is exposed at the bottom of the trench, and the remaining first isolation film is used as the first isolation layer; the active column is formed, and the active column fills the trench; the third isolation film is sequentially formed on the second isolation film, and the third The isolation film covers the top surface of the active column; the third isolation film and the second isolation film are patterned to form through holes, and the remaining second isolation film and the third isolation film together serve as a second isolation layer.
  • the process steps of sequentially forming the first isolation layer, the sacrificial layer and the second isolation layer on the substrate include: forming an active pillar on the substrate; film, the sacrificial layer is also located on part of the side of the active column, and the fourth isolation film is located on part of the side and top surface of the active column; the fourth isolation film is patterned to form a through hole, and the remaining fourth isolation film is used as the second isolation layer.
  • the process steps of forming word lines include: forming a conductive film that fills through holes, and the conductive film is also located between the first isolation layer and the second isolation layer, and the conductive film surrounds the inversion region; patterning the conductive film, forming several separate word lines.
  • the step of patterning the conductive film includes: removing the conductive film located in the through hole, and removing the conductive film directly below the through hole, leaving the conductive film as the word line.
  • the word lines after forming the word lines, it also includes: forming an insulating layer filling the through holes, and the insulating layer also fills the area between adjacent word lines.
  • epitaxial growth process is used to form the bit line; the process steps of forming the bit line include: providing an initial substrate with a channel extending along the first direction; forming the bit line and filling the channel with the bit line.
  • an embodiment of the present disclosure further provides a semiconductor structure on the other hand, including: a substrate having a bit line extending along a first direction in the substrate; an active pillar located on the bit line, having The bottom surface of the source column is in contact with the bit line and the active column is doped with N-type elements; the inversion area is located on the side of the active column, and the inversion area is doped with P-type elements; the dielectric layer and The word line extending along the second direction, the dielectric layer and the word line wrap part of the inversion area, and the dielectric layer is located between the word line and the inversion area.
  • bit line is a semiconductor bit line
  • semiconductor bit line is doped with N-type elements.
  • the host material of the inversion region is the same as that of the active pillar.
  • the main body material of the inversion region includes silicon, germanium or silicon germanium.
  • the thickness of the inversion region ranges from 4 nm to 15 nm.
  • the height of the entire inversion region is 8nm-30nm greater than the height of a part of the inversion region covered by the dielectric layer and the word line.
  • FIGS. 1 to 26 are schematic cross-sectional structure diagrams corresponding to each step in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • 27 to 37 are schematic cross-sectional structure diagrams corresponding to each step in the method for preparing a semiconductor structure provided by another embodiment of the present disclosure.
  • FIG. 38 is a schematic diagram of a partial cross-sectional structure when a positive voltage is applied to the gate terminal and the source terminal of the semiconductor structure provided by an embodiment of the present disclosure
  • 39 is a schematic diagram of a partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure when a positive voltage is applied to the gate terminal and a negative voltage is applied to the source terminal.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the semiconductor structure.
  • An active column is formed on a bit line, the bottom surface of the active column is in contact with the bit line, and N-type elements are doped in the active column;
  • An inversion area is formed on the side of the column, and P-type elements are doped in the inversion area;
  • a dielectric layer and a word line extending along the second direction are formed in sequence to cover part of the inversion area, and the dielectric layer is located between the word line and the inversion area between.
  • the active column can be used as the source or the drain of the semiconductor structure, and the word line can be used as the gate of the semiconductor structure.
  • the inversion area has charge storage function
  • the inversion region can be regarded as an equivalent capacitance. Therefore, the process flow for preparing the capacitor can be simplified, and it is beneficial to reduce the line width of the semiconductor structure, so that the size of the capacitor can be larger to ensure a larger storage capacity of the capacitor, which is beneficial to improving the storage density of the integrated circuit.
  • FIGS. 1 to 26 are schematic cross-sectional structure diagrams corresponding to each step in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure, wherein FIGS. 1 to 13 are diagrams of a semiconductor structure along the second direction Y provided by an embodiment of the present disclosure. Schematic cross-sectional structure diagrams corresponding to each step in the preparation method. FIGS. 14 to 26 are schematic cross-sectional structure diagrams corresponding to each step in a method for preparing a semiconductor structure along the first direction X according to an embodiment of the present disclosure.
  • a substrate 100 is provided; a bit line 101 extending along a first direction X is formed in the substrate 100 .
  • the orthographic projections of the second direction Y and the first direction X on the substrate 100 are perpendicular to each other;
  • the material of the substrate 100 may be a semiconductor material.
  • the semiconductor material may be any one of silicon, germanium, silicon germanium or silicon carbide.
  • an epitaxial growth process is used to form the bit line 101; the process steps of forming the bit line may include: providing an initial substrate having a channel extending along the first direction X in the initial substrate (not shown in the figure); A bit line 101 is formed, and the bit line 101 fills the trench.
  • the bit line 101 is a semiconductor bit line, and the semiconductor bit line is doped with an N-type element, and the doped element can be used as a carrier, which can improve the transfer of carriers between the bit line 101 and the subsequently formed active column and diffusion, which is beneficial to improve the conductivity between the bit line 101 and the active pillar.
  • N-type elements can be doped in situ, and the N-type elements can be group V elements such as phosphorus (P) elements, bismuth (Bi) elements, antimony (Sb) elements, or arsenic (As) elements.
  • the material is the same as that of the initial substrate, which can be any one of silicon, germanium, silicon germanium or silicon carbide.
  • N-type elements can be implanted into the substrate 100 to form semiconductor bit lines through ion implantation process or diffusion process, that is, the bit line 101 and the substrate 100 have an integrated structure, thereby improving the interface performance between the bit line 101 and the substrate 100 , which is conducive to improving the interface state defects, thereby improving the electrical properties of the semiconductor structure.
  • the bit line 101 is a metal bit line
  • the semiconductor structure further includes a bit line barrier layer and a bit line dielectric layer
  • the bit line barrier layer is located between the substrate 100 and the metal bit line
  • the bit line dielectric layer is located between the metal bit line
  • the wire is far away from the surface of the bit line barrier layer, and the resistance of the metal itself is small, which is conducive to improving the conductivity of the bit line 101 and the subsequent formation of the active column, and further conducive to improving the conductivity of the bit line 101 .
  • the material of the metal bit line can be tungsten, copper and silver; the material of the bit line barrier layer can be silicon nitride, silicon oxide or silicon carbide; the material of the bit line dielectric layer can be silicon oxide or silicon nitride.
  • a first isolation layer 110 , a sacrificial layer 102 and a second isolation layer 130 are sequentially formed on the substrate 100 and the top surface of the bit line 101 , and the second isolation layer 130 has a
  • the via hole 114 runs through the thickness of the second isolation layer 130 , and the bottom of the via hole 114 exposes the sacrificial layer 102 ; the sacrificial layer 102 is removed to expose the side of the active pillar 120 .
  • a stacked first isolation film 111, a sacrificial layer 102, a second isolation film 131, and a first opening (not shown in the figure) are sequentially formed. ) of the first mask layer 103.
  • the material of the sacrificial layer 102 is different from that of the first isolation film 111 and the second isolation film 131, and the material of the first mask layer 103 is different from that of the sacrificial layer 102, the first isolation film 111, and the second isolation film.
  • the materials of the film 131 are all different.
  • the material of the sacrificial layer 102 may be silicon nitride or silicon oxide.
  • the material of the first isolation film 111 is an insulating material, and the insulating material may be silicon dioxide, silicon carbide or silicon nitride; the material of the second isolation film 131 is the same as that of the first isolation film 111 .
  • the material of the second isolation film may also be different from that of the first isolation film.
  • the first mask layer 103 As a mask, the first mask layer 103, the second isolation film 131, the sacrificial layer 102, and the first isolation film 111 are sequentially etched along the first opening to form a trench.
  • the groove 104 , the bit line 101 is exposed at the bottom of the groove 104 , and the remaining first isolation film 111 is used as the first isolation layer 110 .
  • the bottom of the trench 104 exposes the bit line 101 to connect the bit line to the subsequently formed active pillar, and can serve as a base for the epitaxial growth of the active pillar, which is beneficial to the integrity of the subsequently formed active pillar.
  • an active column 120 is formed on the bit line 101, the bottom surface of the active column 120 is in contact with the bit line 101 and the active column 120 is doped with N-type elements, and the active column 120 fills the trench Groove 104.
  • the active pillar 120 includes a first region 121 , a second region 122 and a third region 123 sequentially distributed from the surface of the substrate 100 to a direction away from the substrate 100 .
  • the first region 121, the second region 122 and the third region 123 can be regarded as the main body of the active pillar 120
  • the main body of the active pillar 120 can be an intrinsic semiconductor
  • the intrinsic semiconductor material can be silicon, germanium or germanium silicon. It can be understood that an intrinsic semiconductor is a semiconductor that has not been doped.
  • N-type elements are doped in the second region 122 , and the doping elements in the second region 122 and the doping elements in the bit line 101 may be the same. In some other embodiments, the doping elements in the second region 122 and the doping elements in the bit line 101 may also be different, for example, the doping element in the bit line 101 is doped with element phosphorus, and the element doped in the second region 122 is arsenic; The first region 121 , the second region 122 and the third region 123 are all doped with N-type elements.
  • the active column 120 is formed by a low-pressure chemical vapor deposition process; the source materials used in the low-pressure chemical vapor deposition process include source gas and N-type element source gas, and the N-type element source gas is used to provide N-type elements.
  • the source gas may be a silicon source gas, and the silicon source gas may specifically be silane, disilane, dichlorosilane or trichlorosilane; the N-type element source gas may specifically be phosphine, arsine or antimony hydride.
  • the source gas can also be a germanium source gas, and the germanium source gas can specifically be germane.
  • the material of the active pillar 120 is the same as that of the bit line 101, so the lattice mismatch factor between the active pillar 120 and the bit line 101 is 0, effectively avoiding lattice defects inside the active pillar 120 and The problem of increased internal resistance is beneficial to improve the conductivity of the active pillar 120 .
  • the material of the active pillar 120 and the material of the bit line 101 may be different.
  • a third isolation film 132 and a second mask layer 113 are sequentially formed on the second isolation film 131 , and the third isolation film 132 covers the top surface of the active pillar 120 .
  • the material of the third isolation film 132 and the material of the second isolation film 131 may be the same. In other embodiments, the material of the third isolation film may be different from that of the second isolation film.
  • the second mask layer 113, the third isolation film 132, and the second isolation film 131 are patterned to form the through hole 104, and the remaining second isolation film 131 and the third isolation film 132 together serve as the first Two isolation layers 130 .
  • the sacrificial layer 102 is exposed at the bottom of the through hole 104 , which is convenient for subsequent etching to remove the sacrificial layer 102 and form an inversion region and a word line.
  • the sacrificial layer 102 and the second mask layer 113 are removed to expose the sides of the active pillars 120 .
  • the sacrificial layer 102 is removed by a wet etching process, and the etching temperature is kept between 140° C. and 200° C., and the etching temperature may be 160° C. specifically.
  • the etchant used in the wet etching process is a hot phosphoric acid etchant, which is made of 85% concentrated phosphoric acid and 15% deionized water.
  • the etching solution used in the wet etching process is 49% hydrofluoric acid.
  • the sidewall of the partial thickness active pillar 120 is thinned.
  • the sidewall of the second region 122 is thinned.
  • a wet etching process is adopted for the thinning treatment, and the etching liquid used in the wet etching process is an alkaline liquid, and the alkaline liquid may be an alkaline copper chloride etching liquid.
  • an inversion region 140 is formed on the side of the active pillar 120 , and the inversion region 140 is doped with P-type elements.
  • the inversion region 140 is formed on the side of the thinned second region 122, the second region 122 is doped with N-type elements, the inversion region 140 is doped with P-type elements, the second region The doping element type of 122 is opposite to that of the inversion region 140 .
  • the active pillar 120 can be used as a source or drain of the semiconductor structure, and the word line formed subsequently to surround the inversion region 140 can be used as a gate of the semiconductor structure.
  • a bridge is formed in the active column 120, and the P-type elements in the inversion region 140 are converted into electron-hole pairs, and the electrons can leave the inversion along the bridge.
  • the P-type element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga) or indium (In).
  • the thickness of the inversion region 140 ranges from 4 nm to 15 nm, and the thickness of the inversion region 140 can specifically be 4nm, 8nm, 13nm or 15nm, the thickness range of the inversion region 140 can ensure that the hole storage area in the inversion region 140 is larger, and can accommodate more holes, that is, the capacitance of the capacitor is larger, thereby ensuring the capacitance
  • the storage capacity of the semiconductor structure is large, which is beneficial to increase the storage density of the semiconductor structure; it can also avoid the situation that the width of the inversion region 140 in the horizontal direction of the semiconductor structure is too large and the width of the subsequently formed word line is too small.
  • the height of the entire inversion region 140 is 8 nm to 30 nm greater than the height of a part of the inversion region 140 surrounded by the subsequently formed dielectric layer and the word line. , that is, the height of the inversion region 140 located on the sides of the first isolation layer 110 and the third isolation layer 130 ranges from 8nm to 30nm, specifically 8nm, 10nm, 20nm or 30nm, so that the storage space in the inversion region 140 can be ensured.
  • the area of the hole is larger, which can accommodate more holes, that is, the capacity of the capacitor is larger, thereby ensuring a larger storage capacity of the capacitor, which is conducive to improving the storage density of the semiconductor structure; it can also prevent the inversion region 140 from occupying the semiconductor structure.
  • the line width in the vertical direction is too large.
  • the height of the inversion region 140 located on the side of the second region 122 is 8nm, that is, the height of the part of the inversion region 140 covered by the subsequently formed dielectric layer and the word line is 20nm, which is located at the second region 122.
  • the total height of the inversion region 140 on the side of the first isolation layer 110 and the third isolation layer 130 is 8 nm, so the height of the entire inversion region 140 may be 28 nm.
  • the height of the inversion region 140 on the side of the first isolation layer 110 and the height of the inversion region 140 on the side of the third isolation layer 130 may be Equal; the sides of the inversion region 140 are flush with the sides of the first region 121 and the sides of the third region 123, in other words, the orthographic projection of the inversion region 140 on the substrate 100 is located at the orthographic projection of the first region 121 on the substrate 100 Inner and equal, it is beneficial to the surface flatness of the subsequently formed dielectric layer.
  • the inversion region 140 may be partially doped.
  • the inversion region 140 includes a body and two dopant bodies. The body is located between adjacent dopant bodies. The body may be No doping treatment was performed.
  • the body material of the inversion region 140 includes silicon, germanium or silicon germanium.
  • the main body material of the inversion region 140 and the main body material of the active pillar 120 can be the same, then the lattice mismatch factor of the active pillar 120 and the inversion region 140 is 0, effectively avoiding The problems of lattice defects and increased internal resistance are beneficial to improve the conductivity of the inversion region 140 .
  • the body material of the inversion region 140 and the body material of the active pillar 120 may be different.
  • the inversion region 140 is formed by using a Selective Epitaxy Growth (SEG) process; in the process step of forming the inversion region 140 , P-type elements are doped in situ.
  • the source materials used in the selective epitaxial growth process include source gas, etching gas hydrogen chloride, and doping element source gas.
  • the doping element source gas is used to provide P-type elements.
  • the source gas can be silicon source gas.
  • the silicon source gas can be specifically is silane, disilane, dichlorosilane or trichlorosilane, and the doping element source gas can be borane (BH 3 ), diborane (B 2 H 6 ) or boron trichloride (BCl 3 ).
  • the source gas may also be a germanium source gas, and the germanium source gas may specifically be germane.
  • a dielectric layer 150 and a word line 160 extending along the second direction Y are sequentially formed to cover part of the inversion region 140, and the dielectric layer 150 is located between the word line 160 and the inversion region. Between 140.
  • the word line 160 may serve as a gate of the semiconductor structure, and the word line 160 extending along the second direction Y covers part of the inversion region 140, and the inversion region 140 is located on the side of the active pillar 120, that is, the word line 160 also covers part of the active column 120, and the semiconductor structure is a GAA structure, which can realize the four-sided wrapping of the gate to the active column 120, and can avoid the leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size In other cases, the occupied line width of the word line 160 in the vertical direction is reduced, which is beneficial to enhancing gate control performance and improving the integration of the semiconductor structure.
  • a dielectric layer 150 is formed on the side of the inversion region 140 , and the dielectric layer 150 covers part of the inversion region 140 .
  • the dielectric layer 150 is used as a gate dielectric layer or a gate oxide layer for suppressing short channel effects, such as suppressing tunneling leakage current.
  • the material of the dielectric layer 150 may be silicon dioxide, silicon carbide, silicon nitride or other high dielectric constant materials.
  • the conductive film 105 is filled with the via hole 114 , and the conductive film 105 is also located between the first isolation layer 110 and the second isolation layer 130 , and the conductive film 105 surrounds the inversion region 140 .
  • the conductive film 105 is located on the surface of the dielectric layer 150 and surrounds the dielectric layer 150 , and the conductive film 105 extends along the second direction Y.
  • the material of the conductive film 105 can be any one of metal tungsten, copper or aluminum.
  • the second direction Y can be any direction perpendicular to the sidewall of the active pillar 120 and toward the axis of the active pillar 120 .
  • the second direction Y in the embodiment of the present disclosure is a direction perpendicular to the orthographic projection of the first direction X on the substrate 100 is only an example for illustration.
  • the conductive film 105 is patterned to form several word lines 160 separated from each other.
  • the step of patterning the conductive film 105 includes: removing the conductive film 105 inside the via hole 114 and removing the conductive film 105 directly below the via hole 114 , leaving the conductive film 105 as the word line 160 .
  • an insulating layer 170 filling the via hole 114 is formed, and the insulating layer 170 also fills a region between adjacent word lines 160 .
  • the material of the insulating layer 170 may be silicon dioxide, silicon carbide or silicon nitride.
  • the first isolation layer 110 , the second isolation layer 130 and the insulating layer 170 are made of the same material, which can reduce interface defects between the first isolation layer 110 and the insulating layer 170 and between the second isolation layer 130 and the insulating layer 170 .
  • the materials of the first isolation layer 110 , the second isolation layer 130 and the insulating layer 170 may be different or both of them may be the same.
  • the active pillar 120 is doped with N-type elements
  • the inversion region 140 is located on the side of the active pillar 120
  • the inversion region 140 is doped with P-type elements.
  • the Y-extended word line 160 covers part of the inversion region 140 , and the doping element type of the active pillar 120 is opposite to that of the inversion region 140 .
  • the active pillar 140 may serve as a source or drain of the semiconductor structure
  • the word line 160 may serve as a gate of the semiconductor structure.
  • the inversion region 140 can store holes, that is, the inversion region 140 has the function of storing charges, and the inversion region 140 can be regarded as an equivalent capacitance, which can simplify the preparation of capacitance
  • the process flow is beneficial to reduce the line width of the semiconductor structure. Therefore, the size of the capacitor can be larger to ensure a larger storage capacity of the capacitor, which is beneficial to improving the storage density of the semiconductor structure.
  • the foregoing is an example in which the first isolation layer, the sacrificial layer, and the second isolation layer are first formed, and then the active column is formed.
  • Other embodiments of the present disclosure also provide The preparation method of forming the active column first, and then forming the first isolation layer, the sacrificial layer and the second isolation layer is provided. Details of the same or similar contents or elements as the descriptions given in the foregoing embodiments will not be repeated, and only descriptions different from the above descriptions will be described in detail. The following will be described in detail in conjunction with Fig. 27 to Fig. 37:
  • 27 to 37 are schematic diagrams of cross-sectional structures corresponding to various steps in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • a substrate 200 is provided; a bit line 201 extending along the first direction X is formed in the substrate 200; an active column 220 is formed on the bit line 201, and the bottom surface of the active column 220 is in contact with the bit line 201 And the active column 220 is doped with an N-type element; an inversion region 240 is formed on the side of the active column 220, and the inversion region 240 is doped with a P-type element; a dielectric layer 250 is formed in sequence and along the second direction Y
  • the extended word line 260 covers part of the inversion region 240 , and the dielectric layer 250 is located between the word line 260 and the inversion region 240 .
  • a substrate 200 having bit lines 201 extending along a first direction X therein is provided.
  • an active column 220 is formed on a substrate 200, and the active column 220 includes a first region 221, a second region 222, and a third region 223 that are sequentially distributed from the surface of the substrate 200 to a direction away from the substrate 200, and the second region
  • the active pillars 222 are doped with N-type ions.
  • a first isolation layer 210 , a sacrificial layer 202 , a fourth isolation film 233 , and a second mask layer 213 are sequentially formed on the substrate 200 , the sacrificial layer 202 is also located on a part of the side of the active pillar 220 , and the fourth The isolation film 233 is located on a part of the side and the top surface of the active pillar 220 .
  • the first mask layer 103 is patterned to form an opening, and then the fourth isolation film 233 is etched along the opening to form a via hole 214, and the fourth isolation film 233 is left as the first Two isolation layers 230 .
  • the subsequent preparation method for forming the semiconductor structure is the same or similar to the preparation method for forming the semiconductor structure in some embodiments of the present disclosure (refer to FIG. 7-FIG. 13 and FIG. 20-FIG. 26 ), and will not be repeated here.
  • the preparation method for forming a semiconductor structure described in FIGS. 27 to 37 and the preparation method for forming a semiconductor structure described in FIGS. 1 to 26 are only whether the active pillar is formed first or the active pillar is formed later, that is, The difference in the process flow, that is to say, the preparation method, content and components for forming the semiconductor structure described in FIGS. 1 to 26 , and the formation of the semiconductor structure described in FIGS. 27 to 37 are also applicable.
  • Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which can form the semiconductor structure provided in the following embodiments.
  • the semiconductor structure provided in some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 13 and FIG. 26 are schematic cross-sectional structural diagrams of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic cross-sectional structure diagram of a semiconductor structure along the second direction Y provided by an embodiment of the present disclosure
  • FIG. 26 is a schematic cross-sectional structural diagram of a semiconductor structure provided along the first direction X according to an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 100 with a bit line 101 extending along a first direction X in the base 100; In contact with the bit line 101 and doped with N-type elements in the active column 120; the inversion region 140, the inversion region 140 is located on the side of the active column 120, and the inversion region 140 is doped with P-type elements; dielectric The layer 150 and the word line 160 extending along the second direction Y, the dielectric layer 150 and the word line 160 cover part of the inversion region 140 , and the dielectric layer 150 is located between the word line 160 and the inversion region 140 .
  • the orthographic projections of the second direction Y and the first direction X on the substrate 100 are perpendicular to each other;
  • the material of the substrate 100 may be a semiconductor material.
  • the semiconductor material may be any one of silicon, germanium, silicon germanium or silicon carbide.
  • the bit line 101 is a semiconductor bit line
  • the semiconductor bit line is doped with an N-type element
  • the doped element can be used as a carrier, which can improve the carrier between the bit line 101 and the active column 120.
  • the migration and diffusion of carriers is beneficial to improve the conductivity of the bit line 101 and the active pillar 120 .
  • N-type elements can be doped in situ, and the N-type elements can be group V elements such as phosphorus (P) elements, bismuth (Bi) elements, antimony (Sb) elements, or arsenic (As) elements.
  • the material is the same as that of the initial substrate, which can be any one of silicon, germanium, silicon germanium or silicon carbide.
  • N-type elements can be implanted into the substrate 100 to form semiconductor bit lines through ion implantation process or diffusion process, that is, the bit line 101 and the substrate 100 have an integrated structure, thereby improving the interface performance between the bit line 101 and the substrate 100 , which is conducive to improving the interface state defects, thereby improving the electrical properties of the semiconductor structure.
  • the bit line 101 is a metal bit line
  • the semiconductor structure further includes a bit line barrier layer and a bit line dielectric layer
  • the bit line barrier layer is located between the substrate 100 and the metal bit line
  • the bit line dielectric layer is located between the metal bit line
  • the wire is far away from the surface of the bit line barrier layer, and the resistance of the metal itself is small, which is beneficial to improve the conductivity of the bit line 101 and the active column 120 , and further helps to improve the conductivity of the bit line 101 .
  • the material of the metal bit line can be tungsten, copper and silver; the material of the bit line barrier layer can be silicon nitride, silicon oxide or silicon carbide; the material of the bit line dielectric layer can be silicon oxide or silicon nitride.
  • the material of the first isolation layer 110 is an insulating material, and the insulating material may be silicon dioxide, silicon carbide or silicon nitride; the second isolation layer 130 is composed of the second isolation film 131 and the third isolation film 132 As part of the composition, the material of the second isolation film 131 may be silicon dioxide, silicon carbide or silicon nitride, and the material of the third isolation film 132 may be the same as that of the second isolation film 131 . In other embodiments, the material of the third isolation film 132 may be different from that of the second isolation film 131 .
  • the active pillar 120 includes a first region 121 , a second region 122 and a third region 123 sequentially distributed from the surface of the substrate 100 to a direction away from the substrate 100 .
  • the first region 121 , the second region 122 and the third region 123 can be regarded as the main body of the active pillar 120
  • the main body of the active pillar 120 can be an intrinsic semiconductor
  • the intrinsic semiconductor material can be silicon, germanium or silicon germanium. It can be understood that an intrinsic semiconductor is a semiconductor that has not been doped.
  • N-type elements are doped in the second region 122 , and the doping elements in the second region 122 and the doping elements in the bit line 101 may be the same. In some other embodiments, the doping elements in the second region 122 and the doping elements in the bit line 101 may also be different, for example, the doping element in the bit line 101 is doped with element phosphorus, and the element doped in the second region 122 is arsenic; The first region 121 , the second region 122 and the third region 123 are all doped with N-type elements.
  • the material of the active pillar 120 is the same as that of the bit line 101, so the lattice mismatch factor between the active pillar 120 and the bit line 101 is 0, effectively avoiding lattice defects inside the active pillar 120 and The problem of increased internal resistance is beneficial to improve the conductivity of the active pillar 120 .
  • the material of the active pillar 120 and the material of the bit line 101 may be different.
  • the inversion region 140 is located on the side of the thinned second region 122, the second region 122 is doped with N-type elements, the inversion region 140 is doped with P-type elements, and the second region 122 The doping element type of is opposite to that of the inversion region 140 .
  • the active pillar 120 may serve as a source or drain of the semiconductor structure, and the word line 160 surrounding the inversion region 140 may serve as a gate of the semiconductor structure.
  • a bridge is formed in the active column 120, and the P-type elements in the inversion region 140 are converted into electron-hole pairs, and the electrons can leave the inversion along the bridge.
  • the P-type element may be a group III element such as boron (B), aluminum (Al), gallium (Ga) or indium (In).
  • the thickness of the inversion region 140 ranges from 4 nm to 15 nm, and the thickness of the inversion region 140 can specifically be 4nm, 8nm, 13nm or 15nm, the thickness range of the inversion region 140 can ensure that the hole storage area in the inversion region 140 is larger, and can accommodate more holes, that is, the capacitance of the capacitor is larger, thereby ensuring the capacitance
  • the storage capacity of the semiconductor structure is large, which is beneficial to increase the storage density of the semiconductor structure; it can also avoid the situation that the width of the inversion region 140 in the horizontal direction of the semiconductor structure is too large and the width of the word line 160 is too small.
  • the height of the entire inversion region 140 is 8 nm to 30 nm greater than the height of a part of the inversion region 140 covered by the dielectric layer 150 and the word line 160, That is, the height of the inversion region 140 located on the sides of the first isolation layer 110 and the third isolation layer 130 ranges from 8nm to 30nm, specifically 8nm, 10nm, 20nm or 30nm. In this way, the storage of holes in the inversion region 140 can be ensured.
  • the region of the larger region can accommodate more holes, that is, the capacity of the capacitor is larger, thereby ensuring a larger storage capacity of the capacitor, which is conducive to improving the storage density of the semiconductor structure; it can also prevent the inversion region 140 from occupying the vertical position of the semiconductor structure The case where the line width of the direction is too large.
  • the height of the inversion region 140 located on the side of the second region 122 is 8nm, that is, the height of the part of the inversion region 140 covered by the dielectric layer 150 and the word line 160 is 20nm, which is located on the first
  • the total height of the inversion region 140 on the sides of the isolation layer 110 and the third isolation layer 130 is 8 nm, so the height of the entire inversion region 140 may be 28 nm.
  • the height of the inversion region 140 on the side of the first isolation layer 110 and the height of the inversion region 140 on the side of the third isolation layer 130 may be Equal; the sides of the inversion region 140 are flush with the sides of the first region 121 and the sides of the third region 123, in other words, the orthographic projection of the inversion region 140 on the substrate 100 is located at the orthographic projection of the first region 121 on the substrate 100 Inner and equal, it is beneficial to the surface flatness of the subsequently formed dielectric layer.
  • the inversion region 140 may be partially doped.
  • the inversion region 140 includes a body and two dopant bodies. The body is located between adjacent dopant bodies. The body may be No doping treatment was performed.
  • the body material of the inversion region 140 includes silicon, germanium or silicon germanium.
  • the main body material of the inversion region 140 and the main body material of the active pillar 120 can be the same, then the lattice mismatch factor of the active pillar 120 and the inversion region 140 is 0, effectively avoiding The problems of lattice defects and increased internal resistance are beneficial to improve the conductivity of the inversion region 140 .
  • the body material of the inversion region 140 and the body material of the active pillar 120 may be different.
  • the dielectric layer 150 is used as a gate dielectric layer or a gate oxide layer for suppressing short channel effects, such as suppressing tunneling leakage current.
  • the material of the dielectric layer 150 may be silicon dioxide, silicon carbide, silicon nitride or other high dielectric constant materials.
  • the word line 160 extending along the second direction Y covers part of the inversion region 140, and the inversion region 140 is located on the side of the active pillar 120, that is, the word line 160 also covers part of the active pillar 120.
  • the structure is a GAA structure, which can realize the four-sided wrapping of the gate to the active column 120, and can avoid the leakage current, capacitance effect and short channel effect caused by the reduction of the gate pitch size, and reduce the vertical displacement of the word line 160.
  • the occupied line width on the grid is beneficial to enhance the control performance of the gate and improve the integration degree of the semiconductor structure.
  • the material of the word line 160 is any one of metal tungsten, copper or aluminum.
  • the material of the insulating layer 170 may be silicon dioxide, silicon carbide or silicon nitride.
  • the first isolation layer 110 , the second isolation layer 130 and the insulating layer 170 are made of the same material, which can reduce interface defects between the first isolation layer 110 and the insulating layer 170 and between the second isolation layer 130 and the insulating layer 170 .
  • the materials of the first isolation layer 110 , the second isolation layer 130 and the insulating layer 170 may be different or both of them may be the same.
  • another embodiment of the present disclosure also provides a semiconductor structure.
  • the semiconductor structure provided by another embodiment of the present disclosure is substantially the same as the semiconductor structure provided in the foregoing embodiment (FIG. 25 and FIG. 26 ), the main difference is that the present disclosure
  • the second isolation layer in the semiconductor structure provided in the embodiment is composed of a second isolation film and a third isolation film, and the second isolation layer in the semiconductor structure provided in another embodiment of the present disclosure is integral. Details of the same or similar contents or elements as the descriptions given in the foregoing embodiments will not be repeated, and only descriptions different from the above descriptions will be described in detail.
  • the semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to FIG. 37 .
  • FIG. 37 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 200 with a bit line 201 extending along the first direction X; 201 are in contact with each other and the active column 220 is doped with N-type elements; the inversion region 240 is located on the side of the active column 220, and the inversion region 240 is doped with P-type elements; the dielectric layer 250 and The word line 260 extending along the second direction Y, the dielectric layer 250 and the word line 260 cover part of the inversion region 240 , and the dielectric layer 250 is located between the word line 260 and the inversion region 240 .
  • the material of the second isolation layer may be any one of silicon dioxide, silicon carbide or silicon nitride, and the material of the second isolation layer 130 may be the same as that of the first isolation layer 110 . In other embodiments, the material of the second isolation layer 130 may also be different from that of the first isolation layer 110 .
  • FIG. 38 is a schematic diagram of a partial cross-sectional structure when a positive voltage is applied to the gate terminal and the source terminal of the semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 39 is a positive voltage applied to the gate terminal and the source terminal of the semiconductor structure provided by an embodiment of the present disclosure.
  • the active pillar 120 may serve as a source or drain of the semiconductor structure, and the word line 160 may serve as a gate of the semiconductor structure.
  • the word line 160 may serve as a gate of the semiconductor structure.
  • FIG. 38 when a positive voltage is applied to both the gate terminal and the drain terminal to form an external electric field, electron-hole pairs are generated in the inversion region 140 due to the electric field, and N-type elements in the active pillar 120 migrate to form a bridge. Due to the existence of the electric bridge, electrons can leave the inversion region 140, but holes cannot leave the inversion region 140, and due to the voltage on the gate, there is an inversion layer 141 in the region directly below the gate.
  • the inversion region 140 has the function of storing charges, and the inversion region 140 can be regarded as an equivalent capacitor, which can simplify the process flow of manufacturing the capacitor and is beneficial to reduce the line width of the semiconductor structure. Therefore, the size of the capacitor can be larger to ensure a larger storage capacity of the capacitor, which is beneficial to improving the storage density of the semiconductor structure.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及半导体结构的制备方法，半导体结构包括：基底(100)，基底(100)内具有沿第一方向延伸的位线(101)；有源柱(120)，有源柱(120)位于位线(101)上，有源柱(120)的底面与位线(101)相接触且有源柱(120)内掺杂有N型元素；反型区(140)，反型区(140)位于有源柱(120)的侧面，反型区(120)内掺杂有P型元素；介电层(150)以及沿第二方向延伸的字线(160)，介电层(150)以及字线(160)包覆部分反型区(140)，介电层(150)位于字线(160)与反型区(140)之间。

Description

半导体结构及半导体结构的制备方法
交叉引用
本公开要求于2022年01月13日递交的名称为“半导体结构及半导体结构的制备方法”、申请号为202210038578.0的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及半导体结构的制备方法。
背景技术
随着集成电路工艺制程技术的不断发展，为了提高集成电路的集成度，同时提升存储器的工作速度和降低它的功耗，金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)器件的特征尺寸不断缩小，MOSFET器件面临一系列的挑战。例如，为了实现器件线宽的减小，半导体结构已经开始由埋置字线结构向环绕式栅极技术晶体管结构(Gate-All-Around，GAA)方向发展，但GAA结构仍然需要连接电荷存储所需的电容，电容段工艺复杂难度高且存储容量也受到尺寸的限制。
如何简化工艺并进一步提高存储密度，已成为本领域技术人员亟待解决的一个重要问题。
发明内容
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制备方法，包括：提供基底；在基底内形成沿第一方向延伸的位线；在位线上形成有源柱，有源柱的底面与位线相接触且有源柱内掺杂有N型元素；在有源柱的侧面形成反型区，反型区内掺杂有P型元素；依次形成介电层以及沿第二方向延伸的字线包覆部分反型区，介电层位于字线与反型区之间。
另外，采用选择性外延生长工艺，形成反型区。
另外，形成反型区的工艺步骤中，原位掺杂P型元素。
另外，在形成反型区之前，还包括：对部分厚度的有源柱的侧壁进行减薄处理。
另外，采取湿法刻蚀工艺进行减薄处理，且湿法刻蚀工艺采用的刻蚀液体为碱性液体。
另外，进行减薄处理之前，包括：在基底上以及位线顶面依次形成层叠的第一隔离层、牺牲层以及第二隔离层，第二隔离层内具有贯穿第二隔离层厚度的通孔，且通孔底部暴露出牺牲层；去除牺牲层，露出有源柱的侧面。
另外，牺牲层的材料包括氮化硅，采用热磷酸刻蚀液去除牺牲层。
另外，在基底上依次形成层叠的第一隔离层、牺牲层以及第二隔离层的工艺步骤包括：在基底上以及位线顶面依次形成层叠的第一隔离膜、牺牲层、第二隔离膜以及具有第一开口的第一掩膜层；以第一掩膜层为掩膜，沿第一开口依次刻蚀第一掩膜层、第二隔离膜、牺牲层以及第一隔离膜，形成沟槽，沟槽底部暴露出位线，剩余的第一隔离膜作为第一隔离层；形成有源柱，有源柱填充满沟槽；在第二隔离膜上依次形成第三隔离膜，第三隔离膜覆盖有源柱顶面；图形化第三隔离膜以及第二隔离膜，形成通孔，且剩余的第二隔离膜以及第三隔离膜共同作为第二隔离层。
另外，在基底上依次形成第一隔离层、牺牲层以及第二隔离层的工艺步骤包括：在基底上形成有源柱；在基底上依次形成层叠的第一隔离层、牺牲层以及第四隔离膜，牺牲层还位于有源柱的部分侧面，第四隔离膜位于有源柱的部分侧面以及顶面；图形化第四隔离膜，形成通孔，剩余第四隔离膜作为第二隔离层。
另外，形成字线的工艺步骤包括：形成填充满通孔的导电膜，且导电膜还位于第一隔离层与第二隔离层之间，导电膜环绕反型区；图形化导电膜，形成若干相互分立的字线。
另外，图形化导电膜的步骤包括：去除位于通孔内的导电膜，且去除位于通孔正下方的导电膜，剩余导电膜作为字线。
另外，形成字线之后，还包括：形成填充满通孔的绝缘层，绝缘层还填充满相邻的字线之间的区域。
另外，采用外延生长工艺，形成位线；形成位线的工艺步骤包括：提供初始基底，初始基底内具有沿第一方向延伸的沟道；形成位线，位线填充满沟道。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：基底，基底内具有沿第一方向延伸的位线；有源柱，有源柱位于位线上，有源柱的底面与位线相接触且有源柱内掺杂有N型元素；反型区，反型区位于有源柱的侧面，反型区内掺杂有P型元素；介电层以及沿第二方向延伸的字线，介电层以及字线包覆部分反型区，介电层位于字线与反型区之间。
另外，位线为半导体位线，且半导体位线内掺杂有N型元素。
另外，反型区的主体材料与有源柱的主体材料相同。
另外，反型区的主体材料包括硅、锗或者锗化硅。
另外，在沿垂直于有源柱的侧壁并朝向有源柱的轴心的方向上，反型区的厚度范围为4nm～15nm。
另外，在平行于有源柱侧壁的方向上，整个反型区的高度比被介电层以及字线包覆的部分反型区的高度多8nm～30nm。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动新的前提下，还可以根据这些附图获得其他的附图。
图1～图26为本公开一实施例提供的半导体结构的制备方法中各步骤对应的截面结构示意图；
图27～图37为本公开另一实施例提供的半导体结构的制备方法中各步骤对应的截面结构示意图；
图38为本公开一实施例提供的半导体结构的栅极端和源极端施加正压时的一种局部截面结构示意图；
图39为本公开一实施例提供的半导体结构的栅极端施加正压、源极端施加负压时的一种局部截面结构示意图。
具体实施方式
本公开实施例提供一种半导体结构以及半导体结构的制备方法，在位线上形成有源柱，有源柱的底面与位线相接触且有源柱内掺杂有N型元素；在有源柱的侧面形成反型区，反型区内掺杂有P型元素；依次形成介电层以及沿第二方向延伸的字线包覆部分反型区，介电层位于字线与反型区之间。其中，有源柱可以作为半导体结构的源极或漏极，字线可以作为半导体结构的栅极。当栅极端和漏极端都施加正压形成外加电场时，在有源柱内形成电桥，反型区内的P型元素转化为电子-空穴对，由于电桥的存在，使得电子可以离开反型区，而空穴无法离开反型区。又由于栅极上的电压，使得在栅极正下方的区域存在反型层，反型层和隔离层下方区域构成空穴存储区，将空穴固定在了隔离层下方存储起来。当栅极端施加正 压，漏极端施加负压时，空穴则全部被抽离空穴存储区，在有源柱内和反型区内迁移和扩散，换句话说，反型区具有储藏电荷的功能，反型区可以视为等效电容。因此，可以简化制备电容的工艺流程，且有利于降低半导体结构的线宽，从而电容的尺寸可以较大以保证电容的存储容量较大，有利于提高集成电路的存储密度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1～图26为本公开一实施例提供的半导体结构的制备方法中各步骤对应的截面结构示意图，其中，图1～图13为本公开一实施例提供沿第二方向Y的半导体结构的制备方法中各步骤对应的截面结构示意图，图14～图26为本公开一实施例提供沿第一方向X的半导体结构的制备方法中各步骤对应的截面结构示意图。
参考图1或图14，提供基底100；在基底100内形成沿第一方向X延伸的位线101。
在一些实施例中，第二方向Y与第一方向X在基底100上的正投影相互垂直；基底100的材料可以为半导体材料。半导体材料具体可以为硅、锗、锗硅或碳化硅的任意一种。
在一些实施例中，采用外延生长工艺，形成位线101；形成位线的工艺步骤可以包括：提供初始基底，初始基底内具有沿第一方向X延伸的沟道(图中未示出)；形成位线101，位线101填充满沟道。位线101为半导体位线，且半导体位线内掺杂有N型元素，掺杂元素可以作为载流子，可以提高位线101内与后续形成的有源柱之间的载流子的迁移和扩散，有利于提高位线101与有源柱的导电能力。具体地，可以通过原位掺杂N型元素，N型元素可以为磷(P)元素、铋(Bi)元素、锑(Sb)元素或砷(As)元素等Ⅴ族元素，位线101的材料与初始基底的材料相同，可以为硅、锗、锗硅或碳化硅的任意一种。
在另一些实施例中，可以通过离子注入工艺或扩散工艺将N型元素注入基底100形成半导体位线，即位线101与基底100为一体结构，从而改善位线101与基底100之间的界面性能，有利于改善界面态缺陷，进而改善半导体结构的电学性能。
在又一些实施例中，位线101为金属位线，半导体结构还包括位线阻挡层以及位线介质层，位线阻挡层位于基底100与金属位线之间，位线介质层位于金属位线远离位线阻挡层的表面，金属自身的电阻小，有利于提高位线101与后续形成有源柱的导电能力，进一步有利于提高位线101的导电性。具体地，金属位线的材料可以为钨、铜以及银；位线阻挡层的材料可以为氮化硅、氧化硅或碳化硅；位线介质层的材料可以为氧化硅或氮化硅。
参考图2至图7以及图15至图20，在基底100上以及位线101顶面依次形成层叠的第一隔离层110、牺牲层102以及第二隔离层130，第二隔离层130内具有贯穿第二隔离层130厚度的通孔114，且通孔114底部暴露出牺牲层102；去除牺牲层102，露出有源柱120的侧面。
具体地，参考图2或图15，在基底100上以及位线101顶面依次形成层叠的第一隔离膜111、牺牲层102、第二隔离膜131以及具有第一开口(图中未示出)的第一掩膜层103。
在一些实施例中，牺牲层102的材料与第一隔离膜111以及第二隔离膜131的材料均不同，第一掩膜层103的材料与牺牲层102、第一隔离膜111以及第二隔离膜131的材料均不同。牺牲层102的材料可以为氮化硅或氧化硅。第一隔离膜111的材料为绝缘材料，绝缘材料可以为二氧化硅、碳化硅或氮化硅；第二隔离膜131的材料与第一隔离膜111的材料相同。在另一些实施例中，第二隔离膜的材料与第一隔离膜的材料也可以不同。
参考图3或图16，以第一掩膜层103为掩膜，沿第一开口依次刻蚀第一掩膜层103、第二隔离膜131、牺牲层102以及第一隔离膜111，形成沟槽104，沟槽104底部暴露出位线101，剩余的第一隔离膜111作为第一隔离层110。沟槽104底部暴露出位线101以使位线与后续形成的有源柱连接，且可以作为有源柱的外延生长的基底，有利于后续形成的有源柱的完整性。
参考图4或图17，在位线101上形成有源柱120，有源柱120的底面与位线101相接触且有源柱120内掺杂有N型元素，有源柱120填充满沟槽104。
在一些实施例中，有源柱120包括自基底100表面向远离基底100方向依次分布的第一区121、第二区122以及第三区123。其中，第一区121、第二区122以及第三区123可以视为有源柱120的主体，有源柱120的主体可以为本征半导体，本征半导体材料可以为硅、锗或者锗化硅。可以理解的是，本征半导体为未进行掺杂处理的半导体。
在一些实施例中，第二区122内掺杂N型元素，第二区122内掺杂元素与位线101内掺杂元素可以相同。在另一些实施例中，第二区122内掺杂元素与位线101内掺杂元素也可以不相同，例如，位线101内掺杂磷元素，第二区122内掺杂砷元素；第一区121、第二区122以及第三区123内均掺杂有N型元素。
需要说明的是，采用低压化学气相沉积工艺形成有源柱120；低压化学气相沉积工艺采用的源材料包括源气体以及N型元素源气体，N型元素源气体用于提供N型元素。源气体可以为硅源气体，硅源气体具体可以为硅烷、乙硅烷、二氯甲硅烷或者三氯甲硅烷；N型元素源气体具体可以为磷烷、砷烷或者氢化锑。在另一些实施例中，源气体还可以为锗源气 体，锗源气体具体可以为锗烷。
在一些实施例中，有源柱120的材料与位线101的材料相同，则有源柱120与位线101的晶格失配因子为0，有效避免有源柱120内部具有晶格缺陷以及内部电阻增大的问题，有利于提高有源柱120的导电性能。在另一些实施例中，有源柱120的材料与位线101的材料可以不相同。
参考图5或图18，在第二隔离膜131上依次形成第三隔离膜132以及第二掩膜层113，第三隔离膜132覆盖有源柱120顶面。
在一些实施例中，第三隔离膜132的材料与第二隔离膜131的材料可以相同。在另一些实施例中，第三隔离膜的材料与第二隔离膜的材料可以不同。
参考图6或图19，图形化第二掩膜层113、第三隔离膜132以及第二隔离膜131，形成通孔104，且剩余的第二隔离膜131以及第三隔离膜132共同作为第二隔离层130。
在一些实施例中，通孔104底部暴露出牺牲层102，便于后续刻蚀去除牺牲层102以及形成反型区以及字线。
参考图7或图20，去除牺牲层102以及第二掩膜层113，露出有源柱120的侧面。
需要说明的是，采用湿法刻蚀工艺去除牺牲层102，刻蚀温度保持在140℃-200℃之间，刻蚀温度具体可以为160℃。在一些实施例中，湿法刻蚀工艺采用的刻蚀液为热磷酸刻蚀液，热磷酸刻蚀液是由85％浓磷酸和15％去离子水配合而成。在另一些实施例中，湿法刻蚀工艺采用的刻蚀液为49％的氢氟酸。
参考图8或图21，对部分厚度的有源柱120的侧壁进行减薄处理。
在一些实施例中，对第二区122的侧壁进行减薄处理。采取湿法刻蚀工艺进行减薄处理，且湿法刻蚀工艺采用的刻蚀液体为碱性液体，碱性液体可以为碱性氯化铜蚀刻液。
可以理解的是，因为湿法刻蚀工艺的各向同性，不仅对露出的第二区122的侧壁进行减薄处理，还刻蚀位于第一隔离层110以及第二隔离层130侧面的第二区122的侧壁。
参考图9或图22，在有源柱120的侧面形成反型区140，反型区140内掺杂有P型元素。
在一些实施例中，反型区140形成于减薄后的第二区122的侧面，第二区122内掺杂有N型元素，反型区140内掺杂有P型元素，第二区122的掺杂元素类型与反型区140的掺杂元素类型相反。其中，有源柱120可以作为半导体结构的源极或漏极，后续形成包裹反型区140的字线可以作为半导体结构的栅极。当对栅极端与漏极端施加正压，形成外加电 场时，在有源柱120内形成电桥，反型区140内的P型元素转化为电子-空穴对，电子可以沿电桥离开反型区140，空穴无法离开反型区140，也就是说，反型区140可以储藏空穴，即反型区140具有储藏电荷的功能，反型区140可以视为等效电容，有利于降低半导体结构的线宽，有利于提高半导体结构的集成度。P型元素可以为硼(B)元素、铝(Al)元素、镓(Ga)元素或铟(In)元素等Ⅲ族元素。
在一些实施例中，在沿垂直于有源柱120的侧壁并朝向有源柱120的轴心的方向上，反型区140的厚度范围为4nm～15nm，反型区140的厚度具体可以为4nm、8nm、13nm或者15nm，反型区140的厚度范围可以保证反型区140内储藏空穴的区域较大，可以容纳更多的空穴，即电容的容量较大，从而可以保证电容的存储容量较大，有利于提高半导体结构的存储密度；也可以避免反型区140占半导体结构水平方向的线宽过大导致后续形成的字线的宽度过小的情况。
在一些实施例中，在平行于有源柱120侧面的方向上，整个反型区140的高度比被后续形成的介电层以及字线包覆的部分反型区140的高度多8nm～30nm，即位于第一隔离层110和第三隔离层130侧面的反型区140的高度范围为8nm～30nm，具体可以为8nm、10nm、20nm或者30nm，如此，可以保证反型区140内储藏空穴的区域较大，可以容纳更多的空穴，即电容的容量较大，从而可以保证电容的存储容量较大，有利于提高半导体结构的存储密度；也可以避免反型区140占半导体结构垂直方向的线宽过大的情况。在一个具体的例子中，位于第二区122的侧面的反型区140的高度为8nm，即被后续形成的介电层以及字线包覆的部分反型区140的高度为20nm，位于第一隔离层110和第三隔离层130侧面的反型区140的总高度为8nm，那么，整个反型区140的高度可以为28nm。
在一些实施例中，在平行于有源柱120侧面的方向上，位于第一隔离层110的侧面的反型区140的高度与位于第三隔离层130的侧面的反型区140的高度可以相等；反型区140的侧面与第一区121的侧面以及第三区123的侧面齐平，换句话说，反型区140在基底100的正投影位于第一区121在基底100的正投影内且相等，有利于后续形成的介电层的表面平坦性。
在一些实施例中，反型区140可以部分掺杂，沿垂直基底100表面方向上，反型区140包括本体和两个掺杂体，本体位于相邻的掺杂体之间，本体可以为未进行掺杂处理。反型区140的本体材料包括硅、锗或者锗化硅。
在一些实施例中，反型区140的主体材料与有源柱120的主体材料可以相同，则有源柱120与反型区140的晶格失配因子为0，有效避免反型区140内部具有晶格缺陷以及内部电阻增大的问题，有利于提高反型区140的导电性能。在另一些实施例中，反型区140的 主体材料与有源柱120的主体材料可以不相同。
在一些实施例中，采用选择性外延生长工艺(Selective Epitaxy Growth，SEG)，形成反型区140；形成反型区140的工艺步骤中，原位掺杂P型元素。选择性外延生长工艺采用的源材料包括源气体、刻蚀性气体氯化氢以及掺杂元素源气体，掺杂元素源气体用于提供P型元素，源气体可以为硅源气体，硅源气体具体可以为硅烷、乙硅烷、二氯甲硅烷或者三氯甲硅烷，掺杂元素源气体可以为硼烷(BH 3)、乙硼烷(B 2H 6)或者三氯化硼(BCl 3)。在另一些实施例中，源气体还可以为锗源气体，锗源气体具体可以为锗烷。
参考图10至图12以及图23至图25，依次形成介电层150以及沿第二方向Y延伸的字线160包覆部分反型区140，介电层150位于字线160与反型区140之间。
在一些实施例中，字线160可以作为半导体结构的栅极，沿第二方向Y延伸的字线160包覆部分反型区140，反型区140位于有源柱120的侧面，即字线160还包覆部分有源柱120，半导体结构为GAA结构，可以实现栅极对有源柱120的四面包裹，可以避免栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等情况，减少了字线160在垂直方向上的占用线宽，有利于增强栅极控制性能以及提高半导体结构的集成度。
具体地，参考图10或图23，在反型区140的侧面，形成介电层150，介电层150包覆部分反型区140。
介电层150作为栅介质层或栅氧化层，用于抑制短沟道效应，例如抑制隧穿漏电流。介电层150的材料可以为二氧化硅、碳化硅、氮化硅或者其它高介电常数的材料。
参考图11或图24，充满通孔114的导电膜105，且导电膜105还位于第一隔离层110与第二隔离层130之间，导电膜105环绕反型区140。
在一些实施例中，导电膜105位于介电层150的表面且环绕介电层150，导电膜105沿第二方向Y延伸。导电膜105的材料可以为金属钨、铜或者铝的任意一种。
可以理解的是，第二方向Y可以为垂直于有源柱120的侧壁并朝向有源柱120的轴心的任意方向。本公开实施例中的第二方向Y为与第一方向X在基底100上的正投影相互垂直的方向仅为示例说明。
参考图12或图25，图形化导电膜105，形成若干相互分立的字线160。
在一些实施例中，图形化导电膜105的步骤包括：去除位于通孔114内的导电膜105，且去除位于通孔114正下方的导电膜105，剩余导电膜105作为字线160。
参考图13或图26，形成填充满通孔114的绝缘层170，绝缘层170还填充满相邻的 字线160之间的区域。
在一些实施例中，绝缘层170的材料为可以为二氧化硅、碳化硅或氮化硅。第一隔离层110、第二隔离层130以及绝缘层170的材料相同，可以降低第一隔离层110与绝缘层170之间、第二隔离层130与绝缘层170之间的界面缺陷。在另一些实施例中，第一隔离层110、第二隔离层130以及绝缘层170的材料可以各不相同或者其中的两者相同。
本公开实施例提供的技术方案中，有源柱120内掺杂有N型元素，反型区140位于有源柱120的侧面，反型区140内掺杂有P型元素，沿第二方向Y延伸的字线160包覆部分反型区140，有源柱120的掺杂元素类型与反型区140的掺杂元素类型相反。其中，有源柱140可以作为半导体结构的源极或漏极，字线160可以作为半导体结构的栅极。当对栅极端与漏极端施加正压，形成外加电场时，在有源柱120内形成电桥，反型区140内的P型元素转化为电子-空穴对，电子可以沿电桥离开反型区，空穴无法离开反型区，也就是说，反型区140可以储藏空穴，即反型区140具有储藏电荷的功能，反型区140可以视为等效电容，可以简化制备电容的工艺流程，且有利于降低半导体结构的线宽。因此，电容的尺寸可以较大以保证电容的存储容量较大，有利于提高半导体结构的存储密度。
前述(如图1至图26所示的半导体结构)是先形成第一隔离层、牺牲层以及第二隔离层，再形成有源柱的制备方法作为示例，本公开中另一些实施例还提供了先形成有源柱，再形成第一隔离层、牺牲层以及第二隔离层的制备方法。与前述实施例给出的描述相同或相似的内容或元件的细节不再重复，仅详细描述与以上描述不同的描述。以下将结合图27至图37进行具体说明：
图27～图37为本公开另一实施例提供的半导体结构的制备方法中各步骤对应的截面结构示意图。参考图27～图31，提供基底200；在基底200内形成沿第一方向X延伸的位线201；在位线201上形成有源柱220，有源柱220的底面与位线201相接触且有源柱220内掺杂有N型元素；在有源柱220的侧面形成反型区240，反型区240内掺杂有P型元素；依次形成介电层250以及沿第二方向Y延伸的字线260包覆部分反型区240，介电层250位于字线260与反型区240之间。
参考图27，提供基底200，基底200内具有沿第一方向X延伸的位线201。
参考图28，在基底200上形成有源柱220，有源柱220包括自基底200表面向远离基底200方向依次分布的第一区221、第二区222以及第三区223，且第二区的有源柱222内掺杂有N型离子。
参考图29，在基底200上依次形成层叠的第一隔离层210、牺牲层202、第四隔离膜233以及第二掩膜层213，牺牲层202还位于有源柱220的部分侧面，第四隔离膜233位于 有源柱220的部分侧面以及顶面。
参考图30，以第二掩膜层213为掩膜，图案化第一掩膜层103形成开口，再沿开口刻蚀第四隔离膜233，形成通孔214，剩余第四隔离膜233作为第二隔离层230。
后续形成半导体结构的制备方法与本公开上一些实施例(参考图7～图13以及图20～图26)形成半导体结构的制备方法相同或类似，在这里不过多赘述。
可以理解的是，图27～图37所述的形成半导体结构的制备方法与图1～图26所述的形成半导体结构的制备方法仅为先形成有源柱，还是后形成有源柱，即工艺流程的不同，也就是说，图1～图26所述的形成半导体结构的制备方法、内容与元件，图27～图37所述的形成半导体结构同样适用。
本公开一些实施例提供一种半导体结构的制备方法，该半导体结构的制备方法可以形成下一些实施例提供的半导体结构，以下将结合附图对本公开一些实施例提供的半导体结构进行详细说明。
图13和图26为本公开一实施例提供的半导体结构的一种截面结构示意图。图13为本公开一实施例提供沿第二方向Y的半导体结构的一种截面结构示意图，图26为本公开一实施例提供沿第一方向X的半导体结构的一种截面结构示意图。
参考图13或图26，半导体结构包括：基底100，基底100内具有沿第一方向X延伸的位线101；有源柱120，有源柱120位于位线101上，有源柱120的底面与位线101相接触且有源柱120内掺杂有N型元素；反型区140，反型区140位于有源柱120的侧面，反型区140内掺杂有P型元素；介电层150以及沿第二方向Y延伸的字线160，介电层150以及字线160包覆部分反型区140，介电层150位于字线160与反型区140之间。
在一些实施例中，第二方向Y与第一方向X在基底100上的正投影相互垂直；基底100的材料可以为半导体材料。半导体材料具体可以为硅、锗、锗硅或碳化硅的任意一种。
在一些实施例中，位线101为半导体位线，且半导体位线内掺杂有N型元素，掺杂元素可以作为载流子，可以提高位线101内与有源柱120之间的载流子的迁移和扩散，有利于提高位线101与有源柱120的导电能力。具体地，可以通过原位掺杂N型元素，N型元素可以为磷(P)元素、铋(Bi)元素、锑(Sb)元素或砷(As)元素等Ⅴ族元素，位线101的材料与初始基底的材料相同，可以为硅、锗、锗硅或碳化硅的任意一种。在另一些实施例中，可以通过离子注入工艺或扩散工艺将N型元素注入基底100形成半导体位线，即位线101与基底100为一体结构，从而改善位线101与基底100之间的界面性能，有利于改善界面态缺陷，进而改善半导体结构的电学性能。
在又一些实施例中，位线101为金属位线，半导体结构还包括位线阻挡层以及位线介质层，位线阻挡层位于基底100与金属位线之间，位线介质层位于金属位线远离位线阻挡层的表面，金属自身的电阻小，有利于提高位线101与有源柱120的导电能力，进一步有利于提高位线101的导电性。具体地，金属位线的材料可以为钨、铜以及银；位线阻挡层的材料可以为氮化硅、氧化硅或碳化硅；位线介质层的材料可以为氧化硅或氮化硅。
在一些实施例中，第一隔离层110的材料为绝缘材料，绝缘材料可以为二氧化硅、碳化硅或氮化硅；第二隔离层130由第二隔离膜131与第三隔离膜132两部分组成，第二隔离膜131的材料可以为二氧化硅、碳化硅或氮化硅，第三隔离膜132的材料与第二隔离膜131的材料可以相同。在另一些实施例中，第三隔离膜132的材料与第二隔离膜131的材料可以不相同。
在一些实施例中，有源柱120包括自基底100表面向远离基底100方向依次分布的第一区121、第二区122以及第三区123。第一区121、第二区122以及第三区123可以视为有源柱120的主体，有源柱120的主体可以为本征半导体，本征半导体材料可以为硅、锗或者锗化硅。可以理解的是，本征半导体为未进行掺杂处理的半导体。
在一些实施例中，第二区122内掺杂N型元素，第二区122内掺杂元素与位线101内掺杂元素可以相同。在另一些实施例中，第二区122内掺杂元素与位线101内掺杂元素也可以不相同，例如，位线101内掺杂磷元素，第二区122内掺杂砷元素；第一区121、第二区122以及第三区123内均掺杂有N型元素。
在一些实施例中，有源柱120的材料与位线101的材料相同，则有源柱120与位线101的晶格失配因子为0，有效避免有源柱120内部具有晶格缺陷以及内部电阻增大的问题，有利于提高有源柱120的导电性能。在另一些实施例中，有源柱120的材料与位线101的材料可以不相同。
在一些实施例中，反型区140位于减薄后的第二区122的侧面，第二区122内掺杂有N型元素，反型区140内掺杂有P型元素，第二区122的掺杂元素类型与反型区140的掺杂元素类型相反。其中，有源柱120可以作为半导体结构的源极或漏极，包裹反型区140的字线160可以作为半导体结构的栅极。当对栅极端与漏极端施加正压，形成外加电场时，在有源柱120内形成电桥，反型区140内的P型元素转化为电子-空穴对，电子可以沿电桥离开反型区140，空穴无法离开反型区140，也就是说，反型区140可以储藏空穴，即反型区140具有储藏电荷的功能，反型区140可以视为等效电容，可以简化制备电容的工艺流程，且有利于降低半导体结构的线宽。因此，电容的尺寸可以较大以保证电容的存储容量较大，有利于提高半导体结构的存储密度。P型元素可以为硼(B)元素、铝(Al)元素、镓(Ga) 元素或铟(In)元素等Ⅲ族元素。
在一些实施例中，在沿垂直于有源柱120的侧壁并朝向有源柱120的轴心的方向上，反型区140的厚度范围为4nm～15nm，反型区140的厚度具体可以为4nm、8nm、13nm或者15nm，反型区140的厚度范围可以保证反型区140内储藏空穴的区域较大，可以容纳更多的空穴，即电容的容量较大，从而可以保证电容的存储容量较大，有利于提高半导体结构的存储密度；也可以避免反型区140占半导体结构水平方向的线宽过大导致字线160的宽度过小的情况。
在一些实施例中，在平行于有源柱120侧面的方向上，整个反型区140的高度比被介电层150以及字线160包覆的部分反型区140的高度多8nm～30nm，即位于第一隔离层110和第三隔离层130侧面的反型区140的高度范围为8nm～30nm，具体可以为8nm、10nm、20nm或者30nm，如此，可以保证反型区140内储藏空穴的区域较大，可以容纳更多的空穴，即电容的容量较大，从而可以保证电容的存储容量较大，有利于提高半导体结构的存储密度；也可以避免反型区140占半导体结构垂直方向的线宽过大的情况。在一个具体的例子中，位于第二区122的侧面的反型区140的高度为8nm，即被介电层150以及字线160包覆的部分反型区140的高度为20nm，位于第一隔离层110和第三隔离层130侧面的反型区140的总高度为8nm，那么，整个反型区140的高度可以为28nm。
在一些实施例中，在平行于有源柱120侧面的方向上，位于第一隔离层110的侧面的反型区140的高度与位于第三隔离层130的侧面的反型区140的高度可以相等；反型区140的侧面与第一区121的侧面以及第三区123的侧面齐平，换句话说，反型区140在基底100的正投影位于第一区121在基底100的正投影内且相等，有利于后续形成的介电层的表面平坦性。
在一些实施例中，反型区140可以部分掺杂，沿垂直基底100表面方向上，反型区140包括本体和两个掺杂体，本体位于相邻的掺杂体之间，本体可以为未进行掺杂处理。反型区140的本体材料包括硅、锗或者锗化硅。
在一些实施例中，反型区140的主体材料与有源柱120的主体材料可以相同，则有源柱120与反型区140的晶格失配因子为0，有效避免反型区140内部具有晶格缺陷以及内部电阻增大的问题，有利于提高反型区140的导电性能。在另一些实施例中，反型区140的主体材料与有源柱120的主体材料可以不相同。
介电层150作为栅介质层或栅氧化层，用于抑制短沟道效应，例如抑制隧穿漏电流。介电层150的材料可以为二氧化硅、碳化硅、氮化硅或者其它高介电常数的材料。
在一些实施例中，沿第二方向Y延伸的字线160包覆部分反型区140，反型区140位于有源柱120的侧面，即字线160还包覆部分有源柱120，半导体结构为GAA结构，可以实现栅极对有源柱120的四面包裹，可以避免栅极间距尺寸减小后导致的漏电流、电容效应以及短沟道效应等情况，减少了字线160在垂直方向上的占用线宽，有利于增强栅极控制性能以及提高半导体结构的集成度。字线160的材料为金属钨、铜或者铝的任意一种。
在一些实施例中，绝缘层170的材料为可以为二氧化硅、碳化硅或氮化硅。第一隔离层110、第二隔离层130以及绝缘层170的材料相同，可以降低第一隔离层110与绝缘层170之间、第二隔离层130与绝缘层170之间的界面缺陷。在另一些实施例中，第一隔离层110、第二隔离层130以及绝缘层170的材料可以各不相同或者其中的两者相同。
相应的，本公开另一实施例还提供一种半导体结构，本公开另一实施例提供的半导体结构与前述实施例(图25和图26)提供的半导体结构大致相同，主要区别在于本公开一实施例提供的半导体结构中的第二隔离层由第二隔离膜和第三隔离膜两部分组成，本公开另一实施例提供的半导体结构中的第二隔离层为整体。与前述实施例给出的描述相同或相似的内容或元件的细节不再重复，仅详细描述与以上描述不同的描述。以下将结合图37对本公开另一实施例提供的半导体结构进行详细说明。
图37为本公开另一实施例提供的半导体结构的一种结构示意图。
参考图37，半导体结构包括：基底200，基底200内具有沿第一方向X延伸的位线201；有源柱220，有源柱220位于位线201上，有源柱220的底面与位线201相接触且有源柱220内掺杂有N型元素；反型区240，反型区240位于有源柱220的侧面，反型区240内掺杂有P型元素；介电层250以及沿第二方向Y延伸的字线260，介电层250以及字线260包覆部分反型区240，介电层250位于字线260与反型区240之间。
在一些实施例中，第二隔离层的材料可以为二氧化硅、碳化硅或氮化硅的任意一种，第二隔离层130的材料与第一隔离层110的材料可以相同。在另一些实施例中，第二隔离层130的材料与第一隔离层110的材料也可以不同。
以下结合图13、图38以及图39，对半导体结构内形成等效电容的原理进行更为详细的说明。图38为本公开一实施例提供的半导体结构的栅极端和源极端施加正压时的一种局部截面结构示意图；图39为本公开一实施例提供的半导体结构的栅极端施加正压、源极端施加负压时的一种局部截面结构示意图。
参考图25、图38以及图39，有源柱120可以作为半导体结构的源极或漏极，字线160可以作为半导体结构的栅极。参考图38，当栅极端和漏极端都施加正压形成外加电场时， 由于电场作用在反型区140区域产生电子-空穴对，且有源柱120内的N型元素迁移形成电桥。由于电桥的存在，使得电子可以离开反型区140，而空穴无法离开反型区140，又由于栅极上的电压，使得在栅极正下方的区域存在反型层141，反型层141和第二隔离层130下方区域以及反型层和第一隔离层110下方区域构成空穴存储区142，进而将空穴固定在了第一隔离层110以及第二隔离层130下方存储起来。参考图39，当栅极端施加正压，漏极端施加负压时，空穴则全部被抽离空穴存储区142，在有源柱120内和反型区140内迁移和扩散，即反型区140具有储藏电荷的功能，反型区140可以视为等效电容，可以简化制备电容的工艺流程，且有利于降低半导体结构的线宽。因此，电容的尺寸可以较大以保证电容的存储容量较大，有利于提高半导体结构的存储密度。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (19)

  1. 一种半导体结构的制备方法，包括：
    提供基底；
    在所述基底内形成沿第一方向延伸的位线；
    在所述位线上形成有源柱，所述有源柱的底面与所述位线相接触且所述有源柱内掺杂有N型元素；
    在所述有源柱的侧面形成反型区，所述反型区内掺杂有P型元素；
    依次形成介电层以及沿第二方向延伸的字线包覆部分所述反型区，所述介电层位于所述字线与所述反型区之间。
  2. 如权利要求1所述的半导体结构的制备方法，其中，采用选择性外延生长工艺，形成所述反型区。
  3. 如权利要求2所述的半导体结构的制备方法，其中，形成所述反型区的工艺步骤中，原位掺杂所述P型元素。
  4. 如权利要求1所述的半导体结构的制备方法，其中，在形成反型区之前，还包括：对部分厚度的所述有源柱的侧壁进行减薄处理。
  5. 如权利要求4所述的半导体结构的制备方法，其中，采取湿法刻蚀工艺进行所述减薄处理，且所述湿法刻蚀工艺采用的刻蚀液体为碱性液体。
  6. 如权利要求4所述的半导体结构的制备方法，其中，进行所述减薄处理之前，包括：
    在所述基底上以及所述位线顶面依次形成层叠的第一隔离层、牺牲层以及第二隔离层，所述第二隔离层内具有贯穿所述第二隔离层厚度的通孔，且所述通孔底部暴露出所述牺牲层；
    去除所述牺牲层，露出所述有源柱的侧面。
  7. 如权利要求6所述的半导体结构的制备方法，其中，所述牺牲层的材料包括氮化硅，采用热磷酸刻蚀液去除所述牺牲层。
  8. 如权利要求6所述的半导体结构的制备方法，其中，所述在所述基底上依次形成层叠的第一隔离层、牺牲层以及第二隔离层的工艺步骤包括：
    在所述基底上以及所述位线顶面依次形成层叠的第一隔离膜、所述牺牲层、第二隔离膜 以及具有第一开口的第一掩膜层；
    以所述第一掩膜层为掩膜，沿所述第一开口依次刻蚀所述第一掩膜层、所述第二隔离膜、所述牺牲层以及所述第一隔离膜，形成沟槽，所述沟槽底部暴露出所述位线，剩余的所述第一隔离膜作为所述第一隔离层；
    形成所述有源柱，所述有源柱填充满所述沟槽；
    在所述第二隔离膜上依次形成第三隔离膜，所述第三隔离膜覆盖所述有源柱顶面；
    图形化所述第三隔离膜以及所述第二隔离膜，形成所述通孔，且剩余的所述第二隔离膜以及所述第三隔离膜共同作为所述第二隔离层。
  9. 如权利要求6所述的半导体结构的制备方法，其中，所述在所述基底上依次形成所述第一隔离层、牺牲层以及所述第二隔离层的工艺步骤包括：
    在所述基底上形成所述有源柱；
    在所述基底上依次形成层叠的所述第一隔离层、所述牺牲层以及第四隔离膜，所述牺牲层还位于所述有源柱的部分侧面，所述第四隔离膜位于所述有源柱的部分侧面以及顶面；
    图形化所述第四隔离膜，形成所述通孔，剩余所述第四隔离膜作为所述第二隔离层。
  10. 如权利要求6所述的半导体结构的制备方法，其中，形成字线的工艺步骤包括：
    形成填充满所述通孔的导电膜，且所述导电膜还位于所述第一隔离层与所述第二隔离层之间，所述导电膜环绕所述反型区；
    图形化所述导电膜，形成若干相互分立的所述字线。
  11. 如权利要求10所述的半导体结构的制备方法，其中，图形化所述导电膜的步骤包括：
    去除位于所述通孔内的所述导电膜，且去除位于所述通孔正下方的所述导电膜，剩余所述导电膜作为所述字线。
  12. 如权利要求11所述的半导体结构的制备方法，其中，形成字线之后，还包括：
    形成填充满所述通孔的绝缘层，所述绝缘层还填充满相邻的所述字线之间的区域。
  13. 如权利要求1所述的半导体结构的制备方法，其中，采用外延生长工艺，形成所述位线；
    形成所述位线的工艺步骤包括：
    提供初始基底，所述初始基底内具有沿所述第一方向延伸的沟道；
    形成所述位线，所述位线填充满所述沟道。
  14. 一种半导体结构，包括：
    基底，所述基底内具有沿第一方向延伸的位线；
    有源柱，所述有源柱位于所述位线上，所述有源柱的底面与所述位线相接触且所述有源柱内掺杂有N型元素；
    反型区，所述反型区位于所述有源柱的侧面，所述反型区内掺杂有P型元素；
    介电层以及沿第二方向延伸的字线，所述介电层以及字线包覆部分所述反型区，所述介电层位于所述字线与所述反型区之间。
  15. 如权利要求14所述的半导体结构，其中，所述位线为半导体位线，且所述半导体位线内掺杂有N型元素。
  16. 如权利要求14所述的半导体结构，其中，所述反型区的主体材料与所述有源柱的主体材料相同。
  17. 如权利要求14或16所述的半导体结构，其中，所述反型区的主体材料包括硅、锗或者锗化硅。
  18. 如权利要求14所述的半导体结构，其中，在沿垂直于所述有源柱的侧壁并朝向所述有源柱的轴心的方向上，所述反型区的厚度范围为4nm～15nm。
  19. 如权利要求14所述的半导体结构，其中，在平行于所述有源柱侧壁的方向上，整个所述反型区的高度比被所述介电层以及字线包覆的部分所述反型区的高度多8nm～30nm。
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CN108461496A (zh) * 2018-05-09 2018-08-28 睿力集成电路有限公司 集成电路存储器及其形成方法、半导体集成电路器件
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