WO2024040642A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2024040642A1
WO2024040642A1 PCT/CN2022/118568 CN2022118568W WO2024040642A1 WO 2024040642 A1 WO2024040642 A1 WO 2024040642A1 CN 2022118568 W CN2022118568 W CN 2022118568W WO 2024040642 A1 WO2024040642 A1 WO 2024040642A1
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Prior art keywords
area
bit line
lead
shallow trench
trench isolation
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PCT/CN2022/118568
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English (en)
French (fr)
Inventor
蒋懿
肖德元
邱云松
邵光速
苏星松
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长鑫存储技术有限公司
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Publication of WO2024040642A1 publication Critical patent/WO2024040642A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • the preparation process of the conductive layer itself used to lead the bit lines and word lines out of the array area is affected, thereby affecting the conductive performance of the conductive layer itself.
  • the conductive layer is The layout area occupied in the semiconductor structure also needs to be reduced.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least conducive to improving the overall conductive performance of word lines and/or bit lines while reducing the layout area of lead-out regions.
  • embodiments of the present disclosure provide a semiconductor structure, including: an array region and a partition region surrounding the array region; the array region includes partial bit lines extending along a first direction and Part of the word lines extending in the second direction; the isolation area includes a lead-out area adjacent to at least one side of the array area, and the word lines and/or the bit lines are also located in the lead-out area; the The isolation area includes a shallow trench isolation structure, and the shallow trench isolation structure is located on a side of the lead-out area away from the array area.
  • the lead-out area includes a bit line lead-out area arranged along the first direction with the array area, and the bit line is also located in the bit line lead-out area;
  • the shallow trench isolation structure It includes a bit line shallow trench isolation structure, and the bit line shallow trench isolation structure is located on a side of the bit line lead-out area away from the array area.
  • the ratio of the width of the bit line lead-out area to the width of the isolation area is 0.7 ⁇ 0.95.
  • the lead-out area includes a word line lead-out area arranged along the second direction with the array area, and the word line is also located in the word line lead-out area;
  • the shallow trench isolation structure It includes a word line shallow trench isolation structure, and the word line shallow trench isolation structure is located on a side of the word line lead-out area away from the array area.
  • the ratio of the width of the word line lead-out area to the width of the isolation area is 0.7 ⁇ 0.95.
  • the width of the lead-out area ranges from 0.05um to 0.15um.
  • the semiconductor structure further includes: a substrate, the bit line is located on the substrate, and the array area further includes: a semiconductor pillar located on a side of the bit line away from the substrate, a plurality of The semiconductor pillars are spaced apart along the first direction and/or the second direction, wherein along the direction in which the base points to the bit line, the semiconductor pillars include a bottom, a middle and a top, Bit lines are connected to the bottom contacts arranged along the first direction, and the word lines surround the middle portion arranged along the second direction.
  • the bit line includes: a peripheral layer and a conductive block, the peripheral layer surrounds a plurality of cavities arranged along the first direction, the conductive block fills the cavities and is located at the The central area of the conductive block in the array area corresponds to the spacing between adjacent semiconductor pillars arranged along the first direction.
  • the material of the peripheral layer includes a metal semiconductor compound
  • the material of the conductive block includes conductive materials such as tungsten, titanium nitride, or copper.
  • a top surface of the semiconductor pillar is no higher than a top surface of the shallow trench isolation structure in a direction from the substrate to the bit line.
  • the shallow trench isolation structure includes a first region contact-connected with the bit line and a second region located on the first region. , along the first direction, the width of the first area is greater than or equal to the width of the second area.
  • another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate that includes an array region and a partition region surrounding the array region; and forming a semiconductor structure along a first direction. an extended bit line and a word line extending along a second direction, wherein a portion of the bit line extending along the first direction is located in the array region, and a portion of the word line extending along the second direction is also located in the array
  • the partition area includes a lead-out area adjacent to at least one side of the array area, and the word line and/or the bit line are also located in the lead-out area; in the base of the isolation area A shallow trench isolation structure is formed on the lead-out area, and the shallow trench isolation structure is located on a side of the lead-out area away from the array area.
  • forming the bit line includes: providing a substrate; patterning the substrate to form an initial bit line extending along the first direction; and forming an initial bit line located on the initial bit line and A plurality of semiconductor pillars arranged at intervals along the first direction and/or the second direction; the distance between adjacent semiconductor pillars and the distance between the semiconductor pillar and the shallow trench isolation structure is Etching the initial bit line with openings to form a plurality of first cavities, part of the first cavities being located in the lead-out area; metallizing the exposed sidewalls of the first cavities to Forming a peripheral layer, the peripheral layer surrounding a plurality of second cavities arranged along the first direction; forming a conductive block, the conductive block filling the second cavity, the peripheral layer and the conductive block Blocks make up the bit lines.
  • the step of forming the shallow trench isolation structure includes: forming an initial shallow trench isolation structure on the substrate of the isolation area on a side of the lead-out area away from the array area; and etching The initial shallow trench isolation structure is etched to form a second region, and the remaining initial shallow trench isolation structure is a first region, wherein, along the direction of the substrate pointing to the initial bit line, the first The top surface of the region is not lower than the top surface of the initial bit line.
  • the step of forming the conductive block includes: forming a space that fills a gap between adjacent semiconductor pillars, a gap between the semiconductor pillar and the shallow trench isolation structure, and the second cavity. an initial conductive layer; using the top surface of the first region as an etching stop layer, etch the initial conductive layer to form the conductive block.
  • the word lines and/or bit lines are located in the lead-out area. It can be understood that the conductive layer used to lead the word lines and/or bit lines out of the array area can be the word lines and/or bit lines themselves, that is, the word lines are drawn out from the array area.
  • the conductive layer drawn out from the array area and the word lines located in the array area are integrally formed, which is beneficial to reducing the contact resistance between the conductive layer leading the word lines out from the array area and the word lines located in the array area, and is beneficial to improving The overall conductivity of the word line; alternatively, the conductive layer that leads the bit line from the array area and the bit line located in the array area are integrally formed, which is beneficial to reducing the connection between the conductive layer that leads the bit line from the array area and the bit line located in the array area.
  • the contact resistance between bit lines in the array area is beneficial to improving the overall conductive performance of the bit lines.
  • a shallow trench isolation structure is also provided in the isolation area. Using both the shallow trench isolation structure and the array area to design the size of the lead-out area is beneficial to reducing the layout area of the lead-out area in the semiconductor structure.
  • Figure 1 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional view of the semiconductor structure shown in Figure 1 along the first cross-sectional direction AA1;
  • Figure 3 is a schematic cross-sectional view of the semiconductor structure shown in Figure 1 along the second cross-sectional direction BB1;
  • 4 to 8 are partial cross-sectional schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • the pattern density in the array area is higher than the pattern density in the partition area. It can be understood that the pattern here refers to the functional structure used to realize some electrical functions in the semiconductor structure.
  • an initial bit line or initial word line will be formed first.
  • the initial bit line or initial word line will not only be located in the array area, but also in the isolation area.
  • the initial bit line or initial word line will be formed.
  • the word lines are etched to form bit lines or word lines.
  • the etching process has a lower etching rate for the initial bit line or initial word line located in the array area. Lower than the etching rate for the initial bit line or initial word line located in the isolation area.
  • bit lines or word lines are formed in the array area
  • the initial bit lines or initial word lines in the isolation area are over-etched, resulting in a large difference in conductivity between the bit lines in the array area and the isolation area, or causing the array area to
  • bit line and the conductive layer are not integrally formed, and the contact resistance between the bit line and the conductive layer is easily increased, reducing the overall conductive performance of the bit line and the conductive layer, or there is a gap between the word line and the conductive layer. If it is not an integrally formed structure, it is easy to increase the contact resistance between the word line and the conductive layer, and reduce the overall conductive performance of the word line and the conductive layer.
  • bit lines or word lines located in the array area In order to lead out the bit lines or word lines located in the array area and balance the difference in conductivity between the bit lines or word lines in the array area and the isolation area, it is necessary to prepare the bit lines or word lines located in the array area first, and then Preparing a conductive layer that leads the bit lines or word lines out of the array area is not only detrimental to simplifying the preparation process of the semiconductor structure, but also tends to reduce the overall conductive properties of the bit lines or word lines and the conductive layer.
  • the implementation of the present disclosure provides a semiconductor structure and a manufacturing method thereof.
  • word lines and/or bit lines are located in the lead-out area. It can be understood that the word lines and/or bit lines are used to lead out the word lines and/or bit lines from the array area.
  • the conductive layer can be the word line and/or the bit line itself, that is, the conductive layer that leads the word line from the array area and the word line located in the array area are integrally formed, which is beneficial to reducing the cost of leading the word line from the array area.
  • the contact resistance between the conductive layer and the word line located in the array area is conducive to improving the overall conductive performance of the word line; alternatively, the conductive layer leading the bit line from the array area and the bit line located in the array area are integrated into an integral structure. This is beneficial to reducing the contact resistance between the conductive layer that leads the bit lines out of the array area and the bit lines located in the array area, and is beneficial to improving the overall conductive performance of the bit lines.
  • a shallow trench isolation structure is also provided in the isolation area. Using both the shallow trench isolation structure and the array area to design the size of the lead-out area is beneficial to reducing the layout area of the lead-out area in the semiconductor structure.
  • a shallow trench isolation structure is conducive to increasing the pattern density of the isolation area, thereby helping to reduce the difference between the pattern density of the array area and the pattern density of the isolation area.
  • the word line or bit line is located in both the array area and the isolation area, which helps prevent the word line or bit line in the isolation area from being over-etched, thereby helping to reduce the difference in conductivity between the bit lines in the array area and the isolation area. , or reduce the difference in conductive properties between word lines in the array area and isolation area.
  • FIGS. 1 to 3 are all partial structural schematic diagrams of the semiconductor structure.
  • the semiconductor structure includes: an array area 100 and a partition area 101 surrounding the array area 100 ; the array area 100 includes part of the bit lines 102 extending along the first direction X and part of the words extending along the second direction Y. Line 103; the isolation area 101 includes a lead-out area 111 adjacent to at least one side of the array area 100, and the word line 103 and/or the bit line 102 are also located in the lead-out area 111; the isolation area 101 includes a shallow trench isolation structure 104, The shallow trench isolation structure 104 is located on the side of the lead-out area 111 away from the array area 100 .
  • the word line 103 and/or the bit line 102 are located in both the array area 100 and the lead-out area 111. It can be understood that the conductive wires used to lead the word line 103 and/or the bit line 102 out of the array area 100
  • the layer is the word line 103 and/or the bit line 102 itself, that is, the conductive layer leading the word line 103 from the array area 100 and the word line 103 located in the array area 100 are formed into an integrated structure, which is conducive to reducing the cost of the word line 103
  • the contact resistance between the conductive layer led out from the array area 100 and the word line 103 in the array area 100 is conducive to improving the overall conductive performance of the word line 103; or, the conductive layer leading out the bit line 102 from the array area 100 and
  • the bit line 102 located in the array area 100 is an integrally formed structure, which is beneficial to reducing the contact resistance between the conductive layer that leads the bit line 102 from the array area 100 and the bit line 102 located in the array
  • a shallow trench isolation structure 104 is also provided in the isolation area 101.
  • Using both the shallow trench isolation structure 104 and the array area 100 to design the size of the lead-out area 111 is beneficial to reducing the layout area of the lead-out area 111 in the semiconductor structure.
  • arranging the shallow trench isolation structure 104 in the isolation area 101 is beneficial to increasing the pattern density of the isolation area 101, thereby conducive to reducing the difference between the pattern density of the array area 100 and the pattern density of the isolation area 101.
  • word line 103 or bit line 102 it is advantageous to make word line 103 or bit line 102 located in both the array area 100 and the isolation area 101.
  • the semiconductor structure further includes a peripheral area (not shown in the figure), and the isolation area 101 is located between the array area 100 and the peripheral area for isolating the array area 100 and the peripheral area.
  • the lead-out area 111 may include a bit line lead-out area 121 arranged along the first direction X with the array area 100 , and the bit line 102 is also located in the bit line lead-out area 121 ; shallow trench isolation structure 104 A bit line shallow trench isolation structure 114 may be included, and the bit line shallow trench isolation structure 114 is located on a side of the bit line lead-out area 121 away from the array area 100 . In this way, the bit line 102 is located in both the array area 100 and the bit line extraction area 121. It can be understood that the bit line 102 itself can realize the function of leading the bit line 102 of the array area 100 to the isolation area 101.
  • the array The bit line 102 of the area 100 and the bit line 102 of the isolation area 101 are an integrally formed structure. Compared with the bit line being only located in the array area and the conductive layer being located in the isolation area, one embodiment of the present disclosure is beneficial to reducing the size of the bit line 102 of the array area 100.
  • the contact resistance between the bit line 102 in the isolation area 101 is also beneficial to reducing the overall internal defect density of the bit line 102 .
  • the ratio of the thickness of the bit lines 102 in the array area 100 to the thickness of the bit lines 102 in the isolation area 101 is 0.9 ⁇ 1.1. It can be understood that the thickness of the bit lines 102 in the array area 100 and the thickness of the bit lines 102 in the isolation area 101 are basically the same, which is beneficial to reducing the difference in conductive properties between the bit lines 102 in the array area 100 and the isolation area 101, thereby It is beneficial to improve the overall conductive performance of the bit line 102.
  • the ratio of the width of the bit line lead-out area 121 to the width of the isolation area 101 may be 0.7 ⁇ 0.95. In this way, controlling the length of the bit line lead-out area 121 in the first direction Moreover, it is beneficial to reduce the layout area occupied by the bit line lead-out region 121 in the semiconductor structure, and is beneficial to improving the electrical performance of the semiconductor structure and at the same time increasing the integration density of the semiconductor structure. In one example, the ratio of the width of the bit line lead-out area 121 to the width of the isolation area 101 may be 0.91.
  • the lead-out area 111 may include a word line lead-out area 131 arranged along the second direction Y with the array area 100 , and the word line 103 is also located in the word line lead-out area 131 ; shallow trench isolation structure 104 may include a word line shallow trench isolation structure 124 located on a side of the word line lead-out area 131 away from the array area 100 .
  • the word line 103 is located in both the array area 100 and the word line extraction area 131. It can be understood that the word line 103 itself can realize the function of leading the word line 103 of the array area 100 to the isolation area 101.
  • the word line 103 of the array area 100 and the word line 103 of the isolation area 101 are an integrally formed structure. Compared with the word line being only located in the array area and the conductive layer being located in the isolation area, one embodiment of the present disclosure is beneficial to reducing the number of word lines in the array area 100 The contact resistance between the word line 103 and the word line 103 in the isolation area 101 is also beneficial to reducing the overall internal defect density of the word line 103.
  • the ratio of the thickness of the word line 103 in the array area 100 to the thickness of the word line 103 in the isolation area 101 is 0.9 ⁇ 1.1. It can be understood that the thickness of the word lines 103 in the array area 100 and the thickness of the word lines 103 in the isolation area 101 are basically the same, which is beneficial to reducing the difference in conductive properties between the word lines 103 in the array area 100 and the isolation area 101, thereby achieving It is beneficial to improve the overall conductive performance of the word line 103.
  • the ratio of the width of the word line lead-out area 131 to the width of the isolation area 101 is 0.7 ⁇ 0.95. In this way, controlling the length of the word line lead-out area 131 in the second direction Y, while keeping the word line 103 still located in the word line lead-out area 131, is conducive to preventing the word line 103 from being too long in the second direction Y. Moreover, it is beneficial to reduce the layout area occupied by the word line lead-out region 131 in the semiconductor structure, and is beneficial to improving the electrical performance of the semiconductor structure and at the same time increasing the integration density of the semiconductor structure. In one example, the ratio of the width of the word line lead-out area 131 to the width of the isolation area 101 may be 0.91.
  • the lead-out area 111 may only be included as a bit line lead-out area 121 , that is, the bit line 102 is located in both the array area 100 and the isolation area 101 , for word lines. There is no restriction on whether 103 is still located in the partition area 101; in other embodiments, the lead-out area 111 may only be included as the word line lead-out area 131, that is, the word line 103 is located in both the array area 100 and the isolation area 101.
  • the lead-out area 111 can be simultaneously included as a bit line lead-out area 121 and a word line lead-out area 131, that is, the bit line 102 is located in both the array area 100 and the isolation area. area 101, and the word line 103 is located in both the array area 100 and the isolation area 101.
  • the width of the lead-out area 111 may range from 0.05um to 0.15um.
  • the lead-out area 111 here refers to a single lead-out area 111, such as the bit line lead-out area 121 or the word line lead-out area 131.
  • the direction along the lead-out area 111 toward the shallow trench isolation structure 104 refers to the direction along the bit line lead-out area 121 toward the bit line shallow trench isolation structure 114 , that is, the first direction X
  • the width of the bit line lead-out area 121 can range from 0.05um to 0.15um
  • the direction along the lead-out area 111 toward the shallow trench isolation structure 104 refers to: along the word line lead-out area 131 pointing toward the word line shallow trench isolation structure 104.
  • the direction of the trench isolation structure 124, that is, the second direction Y, and the width of the word line lead-out region 131 may range from 0.05um to 0.15um.
  • the width of the word line lead-out area 131 may be 0.105 um, and the width of the isolation area 101 may be 0.115 um.
  • the semiconductor structure may further include: a substrate 105 , the bit line 102 is located on the substrate 105 , and the array area 100 may further include: a semiconductor pillar located on the side of the bit line 102 away from the substrate 105 106.
  • a plurality of semiconductor pillars 106 are arranged at intervals along the first direction , a bit line 102 is in contact with the bottom portion 116 arranged along the first direction X, and a word line 103 surrounds the middle portion 126 arranged along the second direction Y.
  • a plurality of semiconductor pillars 106 can be arranged in an array along the first direction X and the second direction Y, and a plurality of bit lines 102 extending along the first direction X are arranged at intervals along the second direction Y. , a plurality of word lines 103 extending along the second direction Y are arranged at intervals along the first direction X.
  • the semiconductor structure may further include: a gate dielectric layer 107 located at least on the sidewall of the middle portion 126 extending in the direction Z of the substrate 105 pointing toward the bit line 102 .
  • a gate dielectric layer 107 located at least on the sidewall of the middle portion 126 extending in the direction Z of the substrate 105 pointing toward the bit line 102 .
  • the word line 103, the gate dielectric layer 107 and the semiconductor pillar 106 together form a vertical gate-all-around (GAA, Gate-All-Around) transistor structure, in which the bottom 116 serves as the source or drain of the GAA transistor.
  • the top 136 serves as the source or the drain of the GAA transistor
  • the middle 126 serves as the channel region of the GAA transistor.
  • the bit line 102 is located between the substrate 105 and the GAA transistor. Therefore, a 3D stacked semiconductor structure can be formed, which is beneficial to improving the integration density of the semiconductor structure.
  • the material of the word line 103 may be at least one of conductive materials such as tungsten, titanium nitride, or copper, and the material of the gate dielectric layer 107 may be at least one of insulating materials such as silicon oxide or silicon nitride. kind.
  • the substrate 105, the bit line 102 and the semiconductor pillar 106 have the same semiconductor element, which is beneficial to improving interface state defects between the semiconductor pillar 106 and the bit line 102 and improving the performance of the semiconductor structure.
  • the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium.
  • bit lines 102 and semiconductor pillars 106 both include silicon.
  • the bit line and the semiconductor pillar may both include germanium, or the bit line and the semiconductor pillar may both include silicon and germanium, or the bit line and the semiconductor pillar may both include silicon and carbon, or the bit line Both the bit line and the semiconductor pillar include arsenic elements and gallium elements, or the bit lines and the semiconductor pillars both include gallium elements and indium elements.
  • the bit line 102 may include: a peripheral layer 112 and a conductive block 122 .
  • the peripheral layer 112 at least encloses a plurality of cavities 132 arranged along the first direction X.
  • the conductive block 122 fills The cavity 132 is filled, and the central area of the conductive block 122 located in the array area 100 corresponds to the spacing between adjacent semiconductor pillars 106 arranged along the first direction X.
  • peripheral layer 112 can be used as a transition layer between the bottom 116 and the conductive block 122 to avoid a large contact resistance when the conductive block 122 is in direct contact with the bottom 116, which is beneficial to reducing the overall contact resistance between the bit line 102 and the bottom 116. contact resistance to improve the electrical performance of the semiconductor structure.
  • peripheral layer 112 of the array area 100 surrounds a plurality of cavities 132 arranged along the first direction , and also fills the groove 182, which is beneficial to reducing the difference in thickness of the bit lines 102 in the array area 100 and the isolation area 101 in the direction Z, thereby helping to reduce the conductive performance between the array area 100 and the bit lines 102 in the isolation area 101 difference to improve the overall conductive performance of the bit line 102.
  • the material of the peripheral layer 112 may include a metal semiconductor compound, and the material of the conductive block 122 may include at least one of conductive materials such as tungsten, titanium nitride, or copper.
  • the metal semiconductor compound has a relatively smaller resistivity than an unmetallized semiconductor material. Therefore, the resistivity of the peripheral layer 112 is smaller than that of the semiconductor pillar 106 , so that there is It is beneficial to reduce the resistance of the peripheral layer 112 and reduce the contact resistance between the peripheral layer 112 and the bottom 116, further improving the electrical performance of the semiconductor structure.
  • the peripheral layer 112 and the semiconductor pillar 106 include the same semiconductor element, which is beneficial to improving the interface state defects between the semiconductor pillar 106 and the bit line 102 and reducing the majority carrier transmission between the semiconductor pillar 106 and the bit line 102 . The probability of defect trapping is consumed, thereby helping to improve the transmission efficiency of majority carriers between the peripheral layer 112 and the semiconductor pillar 106 .
  • bit line 102 is composed of the peripheral layer 112 in direct contact with the semiconductor pillar 106 and the conductive block 122 located in the cavity 132 surrounded by the peripheral layer 112.
  • it is beneficial to improve the connection between the bit line 102 and the semiconductor through the peripheral layer 112.
  • the transmission efficiency of majority carriers between the pillars 106 is beneficial to improving the overall conductive performance of the bit line 102 through the conductive block 122 .
  • the metal semiconductor compound includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.
  • the semiconductor pillar 106 is doped with N-type ions or P-type ions, where the N-type ions are at least one of arsenic ions, phosphorus ions or antimony ions; the P-type ions are boron ions and indium ions. Or at least one of gallium ions.
  • the top surface of the semiconductor pillar 106 is no higher than the top surface of the shallow trench isolation structure 104 .
  • arranging the shallow trench isolation structure 104 in the isolation area 101 is beneficial to increasing the pattern density of the isolation area 101 , thereby helping to reduce the difference between the pattern density of the array area 100 and the pattern density of the isolation area 101 .
  • Setting the top surface of the semiconductor pillar 106 to be no higher than the top surface of the shallow trench isolation structure 104 is beneficial to forming a groove between the entire semiconductor pillar 106 and the shallow trench isolation structure 104 , and subsequently between adjacent semiconductor pillars 106
  • the shallow trench isolation structure 104 may include a first region 134 in contact connection with the bit line 102 and located at the first In the second area 144 on the area 134, along the first direction X, the width of the first area 134 is greater than or equal to the width of the second area 144.
  • the width of the first region 134 is greater than or equal to the width of the second region 144, which is beneficial to prevent the subsequent area used to form the bit line 102 from being covered by the shallow trench isolation structure 104, and along the direction Z, the first region
  • the top surface of 134 can serve as an etching stop layer when the bit line 102 is formed using an etching process.
  • the word line shallow trench isolation structure 124 may not be divided into Two parts with different widths in the second direction Y.
  • the semiconductor structure may further include a mask layer 108 for protecting the tops 136 of the semiconductor pillars 106 .
  • the gate dielectric layer 107 covers the sidewalls of the semiconductor pillars 106 and the mask layer 108 extending in the direction Z, and the gate dielectric layer 107 also covers the shallow trench isolation structure 104 along the direction Z.
  • the sidewall extending upward is an example. In practical applications, the gate dielectric layer 107 may only cover the sidewall extending along the direction Z of the middle portion 126 .
  • the conductor structure may further include: a dielectric layer 109 located between the bit line 102 and the word line 103 , and the dielectric layer 109 surrounds the sidewalls of the bottom 116 of the semiconductor pillar 106 along the direction Z.
  • the dielectric layer 109 has a gate dielectric layer 107 between the bottom 116; in another example, the dielectric layer 109 may be in direct contact with the sidewalls of the bottom 116 along the direction Z.
  • the semiconductor structure may further include: a capacitive contact layer (not shown in the figure), and a conductive plug (not shown in the figure) located in the lead-out area 111, and the conductive plug is connected to the lead-out area 111.
  • the bit line 102 and/or the word line 103 are in contact connection, and the conductive plug is used to lead out the bit line 102 and/or the word line 103 in the direction Z. It should be noted that after removing the mask layer 108 located on the top 136 of the semiconductor pillar 106, a capacitive contact layer is formed on the top 136.
  • the word line 103 and/or the bit line 102 are located in both the array area 100 and the lead-out area 111. It can be understood that the word line 103 and/or the bit line 102 are used to remove the word line 103 and/or the bit line 102 from the array area 100.
  • the lead-out conductive layer is the word line 103 and/or the bit line 102 itself. In this way, it is beneficial to reduce the contact resistance between the conductive layer leading the word line 103 out of the array area 100 and the word line 103 located in the array area 100.
  • the word line 103 or the bit line 102 it is beneficial to make the word line 103 or the bit line 102 both located in the array area 100. Also located in the isolation area 101, there is no need to prepare an additional conductive layer in the isolation area 101 for leading out the word line 103 or the bit line 102 of the array area 100, and it is beneficial to reduce the gap between the bit lines 102 in the array area 100 and the isolation area 101. The difference in conductive properties between the word lines 103 in the array area 100 and the isolation area 101 is reduced.
  • Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure provided in the previous embodiment.
  • a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to FIGS. 1 to 8 .
  • 4 to 8 are partial cross-sectional schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
  • the manufacturing method of a semiconductor structure includes: providing a substrate 105 that includes an array region 100 and a partition region 101 surrounding the array region 100 ; forming a bit line 102 extending along a first direction The word line 103 extending in Y, wherein part of the bit line 102 extending in the first direction The lead-out area 111 adjacent to at least one side of the area 100, the word line 103 and/or the bit line 102 are also located in the lead-out area 111; a shallow trench isolation structure 104 is formed on the substrate 105 of the isolation area 101, and the shallow trench isolation structure 104 Located on the side of the lead-out area 111 away from the array area 100 .
  • the shallow trench isolation structure 104 is first formed in the isolation area 101. In this way, it is beneficial to utilize the reserved space of both the shallow trench isolation structure 104 and the array area 100. Increasing the size of the lead-out area 111 is beneficial to reducing the layout area of the lead-out area 111 in the semiconductor structure. Moreover, forming the shallow trench isolation structure 104 first in the isolation area 101 is beneficial to increasing the pattern density of the isolation area 101, thereby helping to reduce the difference between the pattern density of the array area 100 and the pattern density of the isolation area 101.
  • the word line 103 or the bit line 102 In the step of preparing the word line 103 or the bit line 102, it is advantageous to make the word line 103 or the bit line 102 located in both the array area 100 and the isolation area 101. There is no need to prepare additional words in the isolation area 101 for connecting the array area 100.
  • the conductive layer drawn out from the line 103 or the bit line 102 thereby improves the conductive performance of the formed word line 103 or bit line 102 and is conducive to simplifying the process steps of forming the word line 103 or bit line 102. Moreover, it is conducive to reducing the cost of the array.
  • the difference in conductive properties between the bit lines 102 in the area 100 and the isolation area 101 is reduced, or the difference in electrical conductivity between the word lines 103 in the array area 100 and the isolation area 101 is reduced.
  • bit line 102 may include the following steps:
  • a substrate 105 is provided; the substrate 105 is patterned to form an initial bit line 142 extending along the first direction A plurality of semiconductor pillars 106 arranged at Y intervals.
  • the initial bit line 142 and the semiconductor pillar 106 are formed by patterning the substrate 105, and the remaining unpatterned substrate 105 is used to support the initial bit line 142 and the semiconductor pillar 106, and to support Other structures subsequently formed on the substrate 105, that is, the substrate 105, the initial bit line 142 and the semiconductor pillar 106 have the same semiconductor elements, then the semiconductor pillar 106 and the initial bit line 142 can be formed using the same film layer structure.
  • the film layer structure is composed of It is composed of semiconductor elements so that the semiconductor pillar 106 and the initial bit line 142 have an integrated structure, thereby improving the interface state defects between the semiconductor pillar 106 and the initial bit line 142 .
  • part of the substrate 105 in the isolation region 101 can be etched to form the shallow trench isolation structure 104 ; or, before forming the initial bit line 142 After the bit lines 142 and the semiconductor pillars 106, a portion of the substrate 105 in the isolation area 101 is etched. It can be understood that in the manufacturing method provided by another embodiment of the present disclosure, the order of forming the initial bit line 142 and the semiconductor pillar 106 and forming the shallow trench isolation structure 104 is not limited.
  • the step of forming the shallow trench isolation structure 104 may include: forming an initial shallow trench isolation structure on the substrate 105 of the isolation area 101 on a side of the lead area 111 away from the array area 100 (not shown in the figure). ); Referring to Figure 4, the initial shallow trench isolation structure is etched to form the second region 144, and the remaining initial shallow trench isolation structure is the first region 134, wherein the direction Z along the substrate 105 points to the initial bit line 142, The top surface of the first area 134 is not lower than the top surface of the initial bit line 142 .
  • the top surface of the first region 134 can be used as an etching stop layer, which is beneficial to improving the dimensional accuracy of the formed bit line 102 .
  • the following describes the formation method of the shallow trench isolation structure 104 in detail through three embodiments.
  • the lead-out area 111 may include a bit line lead-out area 121 arranged along the first direction X with the array area 100.
  • the step of forming the shallow trench isolation structure 104 may include: referring to FIG. A bit line shallow trench isolation structure 114 is formed in the isolation area 101 of the array area 100, and along the direction Z of the substrate 105 pointing to the bit line 102, the bit line shallow trench isolation structure 114 may include a third contact connection with the bit line 102.
  • the width of the first area 134 is greater than or equal to the width of the second area 144.
  • the lead-out area 111 may include a word line lead-out area 131 arranged along the second direction Y with the array area 100, and the step of forming the shallow trench isolation structure 104 may include: referring to FIG. 3, in the word line lead-out area 131 A word line shallow trench isolation structure 124 is formed in the isolation area 101 away from the array area 100 .
  • the lead-out area 111 may include both a bit line lead-out area 121 arranged along the first direction
  • the step of forming the shallow trench isolation structure 104 may include: forming the bit line shallow trench isolation structure 114 in the isolation area 101 of the bit line lead-out area 121 away from the array area 100, and forming the bit line shallow trench isolation structure 114 in the isolation area of the word line lead-out area 131 away from the array area 100.
  • a word line shallow trench isolation structure 124 is formed in 101 .
  • the manufacturing method of the semiconductor structure may further include forming a mask layer 108 for protecting the top 136 of the semiconductor pillar 106 . It can be understood that when an etching process is subsequently used to form the bit line 102 (refer to FIG. 2) and the word line 103 (refer to FIG. 3), the mask layer 108 can be used to protect the semiconductor pillar 106 to prevent the top 136 of the semiconductor pillar 106 from being etching.
  • the manufacturing method of the semiconductor structure may further include: forming a gate dielectric layer 107 covering the semiconductor pillar 106 and the mask.
  • the film layer 108 extends along the sidewalls in the direction Z, and the gate dielectric layer 107 also covers the sidewalls of the shallow trench isolation structure 104 extending along the direction Z.
  • the gate dielectric layer 107 is conducive to protecting the sidewalls of the semiconductor pillar 106 along the direction Z, and further prevents the semiconductor
  • the pillars 106 are etched, which is beneficial to protecting the shallow trench isolation structure 104 and preventing the shallow trench isolation structure 104 from being etched.
  • part of the gate dielectric layer 107 can be etched so that the gate dielectric layer 107 only covers the sidewalls extending in the direction Z of the middle portion 126; or, in After the bit line 102 is formed, the gate dielectric layer 107 affected by the etching process is removed, and then a new gate dielectric layer 107 is formed.
  • the new gate dielectric layer 107 at least covers the sidewalls of the middle portion 126 extending in the direction Z. It is understood that the new gate dielectric layer 107 is not affected by the etching process and has better density, which is beneficial to ensuring the good density and insulation performance of the new gate dielectric layer 107 itself.
  • the initial bit lines 142 are etched using the spacing between adjacent semiconductor pillars 106 and the spacing between the semiconductor pillars 106 and the shallow trench isolation structure 104 as openings to form a plurality of first cavities 152 , Part of the first cavity 152 is located in the lead-out area 111 .
  • the pattern density of the array area 100 is higher than the pattern density of the isolation area 101. Therefore, when etching the initial bit line 142, in the array area
  • the first cavity 152 formed in 100 is different from the first cavity 152 formed in the partition area 101 .
  • the cross-sectional shape of the first cavity 152 formed in the array area 100 perpendicular to the second direction Y is a bowl, which is beneficial to the subsequent formation of multiple conductive blocks 122 (refer to FIG. 2).
  • the formed first cavity 152 is a groove, and most of the area is exposed, which facilitates the subsequent formation of the conductive block 122 in the isolation area 101 .
  • the exposed sidewalls of the first cavity 152 are metallized to form a peripheral layer 112 , and the peripheral layer 112 surrounds a plurality of second cavities 162 arranged along the first direction X.
  • the step of metallizing the exposed sidewalls of the first cavity 152 may include: forming a metal layer (not shown in the figure) on the exposed sidewalls of the first cavity 152.
  • the layer provides metal elements for the subsequent formation of the peripheral layer 112; an annealing process is performed to convert at least part of the thickness of the initial bit line 142 into the peripheral layer 112; and after the peripheral layer 112 is formed, the remaining metal layer is removed.
  • the material of the metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.
  • the peripheral layer 112 surrounds a plurality of second cavities 162 arranged along the first direction
  • the partition area 101 also has a second cavity 162 .
  • the second cavity 162 formed in the array area 100 is different from the second cavity 162 formed in the partition area 101 .
  • the cross-sectional shape of the second cavity 162 formed in the array area 100 perpendicular to the second direction Y is a bowl
  • the second cavity 162 formed in the partition area 101 is a groove, and most areas are Exposed.
  • a conductive block 122 is formed, the conductive block 122 fills the second cavity 162 , and the peripheral layer 112 and the conductive block 122 form the bit line 102 .
  • forming the conductive block 122 may include the following steps:
  • an initial conductive layer 172 is formed that fills the space between adjacent semiconductor pillars 106 , the space between the semiconductor pillars 106 and the shallow trench isolation structure 104 , and the second cavity 162 .
  • the step of forming the initial conductive layer 172 may include: referring to FIG. 7 , first forming an initial conductive layer that fills the space between adjacent semiconductor pillars 106 , the space between the semiconductor pillars 106 and the shallow trench isolation structure 104 , and the second cavity 162 172; Referring to FIG. 8, a chemical mechanical planarization process is performed on the initial conductive layer 172 to eliminate the grooves of the initial conductive layer 172 at the bit line lead-out area 121.
  • the initial conductive layer 172 is etched to form the conductive block 122 .
  • the shallow trench isolation structure 104 (refer to FIG. 1 ) is not formed in the isolation area 101
  • a shallow trench is first formed in the isolation area 101
  • the isolation structure 104 can reduce the length of the bit line lead-out area 121 in the first direction
  • the conductive block 122 formed by etching is located in both the array area 100 and the bit line lead-out area 121. There is no need to prepare an additional conductive layer in the bit line lead-out area 121 for leading out the bit line 102 of the array area 100.
  • the manufacturing method of the semiconductor structure may further include the following steps:
  • a dielectric layer 109 is formed surrounding the sidewalls of the bottom 116 of the semiconductor pillar 106 in the direction Z, and the dielectric layer 109 fills the space between adjacent bottoms 116 and fills the bottom 116 and the shallow trench isolation structure 104 (refer to FIG. 1) The interval between. It can be understood that the dielectric layer 109 is used to achieve electrical isolation between the bit line 102 and the subsequently formed word line 103.
  • a word line 103 extending along the second direction Y is formed, and the word line 103 surrounds the sidewalls extending in the direction Z of a plurality of middle portions 126 spaced apart along the second direction Y, and the word line 103 and the middle portion 126 There is a gate dielectric layer 107 in between.
  • the step of forming the word line 103 includes: forming an initial word line (not shown in the figure), filling the space between adjacent remaining semiconductor pillars 106, and connecting the semiconductor pillar 106 with the shallow trench.
  • the space between the isolation structures 104 and the initial bit line are located on the top surface of the mask layer 108; the initial word line is etched to form the word line 103.
  • the shallow trench isolation structure 104 (refer to FIG. 1 ) is not formed in the isolation area 101
  • a shallow trench is first formed in the isolation area 101
  • the isolation structure 104 can reduce the length of the word line lead-out area 131 in the second direction Y, which is beneficial to reducing the difference between the pattern density of the array area 100 and the pattern density of the isolation area 101.
  • the word line 103 When preparing the word line 103, that is, at the initial stage of etching In the step of forming the word line 103, it is beneficial to reduce the difference between the etching rate of the initial word line in the array region 100 and the etching rate of the initial word line in the word line lead-out region 131 during the etching process, thereby facilitating the formation of the word line 103.
  • the word line 103 is located in both the array area 100 and the word line lead-out area 131. There is no need to prepare an additional conductive layer in the word line lead-out area 131 for leading out the word line 103 in the array area 100.
  • the word line 103, the gate dielectric layer 107 and the semiconductor pillar 106 together form a vertical gate-all-around (GAA, Gate-All-Around) transistor structure, in which the bottom 116 serves as one of the source or drain of the GAA transistor.
  • the top 136 serves as the other one of the source or drain of the GAA transistor, and the middle 126 serves as the channel region of the GAA transistor.
  • the manufacturing method of the semiconductor structure may further include: forming a conductive plug, the conductive plug is in contact with the bit line 102 located in the bit line lead-out area 121, and the conductive plug is used to connect the bit line 102 to the bit line 102. Bit lines 102 are led out in direction Z.
  • the manufacturing method of the semiconductor structure may further include: forming a conductive plug, the conductive plug is in contact with the word line 103 located in the word line lead-out area 131, and the conductive plug is used to connect the word line 103 to the word line 103.
  • the word line 103 is drawn out in the direction Z.
  • the method of manufacturing the conductor structure may further include: removing the mask layer 108 located on the top 136 of the semiconductor pillar 106 and forming a capacitive contact on the exposed top 136 layer.
  • forming the shallow trench isolation structure 104 in the isolation area 101 is beneficial to utilizing both the shallow trench isolation structure 104 and the array area 100 to reserve the size of the lead-out area 111 , and is beneficial to reducing the size of the lead-out area 111
  • the layout area in a semiconductor structure is beneficial to forming the shallow trench isolation structure 104 first in the isolation area 101 is beneficial to increasing the pattern density of the isolation area 101, thereby helping to reduce the difference between the pattern density of the array area 100 and the pattern density of the isolation area 101.
  • the conductive layer drawn out from the line 103 or the bit line 102 thereby improves the conductive performance of the formed word line 103 or bit line 102 and is conducive to simplifying the process steps of forming the word line 103 or bit line 102, and is conducive to avoiding isolation.
  • the word line 103 or the bit line 102 in the area 101 is over-etched, which is beneficial to reducing the difference in conductivity between the bit lines 102 in the array area 100 and the isolation area 101, or reducing the difference between the word lines 103 in the array area 100 and the isolation area 101. differences in conductive properties.

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Abstract

本公开实施例涉及半导体技术领域，提供一种半导体结构及其制造方法，半导体结构包括：阵列区和包围所述阵列区的隔断区；阵列区中包括沿第一方向延伸的部分位线以及沿第二方向延伸的部分字线；隔断区中包括与阵列区至少一侧相邻的引出区，字线和/或位线还位于引出区中；隔断区中包括浅沟槽隔离结构，浅沟槽隔离结构位于引出区远离阵列区的一侧。本公开实施例至少有利于在降低引出区的布局面积的同时，提高字线和/或位线整体的导电性能。

Description

半导体结构及其制造方法
交叉引用
本申请要求于2022年08月23日递交的名称为“半导体结构及其制造方法”、申请号为202211012623.1的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制造方法。
背景技术
随着半导体结构的不断发展，其关键尺寸不断减小，但由于光刻机的限制，其关键尺寸的缩小存在极限，因此如何在一片晶圆上做出更高存储密度的芯片，是众多科研工作者和半导体从业人员的研究方向。半导体结构的阵列区中，多个存储单元均由位线和字线控制，位于阵列区的位线和字线需要通过导电层从阵列区中引出，使得位线和字线与外围区的控制电路电连接。
然而，随着半导体结构的关键尺寸的缩小，用于将位线和字线从阵列区中引出的导电层自身的制备工艺受影响，从而影响导电层自身的导电性能，而且，导电层在把半导体结构中所占据的布局面积也有待降低。
发明内容
本公开实施例提供一种半导体结构及其制造方法，至少有利于在降低引出区的布局面积的同时，提高字线和/或位线整体的导电性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：阵列区和包围所述阵列区的隔断区；所述阵列区中包括沿第一方向延伸的部分位线以及沿第二方向延伸的部分字线；所述隔断区中包括与所述阵列区至少一侧相邻的引出区，所述字线和/或所述位线还位于所述引出区中；所述隔断区中包括浅沟槽隔离结构，所述浅沟槽隔离结构位于所述引出区远离所述阵列区的一侧。
在一些实施例中，所述引出区包括与所述阵列区沿所述第一方向排列的位线引出区，所述位线还位于所述位线引出区中；所述浅沟槽隔离结构包括位线浅沟槽隔离结构，所述位线浅沟槽隔离结构位于所述位线引出区远离所述阵列区的一侧。
在一些实施例中，沿所述第一方向上，所述位线引出区的宽度与所述隔断区的宽度的比值为0.7～0.95。
在一些实施例中，所述引出区包括与所述阵列区沿所述第二方向排列的字线引出区，所述字线还位于所述字线引出区中；所述浅沟槽隔离结构包括字线浅沟槽隔离结构，所述字 线浅沟槽隔离结构位于所述字线引出区远离所述阵列区的一侧。
在一些实施例中，沿所述第二方向上，所述字线引出区的宽度与所述隔断区的宽度的比值为0.7～0.95。
在一些实施例中，沿所述引出区指向所述浅沟槽隔离结构的方向上，所述引出区的宽度的范围为0.05um～0.15um。
在一些实施例中，所述半导体结构还包括：基底，所述位线位于所述基底上，所述阵列区中还包括：位于所述位线远离所述基底一侧的半导体柱，多个所述半导体柱沿所述第一方向和/或所述第二方向间隔排布，其中，沿所述基底指向所述位线的方向上，所述半导体柱包括底部、中部以及顶部，所述位线与沿所述第一方向排列的所述底部接触连接，所述字线环绕沿所述第二方向排列的所述中部。
在一些实施例中，所述位线包括：外围层和导电块，所述外围层围成多个沿所述第一方向排列的空腔，所述导电块填充满所述空腔，位于所述阵列区的所述导电块的中心区域与沿所述第一方向排列的相邻所述半导体柱间的间隔对应。
在一些实施例中，所述外围层的材料包括金属半导体化合物，所述导电块的材料包括钨、氮化钛或铜等导电材料。
在一些实施例中，沿所述基底指向所述位线的方向上，所述半导体柱的顶面不高于所述浅沟槽隔离结构的顶面。
在一些实施例中，沿所述基底指向所述位线的方向上，所述浅沟槽隔离结构包括与所述位线接触连接的第一区以及位于所述第一区上的第二区，沿所述第一方向上，所述第一区的宽度大于等于所述第二区的宽度。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，包括：提供基底，所述基底包括阵列区和包围所述阵列区的隔断区；形成沿第一方向延伸的位线以及沿第二方向延伸的字线，其中，沿第一方向延伸的部分所述位线位于所述阵列区中，沿第二方向延伸的部分所述字线也位于所述阵列区中，所述隔断区包括与所述阵列区至少一侧相邻的引出区，所述字线和/或所述位线还位于所述引出区中；在所述隔断区的所述基底上形成浅沟槽隔离结构，所述浅沟槽隔离结构位于所述引出区远离所述阵列区的一侧。
在一些实施例中，形成所述位线步骤包括：提供基底；对所述基底进行图形化处理，以形成沿所述第一方向延伸的初始位线，以及形成位于所述初始位线上且沿所述第一方向和/或所述第二方向间隔排布的多个半导体柱；以相邻所述半导体柱间的间隔和所述半导体柱和所述浅沟槽隔离结构间的间隔为开口刻蚀所述初始位线，以形成多个第一空腔，部分所述第一空腔位于所述引出区中；对所述第一空腔暴露出的侧壁进行金属化处理，以形成外围层，所述外围层围成多个沿所述第一方向排列的第二空腔；形成导电块，所述导电块填充满所述第二空腔，所述外围层和所述导电块构成所述位线。
在一些实施例中，形成所述浅沟槽隔离结构的步骤包括：在所述引出区远离所述阵列区的一侧的所述隔断区的所述基底上形成初始浅沟槽隔离结构；刻蚀所述初始浅沟槽隔离结构，以形成第二区，剩余所述初始浅沟槽隔离结构为第一区，其中，沿所述基底指向所述初始位线的方向上，所述第一区顶面不低于所述初始位线顶面。
在一些实施例中，形成所述导电块的步骤包括：形成填充满相邻所述半导体柱间的间隔、所述半导体柱与所述浅沟槽隔离结构间的间隔以及所述第二空腔的初始导电层；以所述第一区的顶面为刻蚀停止层，刻蚀所述初始导电层，以形成所述导电块。
本公开实施例提供的技术方案至少具有以下优点：
字线和/或位线位于引出区中，可以理解的是，用于将字线和/或位线从阵列区中引出的导电层可以为字线和/或位线本身，即将字线从阵列区中引出的导电层与位于阵列区中的字线为一体成型结构，如此有利于降低将字线从阵列区中引出的导电层与位于阵列区中字线之间的接触电阻，有利于提高字线整体的导电性能；或者，将位线从阵列区中引出的导电层与位于阵列区中的位线为一体成型结构，如此有利于降低将位线从阵列区中引出的导电层与位于阵列区中位线之间的接触电阻，有利于提高位线整体的导电性能。此外，在隔断区中还设置有浅沟槽隔离结构，利用浅沟槽隔离结构和阵列区两者设计引出区的尺寸，有利于降低引出区在半导体结构中的布局面积。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的一种俯视结构示意图；
图2为图1所示半导体结构沿第一截面方向AA1的一种剖面示意图；
图3为图1所示半导体结构沿第二截面方向BB1的一种剖面示意图；
图4至图8为本公开另一实施例提供的半导体结构的制造方法各步骤对应的局部剖面示意图。
具体实施方式
半导体结构中，阵列区的图案密度高于隔断区的图案密度，可以理解的是，此处的图案指的是半导体结构中用于实现一些电学功能的功能结构。目前在制备位线或字线的工艺步 骤中，会先形成初始位线或初始字线，初始位线或初始字线不仅会位于阵列区，还会位于隔断区，后续对初始位线或初始字线进行刻蚀，以形成位线或字线。然而，在刻蚀初始位线或初始字线的步骤中，由于阵列区的图案密度高于隔断区的图案密度，使得刻蚀工艺对位于阵列区的初始位线或初始字线的刻蚀速率低于对位于隔断区的初始位线或初始字线的刻蚀速率。如此，在阵列区形成位线或字线时，隔断区的初始位线或初始字线被过刻蚀，导致阵列区和隔断区中的位线之间的导电性能差异大，或导致阵列区和隔断区中的字线之间的导电性能差异大，或者隔断区的初始位线或初始字线被完全去除，从而需要额外在隔断区再形成用于引出位线或字线的导电层。因此，位线与导电层之间不为一体成型结构，容易增大为位线与导电层之间的接触电阻，降低位线与导电层整体的导电性能，或者，字线与导电层之间不为一体成型结构，容易增大为字线与导电层之间的接触电阻，降低字线与导电层整体的导电性能。
可见，为了将位于阵列区的位线或字线引出，以及平衡阵列区和隔断区中的位线或字线之间导电性能的差异，需要先制备位于阵列区的位线或字线，然后制备将位线或字线从阵列区中引出的导电层，不仅不利于简化半导体结构的制备工艺，还容易降低位线或字线与导电层整体的导电性能。
本公开实施提供一种半导体结构及其制造方法，半导体结构中，字线和/或位线位于引出区中，可以理解的是，用于将字线和/或位线从阵列区中引出的导电层可以为字线和/或位线本身，即将字线从阵列区中引出的导电层与位于阵列区中的字线为一体成型结构，如此有利于降低将字线从阵列区中引出的导电层与位于阵列区中字线之间的接触电阻，有利于提高字线整体的导电性能；或者，将位线从阵列区中引出的导电层与位于阵列区中的位线为一体成型结构，如此有利于降低将位线从阵列区中引出的导电层与位于阵列区中位线之间的接触电阻，有利于提高位线整体的导电性能。此外，在隔断区中还设置有浅沟槽隔离结构，利用浅沟槽隔离结构和阵列区两者设计引出区的尺寸，有利于降低引出区在半导体结构中的布局面积，而且，在隔断区设置浅沟槽隔离结构，有利于增大隔断区的图案密度，从而有利于缩小阵列区的图案密度与隔断区的图案密度之间的差异，在制备字线或位线的步骤中，有利于使得字线或位线既位于阵列区，也位于隔断区，有利于避免隔断区的字线或位线被过刻蚀，从而有利于降低阵列区和隔断区中位线之间导电性能的差异，或者降低阵列区和隔断区中字线之间导电性能的差异。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种半导体结构，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。图1为本公开实施例提供的半导体结构的一种俯视结构示意图；图2 为图1所示半导体结构沿第一截面方向AA1的一种剖面示意图；图3为图1所示半导体结构沿第二截面方向BB1的一种剖面示意图。需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，本实施例中的图1至图3均为半导体结构的局部结构示意图。
参考图1至图3，半导体结构包括：阵列区100和包围阵列区100的隔断区101；阵列区100中包括沿第一方向X延伸的部分位线102以及沿第二方向Y延伸的部分字线103；隔断区101中包括与阵列区100至少一侧相邻的引出区111，字线103和/或位线102还位于引出区111中；隔断区101中包括浅沟槽隔离结构104，浅沟槽隔离结构104位于引出区111远离阵列区100的一侧。
其中，字线103和/或位线102既位于阵列区100中，又位于引出区111中，可以理解的是，用于将字线103和/或位线102从阵列区100中引出的导电层即为字线103和/或位线102本身，即将字线103从阵列区100中引出的导电层与位于阵列区100中的字线103为一体成型结构，如此有利于降低将字线103从阵列区100中引出的导电层与位于阵列区100中字线103之间的接触电阻，有利于提高字线103整体的导电性能；或者，将位线102从阵列区100中引出的导电层与位于阵列区100中的位线102为一体成型结构，如此有利于降低将位线102从阵列区100中引出的导电层与位于阵列区100中位线102之间的接触电阻，有利于提高位线102整体的导电性能。
此外，在隔断区101中还设置有浅沟槽隔离结构104，利用浅沟槽隔离结构104和阵列区100两者设计引出区111的尺寸，有利于降低引出区111在半导体结构中的布局面积，而且，在隔断区101设置浅沟槽隔离结构104，有利于增大隔断区101的图案密度，从而有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异，在制备字线103或位线102的步骤中，有利于使得字线103或位线102既位于阵列区100，也位于隔断区101，无需额外在隔断区101中制备用于将阵列区100的字线103或位线102引出的导电层，而且，有利于避免隔断区101的字线103或位线102被过刻蚀，从而有利于降低阵列区100和隔断区101中位线102之间导电性能的差异，或者降低阵列区100和隔断区101中字线103之间导电性能的差异。
在一些实施例中，半导体结构还包括外围区(图中未示出)，隔断区101位于阵列区100和外围区之间，用于将阵列区100和外围区间隔开。
以下将结合附图对本公开一实施例提供的半导体结构进行更为详细的说明。
在一些实施例中，参考图2，引出区111可以包括与阵列区100沿第一方向X排列的位线引出区121，位线102还位于位线引出区121中；浅沟槽隔离结构104可以包括位线浅沟槽隔离结构114，位线浅沟槽隔离结构114位于位线引出区121远离阵列区100的一侧。如此，位线102既位于阵列区100中，又位于位线引出区121中，可以理解的是，即位线102自身可以实现将阵列区100的位线102引出至隔断区101中的功能，阵列区100的位线102 和隔断区101的位线102为一体成型结构，相较于位线仅位于阵列区，导电层位于隔断区，本公开一实施例有利于降低阵列区100的位线102和隔断区101的位线102之间的接触电阻，还有利于降低位线102整体的内部缺陷密度。
在一些实施例中，继续参考图2，沿方向Z上，阵列区100的位线102的厚度与隔断区101中的位线102的厚度的比值为0.9～1.1。可以理解的是，阵列区100的位线102的厚度与隔断区101中的位线102的厚度基本相同，有利于降低阵列区100和隔断区101中位线102之间导电性能的差异，从而有利于提高位线102整体的导电性能。
在一些实施例中，沿第一方向X上，位线引出区121的宽度与隔断区101的宽度的比值可以为0.7～0.95。如此，控制位线引出区121在第一方向X上的长度，在使得位线102还位于位线引出区121中的同时，有利于避免位线102在第一方向X上的长度过长，且有利于降低位线引出区121在半导体结构中占据的布局面积，有利于在提高半导体结构的电学性能的同时，提高半导体结构的集成密度。在一个例子中，位线引出区121的宽度与隔断区101的宽度的比值可以为0.91。
在另一些实施例中，参考图3，引出区111可以包括与阵列区100沿第二方向Y排列的字线引出区131，字线103还位于字线引出区131中；浅沟槽隔离结构104可以包括字线浅沟槽隔离结构124，字线浅沟槽隔离结构124位于字线引出区131远离阵列区100的一侧。如此，字线103既位于阵列区100中，又位于字线引出区131中，可以理解的是，即字线103自身可以实现将阵列区100的字线103引出至隔断区101中的功能，阵列区100的字线103和隔断区101的字线103为一体成型结构，相较于字线仅位于阵列区，导电层位于隔断区，本公开一实施例有利于降低阵列区100的字线103和隔断区101的字线103之间的接触电阻，还有利于降低字线103整体的内部缺陷密度。
在一些实施例中，继续参考图3，沿方向Z上，阵列区100的字线103的厚度与隔断区101中的字线103的厚度的比值为0.9～1.1。可以理解的是，阵列区100的字线103的厚度与隔断区101中的字线103的厚度基本相同，有利于降低阵列区100和隔断区101中字线103之间导电性能的差异，从而有利于提高字线103整体的导电性能。
在一些实施例中，沿第二方向Y上，字线引出区131的宽度与隔断区101的宽度的比值为0.7～0.95。如此，控制字线引出区131在第二方向Y上的长度，在使得字线103还位于字线引出区131中的同时，有利于避免字线103在第二方向Y上的长度过长，且有利于降低字线引出区131在半导体结构中占据的布局面积，有利于在提高半导体结构的电学性能的同时，提高半导体结构的集成密度。在一个例子中，字线引出区131的宽度与隔断区101的宽度的比值可以为0.91。
需要说明的是，结合参考图1至图3，在一些实施例中，引出区111可以仅包含为位线引出区121，即位线102既位于阵列区100也位于隔断区101中，对字线103是否还位于 隔断区101中不做限制；在另一些实施例中，引出区111可以仅包含为字线引出区131，即字线103既位于阵列区100也位于隔断区101中，对位线102是否还位于隔断区101中不做限制；在又一些实施例中，引出区111可以同时包含为位线引出区121和字线引出区131，即位线102既位于阵列区100也位于隔断区101中，且字线103既位于阵列区100也位于隔断区101中。
在上述实施例中，沿引出区111指向浅沟槽隔离结构104的方向上，引出区111的宽度的范围可以为0.05um～0.15um。
需要说明是，此处的引出区111是指单个引出区111，例如位线引出区121或者字线引出区131。可以理解的是，参考图2，沿引出区111指向浅沟槽隔离结构104的方向上指的是：沿位线引出区121指向位线浅沟槽隔离结构114的方向，即第一方向X，位线引出区121的宽度的范围可以为0.05um～0.15um；参考图3，沿引出区111指向浅沟槽隔离结构104的方向上指的是：沿字线引出区131指向字线浅沟槽隔离结构124的方向，即第二方向Y，字线引出区131的宽度的范围可以为0.05um～0.15um。
在一个例子中，沿第一方向X上，位线引出区121的宽度可以为0.105um，隔断区101的宽度可以为0.115um。在另一个例子中，沿第二方向Y上，字线引出区131的宽度可以为0.105um，隔断区101的宽度可以为0.115um。
在一些实施例中，参考图2和图3，半导体结构还可以包括：基底105，位线102位于基底105上，阵列区100中还可以包括：位于位线102远离基底105一侧的半导体柱106，多个半导体柱106沿第一方向X和/或第二方向Y间隔排布，其中，沿基底105指向位线102的方向Z上，半导体柱106可以包括底部116、中部126以及顶部136，一位线102与沿第一方向X排列的底部116接触连接，一字线103环绕沿第二方向Y排列的中部126。
可以理解的是，在一个例子中，多个半导体柱106可以沿第一方向X和第二方向Y阵列排布，多个沿第一方向X延伸的位线102沿第二方向Y间隔排布，多个沿第二方向Y延伸的字线103沿第一方向X间隔排布。
在一些实施例中，半导体结构还可以包括：栅介质层107，栅介质层107至少位于中部126沿基底105指向位线102的方向Z上延伸的侧壁。可以理解的是，字线103、栅介质层107以及半导体柱106共同构成垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构，其中，底部116作为GAA晶体管的源极或漏极中的一者，顶部136作为GAA晶体管的源极或漏极中的另一者，中部126作为GAA晶体管的沟道区。
其中，基底105上具有垂直的GAA晶体管，且位线102位于基底105与GAA晶体管之间，因而可以构成3D堆叠的半导体结构，有利于提高半导体结构的集成密度。
在一些实施例中，字线103的材料可以为钨、氮化钛或铜等导电材料中的至少一种，栅介质层107的材料可以为氧化硅或氮化硅等绝缘材料中的至少一种。
在一些实施例中，基底105、位线102和半导体柱106具有相同的半导体元素，有利于改善半导体柱106与位线102之间的界面态缺陷，改善半导体结构的性能。
其中，半导体元素可以包括硅、碳、锗、砷、镓、铟中的至少一种。在一个例子中，位线102与半导体柱106均包括硅元素。在其他例子中，位线与半导体柱可以均包括锗元素，或者，位线与半导体柱均包括硅元素和锗元素，或者，位线与半导体柱均包括硅元素和碳元素，或者，位线与半导体柱均包括砷元素和镓元素，或者，位线与半导体柱均包括镓元素和铟元素。
在一些实施例中，参考图2和图3，位线102可以包括：外围层112和导电块122，外围层112至少围成多个沿第一方向X排列的空腔132，导电块122填充满空腔132，位于阵列区100的导电块122的中心区域与沿第一方向X排列的相邻半导体柱106间的间隔对应。
可以理解的是，外围层112可以作为底部116和导电块122之间的过渡层，以避免导电块122与底部116直接接触时产生较大的接触电阻，有利于降低位线102整体与底部116之间的接触电阻，以提高半导体结构的电学性能。
需要说明的是，阵列区100的外围层112围成多个沿第一方向X排列的空腔132，且隔断区101的外围层112围成凹槽182，导电块122不仅填充满空腔132，还填充满凹槽182，有利于降低阵列区100和隔断区101的位线102在方向Z上厚度的差异，从而有利于降低阵列区100和隔断区101的位线102之间导电性能的差异，以提高位线102整体的导电性能。
在一些实施例中，外围层112的材料可以包括金属半导体化合物，导电块122的材料可以包括钨、氮化钛或铜等导电材料中的至少一种。
可以理解的是，金属半导体化合物相较于未金属化的半导体材料而言，具有相对较小的电阻率，因此，相较于半导体柱106而言，外围层112的电阻率更小，从而有利于降低外围层112的电阻，且降低外围层112与底部116之间的接触电阻，进一步改善半导体结构的电学性能。此外，外围层112与半导体柱106中包括相同的半导体元素，有利于改善半导体柱106与位线102之间的界面态缺陷，降低多数载流子在半导体柱106和位线102之间传输时缺陷捕获消耗的概率，从而有利于提高外围层112与半导体柱106之间多数载流子的传输效率。
而且，位线102由与半导体柱106直接接触的外围层112和位于外围层112围成的空腔132中的导电块122共同组成，一方面，有利于通过外围层112提高位线102与半导体柱106之间多数载流子的传输效率，另一方面，有利于通过导电块122提高位线102整体的导电性能。
在一些实施例中，以半导体元素为硅为例，金属半导体化合物包括硅化钴、硅化镍、硅化钼、硅化钛、硅化钨、硅化钽或者硅化铂中的至少一种。
在一些实施例中，半导体柱106中掺杂有N型离子或P型离子，其中，N型离子为 砷离子、磷离子或者锑离子中的至少一种；P型离子为硼离子、铟离子或者镓离子中的至少一种。
在一些实施例中，参考图2和图3，沿基底105指向位线102的方向Z上，半导体柱106的顶面不高于浅沟槽隔离结构104的顶面。
可以理解的是，在隔断区101设置浅沟槽隔离结构104，有利于增大隔断区101的图案密度，从而有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异。设置半导体柱106的顶面不高于浅沟槽隔离结构104的顶面，有利于使得半导体柱106整体与浅沟槽隔离结构104之间均形成凹槽，后续在相邻半导体柱106之间以及凹糟中形成其他结构需要采用刻蚀工艺时，有利于降低刻蚀工艺在阵列区100的刻蚀速率与在隔断区101的刻蚀速率的差异，以形成尺寸精度更高的其他结构。
在一些实施例中，参考图2，沿基底105指向位线102的方向Z上，浅沟槽隔离结构104(参考图1)可以包括与位线102接触连接的第一区134以及位于第一区134上的第二区144，沿第一方向X上，第一区134的宽度大于等于第二区144的宽度。可以理解的是，第一区134的宽度大于等于第二区144的宽度，有利于避免后续用于形成位线102的区域被浅沟槽隔离结构104遮盖，而且沿方向Z上，第一区134的顶面可以作为采用刻蚀工艺形成位线102时的刻蚀停止层。
需要说明的是，参考图3，在形成字线103的过程中，无需字线浅沟槽隔离结构124的部分区域作为刻蚀停止层，则字线浅沟槽隔离结构124可以不被划分为在第二方向Y上宽度不同的两个部分。
在一些实施例中，半导体结构还可以包括：掩膜层108，用于保护半导体柱106的顶部136。需要说明的是，图2和图3中以栅介质层107覆盖半导体柱106与掩膜层108沿方向Z上延伸的侧壁，且栅介质层107还覆盖浅沟槽隔离结构104沿方向Z上延伸的侧壁为示例，在实际应用中，栅介质层107可以仅覆盖中部126沿方向Z上延伸的侧壁。
在一些实施例中，导体结构还可以包括：介质层109，位于位线102和字线103之间，且介质层109环绕半导体柱106中底部116沿方向Z上的侧壁。在一个例子中，介质层109于底部116之间具有栅介质层107；在另一个例子中，介质层109可以与底部116沿方向Z上的侧壁直接接触。
在一些实施例中，半导体结构还可以包括：电容接触层(图中未示出)，以及位于引出区111中的导电插塞(图中未示出)，导电插塞与位于引出区111的位线102和/或字线103接触连接，导电插塞用于将位线102和/或字线103沿方向Z上引出。需要说明的是，在去除位于半导体柱106的顶部136的掩膜层108之后，在顶部136上形成电容接触层。
综上所述，字线103和/或位线102既位于阵列区100中，又位于引出区111中，可以理解的是，用于将字线103和/或位线102从阵列区100中引出的导电层即为字线103和/ 或位线102本身，如此，有利于降低将字线103从阵列区100中引出的导电层与位于阵列区100中字线103之间的接触电阻，有利于提高字线103整体的导电性能；或者，有利于降低将位线102从阵列区100中引出的导电层与位于阵列区100中位线102之间的接触电阻，有利于提高位线102整体的导电性能。此外，利用浅沟槽隔离结构104和阵列区100两者设计引出区111的尺寸，有利于降低引出区111在半导体结构中的布局面积，而且，有利于增大隔断区101的图案密度，从而有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异，在制备字线103或位线102的步骤中，有利于使得字线103或位线102既位于阵列区100，也位于隔断区101，无需额外在隔断区101中制备用于将阵列区100的字线103或位线102引出的导电层，而且，有利于降低阵列区100和隔断区101中位线102之间导电性能的差异，或者降低阵列区100和隔断区101中字线103之间导电性能的差异。
本公开另一实施例还提供一种半导体结构的制造方法，用于制备前述实施例提供的半导体结构。以下将结合图1至图8对本公开另一实施例提供的半导体结构的制造方法进行详细说明。图4至图8为本公开另一实施例提供的半导体结构的制造方法各步骤对应的局部剖面示意图。需要说明的是，与前述实施例相同或相应的部分在此不再赘述。
参考图2至图8，半导体结构的制造方法包括：提供基底105，基底105包括阵列区100和包围阵列区100的隔断区101；形成沿第一方向X延伸的位线102以及沿第二方向Y延伸的字线103，其中，沿第一方向X延伸的部分位线102位于阵列区100中，沿第二方向Y延伸的部分字线103也位于阵列区100中，隔断区101包括与阵列区100至少一侧相邻的引出区111，字线103和/或位线102还位于引出区111中；在隔断区101的基底105上形成浅沟槽隔离结构104，浅沟槽隔离结构104位于引出区111远离阵列区100的一侧。
可以理解的是，在形成为位线102和字线103之前，先在隔断区101中形成浅沟槽隔离结构104，如此，有利于利用浅沟槽隔离结构104和阵列区100两者预留出引出区111的尺寸，有利于降低引出区111在半导体结构中的布局面积。而且，在隔断区101中先形成浅沟槽隔离结构104，有利于增大隔断区101的图案密度，从而有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异，在制备字线103或位线102的步骤中，有利于使得字线103或位线102既位于阵列区100，也位于隔断区101，无需额外在隔断区101中制备用于将阵列区100的字线103或位线102引出的导电层，从而在提高形成的字线103或位线102的导电性能的同时，有利于简化形成字线103或位线102的工艺步骤，而且，有利于降低阵列区100和隔断区101中位线102之间导电性能的差异，或者降低阵列区100和隔断区101中字线103之间导电性能的差异。
在一些实施例中，形成位线102可以包括如下步骤：
参考图4，提供基底105；对基底105进行图形化处理，以形成沿第一方向X延伸的初始位线142，以及形成位于初始位线142上且沿第一方向X和/或第二方向Y间隔排布的多个半导体柱106。
可以理解的是，初始位线142与半导体柱106均是由对基底105进行图形化处理而形成的，剩余未被图形化处理的基底105用于支撑初始位线142以及半导体柱106，以及支撑后续在基底105上形成的其他结构，即基底105、初始位线142和半导体柱106具有相同的半导体元素，则半导体柱106与初始位线142可以利用同一膜层结构形成，该膜层结构由半导体元素构成，使得半导体柱106与初始位线142为一体结构，从而改善半导体柱106与初始位线142之间的界面态缺陷。
需要说明的是，参考图4，在形成初始位线142和半导体柱106之前，即可对隔断区101中的部分基底105进行刻蚀，以形成浅沟槽隔离结构104；或者，在形成初始位线142和半导体柱106之后，对隔断区101中的部分基底105进行刻蚀。可以理解的是，本公开另一实施例提供的制造方法中，对形成初始位线142和半导体柱106以及形成浅沟槽隔离结构104的顺序不做限制。
在一些实施例中，形成浅沟槽隔离结构104的步骤可以包括：在引出区111远离阵列区100的一侧的隔断区101的基底105上形成初始浅沟槽隔离结构(图中未示出)；参考图4，刻蚀初始浅沟槽隔离结构，以形成第二区144，剩余初始浅沟槽隔离结构为第一区134，其中，沿基底105指向初始位线142的方向Z上，第一区134顶面不低于初始位线142顶面。
如此，在后续采用刻蚀工艺形成位线102(参考图2)的步骤中，可以将第一区134的顶面作为刻蚀停止层，有利于提高形成的位线102的尺寸精度。
以下通过三种实施例中对浅沟槽隔离结构104的形成方法进行详细说明。
在一个例子中，引出区111可以包括与阵列区100沿第一方向X排列的位线引出区121，形成浅沟槽隔离结构104的步骤可以包括：参考图2，在位线引出区121远离阵列区100的隔断区101中形成位线浅沟槽隔离结构114，而且，沿基底105指向位线102的方向Z上，位线浅沟槽隔离结构114可以包括与位线102接触连接的第一区134以及位于第一区134上的第二区144，沿第一方向X上，第一区134的宽度大于等于第二区144的宽度。
在另一个例子中，引出区111可以包括与阵列区100沿第二方向Y排列的字线引出区131，形成浅沟槽隔离结构104的步骤可以包括：参考图3，在字线引出区131远离阵列区100的隔断区101中形成字线浅沟槽隔离结构124。
在又一个例子中，引出区111可以既包括与阵列区100沿第一方向X排列的位线引出区121，又包括与阵列区100沿第二方向Y排列的字线引出区131，则形成浅沟槽隔离结构104的步骤可以包括：在位线引出区121远离阵列区100的隔断区101中形成位线浅沟槽隔离结构114，且在字线引出区131远离阵列区100的隔断区101中形成字线浅沟槽隔离结构124。
在一些实施例中，在形成初始位线142和半导体柱106之后，在形成位线102之前，半导体结构的制造方法还可以包括：形成掩膜层108，用于保护半导体柱106的顶部136。可 以理解的是，后续采用刻蚀工艺形成位线102(参考图2)以及字线103(参考图3)时，掩膜层108可以用于保护半导体柱106，避免半导体柱106的顶部136被刻蚀。
在一些实施例中，在形成初始位线142和半导体柱106之后，在形成位线102之前，半导体结构的制造方法还可以包括：形成栅介质层107，栅介质层107覆盖半导体柱106与掩膜层108沿方向Z上延伸的侧壁，且栅介质层107还覆盖浅沟槽隔离结构104沿方向Z上延伸的侧壁。如此，后续采用刻蚀工艺形成位线102(参考图2)以及字线103(参考图3)时，栅介质层107一方面有利于保护半导体柱106沿方向Z上的侧壁，进一步避免半导体柱106被刻蚀，另一方面有利于保护浅沟槽隔离结构104，避免浅沟槽隔离结构104被刻蚀。
需要说明的是，在实际应用中，在形成位线102之后，可以对刻蚀部分栅介质层107，使得栅介质层107仅覆盖中部126沿方向Z上延伸的侧壁即可；或者，在形成位线102之后，将被刻蚀工艺影响的栅介质层107去除，然后形成一层新的栅介质层107，新的栅介质层107至少覆盖中部126沿方向Z上延伸的侧壁，可以理解的是，新的栅介质层107没有受刻蚀工艺的影响，致密性更好，有利于保证新的栅介质层107自身良好的致密性和绝缘性能。
结合参考图4和图5，以相邻半导体柱106间的间隔和半导体柱106和浅沟槽隔离结构104间的间隔为开口刻蚀初始位线142，以形成多个第一空腔152，部分第一空腔152位于引出区111中。
可以理解的是，由于阵列区100在具有多个阵列排布的半导体柱106，阵列区100的图案密度高于隔断区101的图案密度，因而，在刻蚀初始位线142时，在阵列区100中形成的第一空腔152与在隔断区101中形成的第一空腔152不同。具体的，在阵列区100中形成的第一空腔152在垂直于第二方向Y上的截面形状为碗装，有利于后续形成多个导电块122(参考图2)，在隔断区101中形成的第一空腔152为凹槽，大部分区域均暴露在外，有利于后续在隔断区101形成导电块122。
结合参考图5和图6，对第一空腔152暴露出的侧壁进行金属化处理，以形成外围层112，外围层112围成多个沿第一方向X排列的第二空腔162。
在一些实施例中，对第一空腔152暴露出的侧壁进行金属化处理的步骤可以包括：在第一空腔152暴露出的侧壁上形成金属层(图中未示出)，金属层为后续形成外围层112提供金属元素；进行退火处理，以将至少部分厚度的初始位线142转化为外围层112；在形成外围层112之后，去除剩余的金属层。其中，金属层的材料包括钴、镍、钼、钛、钨、钽或者铂中的至少一种。
需要说明的是，外围层112围成多个沿第一方向X排列的第二空腔162，第二空腔162用于后续形成导电块122，且不仅阵列区100中具有第二空腔162，隔断区101中也具有第二空腔162。需要说明的是，在阵列区100中形成的第二空腔162与在隔断区101中形成的第二空腔162不同。具体的，在阵列区100中形成的第二空腔162在垂直于第二方向Y上 的截面形状为碗装，在隔断区101中形成的第二空腔162为凹槽，大部分区域均暴露在外。
参考图7、图8和图2，形成导电块122，导电块122填充满第二空腔162，外围层112和导电块122构成位线102。
在一些实施例中，形成导电块122的可以包括如下步骤：
参考图7和图8，形成填充满相邻半导体柱106间的间隔、半导体柱106与浅沟槽隔离结构104间的间隔以及第二空腔162的初始导电层172。
可以理解的是，参考图7，由于阵列区100中，相邻半导体柱106间的间隔的尺寸较小，隔断区101中，半导体柱106与浅沟槽隔离结构104间的间隔的尺寸较大，即位线引出区121的开口较大，使得形成的初始导电层172在位线引出区121处具有凹槽。形成初始导电层172的步骤可以包括：参考图7，先形成填充满相邻半导体柱106间的间隔、半导体柱106与浅沟槽隔离结构104间的间隔以及第二空腔162的初始导电层172；参考图8，对初始导电层172进行化学机械平坦化处理至消除初始导电层172在位线引出区121处的凹槽。
结合参考图8和图2，以第一区134的顶面为刻蚀停止层，刻蚀初始导电层172，以形成导电块122。
可以理解的是，相较于在隔断区101没有形成浅沟槽隔离结构104(参考图1)的技术方案，本公开另一实施例提供的制造方法中，先在隔断区101形成浅沟槽隔离结构104，可以降低位线引出区121在第一方向X上的长度，有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异，在制备位线102，即刻蚀初始导电层172以形成导电块122的步骤中，有利于降低刻蚀工艺对阵列区100的初始导电层172的刻蚀速率和位线引出区121的初始导电层172的刻蚀速率的差异，有利于使得刻蚀形成的导电块122既位于阵列区100，也位于位线引出区121，无需额外在位线引出区121中制备用于将阵列区100的位线102引出的导电层。
在一些实施例中，结合参考图2和图3，在形成位线102之后，半导体结构的制造方法还可以包括如下步骤：
形成环绕半导体柱106中底部116沿方向Z上的侧壁的介质层109，且介质层109填充满相邻底部116之间的间隔，以及填充满底部116与浅沟槽隔离结构104(参考图1)之间的间隔。可以理解的是，介质层109用于实现位线102与后续形成的字线103之间的电隔离。
参考图3，形成沿第二方向Y延伸的字线103，且字线103环绕沿第二方向Y间隔排列的多个中部126沿方向Z上延伸的侧壁，而且，字线103与中部126之间具有栅介质层107。
在一些实施例中，形成字线103的步骤包括：形成初始字线(图中未示出)，初始字线填充满剩余半导体柱106相邻之间的间隔，以及半导体柱106与浅沟槽隔离结构104之间的间隔，且初始位线位于掩膜层108的顶面上；刻蚀初始字线，以形成字线103。
可以理解的是，相较于在隔断区101没有形成浅沟槽隔离结构104(参考图1)的技术方案，本公开另一实施例提供的制造方法中，先在隔断区101形成浅沟槽隔离结构104，可以降低字线引出区131在第二方向Y上的长度，有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异，在制备字线103，即刻蚀初始字线以形成字线103的步骤中，有利于降低刻蚀工艺对阵列区100的初始字线的刻蚀速率和字线引出区131的初始字线的刻蚀速率的差异，从而有利于形成的字线103既位于阵列区100，也位于字线引出区131，无需额外在字线引出区131中制备用于将阵列区100的字线103引出的导电层。
此外，字线103、栅介质层107以及半导体柱106共同构成垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构，其中，底部116作为GAA晶体管的源极或漏极中的一者，顶部136作为GAA晶体管的源极或漏极中的另一者，中部126作为GAA晶体管的沟道区。
在一些实施例中，在形成位线102之后，半导体结构的制造方法还可以包括：形成导电插塞，导电插塞与位于位线引出区121的位线102接触连接，导电插塞用于将位线102沿方向Z上引出。
在一些实施例中，在形成字线103之后，半导体结构的制造方法还可以包括：形成导电插塞，导电插塞与位于字线引出区131的字线103接触连接，导电插塞用于将字线103沿方向Z上引出。
在一些实施例中，在形成位线102和字线103之后，导体结构的制造方法还可以包括：去除位于半导体柱106的顶部136的掩膜层108，在暴露出的顶部136上形成电容接触层。
综上所述，在隔断区101中形成浅沟槽隔离结构104，如此，有利于利用浅沟槽隔离结构104和阵列区100两者预留出引出区111的尺寸，有利于降低引出区111在半导体结构中的布局面积。而且，在隔断区101中先形成浅沟槽隔离结构104，有利于增大隔断区101的图案密度，从而有利于缩小阵列区100的图案密度与隔断区101的图案密度之间的差异，在制备字线103或位线102的步骤中，有利于使得字线103或位线102既位于阵列区100，也位于隔断区101，无需额外在隔断区101中制备用于将阵列区100的字线103或位线102引出的导电层，从而在提高形成的字线103或位线102的导电性能的同时，有利于简化形成字线103或位线102的工艺步骤，而且，有利于避免隔断区101的字线103或位线102被过刻蚀，从而有利于降低阵列区100和隔断区101中位线102之间导电性能的差异，或者降低阵列区100和隔断区101中字线103之间导电性能的差异。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种半导体结构，包括：
    阵列区和包围所述阵列区的隔断区；
    所述阵列区中包括沿第一方向延伸的部分位线以及沿第二方向延伸的部分字线；
    所述隔断区中包括与所述阵列区至少一侧相邻的引出区，所述字线和/或所述位线还位于所述引出区中；
    所述隔断区中包括浅沟槽隔离结构，所述浅沟槽隔离结构位于所述引出区远离所述阵列区的一侧。
  2. 如权利要求1所述的半导体结构，其中，所述引出区包括与所述阵列区沿所述第一方向排列的位线引出区，所述位线还位于所述位线引出区中；所述浅沟槽隔离结构包括位线浅沟槽隔离结构，所述位线浅沟槽隔离结构位于所述位线引出区远离所述阵列区的一侧。
  3. 如权利要求2所述的半导体结构，其中，沿所述第一方向上，所述位线引出区的宽度与所述隔断区的宽度的比值为0.7～0.95。
  4. 如权利要求1或2所述的半导体结构，其中，所述引出区包括与所述阵列区沿所述第二方向排列的字线引出区，所述字线还位于所述字线引出区中；所述浅沟槽隔离结构包括字线浅沟槽隔离结构，所述字线浅沟槽隔离结构位于所述字线引出区远离所述阵列区的一侧。
  5. 如权利要求4所述的半导体结构，其中，沿所述第二方向上，所述字线引出区的宽度与所述隔断区的宽度的比值为0.7～0.95。
  6. 如权利要求1所述的半导体结构，其中，沿所述引出区指向所述浅沟槽隔离结构的方向上，所述引出区的宽度的范围为0.05um～0.15um。
  7. 如权利要求1所述的半导体结构，还包括：
    基底，所述位线位于所述基底上；
    所述阵列区中还包括：位于所述位线远离所述基底一侧的半导体柱，多个所述半导体柱沿所述第一方向和/或所述第二方向间隔排布，其中，沿所述基底指向所述位线的方向上，所述半导体柱包括底部、中部以及顶部，所述位线与沿所述第一方向排列的所述底部接触连接，所述字线环绕沿所述第二方向排列的所述中部。
  8. 如权利要求7所述的半导体结构，其中，所述位线包括：外围层和导电块，所述外围层至少围成多个沿所述第一方向排列的空腔，所述导电块填充满所述空腔，位于所述阵列区的所述导电块的中心区域与沿所述第一方向排列的相邻所述半导体柱间的间隔对应。
  9. 如权利要求8所述的半导体结构，其中，所述外围层的材料包括金属半导体化合物，所 述导电块的材料包括钨、氮化钛或铜等导电材料中的至少一种。
  10. 如权利要求7所述的半导体结构，其中，沿所述基底指向所述位线的方向上，所述半导体柱的顶面不高于所述浅沟槽隔离结构的顶面。
  11. 如权利要求10所述的半导体结构，其中，沿所述基底指向所述位线的方向上，所述浅沟槽隔离结构包括与所述位线接触连接的第一区以及位于所述第一区上的第二区，沿所述第一方向上，所述第一区的宽度大于等于所述第二区的宽度。
  12. 一种半导体结构的制造方法，包括：
    提供基底，所述基底包括阵列区和包围所述阵列区的隔断区；
    形成沿第一方向延伸的位线以及沿第二方向延伸的字线，其中，沿第一方向延伸的部分所述位线位于所述阵列区中，沿第二方向延伸的部分所述字线也位于所述阵列区中，所述隔断区包括与所述阵列区至少一侧相邻的引出区，所述字线和/或所述位线还位于所述引出区中；
    在所述隔断区的所述基底上形成浅沟槽隔离结构，所述浅沟槽隔离结构位于所述引出区远离所述阵列区的一侧。
  13. 如权利要求12所述的制造方法，其中，形成所述位线步骤包括：
    提供基底；
    对所述基底进行图形化处理，以形成沿所述第一方向延伸的初始位线，以及形成位于所述初始位线上且沿所述第一方向和/或所述第二方向间隔排布的多个半导体柱；
    以相邻所述半导体柱间的间隔和所述半导体柱和所述浅沟槽隔离结构间的间隔为开口刻蚀所述初始位线，以形成多个第一空腔，部分所述第一空腔位于所述引出区中；
    对所述第一空腔暴露出的侧壁进行金属化处理，以形成外围层，所述外围层围成多个沿所述第一方向排列的第二空腔；
    形成导电块，所述导电块填充满所述第二空腔，所述外围层和所述导电块构成所述位线。
  14. 如权利要求13所述的制造方法，其中，形成所述浅沟槽隔离结构的步骤包括：
    在所述引出区远离所述阵列区的一侧的所述隔断区的所述基底上形成初始浅沟槽隔离结构；
    刻蚀所述初始浅沟槽隔离结构，以形成第二区，剩余所述初始浅沟槽隔离结构为第一区，其中，沿所述基底指向所述初始位线的方向上，所述第一区顶面不低于所述初始位线顶面。
  15. 如权利要求14所述的制造方法，其中，形成所述导电块的步骤包括：
    形成填充满相邻所述半导体柱间的间隔、所述半导体柱与所述浅沟槽隔离结构间的间隔以及所述第二空腔的初始导电层；
    以所述第一区的顶面为刻蚀停止层，刻蚀所述初始导电层，以形成所述导电块。
PCT/CN2022/118568 2022-08-23 2022-09-13 半导体结构及其制造方法 WO2024040642A1 (zh)

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