WO2022205732A1 - 半导体结构和半导体结构的形成方法 - Google Patents

半导体结构和半导体结构的形成方法 Download PDF

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WO2022205732A1
WO2022205732A1 PCT/CN2021/112012 CN2021112012W WO2022205732A1 WO 2022205732 A1 WO2022205732 A1 WO 2022205732A1 CN 2021112012 W CN2021112012 W CN 2021112012W WO 2022205732 A1 WO2022205732 A1 WO 2022205732A1
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layer
substrate
region
conductive
conductive channel
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PCT/CN2021/112012
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English (en)
French (fr)
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张魁
李新
应战
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长鑫存储技术有限公司
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Priority to US17/449,493 priority Critical patent/US20220310596A1/en
Publication of WO2022205732A1 publication Critical patent/WO2022205732A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present application relates to, but is not limited to, a semiconductor structure and a method of forming the semiconductor structure.
  • nFET and pFET cylindrical nanowire (Nanowire) or nanosheet (Nanosheet or Nanoribbon) channels are vertically cross-stacked to form complementary fully surrounding gate cylindrical nanowire or nanosheet field effect transistor (CFET) devices structure.
  • the nFET and pFET share a gate electrode as a signal input terminal, a common drain as a signal output terminal, and the source electrodes are grounded and powered respectively.
  • the device size can be flexibly adjusted to meet different chip performance requirements. While retaining the electrical integrity of the vertically stacked nanowire or nanosheet fully surrounded gate field effect transistor, the chip area is greatly saved, the device driving current is enhanced, and the chip device integration degree is improved.
  • the CFET greatly saves the chip area and improves the integration of the chip device while enhancing the drive current of the device.
  • pFET and nFET share a source or drain connection and the fabrication process is complex and difficult to control
  • the current nFET or pFET uses horizontally placed GAA transistors, and the horizontally placed conductive channel occupies a large amount of space in the horizontal direction. The large area limits the development of CFETs.
  • the first aspect of the embodiments of the present application provides a semiconductor structure, including: a substrate, and a conductive channel structure on the substrate, the conductive channel structure includes first conductive channel layers stacked in sequence, and a conductive buffer layer and a second conductive channel layer; the first conductive channel layer includes a first conductive channel and a first doped region and a second doped region located at both ends of the first conductive channel, wherein the first doped region is close to the first doped region Two conductive channel layers; the second conductive channel layer includes a second conductive channel and a third doping region and a fourth doping region located at both ends of the second conductive channel, wherein the third doping region is close to the first conductive channel layer
  • the conductive buffer layer is used to reduce the electrical interference between the first doping region and the third doping region; the first wire layer, located on the substrate, extends in the first direction, and is connected with the second doping region in the first direction. the impurity region is in contact; the second wire layer extend
  • embodiments of the present application further provide a method for forming a semiconductor structure, including: providing a substrate including a structure region and a wiring region, the substrate comprising a substrate, a first wire layer and an isolation layer, and the first wire layer extending in the first direction; forming a first sacrificial layer on the base of the structure area, forming a peripheral insulating structure on the base of the wiring area; patterning the first sacrificial layer to form a first channel penetrating the first sacrificial layer; forming a second wire layer that fills the first channel and is partially located on the first sacrificial layer, the second wire layer extends into the peripheral insulating structure of the connection area, and the second wire layer extends in the second direction; on the base of the structure area
  • the second sacrificial layer and the protective layer are formed in sequence on the top; the second sacrificial layer is patterned to form through the second sacrificial layer and the second channel, and the projections of the first
  • embodiments of the present application further provide a method for forming a semiconductor structure, including: providing a substrate including a structure region and a wiring region, the substrate comprising a substrate, a first wire layer and an isolation layer, and the first wire layer extending in the first direction; forming a first sacrificial layer on the base of the structure area, forming a peripheral insulating structure on the base of the connection area; forming a second wire layer on the first sacrificial layer, the second wire layer extending to the connection area In the peripheral insulating structure of the wire area, and the second wire layer extends in the second direction; the second sacrificial layer and the protective layer are sequentially formed on the substrate of the structure area; the patterned protective layer, the second sacrificial layer and the first sacrificial layer are , forming an opening and filling the opening to form a conductive channel structure; patterning part of the protective layer until the second sacrificial layer is exposed, removing the second sacrificial
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of a semiconductor structure provided in an AA1 direction according to an embodiment of the present application
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application in a BB1 direction;
  • FIG. 4 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application in the direction of CC1;
  • FIG. 5 is a schematic cross-sectional view of another semiconductor structure in the AA1 direction provided by an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of another BB1 direction of the semiconductor structure provided by an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of another CC1 direction of the semiconductor structure provided by an embodiment of the application.
  • FIG. 8 , FIG. 11 , FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 and FIG. 27 are schematic top-view structural diagrams corresponding to each step in the method for forming a semiconductor structure provided by another embodiment of the present application;
  • FIGS. 9 , 12 , 14 , 16 , 18 , 20 , 22 , 23 and 28 are schematic cross-sectional structural diagrams corresponding to each step in a method for forming a semiconductor structure provided by another embodiment of the present application;
  • FIG. 10 , FIG. 24 , FIG. 25 and FIG. 26 are schematic cross-sectional structural diagrams corresponding to the formation of the first wire layer in the substrate according to the method for forming a semiconductor structure provided by another embodiment of the present application;
  • FIGS. 29 to 34 are schematic cross-sectional structural diagrams corresponding to each step in a method for forming a semiconductor structure according to another embodiment of the present application.
  • An embodiment of the present application provides a semiconductor structure, including: a substrate, and a conductive channel structure on the substrate, the conductive channel structure including a first conductive channel layer, a conductive buffer layer and a second conductive channel stacked in sequence
  • the first conductive channel layer includes a first conductive channel and a first doped region and a second doped region located at both ends of the first conductive channel, wherein the first doped region is close to the second conductive channel layer;
  • the second The conductive channel layer includes a second conductive channel and a third doping region and a fourth doping region located at both ends of the second conductive channel, wherein the third doping region is close to the first conductive channel layer;
  • the conductive buffer layer is used to reduce Electrical interference between the first doped region and the third doped region;
  • the first wire layer, located on the substrate extends in the first direction, and is in contact with the second doped region in the first direction;
  • the second The wire layer extends in the second direction and is in contact with the first
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided in this embodiment
  • FIG. 2 is a schematic cross-sectional view of a semiconductor structure provided in this embodiment in an AA1 direction
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure provided in this embodiment in a BB1 direction
  • 4 is a schematic cross-sectional view of a semiconductor structure provided in this embodiment in the direction of CC1
  • FIG. 5 is a schematic cross-sectional view of another semiconductor structure provided in this embodiment in an AA1 direction
  • FIG. 6 is another semiconductor structure provided by this embodiment
  • FIG. 7 is another schematic cross-sectional view of the semiconductor structure provided in the present embodiment along the CC1 direction.
  • the semiconductor structure including:
  • the number of conductive channel structures 500 located on the substrate may be one or multiple, and the plurality of conductive channel structures 500 are discretely disposed on the substrate (not marked); with reference to FIG.
  • the four conductive channel structures 500 are taken as an example for specific description, which does not constitute a limitation to this embodiment. In other embodiments, the number of conductive channel structures may be 1, 3, 5, etc.; The number of structures 500 can be specifically set according to requirements. In addition, in this embodiment, the four conductive channel structures 500 are arranged in a quadrangular arrangement.
  • one of the first conductive channel layer 501 and the second conductive channel layer 503 is an N-type conductive channel, and the other is a P-type conductive channel.
  • the first conductive channel layer 501 is an N-type conductive channel and the second conductive channel layer 503 is a P-type conductive channel as an example for detailed description, which does not constitute a limitation to this embodiment; in other embodiments , the first conductive channel layer is a P-type conductive channel, and the second conductive channel layer is an N-type conductive channel as an example for detailed description.
  • the first conductive channel layer 501 includes a first conductive channel (not identified) and a first doped region (not identified) and a second doped region (not identified) located at both ends of the first conductive channel (not identified), wherein , the first doped region (not marked) is close to the second conductive channel layer 503 .
  • the first conductive channel layer 501 is formed by in-situ doping or first deposition and then doping, and the material of the first conductive channel layer 501 is an N-type semiconductor formed by doping VA group elements into single crystal silicon Material.
  • the doping concentration at both ends of the first conductive channel layer 501 is greater than the intermediate doping concentration, thereby forming a first doping region (not marked) and a second doping region (not marked).
  • the second doped region (not marked) is close to the substrate (not marked), and the first doped region (not marked) is close to the second conductive channel layer 503 as an example for detailed description, which does not constitute a description of this embodiment.
  • the first doped region may be close to the substrate, and the second doped region may be close to the second conductive channel layer.
  • the second conductive channel layer 503 includes a second conductive channel (not identified) and a third doped region (not identified) and a fourth doped region (not identified) located at both ends of the second conductive channel (not identified), wherein , the third doped region (not marked) is close to the first conductive channel layer 501 .
  • the second conductive channel layer 503 is formed by in-situ doping or first deposition and then doping, and the material of the second conductive channel layer 503 is a P-type semiconductor formed by doping group IIIA elements into single crystal silicon Material.
  • the doping concentration at both ends of the second conductive channel layer 503 is greater than the intermediate doping concentration, thereby forming a third doping region (not marked) and a fourth doping region (not marked).
  • the fourth doped region (not marked) is far away from the substrate (not marked), and the third doped region (not marked) is close to the first conductive channel layer 501 as an example for detailed description, which does not constitute a description of this embodiment.
  • the third doping region may be far away from the substrate, and the fourth doping region may be close to the first conductive channel layer.
  • the conductive buffer layer 502 is located between the first conductive channel layer 501 and the second conductive channel layer 503 for reducing electrical interference between the first doped region (not identified) and the third doped region (not identified).
  • the conductive buffer layer 502 is made of polysilicon, and the conductive buffer layer 502 reduces the dielectric constant between the first doped region (not identified) and the third doped region (not identified), thereby preventing the first The problem of electrical interference between the doped region (not identified) and the third doped region (not identified).
  • the first wire layer is located on the substrate (not marked), extends in the first direction, and is in contact with the second doped region (not marked) in the first direction.
  • the material of the first wire layer is a semiconductor conductive material or a metal conductive material such as tungsten.
  • the description is made in a manner that the first direction is the BB1 direction, which does not constitute a limitation of this embodiment.
  • the extending direction of the first wire layer may be determined according to specific requirements.
  • the first wire layer is in contact with the second doped regions (not marked) of all the conductive channel structures 500 disposed in the first direction at the same time. Specifically, the first wire layer is in contact with the second doped regions (not marked) of the two conductive channel structures 500 arranged in the first direction at the same time, so as to lead out the second doped regions in the two conductive channel structures 500 (not identified) electrical signal.
  • this embodiment provides two implementations of the first wire layer, as follows:
  • a substrate (not identified) includes a substrate 101 and an isolation layer 102 , the isolation layer 102 is located on the top surface of the substrate 101 , and the first wire layer 201 is located on the top surface of the isolation layer 102 .
  • a first barrier layer 211 is further included, which is located on the plane where the first wire layer 201 is located, and is formed of an insulating material, so as to improve the stability of the semiconductor structure.
  • the base (not identified) includes a substrate 101 and an isolation layer 102 , a first wire layer (not identified) is located in the substrate, and the isolation layer 102 is located on the top surface of the substrate 101 ,
  • the first conductive channel layer 501 penetrates the isolation layer 102 and part of the substrate 101 so that the second doped region (not identified) and the first conductive layer (not identified) are in contact with each other.
  • the material of the substrate 101 includes silicon, silicon carbide, or gallium arsenide, etc.; in this embodiment, the substrate 101 is formed of a silicon material, and the silicon material is used as the substrate 101 in this embodiment for the convenience of this embodiment.
  • an appropriate material of the substrate 101 can be selected according to requirements; in addition, the material of the isolation layer 102 is silicon nitride.
  • the second wire layer 202 is nested on the conductive channel structure 500 and is in phase with the first doped region (not identified) and the third doped region (not identified) in the second direction touch.
  • the material of the second wire layer 202 is a semiconductor conductive material or a metal conductive material such as tungsten.
  • a second barrier layer 212 is further included, which is located on the plane where the second wire layer 202 is located, and is formed of an insulating material, so as to improve the stability of the semiconductor structure.
  • the extension angle between the first direction and the second direction is greater than 0 degree, that is, the first direction and the second direction do not overlap, and there is an angle between the first direction and the second direction, so that the follow-up can be at different positions
  • the electrical connection to the first wire layer 201 and the second wire layer 202 is achieved.
  • the description is made in the manner that the second direction is the CC1 direction, that is, the first direction and the second direction are perpendicular, which does not constitute a limitation on this embodiment.
  • the extending direction of the second wire layer 202 is determined. When the first wire layer 201 and the second wire layer 202 have an included angle, it should belong to the protection scope of the present application.
  • the first doped regions (not marked) and the third doped regions (not marked) of all the conductive channel structures 500 disposed in the second direction of the second wire layer 202 are in contact with each other.
  • the second wire layer 202 is in contact with the first doped region (not marked) and the third doped region (not marked) of the two conductive channel structures 500 disposed in the second direction at the same time, for deriving 2 Electrical signals of a first doped region (not identified) and a third doped region (not identified) in the conductive channel structure 500 .
  • the second barrier layer 212 has sub-connection holes penetrating the second barrier layer 212 (refer to FIG. 2 or FIG. 5 ).
  • the height of the contact surface between the conductive buffer layer 502 and the first doped region is lower than the height of the central thickness position of the second wire layer 202 and higher than the height of the bottom surface of the second wire layer 202 ;
  • the height of the contact between the conductive buffer layer 502 and the third doped region is higher than the height of the center thickness position of the second wire layer 202 and lower than the height of the top surface of the second wire layer 202 .
  • the second wire layer 202 has a larger contact area with the first doped region (not marked) and the third doped region (not marked), thereby ensuring that the second wire layer 202 Stability of electrical connection to first doped region (not identified) and third doped region (not identified).
  • the thickness of the conductive buffer layer 502 is less than 1/3 of the thickness of the second wire layer 202 .
  • the second wire layer 202 has a larger contact area with the first doped region (not marked) and the third doped region (not marked), thereby ensuring that the second wire layer 202 Stability of electrical connection to first doped region (not identified) and third doped region (not identified).
  • a gate structure 700 is disposed around a first conductive channel (not identified) and a second conductive channel (not identified).
  • the gate structure 700 includes a gate oxide layer 702 and a metal gate layer 701 , and the gate oxide layer covers the first conductive channel, the second conductive channel, and the first wire layer 201 (refer to FIGS. 2 to 4 ) Or the exposed surface of the isolation layer 102 (refer to FIG. 5 to FIG. 7 ) and the second wire layer 202 ; the metal gate layer 701 is used to fill the gap between the gate oxide layers 702 , thereby forming the gate structure 700 .
  • the semiconductor structure further includes: a first insulating layer (not shown in the figure) disposed surrounding the first wire layer 201 shown); and a second insulating layer (not shown) disposed surrounding the second wire layer 202 .
  • the semiconductor structure further includes: a protective layer 104 nested on top of the discrete all conductive channel structures 500, in contact with the fourth doped region (not identified), In a direction perpendicular to the surface of the substrate (not marked), the protective layer 104 has vias (refer to FIGS. 2 and 5 ) through the protective layer 104 , and the gate structure 700 also fills the vias.
  • the gate structure also fills the plane where the first wire layer is located and the plane where the second wire layer is located Flat voids.
  • the top surface of the protective layer 104 is flush with the top surface of the second conductive channel layer 503, so as to facilitate subsequent extraction and packaging of electrical signals to the semiconductor structure.
  • the substrate (not marked) of the semiconductor structure includes a structure area and a wiring area, and the wiring area is arranged on the periphery of the structure area; the substrate (not marked) of the wiring area is provided with a peripheral insulating structure 103, The first wire layer 201 and the second wire 202 also extend into the peripheral insulating structure 103 of the connecting area on one side, so as to electrically connect the first wire layer 201 and the second wire 202 through the connecting area subsequently.
  • the first conductive plug 801 is electrically connected to the first wire layer 201
  • the second conductive plug 802 is electrically connected to the second wire 202
  • the third conductive plug 803 is electrically connected to the fourth doped region (not marked).
  • the fourth conductive plug 804 is electrically connected to the gate structure 700, as follows:
  • the first conductive plug 801 penetrates through the peripheral insulating structure 103 and is electrically connected to the first wire layer 201 . Further, the first conductive plug 801 also penetrates part of the first wire layer 201 to increase the contact area between the first conductive plug 801 and the first wire layer 201, thereby reducing the size of the first conductive plug 801 and the first wire Contact resistance between layers 201.
  • the first conductive plug 801 penetrates the peripheral insulating structure 103 and the isolation layer 102 and is electrically connected to the first wire layer in the substrate 101 . Further, the first conductive plug 801 also penetrates part of the substrate 101 and the first wire layer, so as to increase the contact area between the first conductive plug 801 and the first wire layer, thereby reducing the distance between the first conductive plug 801 and the first wire layer. Contact resistance between a conductor layer.
  • the second conductive plug 802 penetrates part of the peripheral insulating structure 103 and is in contact with the second wire 202 . Further, the second conductive plug 802 also penetrates part of the second wire 202 to increase the contact area between the second conductive plug 802 and the second wire 202 , thereby reducing the distance between the second conductive plug 802 and the second wire 202 contact resistance between.
  • the third conductive plug 803 is in contact with the fourth doped region (not marked). Further, the third conductive plug 803 also penetrates part of the fourth doped region (not identified), so as to increase the contact area between the third conductive plug 803 and the fourth doped region (not identified), thereby reducing the third Contact resistance between the conductive plug 803 and the fourth doped region (not identified).
  • the fourth conductive plug 804 is in contact with the top of the gate structure 700 . Further, the fourth conductive plug 804 also penetrates part of the gate structure 700 to increase the contact area between the fourth conductive plug 804 and the gate structure 700 , thereby reducing the distance between the fourth conductive plug 804 and the gate structure 700 contact resistance between.
  • the vertically arranged first conductive channel layer and the second conductive channel layer namely two vertically arranged conductive channels
  • the conductive channels are vertically arranged
  • the gate structure surrounds the first conductive channel in the horizontal direction. track and the second conductive channel, thereby preventing the conductive channel from occupying a large area in the horizontal direction.
  • Another embodiment of the present application relates to a method for forming a semiconductor structure, including: providing a substrate including a structure region and a wiring region, the substrate comprising a substrate, a first wire layer and an isolation layer, and the first wire layer is in a first direction extending; a first sacrificial layer is formed on the base of the structure area, and a peripheral insulating structure is formed on the base of the connection area; a second wire layer is formed on the first sacrificial layer, and the second wire layer extends to the peripheral insulation of the connection area In the structure, and the second wire layer extends in the second direction; the second sacrificial layer and the protective layer are sequentially formed on the substrate of the structural region; the patterned protective layer, the second sacrificial layer and the first sacrificial layer form openings, and Filling the opening to form a conductive channel structure; patterning part of the protective layer until the second sacrificial layer is exposed, removing the second sacrificial layer and the first sa
  • FIG. 8 , FIG. 11 , FIG. 13 , FIG. 15 , FIG. 17 , FIG. 19 , FIG. 21 , and FIG. 27 are schematic top-view structural diagrams corresponding to each step in the method for forming a semiconductor structure provided by this embodiment
  • FIG. 16, FIG. 18, FIG. 20, FIG. 22, FIG. 23, and FIG. 28 are schematic cross-sectional structural diagrams corresponding to each step in the method for forming a semiconductor structure provided in this embodiment, FIG. 10, FIG. 24, FIG. 25, and FIG. 26
  • the method for forming the semiconductor structure provided in this embodiment is a schematic diagram of the cross-sectional structure corresponding to the formation of the first wire layer in the substrate. The same or corresponding parts of the examples will not be described in detail below.
  • a substrate including a structure region and a wiring region is provided, and the substrate (not identified) includes a substrate 101 , a first wire layer 201 and an isolation layer 102 , wherein the first wire layer 201 is in the extending in the first direction.
  • providing a substrate (not identified) including a structure region and a wiring region includes: providing a substrate 101 including a structure region and a wiring region, and forming an isolation layer on the substrate 101 in the structure region 102 , and a first wire layer 201 is formed on the isolation layer 102 .
  • a first barrier layer 211 located on the plane where the first wire layer 201 is located is further included, and the first barrier layer 211 is formed of an insulating material to improve the stability of the semiconductor structure.
  • providing a substrate (not identified) including a structured region and a wiring region includes: providing a substrate 101 including a structured region and a wiring region, and doping the substrate 101 in the structured region A first wiring layer (not shown) is formed, and an isolation layer 102 is formed on the substrate 101 in the structure region.
  • the material of the substrate 101 includes silicon, silicon carbide or gallium arsenide, etc.; in this embodiment, the substrate 101 is formed of a silicon material, and the silicon material is used as the substrate 101 in this embodiment for convenience in the art The technical personnel's understanding of the subsequent formation method does not constitute a limitation.
  • an appropriate material of the substrate 101 can be selected according to requirements; in addition, the material of the isolation layer 102 is silicon nitride; the first wire layer 201 is composed of It is formed of semiconductor conductive material or metal conductive material, such as doped silicon or tungsten, etc.
  • a first sacrificial layer 301 is formed on the substrate (not marked) of the structure region, a peripheral insulating structure 103 (refer to FIG. 13) is formed on the substrate (not marked) of the wiring region, and a first sacrificial layer 301 is formed on the substrate (not marked) of the wiring region A second wire layer 202 is formed on the layer 301, wherein the second wire layer 202 extends in the second direction.
  • a second barrier layer 212 located on the plane where the second wire layer 202 is located is further included, and the second barrier layer 212 is formed of an insulating material to improve the stability of the semiconductor structure.
  • first wire layer 201 and the second wire layer 202 are vertically arranged, which does not constitute a limitation on this embodiment. In other embodiments, only the first wire layer 201 and The included angles exist between the second conductive layers 202, which all fall within the protection scope of the present application.
  • the spin coating method is used to form the first sacrificial layer 301 , and the selective coating method is used to deposit a fast deposition rate, and a thicker first sacrificial layer 301 can be deposited in a short time.
  • the first sacrificial layer 301 is formed of a semiconductor material containing carbon or oxygen, and the first sacrificial layer can be removed by ashing or dry etching subsequently without affecting other structures.
  • the second wire layer 202 is formed of a semiconductor conductive material or a metal conductive material, such as doped silicon or tungsten.
  • the formed second wire layer 202 extends into the peripheral insulating structure 103 of the connection area.
  • the formed first wire layer 201 also extends to the peripheral insulating structure 103 of the connection area,
  • the first wire layer 201 extends into the peripheral insulating structure 103 on the first side of the wiring area
  • the second wire layer 202 extends into the peripheral insulating structure 103 on the second side of the wiring area
  • the second wire layer 202 extends into the peripheral insulating structure 103 on the second side of the wiring area.
  • One side and the second side are on different sides of the structured area.
  • the extension directions of the first wire layer 201 and the second wire layer 202 are different, so that the electrical signals of the first wire layer 201 and the second wire layer 202 can be derived in the connection areas on different sides of the structure area, and the semiconductor structure is further reduced. the horizontal area.
  • the protective layer 104 of the second sacrificial layer 302 is sequentially formed on the substrate (not marked) of the structure region.
  • the spin coating method is used to form the second sacrificial layer 302 , and the selective coating method has a high deposition rate and can deposit the thick second sacrificial layer 302 in a short time.
  • the second sacrificial layer 302 is formed of a semiconductor material containing carbon or oxygen, and the first sacrificial layer can be removed by ashing or dry etching subsequently without affecting other structures.
  • the material of the protective layer 104 is silicon nitride.
  • the patterned protective layer 104 , the second sacrificial layer 302 , the second wire layer 202 , and the first sacrificial layer 301 form openings 401 . Further, in this embodiment, a part of the first wire layer 201 is also patterned to increase the surface area of the first wire layer 201 exposed by the opening 401 .
  • the patterning method includes, but is not limited to, forming a mask layer on the protective layer 104, and then implementing the process of patterning the semiconductor structure based on the formed mask layer.
  • the patterned opening 401 may be one or a plurality of openings, and the plurality of openings are discretely arranged on the substrate (not marked); referring to FIG. 15 , in this embodiment, four openings 401 are formed by patterning as an example.
  • the number of openings formed by patterning may be 1, 3, 5, etc.; in specific applications, the number of openings 401 formed by patterning may be Make specific settings according to your needs.
  • the four openings are arranged in a quadratic arrangement.
  • conductive via structures 500 filling openings 401 are formed.
  • the conductive channel structure 500 includes a first conductive channel layer 501 , a conductive buffer layer 502 and a second conductive channel layer 503 that are stacked in sequence.
  • the first conductive channel layer 501 includes a first conductive channel (not identified) and a first doped region (not identified) and a second doped region (not identified) located at both ends of the first conductive channel (not identified), wherein , the first doped region (not marked) is close to the second conductive channel layer 503 .
  • the first conductive channel layer 501 is formed by in-situ doping or first deposition and then doping, and the material of the first conductive channel layer 501 is an N-type semiconductor formed by doping VA group elements into single crystal silicon Material.
  • the doping concentration at both ends of the first conductive channel layer 501 is greater than the middle doping concentration, thereby forming a first doping region (not marked) and a second doping region (not marked).
  • the second doped region (not marked) is close to the substrate (not marked), and the first doped region (not marked) is close to the second conductive channel layer 503 as an example for detailed description, which does not constitute a description of this embodiment.
  • the first doped region may be close to the substrate, and the second doped region may be close to the second conductive channel layer.
  • the second conductive channel layer 503 includes a second conductive channel (not identified) and a third doped region (not identified) and a fourth doped region (not identified) located at both ends of the second conductive channel (not identified), wherein , the third doped region (not marked) is close to the first conductive channel layer 501 .
  • the second conductive channel layer 503 is formed by in-situ doping or first deposition and then doping, and the material of the second conductive channel layer 503 is a P-type semiconductor formed by doping group IIIA elements into single crystal silicon Material.
  • the doping concentration at both ends of the second conductive channel layer 503 is greater than the intermediate doping concentration, thereby forming a third doping region (not marked) and a fourth doping region (not marked).
  • the fourth doped region (not marked) is far away from the substrate (not marked), and the third doped region (not marked) is close to the first conductive channel layer 501 as an example for detailed description, which does not constitute a description of this embodiment.
  • the third doping region may be far away from the substrate, and the fourth doping region may be close to the first conductive channel layer.
  • one of the first conductive channel layer 501 and the second conductive channel layer 503 is an N-type conductive channel, and the other is a P-type conductive channel.
  • the first conductive channel layer 501 is an N-type conductive channel and the second conductive channel layer 503 is a P-type conductive channel as an example for detailed description, which does not constitute a limitation to this embodiment; in other embodiments , the first conductive channel layer is a P-type conductive channel, and the second conductive channel layer is an N-type conductive channel as an example for detailed description.
  • the conductive buffer layer 502 is located between the first conductive channel layer 501 and the second conductive channel layer 503 for reducing electrical interference between the first doped region (not identified) and the third doped region (not identified).
  • the conductive buffer layer 502 is made of polysilicon, and the conductive buffer layer 502 reduces the dielectric constant between the first doped region (not identified) and the third doped region (not identified), thereby preventing the first The problem of electrical interference between the doped region (not identified) and the third doped region (not identified).
  • part of the protective layer 104 is patterned until the second sacrificial layer 302 is not exposed, via holes 602 are formed, and the second sacrificial layer is removed based on the via holes 602 ; part of the second barrier layer 212 is patterned until exposed In the first sacrificial layer 301 , a sub-connection hole 601 is formed, and the first sacrificial layer 301 is removed based on the sub-connection hole 601 .
  • the patterning method includes, but is not limited to, forming a mask layer on the protective layer 104, and then implementing the process of patterning the semiconductor structure based on the formed mask layer.
  • the first sacrificial layer 301 and the second sacrificial layer 302 are removed by wet etching.
  • wet etching is used to etch a certain semiconductor material. , does not affect other semiconductor structures; in addition, in other embodiments, the first sacrificial layer and the second sacrificial layer can be removed by ashing, and the removal rate of the first sacrificial layer and the second sacrificial layer can be removed by an ashing process. Faster without affecting other semiconductor structures.
  • first barrier layer 211 filling the plane where the first conductor layer 201 is located
  • second barrier layer 212 filling the plane where the second conductor layer 202 is located.
  • patterned Part of the protective layer 104 is removed until the second sacrificial layer 302 is exposed, and the second sacrificial layer 302 and the first sacrificial layer 301 are removed.
  • a gate structure 700 filling the void is formed.
  • the gate structure 700 includes a gate oxide layer 702 and a metal gate layer 701 , and the gate oxide layer covers the first conductive channel, the second conductive channel, and the first wire layer 201 (refer to FIGS. 2 to 4 ) Or the exposed surface of the isolation layer 102 (refer to FIG. 5 to FIG. 7 ) and the second wire layer 202 ; the metal gate layer 701 is used to fill the gap between the gate oxide layers 702 , thereby forming the gate structure 700 .
  • forming the above semiconductor structure further includes: forming the first wire layer 201 and the gate structure 700 A first insulating layer (not shown) between them; and a second insulating layer (not shown) formed between the second wire layer 202 and the gate structure 700 .
  • a first conductive plug 801 electrically connected to the first wire layer 201 is formed, and a second conductive plug 801 is electrically connected to the second wire layer 202 Plug 802, electrically connected to the third conductive plug 803 of the fourth doped region (not identified), and electrically connected to the fourth conductive plug 804 of the gate structure 700, specifically:
  • the first conductive plug 801 penetrates through the peripheral insulating structure 103 and is electrically connected to the first wire layer 201 . Further, the first conductive plug 801 also penetrates part of the first wire layer 201 to increase the contact area between the first conductive plug 801 and the first wire layer 201, thereby reducing the size of the first conductive plug 801 and the first wire Contact resistance between layers 201.
  • the first conductive plug 801 penetrates the peripheral insulating structure 103 and the isolation layer 102 and is electrically connected to the first wire layer in the substrate 101 . Further, the first conductive plug 801 also penetrates part of the substrate 101 and the first wire layer, so as to increase the contact area between the first conductive plug 801 and the first wire layer, thereby reducing the distance between the first conductive plug 801 and the first wire layer. Contact resistance between a conductor layer.
  • the second conductive plug 802 penetrates part of the peripheral insulating structure 103 and is in contact with the second wire layer 202 . Further, the second conductive plug 802 also penetrates part of the second wire layer 202 to increase the contact area between the second conductive plug 802 and the second wire layer 202 , thereby reducing the size of the second conductive plug 802 and the second wire Contact resistance between layers 202 .
  • the third conductive plug 803 is in contact with the fourth doped region (not marked). Further, the third conductive plug 803 also penetrates part of the fourth doped region (not identified), so as to increase the contact area between the third conductive plug 803 and the fourth doped region (not identified), thereby reducing the third Contact resistance between the conductive plug 803 and the fourth doped region (not identified).
  • the fourth conductive plug 804 is in contact with the top of the gate structure 700 . Further, the fourth conductive plug 804 also penetrates part of the gate structure 700 to increase the contact area between the fourth conductive plug 804 and the gate structure 700 , thereby reducing the distance between the fourth conductive plug 804 and the gate structure 700 contact resistance between.
  • the conductive channels are vertically arranged, and the gate structure is surrounded in the horizontal direction.
  • the first conductive channel and the second conductive channel are used to prevent the conductive channel from occupying a large area in the horizontal direction.
  • Still another embodiment of the present application relates to a method for forming a semiconductor structure, including: providing a substrate including a structure region and a wiring region, the substrate comprising a substrate, a first wire layer and an isolation layer, and the first wire layer is in a first direction extending; forming a first sacrificial layer on the base of the structure area, and forming a peripheral insulating structure on the base of the connection area; patterning the first sacrificial layer to form a first channel penetrating the first sacrificial layer; forming a filling first channel and a second wire layer partially located on the first sacrificial layer, the second wire layer extends into the peripheral insulating structure of the connection area, and the second wire layer extends in the second direction; the second wire layer is sequentially formed on the base of the structure area sacrificial layer and protective layer; patterning the second sacrificial layer to form through the second sacrificial layer and the second channel, the projections of the first channel and the second channel
  • the conductive channel structure is formed in different steps in this embodiment. Compared with the conductive channel structure formed at one time, the depth and width of the trench to be filled are relatively small, so as to ensure that the formed conductive channel structure has Good compactness.
  • 29 to 34 are schematic cross-sectional structural diagrams corresponding to each step in the method for forming a semiconductor structure provided by this embodiment.
  • the following will describe the method for forming a semiconductor structure provided by this embodiment in detail with reference to the accompanying drawings, which are the same as the above-mentioned embodiments or The corresponding parts will not be described in detail below.
  • a substrate including a structure region and a wiring region is provided, and the substrate (not identified) includes a substrate 101 , a first wire layer 201 and an isolation layer 102 .
  • a first sacrificial layer 301 is formed on a substrate (not identified) of the structure region.
  • the peripheral insulating structure 103 is formed on the substrate (not marked) of the connection region, the first sacrificial layer 301 is patterned, and the first channel 402 penetrating the first sacrificial layer is formed.
  • the patterning method includes but is not limited to: forming a mask layer on the first sacrificial layer 301 , and then implementing the process of patterning the semiconductor structure based on the formed mask layer.
  • the patterned first channel 402 may be one or multiple, and the plurality of openings are discretely disposed on the substrate (not marked); referring to FIG. 31 , in this embodiment, four first channels are formed by patterning 402 is taken as an example for specific description, which does not constitute a limitation to this embodiment. In other embodiments, the number of openings formed by patterning may be 1, 3, 5, etc.; The number of channels 402 can be specifically set according to requirements. In addition, in this embodiment, the four openings are arranged in a quadratic arrangement.
  • a second wire layer 202 is formed to fill the first channel 402 and cover the first sacrificial layer 301 .
  • the second wire layer 202 extends to the peripheral insulating structure 103 of the connection area, wherein the first channel 402 is filled with the first wire layer 202 .
  • the two wire layers 202 serve as the first conductive channel layer 501 .
  • the first conductive channel layer 501 includes a first conductive channel (not identified) and a first doped region (not identified) and a second doped region (not identified) located at both ends of the first conductive channel (not identified), wherein , the first doped region (not marked) is close to the second conductive channel layer 503 .
  • the first conductive channel layer 501 is formed by in-situ doping or first deposition and then doping, and the material of the first conductive channel layer 501 is an N-type semiconductor formed by doping VA group elements into single crystal silicon Material.
  • the doping concentration at both ends of the first conductive channel layer 501 is greater than the intermediate doping concentration, thereby forming a first doping region (not marked) and a second doping region (not marked).
  • the second doped region (not marked) is close to the substrate (not marked), and the first doped region (not marked) is close to the second conductive channel layer 503 as an example for detailed description, which does not constitute a description of this embodiment.
  • the first doped region may be close to the substrate, and the second doped region may be close to the second conductive channel layer.
  • a second sacrificial layer 302 and a protective layer 104 are sequentially formed on the substrate (not marked) of the structure region; the second sacrificial layer 302 is patterned to form a first channel penetrating the second sacrificial layer 302 and the second channel 403 .
  • the projections of 402 and the second channel 403 on the substrate coincide.
  • the patterning method includes, but is not limited to, forming a mask layer on the second sacrificial layer 302 , and then implementing the process of patterning the semiconductor structure based on the formed mask layer.
  • the number of second channels 403 formed by patterning may be one or more, and the plurality of openings are discretely disposed on the substrate (not marked); referring to FIG. 33 , in this embodiment, four second channels are formed by patterning 403 is taken as an example for specific description, which does not constitute a limitation to this embodiment. In other embodiments, the number of openings formed by patterning may be 1, 3, 5, etc.; The number of channels 402 can be specifically set according to requirements. In addition, in this embodiment, the projections of the first channel 402 and the second channel 403 on the substrate coincide; in other embodiments, the first channel and the second channel can be arbitrarily set.
  • a conductive buffer layer 502 and a second conductive channel layer 503 filling the second channel are formed.
  • the second conductive channel layer 503 includes a second conductive channel (not identified) and a third doped region (not identified) and a fourth doped region (not identified) located at both ends of the second conductive channel (not identified), wherein , the third doped region (not marked) is close to the first conductive channel layer 501 .
  • the second conductive channel layer 503 is formed by in-situ doping or first deposition and then doping, and the material of the second conductive channel layer 503 is a P-type semiconductor formed by doping group IIIA elements into single crystal silicon Material.
  • the doping concentration at both ends of the second conductive channel layer 503 is greater than the intermediate doping concentration, thereby forming a third doping region (not marked) and a fourth doping region (not marked).
  • the fourth doped region (not marked) is far away from the substrate (not marked), and the third doped region (not marked) is close to the first conductive channel layer 501 as an example for detailed description, which does not constitute a description of this embodiment.
  • the third doping region may be far away from the substrate, and the fourth doping region may be close to the first conductive channel layer.
  • one of the first conductive channel layer 501 and the second conductive channel layer 503 is an N-type conductive channel, and the other is a P-type conductive channel.
  • the first conductive channel layer 501 is an N-type conductive channel and the second conductive channel layer 503 is a P-type conductive channel as an example for detailed description, which does not constitute a limitation to this embodiment; in other embodiments , the first conductive channel layer is a P-type conductive channel, and the second conductive channel layer is an N-type conductive channel as an example for detailed description.
  • the conductive buffer layer 502 is located between the first conductive channel layer 501 and the second conductive channel layer 503 for reducing electrical interference between the first doped region (not identified) and the third doped region (not identified).
  • the conductive buffer layer 502 is made of polysilicon, and the conductive buffer layer 502 reduces the dielectric constant between the first doped region (not identified) and the third doped region (not identified), thereby preventing the first The problem of electrical interference between the doped region (not identified) and the third doped region (not identified).
  • part of the protective layer 104 is patterned until the second sacrificial layer 302 is not exposed, via holes 602 are formed, and the second sacrificial layer is removed based on the via holes 602 ; part of the second barrier layer 212 is patterned until exposed In the first sacrificial layer 301 , a sub-connection hole 601 is formed, and the first sacrificial layer 301 is removed based on the sub-connection hole 601 .
  • the patterning method includes, but is not limited to, forming a mask layer on the protective layer 104, and then implementing the process of patterning the semiconductor structure based on the formed mask layer.
  • the first sacrificial layer 301 and the second sacrificial layer 302 are removed by wet etching.
  • wet etching is used to etch a certain semiconductor material. , does not affect other semiconductor structures; in addition, in other embodiments, the first sacrificial layer and the second sacrificial layer can be removed by ashing, and the removal rate of the first sacrificial layer and the second sacrificial layer can be removed by an ashing process. Faster without affecting other semiconductor structures.
  • first barrier layer 211 filling the plane where the first conductor layer 201 is located
  • second barrier layer 212 filling the plane where the second conductor layer 202 is located.
  • patterned Part of the protective layer 104 is removed until the second sacrificial layer 302 is exposed, and the second sacrificial layer 302 and the first sacrificial layer 301 are removed.
  • a gate structure 700 filling the void is formed.
  • the gate structure 700 includes a gate oxide layer 702 and a metal gate layer 701 , and the gate oxide layer covers the first conductive channel, the second conductive channel, and the first wire layer 201 (refer to FIGS. 2 to 4 ) Or the exposed surface of the isolation layer 102 (refer to FIG. 5 to FIG. 7 ) and the second wire layer 202 ; the metal gate layer 701 is used to fill the gap between the gate oxide layers 702 , thereby forming the gate structure 700 .
  • forming the above semiconductor structure further includes: forming the first wire layer 201 and the gate structure 700 A first insulating layer (not shown) between them; and a second insulating layer (not shown) formed between the second wire layer 202 and the gate structure 700 .
  • a first conductive plug 801 electrically connected to the first wire layer 201 is formed, and a second conductive plug 801 is electrically connected to the second wire layer 202 Plug 802, electrically connected to the third conductive plug 803 of the fourth doped region (not identified), and electrically connected to the fourth conductive plug 804 of the gate structure 700, specifically:
  • the first conductive plug 801 penetrates through the peripheral insulating structure 103 and is electrically connected to the first wire layer 201 . Further, the first conductive plug 801 also penetrates part of the first wire layer 201 to increase the contact area between the first conductive plug 801 and the first wire layer 201, thereby reducing the size of the first conductive plug 801 and the first wire Contact resistance between layers 201.
  • the first conductive plug 801 penetrates the peripheral insulating structure 103 and the isolation layer 102 and is electrically connected to the first wire layer in the substrate 101 . Further, the first conductive plug 801 also penetrates part of the substrate 101 and the first wire layer, so as to increase the contact area between the first conductive plug 801 and the first wire layer, thereby reducing the distance between the first conductive plug 801 and the first wire layer. Contact resistance between a conductor layer.
  • the second conductive plug 802 penetrates part of the peripheral insulating structure 103 and is in contact with the second wire layer 202 . Further, the second conductive plug 802 also penetrates part of the second wire layer 202 to increase the contact area between the second conductive plug 802 and the second wire layer 202 , thereby reducing the size of the second conductive plug 802 and the second wire Contact resistance between layers 202 .
  • the third conductive plug 803 is in contact with the fourth doped region (not marked). Further, the third conductive plug 803 also penetrates part of the fourth doped region (not identified), so as to increase the contact area between the third conductive plug 803 and the fourth doped region (not identified), thereby reducing the third Contact resistance between the conductive plug 803 and the fourth doped region (not identified).
  • the fourth conductive plug 804 is in contact with the top of the gate structure 700 . Further, the fourth conductive plug 804 also penetrates part of the gate structure 700 to increase the contact area between the fourth conductive plug 804 and the gate structure 700 , thereby reducing the distance between the fourth conductive plug 804 and the gate structure 700 contact resistance between.
  • the conductive channels are vertically arranged, and the gate structure is surrounded in the horizontal direction.
  • the first conductive channel and the second conductive channel are used to prevent the conductive channel from occupying a large area in the horizontal direction.

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Abstract

本申请实施例提供一种半导体结构和半导体结构的形成方法，其中，半导体结构，包括：基底，以及导电通道结构，导电沟道结构包括：第一导电通道层包括第一导电沟道以及位于第一导电沟道两端的第一掺杂区和第二掺杂区；第二导电通道层包括第二导电沟道以及位于第二导电沟道两端的第三掺杂区和第四掺杂区；导电缓冲层用于降低第一掺杂区和第三掺杂区之间的电干扰；第一导线层，位于基底上，在第一方向上延伸，且与第二掺杂区相接触；第二导线层，在第二方向上延伸，且与第一掺杂区和第三掺杂区相接触；栅极结构，环绕第一导电沟道和第二导电沟道设置。

Description

半导体结构和半导体结构的形成方法
相关申请的交叉引用
本申请基于申请号为202110336399.0、申请日为2021年03月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于一种半导体结构和半导体结构的形成方法。
背景技术
集成电路芯片工艺与性能跟晶体管器件结构息息相关。5nm以下技术节点，基于PN结理论的MOS场效应晶体管器件弊端就愈加明显：器件沟道长度不断缩小，源漏间距离越来越近。为防止源漏穿通，产业界普遍采用超陡峭源漏浓度梯度掺杂工艺，这将严重限制器件工艺的热预算。此外，由于掺杂原子的统计分布及一定温度下掺杂原子易于扩散的自然属性，纳米尺度范围内制作超陡峭PN结变得异常困难，产生严重的短沟道效应，导致晶体管阈值电压下降，器件栅控能力变差，漏电流增大，功耗增加，严重时器件甚至不能关断。
将一对或多对nFET和pFET圆柱体纳米线(Nanowire)或纳米薄片(Nanosheet或Nanoribbon)沟道垂直交叉堆叠起来，组成互补全包围栅圆柱体纳米线或纳米薄片场效应晶体管(CFET)器件结构。在CFET器件结构中，nFET和pFET共用一个栅电极作为信号输入端，共用一个漏极作为信号输出端，源电极分别接地和供电电源。器件尺寸可灵活调节以满足不同芯片性能要求。在保留垂直堆叠纳米线或纳米薄片全包围栅场效应晶体 管电完整性的同时，又大大节省芯片面积，增强器件驱动电流，提高芯片器件集成度。
CFET在增强器件驱动电流而同时，又大大节省芯片面积，提高芯片器件集成度。但是，由于pFET和nFET共用一个源极或者漏极连线且制备工艺复杂多变难以控制，目前的nFET或者pFET都是采用水平放置的GAA晶体管，水平设置的导电沟道在水平方向上占用很大的面积，限制了CFET的发展。
发明内容
根据一些实施例，本申请实施例第一方面提供了一种半导体结构，包括：基底，以及位于基底上的导电通道结构，导电沟道结构包括依次堆叠设置的第一导电沟道层，导电缓冲层和第二导电沟道层；第一导电通道层包括第一导电沟道以及位于第一导电沟道两端的第一掺杂区和第二掺杂区，其中，第一掺杂区靠近第二导电通道层；第二导电通道层包括第二导电沟道以及位于第二导电沟道两端的第三掺杂区和第四掺杂区，其中，第三掺杂区靠近第一导电通道层；导电缓冲层用于降低第一掺杂区和第三掺杂区之间的电干扰；第一导线层，位于基底上，在第一方向上延伸，且与第一方向上的第二掺杂区相接触；第二导线层，在第二方向上延伸，且与第二方向上的第一掺杂区和第三掺杂区相接触；栅极结构，环绕第一导电沟道和第二导电沟道设置。
根据一些实施例，本申请实施例还提供了一种半导体结构的形成方法，包括：提供包括结构区和连线区的基底，基底包括衬底、第一导线层和隔离层，第一导线层在第一方向上延伸；在结构区的基底上形成第一牺牲层，在连线区的基底上形成外围绝缘结构；图形化第一牺牲层，形成贯穿第一牺牲层的第一通道；形成填充第一通道且部分位于第一牺牲层上的第二导线层，第二导线层延伸至连线区的外围绝缘结构中，且第二导线层在第二 方向上延伸；在结构区的基底上依次形成第二牺牲层和保护层；图形化第二牺牲层，形成贯穿第二牺牲层和第二通道，第一通道和第二通道在基底上的投影重合；形成填充第二通道的第二导电通道层；图形化部分保护层，直至暴露出第二牺牲层，去除第二牺牲层和第一牺牲层；形成填充空隙的栅极结构。
根据一些实施例，本申请实施例还提供了一种半导体结构的形成方法，包括：提供包括结构区和连线区的基底，基底包括衬底、第一导线层和隔离层，第一导线层在第一方向上延伸；在结构区的基底上形成第一牺牲层，在连线区的基底上形成外围绝缘结构；在第一牺牲层上形成第二导线层，第二导线层延伸至连线区的外围绝缘结构中，且第二导线层在第二方向上延伸；在结构区的基底上依次形成第二牺牲层和保护层；图形化保护层，第二牺牲层和第一牺牲层，形成开口，并填充开口形成导电通道结构；图形化部分保护层，直至暴露出第二牺牲层，去除第二牺牲层和第一牺牲层；形成填充空隙的栅极结构。
附图说明
图1为本申请一实施例提供的半导体结构的剖面示意图；
图2为本申请一实施例提供的半导体结构一种AA1方向的剖面示意图；
图3为本申请一实施例提供的半导体结构一种BB1方向的剖面示意图；
图4为本申请一实施例提供的半导体结构一种CC1方向的剖面示意图；
图5为本申请一实施例提供的半导体结构另一种AA1方向的剖面示意图；
图6为本申请一实施例提供的半导体结构另一种BB1方向的剖面示意图；
图7为本申请一实施例提供的半导体结构另一种CC1方向的剖面示意 图；
图8、图11、图13、图15、图17、图19、图21和图27为本申请另一实施例提供的半导体结构的形成方法中各步骤对应的俯视结构示意图；
图9、图12、图14、图16、图18、图20、图22、图23和图28为本申请另一实施例提供的半导体结构的形成方法中各步骤对应的剖面结构示意图；
图10、图24、图25和图26为本申请另一实施例提供的半导体结构的形成方法针对将第一导线层形成于衬底中对应的剖面结构示意图；
图29～图34为本申请又一实施例提供的半导体结构的形成方法中各步骤对应的剖面结构示意图。
具体实施方式
本申请一实施例提供了一种半导体结构，包括：基底，以及位于基底上的导电通道结构，导电沟道结构包括依次堆叠设置的第一导电沟道层，导电缓冲层和第二导电沟道层；第一导电通道层包括第一导电沟道以及位于第一导电沟道两端的第一掺杂区和第二掺杂区，其中，第一掺杂区靠近第二导电通道层；第二导电通道层包括第二导电沟道以及位于第二导电沟道两端的第三掺杂区和第四掺杂区，其中，第三掺杂区靠近第一导电通道层；导电缓冲层用于降低第一掺杂区和第三掺杂区之间的电干扰；第一导线层，位于基底上，在第一方向上延伸，且与第一方向上的第二掺杂区相接触；第二导线层，在第二方向上延伸，且与第二方向上的第一掺杂区和第三掺杂区相接触；栅极结构，环绕第一导电沟道和第二导电沟道设置。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变 化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的半导体结构的剖面示意图，图2为本实施例提供的半导体结构一种AA1方向的剖面示意图，图3为本实施例提供的半导体结构一种BB1方向的剖面示意图，图4为本实施例提供的半导体结构一种CC1方向的剖面示意图，图5为本实施例提供的半导体结构另一种AA1方向的剖面示意图，图6为本实施例提供的半导体结构另一种BB1方向的剖面示意图，图7为本实施例提供的半导体结构另一种CC1方向的剖面示意图，以下结合附图对本实施例提供的半导体结构作进一步详细说明。
参考图1～图7，半导体结构，包括：
基底(未标识)，以及位于基底(未标识)上的导电通道结构500，导电通道结构500包括依次堆叠设置的第一导电通道层501、导电缓冲层502和第二导电通道层503。
需要说明的是，位于基底上的导电通道结构500可以是一个，也可以是多个，多个导电通道结构500分立设置在基底(未标识)上；参考图1，本实施例以位于基底上的4个导电通道结构500为例进行具体说明，并不构成对本实施例的限定，在其他实施例中，导电通道结构可以为1个、3个、5个等；在具体应用中，导电通道结构500的个数可以根据需求进行具体设置。另外，在本实施例中，4个导电通道结构500呈四方排布的方式排列。
具体地，第一导电通道层501和第二导电通道层503的其中一者为N型导电通道，另一者为P型导电通道。在本实施例中，以第一导电通道层501为N型导电通道，第二导电通道层503为P型导电通道为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第一导电通道层为P型导电通道，第二导电通道层为N型导电通道为例进行详细说明。
第一导电通道层501包括第一导电沟道(未标识)以及位于第一导电沟道(未标识)两端的第一掺杂区(未标识)和第二掺杂区(未标识)，其中，第一掺杂区(未标识)靠近第二导电通道层503。
具体地，第一导电通道层501通过原位掺杂或先沉积后掺杂的方式形成，第一导电通道层501的材料为通过向单晶硅中掺杂ⅤA族元素后形成的N型半导体材料。其中，第一导电通道层501的两端掺杂浓度大于中间掺杂浓度，从而形成第一掺杂区(未标识)和第二掺杂区(未标识)。在本实施例中，以第二掺杂区(未标识)靠近基底(未标识)，第一掺杂区(未标识)靠近第二导电通道层503为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第一掺杂区靠近基底，第二掺杂区靠近第二导电通道层。
第二导电通道层503包括第二导电沟道(未标识)以及位于第二导电沟道(未标识)两端的第三掺杂区(未标识)和第四掺杂区(未标识)，其中，第三掺杂区(未标识)靠近第一导电通道层501。
具体地，第二导电通道层503通过原位掺杂或先沉积后掺杂的方式形成，第二导电通道层503的材料为通过向单晶硅中掺杂IIIA族元素后形成的P型半导体材料。其中，第二导电通道层503的两端掺杂浓度大于中间掺杂浓度，从而形成第三掺杂区(未标识)和第四掺杂区(未标识)。在本实施例中，以第四掺杂区(未标识)远离基底(未标识)，第三掺杂区(未标识)靠近第一导电通道层501为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第三掺杂区远离基底，第四掺杂区靠近第一导电通道层。
导电缓冲层502位于第一导电通道层501和第二导电通道层503之间，用于降低第一掺杂区(未标识)和第三掺杂区(未标识)之间的电干扰。在一个例子中，导电缓冲层502的材料为多晶硅，导电缓冲层502通过降 低第一掺杂区(未标识)和第三掺杂区(未标识)之间的介电常数，从而防止第一掺杂区(未标识)和第三掺杂区(未标识)之间的电干扰的问题。
继续参考图1～图7，第一导线层，位于基底(未标识)上，在第一方向上延伸，且与第一方向上的第二掺杂区(未标识)相接触。在本实施例中，第一导线层的材料为半导体导电材料或钨等金属导电材料。
在本实施例中，以第一方向为BB1方向排列的方式进行描述，并不构成对本实施例的限定，在其他实施例中，可以根据具体需求，确定第一导线层的延伸方向。
另外，第一导线层同时与在第一方向上设置的所有导电通道结构500的第二掺杂区(未标识)相接触。具体地，第一导线层同时与在第一方向上设置的2个导电通道结构500的第二掺杂区(未标识)相接触，用于导出2个导电通道结构500中第二掺杂区(未标识)的电信号。
具体地，本实施例给出了两种第一导线层的实现方式，具体如下：
在一个例子中，参考图2～图4，基底(未标识)包括衬底101和隔离层102，隔离层102位于衬底101顶部表面，第一导线层201位于隔离层102顶部表面。在本实施例中，还包括第一阻挡层211，位于第一导线层201所在平面，由绝缘材料形成，以提高半导体结构的稳定性。
在另一个例子中，参考图5～图7，基底(未标识)包括衬底101和隔离层102，第一导线层(未标识)位于衬底内，隔离层102位于衬底101顶部表面，第一导电通道层501贯穿隔离层102和部分衬底101，以使第二掺杂区(未标识)与第一导线层(未标识)相互接触。
在上述两个示例中，衬底101的材料包括硅、碳化硅或砷化镓等；在本实施例中衬底101采用硅材料形成，本实施例采用硅材料作为衬底101是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的衬底101的材料；另外，隔离层 102的材料为氮化硅。
继续参考图1～图7，第二导线层202嵌套设置在导电通道结构500上，且与第二方向上的第一掺杂区(未标识)和第三掺杂区(未标识)相接触。在本实施例中，第二导线层202的材料为半导体导电材料或钨等金属导电材料。
在本实施例中，还包括第二阻挡层212，位于第二导线层202所在平面，由绝缘材料形成，以提高半导体结构的稳定性。
具体地，在本实施例，第一方向和第二方向的延伸夹角大于0度，即第一方向和第二方向不重合，第一方向和第二方向存在角度，使得后续可以在不同位置实现对第一导线层201和第二导线层202的电连接。
在本实施例中，以第二方向为CC1方向排列的方式进行描述，即第一方向和第二方向相垂直，并不构成对本实施例的限定，在其他实施例中，可以根据具体需求，确定第二导线层202的延伸方向，当第一导线层201和第二导线层202存在夹角，理应属于本申请的保护范围。
具体地，第二导线层202第二方向上设置的所有导电通道结构500的第一掺杂区(未标识)和第三掺杂区(未标识)相接触。具体地，第二导线层202同时与在第二方向上设置的2个导电通道结构500的第一掺杂区(未标识)和第三掺杂区(未标识)相接触，用于导出2个导电通道结构500中第一掺杂区(未标识)和第三掺杂区(未标识)的电信号。
进一步地，在垂直于基底(未标识)表面方向上，第二阻挡层212中具有贯穿第二阻挡层212的子连通孔(参考图2或图5)。
在本实施例中，导电缓冲层502与第一掺杂区(未标识)的接触面的高度低于第二导线层202中心厚度位置的高度，且高于第二导线层202底部表面的高度；导电缓冲层502与第三掺杂区(未标识)的接触的高度高于第二导线层202中心厚度位置的高度，且低于第二导线层202顶部表面 的高度。通过对第二导线层202的厚度限定，使第二导线层202与第一掺杂区(未标识)和第三掺杂区(未标识)存在较大接触面积，从而保证第二导线层202与第一掺杂区(未标识)和第三掺杂区(未标识)电连接的稳定性。
进一步地，导电缓冲层502的厚度小于第二导线层202厚度的1/3。通过对导电缓冲层502的厚度限定，进一步使第二导线层202与第一掺杂区(未标识)和第三掺杂区(未标识)存在较大接触面积，从而保证第二导线层202与第一掺杂区(未标识)和第三掺杂区(未标识)电连接的稳定性。
继续参考图1～图7，栅极结构700环绕第一导电沟道(未标识)和第二导电沟道(未标识)设置。
具体地，栅极结构700包括栅极氧化层702和金属栅极层701，栅极氧化层覆盖第一导电沟道、第二导电沟道、第一导线层201(参考图2～图4)或隔离层102(参考图5～图7)、第二导线层202暴露出的表面；金属栅极层701用于填充栅极氧化层702之间的间隙，从而形成栅极结构700。
在一个例子中，为了防止第一导线层201和第二导线层202与栅极结构700之间的电串扰问题，半导体结构还包括：包围第一导线层201设置的第一绝缘层(未图示)；以及包围第二导线层202设置的第二绝缘层(未图示)。
在另一例子中，为了保护栅极结构700顶部表面，半导体结构还包括：保护层104，嵌套设置在分立的所有导电通道结构500顶部，与第四掺杂区(未标识)相接触，在垂直于基底(未标识)表面方向上，保护层104中具有贯穿保护层104的连通孔(参考图2和图5)，栅极结构700还填充连通孔。
在其他实施例中，若没有第一阻挡层填充第一导线层所在平面，没有 第二阻挡层填充第二导线层所在平面，栅极结构还填充第一导线层所在平面和第二导线层所在平面的空隙。
具体地，保护层104顶部表面与第二导电通道层503的顶部表面齐平，以便于后续对半导体结构的电信号引出和封装。
继续参考图1～图7，半导体结构的基底(未标识)包括结构区和连线区，连线区设置在结构区外围；连线区的基底(未标识)上设置有外围绝缘结构103，第一导线层201和第二导线202还延伸至一侧的连线区的外围绝缘结构103中，以供后续通过连线区电连接第一导线层201和第二导线202。
具体地，本实施例通过第一导电插塞801电连接第一导线层201，第二导电插塞802电连接第二导线202，第三导电插塞803电连接第四掺杂区(未标识)，第四导电插塞804电连接栅极结构700，具体如下：
若第一导线层201和衬底101分立设置，参考图2和图3，第一导电插塞801贯穿外围绝缘结构103，与第一导线层201电连接。进一步地，第一导电插塞801还贯穿部分第一导线层201，以增大第一导电插塞801与第一导线层201的接触面积，从而减小第一导电插塞801与第一导线层201之间的接触电阻。
若第一导线层设置在衬底101中，参考图4和图5，第一导电插塞801贯穿外围绝缘结构103和隔离层102，与衬底101中的第一导线层电连接。进一步地，第一导电插塞801还贯穿部分衬底101和第一导线层，以增大第一导电插塞801与第一导线层的接触面积，从而减小第一导电插塞801与第一导线层之间的接触电阻。
第二导电插塞802，贯穿部分外围绝缘结构103，与第二导线202相接触。进一步地，第二导电插塞802还贯穿部分第二导线202，以增大第二导电插塞802与第二导线202的接触面积，从而减小第二导电插塞802与第 二导线202之间的接触电阻。
第三导电插塞803，与第四掺杂区(未标识)相接触。进一步地，第三导电插塞803还贯穿部分第四掺杂区(未标识)，以增大第三导电插塞803与第四掺杂区(未标识)的接触面积，从而减小第三导电插塞803与第四掺杂区(未标识)之间的接触电阻。
第四导电插塞804，与栅极结构700顶部相接触。进一步地，第四导电插塞804还贯穿部分栅极结构700，以增大第四导电插塞804与栅极结构700的接触面积，从而减小第四导电插塞804与栅极结构700之间的接触电阻。
相对于相关技术而言，垂直设置的第一导电通道层和第二导电通道层，即垂直设置的两个导电沟道，导电沟道垂直设置，栅极结构在水平方向上环绕第一导电沟道和第二导电沟道，从而避免导电沟道在水平方向上占用很大的面积。
本申请另一实施例涉及一种半导体结构的形成方法，包括：提供包括结构区和连线区的基底，基底包括衬底、第一导线层和隔离层，第一导线层在第一方向上延伸；在结构区的基底上形成第一牺牲层，在连线区的基底上形成外围绝缘结构；在第一牺牲层上形成第二导线层，第二导线层延伸至连线区的外围绝缘结构中，且第二导线层在第二方向上延伸；在结构区的基底上依次形成第二牺牲层和保护层；图形化保护层，第二牺牲层和第一牺牲层，形成开口，并填充开口形成导电通道结构；图形化部分保护层，直至暴露出第二牺牲层，去除第二牺牲层和第一牺牲层；形成填充空隙的栅极结构。
图8、图11、图13、图15、图17、图19、图21和图27为本实施例提供的半导体结构的形成方法中各步骤对应的俯视结构示意图，图9、图12、图14、图16、图18、图20、图22、图23和图28为本实施例提供的 半导体结构的形成方法中各步骤对应的剖面结构示意图，图10、图24、图25和图26为本实施例提供的半导体结构的形成方法针对将第一导线层形成于衬底中对应的剖面结构示意图，以下将结合附图对本实施例提供的半导体结构的形成方法进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图8～图10，提供包括结构区和连线区的基底(未标识)，基底(未标识)包括衬底101、第一导线层201和隔离层102，其中，第一导线层201在第一方向上延伸。
在一个例子中，参考图9，提供包括结构区和连线区的基底(未标识)，包括：提供包括结构区和连线区的衬底101，在结构区的衬底101上形成隔离层102，并在隔离层102上形成第一导线层201。
需要说明的是，在本实施例中，还包括形成位于第一导线层201所在平面的第一阻挡层211，第一阻挡层211采用绝缘材料形成，以提高半导体结构的稳定性。
在另一例子中，参考图10，提供包括结构区和连线区的基底(未标识)，包括：提供包括结构区和连线区的衬底101，在结构区的衬底101中掺杂形成第一导线层(未图示)，并在结构区的衬底101上形成隔离层102。
在本实施例中，衬底101的材料包括硅、碳化硅或砷化镓等；在本实施例中衬底101采用硅材料形成，本实施例采用硅材料作为衬底101是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的衬底101的材料；另外，隔离层102的材料为氮化硅；第一导线层201由半导体导电材料或金属导电材料形成，例如掺杂硅或钨等。
参考图11和图12，在结构区的基底(未标识)上形成第一牺牲层301，在连线区的基底(未标识)上形成外围绝缘结构103(参考图13)，在第一 牺牲层301上形成第二导线层202，其中，第二导线层202在第二方向上延伸。
需要说明的是，在本实施例中，还包括形成位于第二导线层202所在平面的第二阻挡层212，第二阻挡层212采用绝缘材料形成，以提高半导体结构的稳定性。
需要说明的是，在本实施例中，形成的第一导线层201和第二导线层202垂直设置，并不构成对本实施例的限定，在其他实施例中，仅保证第一导线层201和第二导线层202之间存在夹角，均属于本申请的保护范围之内。
在本实施例中，采用旋转涂覆的方式形成第一牺牲层301，采用选择涂覆的方式沉积速率快，可以在较短时间内沉积厚度较厚的第一牺牲层301。另外，第一牺牲层301采用含碳或含氧的半导体材料形成，后续可以通过灰化或干法刻蚀的方式去除第一牺牲层，而不对其他结构造成影响。另外，第二导线层202由半导体导电材料或金属导电材料形成，例如掺杂硅或钨等。
结合图13和图14，形成的第二导线层202延伸至连线区的外围绝缘结构103中。具体地，形成的第一导线层201也延伸至连线区的外围绝缘结构103，
优选地，第一导线层201延伸至连线区的第一侧的外围绝缘结构103中，第二导线层202延伸至连线区的第二侧的外围绝缘结构103中，连线区的第一侧和第二侧位于结构区的不同侧。第一导线层201和第二导线层202的延伸方向不同，从而实现在结构区的不同侧的连线区中导出第一导线层201和第二导线层202的电信号，进一步减小半导体结构的水平面积。
参考图15和图16，在结构区的基底(未标识)上依次形成第二牺牲层302的保护层104。
在本实施例中，采用旋转涂覆的方式形成第二牺牲层302，采用选择涂覆的方式沉积速率快，可以在较短时间内沉积厚度较厚的第二牺牲层302。另外，第二牺牲层302采用含碳或含氧的半导体材料形成，后续可以通过灰化或干法刻蚀的方式去除第一牺牲层，而不对其他结构造成影响。另外，保护层104的材料为氮化硅。
参考图17和同18，图形化保护层104，第二牺牲层302、第二导线层202、第一牺牲层301形成开口401。进一步地，在本实施例中，还图形化部分第一导线层201，以增大开口401暴露出的第一导线层201的表面面积。
其中，图形化的方式包括但不限于：在保护层104上形成掩膜层，然后基于形成的掩膜层实现图形化上述半导体结构的工艺。另外，图形化形成的开口401可以是一个，也可以是多个，多个开口分立设置在基底(未标识)上；参考图15，本实施例以位于图形化形成4个开口401为例进行具体说明，并不构成对本实施例的限定，在其他实施例中，图形化形成的开口可以为1个、3个、5个等；在具体应用中，图形化形成的开口401的个数可以根据需求进行具体设置。另外，在本实施例中，4个开口呈四方排布的方式排列。
参考图19和图20，形成填充开口401的导电通道结构500。
具体地，导电通道结构500包括依次堆叠设置的第一导电通道层501、导电缓冲层502和第二导电通道层503。
第一导电通道层501包括第一导电沟道(未标识)以及位于第一导电沟道(未标识)两端的第一掺杂区(未标识)和第二掺杂区(未标识)，其中，第一掺杂区(未标识)靠近第二导电通道层503。
具体地，第一导电通道层501通过原位掺杂或先沉积后掺杂的方式形成，第一导电通道层501的材料为通过向单晶硅中掺杂ⅤA族元素后形成的N型半导体材料。其中，第一导电通道层501的两端掺杂浓度大于中间 掺杂浓度，从而形成第一掺杂区(未标识)和第二掺杂区(未标识)。在本实施例中，以第二掺杂区(未标识)靠近基底(未标识)，第一掺杂区(未标识)靠近第二导电通道层503为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第一掺杂区靠近基底，第二掺杂区靠近第二导电通道层。
第二导电通道层503包括第二导电沟道(未标识)以及位于第二导电沟道(未标识)两端的第三掺杂区(未标识)和第四掺杂区(未标识)，其中，第三掺杂区(未标识)靠近第一导电通道层501。
具体地，第二导电通道层503通过原位掺杂或先沉积后掺杂的方式形成，第二导电通道层503的材料为通过向单晶硅中掺杂IIIA族元素后形成的P型半导体材料。其中，第二导电通道层503的两端掺杂浓度大于中间掺杂浓度，从而形成第三掺杂区(未标识)和第四掺杂区(未标识)。在本实施例中，以第四掺杂区(未标识)远离基底(未标识)，第三掺杂区(未标识)靠近第一导电通道层501为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第三掺杂区远离基底，第四掺杂区靠近第一导电通道层。
需要说明的是，第一导电通道层501和第二导电通道层503的其中一者为N型导电通道，另一者为P型导电通道。在本实施例中，以第一导电通道层501为N型导电通道，第二导电通道层503为P型导电通道为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第一导电通道层为P型导电通道，第二导电通道层为N型导电通道为例进行详细说明。
导电缓冲层502位于第一导电通道层501和第二导电通道层503之间，用于降低第一掺杂区(未标识)和第三掺杂区(未标识)之间的电干扰。在一个例子中，导电缓冲层502的材料为多晶硅，导电缓冲层502通过降 低第一掺杂区(未标识)和第三掺杂区(未标识)之间的介电常数，从而防止第一掺杂区(未标识)和第三掺杂区(未标识)之间的电干扰的问题。
参考图21～图23，图形化部分保护层104，直至不露出第二牺牲层302，形成连通孔602，基于连通孔602去除第二牺牲层；图形化部分第二阻挡层212，直至暴露出第一牺牲层301，形成子连通孔601，基于子连通孔601去除第一牺牲层301。
其中，图形化的方式包括但不限于：在保护层104上形成掩膜层，然后基于形成的掩膜层实现图形化上述半导体结构的工艺。
在本实施例中，采用湿法刻蚀的方式去除第一牺牲层301和第二牺牲层302，本领域技术人员清楚，采用湿法刻蚀的方式，针对于某一种半导体材料进行刻蚀，并不影响其他半导体结构；另外，在其他实施例中，可以采用灰化的方式去除第一牺牲层和第二牺牲层，采用灰化工艺去除第一牺牲层和第二牺牲层的去除速率较快，同时也不影响其他半导体结构。
在其他实施例中，若不存在填充第一导线层201所在平面的第一阻挡层211，不存在填充第二导线层202所在平面的第二阻挡层212，参考图24～图26，图形化部分保护层104，直至暴露出第二牺牲层302，去除第二牺牲层302和第一牺牲层301。
参考图27和图28，形成填充空隙的栅极结构700。
具体地，栅极结构700包括栅极氧化层702和金属栅极层701，栅极氧化层覆盖第一导电沟道、第二导电沟道、第一导线层201(参考图2～图4)或隔离层102(参考图5～图7)、第二导线层202暴露出的表面；金属栅极层701用于填充栅极氧化层702之间的间隙，从而形成栅极结构700。
在一个例子中，为了防止第一导线层201和第二导线层202与栅极结构700之间的电串扰问题，在形成上述半导体结构还包括：形成位于第一导线层201与栅极结构700之间的第一绝缘层(未图示)；以及形成位于第 二导线层202与栅极结构700之间的第二绝缘层(未图示)。
参考图1～图7(以基底为第一导线层参考图5～图7)，形成电连接第一导线层201的第一导电插塞801，电连接第二导线层202的第二导电插塞802，电连接第四掺杂区(未标识)的第三导电插塞803，电连接栅极结构700的第四导电插塞804，具体地：
若第一导线层201和衬底101分立设置，参考图2和图3，第一导电插塞801贯穿外围绝缘结构103，与第一导线层201电连接。进一步地，第一导电插塞801还贯穿部分第一导线层201，以增大第一导电插塞801与第一导线层201的接触面积，从而减小第一导电插塞801与第一导线层201之间的接触电阻。
若第一导线层设置在衬底101中，参考图4和图5，第一导电插塞801贯穿外围绝缘结构103和隔离层102，与衬底101中的第一导线层电连接。进一步地，第一导电插塞801还贯穿部分衬底101和第一导线层，以增大第一导电插塞801与第一导线层的接触面积，从而减小第一导电插塞801与第一导线层之间的接触电阻。
第二导电插塞802，贯穿部分外围绝缘结构103，与第二导线层202相接触。进一步地，第二导电插塞802还贯穿部分第二导线层202，以增大第二导电插塞802与第二导线层202的接触面积，从而减小第二导电插塞802与第二导线层202之间的接触电阻。
第三导电插塞803，与第四掺杂区(未标识)相接触。进一步地，第三导电插塞803还贯穿部分第四掺杂区(未标识)，以增大第三导电插塞803与第四掺杂区(未标识)的接触面积，从而减小第三导电插塞803与第四掺杂区(未标识)之间的接触电阻。
第四导电插塞804，与栅极结构700顶部相接触。进一步地，第四导电插塞804还贯穿部分栅极结构700，以增大第四导电插塞804与栅极结构 700的接触面积，从而减小第四导电插塞804与栅极结构700之间的接触电阻。
相比于相关技术而言，通过形成垂直设置的第一导电通道层和第二导电通道层，即形成垂直设置的两个导电沟道，导电沟道垂直设置，栅极结构在水平方向上环绕第一导电沟道和第二导电沟道，从而避免导电沟道在水平方向上占用很大的面积。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本申请又一实施例涉及一种半导体结构的形成方法，包括：提供包括结构区和连线区的基底，基底包括衬底、第一导线层和隔离层，第一导线层在第一方向上延伸；在结构区的基底上形成第一牺牲层，在连线区的基底上形成外围绝缘结构；图形化第一牺牲层，形成贯穿第一牺牲层的第一通道；形成填充第一通道且部分位于第一牺牲层上的第二导线层，第二导线层延伸至连线区的外围绝缘结构中，且第二导线层在第二方向上延伸；在结构区的基底上依次形成第二牺牲层和保护层；图形化第二牺牲层，形成贯穿第二牺牲层和第二通道，第一通道和第二通道在基底上的投影重合；形成填充第二通道的第二导电通道层；图形化部分保护层，直至暴露出第二牺牲层，去除第二牺牲层和第一牺牲层；形成填充空隙的栅极结构。相 比于上一实施例，本实施例在不同步骤中形成导电通道结构，相比于一次形成的导电通道结构，所需填充的沟槽的深宽比较小，从而保证形成的导电通道结构具有良好的致密性。
图29～图34为本实施例提供的半导体结构的形成方法中各步骤对应的剖面结构示意图，以下将结合附图对本实施例提供的半导体结构的形成方法进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图8和图29，提供包括结构区和连线区的基底(未标识)，基底(未标识)包括衬底101、第一导线层201和隔离层102。
参考图30，在结构区的基底(未标识)上形成第一牺牲层301。
参考图31，在连线区的基底(未标识)上形成外围绝缘结构103，图形化第一牺牲层301，形成贯穿第一牺牲层的第一通道402。
其中，图形化的方式包括但不限于：在第一牺牲层301上形成掩膜层，然后基于形成的掩膜层实现图形化上述半导体结构的工艺。另外，图形化形成的第一通道402可以是一个，也可以是多个，多个开口分立设置在基底(未标识)上；参考图31，本实施例以位于图形化形成4个第一通道402为例进行具体说明，并不构成对本实施例的限定，在其他实施例中，图形化形成的开口可以为1个、3个、5个等；在具体应用中，图形化形成的第一通道402的个数可以根据需求进行具体设置。另外，在本实施例中，4个开口呈四方排布的方式排列。
参考图32，形成填充第一通道402且覆盖第一牺牲层301上形成第二导线层202，第二导线层202延伸至连线区的外围绝缘结构103中，其中填充第一通道402的第二导线层202作为第一导电通道层501。
第一导电通道层501包括第一导电沟道(未标识)以及位于第一导电沟道(未标识)两端的第一掺杂区(未标识)和第二掺杂区(未标识)，其中，第一掺杂区(未标识)靠近第二导电通道层503。
具体地，第一导电通道层501通过原位掺杂或先沉积后掺杂的方式形成，第一导电通道层501的材料为通过向单晶硅中掺杂ⅤA族元素后形成的N型半导体材料。其中，第一导电通道层501的两端掺杂浓度大于中间掺杂浓度，从而形成第一掺杂区(未标识)和第二掺杂区(未标识)。在本实施例中，以第二掺杂区(未标识)靠近基底(未标识)，第一掺杂区(未标识)靠近第二导电通道层503为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第一掺杂区靠近基底，第二掺杂区靠近第二导电通道层。
参考图33，在结构区的基底(未标识)上依次形成第二牺牲层302和保护层104；图形化第二牺牲层302，形成贯穿第二牺牲层302和第二通道403，第一通道402和第二通道403在基底上的投影重合。
其中，图形化的方式包括但不限于：在第二牺牲层302上形成掩膜层，然后基于形成的掩膜层实现图形化上述半导体结构的工艺。另外，图形化形成的第二通道403可以是一个，也可以是多个，多个开口分立设置在基底(未标识)上；参考图33，本实施例以位于图形化形成4个第二通道403为例进行具体说明，并不构成对本实施例的限定，在其他实施例中，图形化形成的开口可以为1个、3个、5个等；在具体应用中，图形化形成的第一通道402的个数可以根据需求进行具体设置。另外，在本实施例中，第一通道402和第二通道403在基底上的投影重合；在其他实施例中，第一通道和第二通道可以任意设置。
参考图34，形成填充第二通道的导电缓冲层502和第二导电通道层503。
第二导电通道层503包括第二导电沟道(未标识)以及位于第二导电沟道(未标识)两端的第三掺杂区(未标识)和第四掺杂区(未标识)，其中，第三掺杂区(未标识)靠近第一导电通道层501。
具体地，第二导电通道层503通过原位掺杂或先沉积后掺杂的方式形成，第二导电通道层503的材料为通过向单晶硅中掺杂IIIA族元素后形成的P型半导体材料。其中，第二导电通道层503的两端掺杂浓度大于中间掺杂浓度，从而形成第三掺杂区(未标识)和第四掺杂区(未标识)。在本实施例中，以第四掺杂区(未标识)远离基底(未标识)，第三掺杂区(未标识)靠近第一导电通道层501为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第三掺杂区远离基底，第四掺杂区靠近第一导电通道层。
需要说明的是，第一导电通道层501和第二导电通道层503的其中一者为N型导电通道，另一者为P型导电通道。在本实施例中，以第一导电通道层501为N型导电通道，第二导电通道层503为P型导电通道为例进行详细说明，并不构成对本实施例的限定；在其他实施例中，可以以第一导电通道层为P型导电通道，第二导电通道层为N型导电通道为例进行详细说明。
导电缓冲层502位于第一导电通道层501和第二导电通道层503之间，用于降低第一掺杂区(未标识)和第三掺杂区(未标识)之间的电干扰。在一个例子中，导电缓冲层502的材料为多晶硅，导电缓冲层502通过降低第一掺杂区(未标识)和第三掺杂区(未标识)之间的介电常数，从而防止第一掺杂区(未标识)和第三掺杂区(未标识)之间的电干扰的问题。
参考图21～图23，图形化部分保护层104，直至不露出第二牺牲层302，形成连通孔602，基于连通孔602去除第二牺牲层；图形化部分第二阻挡层212，直至暴露出第一牺牲层301，形成子连通孔601，基于子连通孔601去除第一牺牲层301。
其中，图形化的方式包括但不限于：在保护层104上形成掩膜层，然后基于形成的掩膜层实现图形化上述半导体结构的工艺。
在本实施例中，采用湿法刻蚀的方式去除第一牺牲层301和第二牺牲层302，本领域技术人员清楚，采用湿法刻蚀的方式，针对于某一种半导体材料进行刻蚀，并不影响其他半导体结构；另外，在其他实施例中，可以采用灰化的方式去除第一牺牲层和第二牺牲层，采用灰化工艺去除第一牺牲层和第二牺牲层的去除速率较快，同时也不影响其他半导体结构。
在其他实施例中，若不存在填充第一导线层201所在平面的第一阻挡层211，不存在填充第二导线层202所在平面的第二阻挡层212，参考图24～图26，图形化部分保护层104，直至暴露出第二牺牲层302，去除第二牺牲层302和第一牺牲层301。
参考图27和图28，形成填充空隙的栅极结构700。
具体地，栅极结构700包括栅极氧化层702和金属栅极层701，栅极氧化层覆盖第一导电沟道、第二导电沟道、第一导线层201(参考图2～图4)或隔离层102(参考图5～图7)、第二导线层202暴露出的表面；金属栅极层701用于填充栅极氧化层702之间的间隙，从而形成栅极结构700。
在一个例子中，为了防止第一导线层201和第二导线层202与栅极结构700之间的电串扰问题，在形成上述半导体结构还包括：形成位于第一导线层201与栅极结构700之间的第一绝缘层(未图示)；以及形成位于第二导线层202与栅极结构700之间的第二绝缘层(未图示)。
参考图1～图7(以基底为第一导线层参考图5～图7)，形成电连接第一导线层201的第一导电插塞801，电连接第二导线层202的第二导电插塞802，电连接第四掺杂区(未标识)的第三导电插塞803，电连接栅极结构700的第四导电插塞804，具体地：
若第一导线层201和衬底101分立设置，参考图2和图3，第一导电插塞801贯穿外围绝缘结构103，与第一导线层201电连接。进一步地，第一导电插塞801还贯穿部分第一导线层201，以增大第一导电插塞801与第一 导线层201的接触面积，从而减小第一导电插塞801与第一导线层201之间的接触电阻。
若第一导线层设置在衬底101中，参考图4和图5，第一导电插塞801贯穿外围绝缘结构103和隔离层102，与衬底101中的第一导线层电连接。进一步地，第一导电插塞801还贯穿部分衬底101和第一导线层，以增大第一导电插塞801与第一导线层的接触面积，从而减小第一导电插塞801与第一导线层之间的接触电阻。
第二导电插塞802，贯穿部分外围绝缘结构103，与第二导线层202相接触。进一步地，第二导电插塞802还贯穿部分第二导线层202，以增大第二导电插塞802与第二导线层202的接触面积，从而减小第二导电插塞802与第二导线层202之间的接触电阻。
第三导电插塞803，与第四掺杂区(未标识)相接触。进一步地，第三导电插塞803还贯穿部分第四掺杂区(未标识)，以增大第三导电插塞803与第四掺杂区(未标识)的接触面积，从而减小第三导电插塞803与第四掺杂区(未标识)之间的接触电阻。
第四导电插塞804，与栅极结构700顶部相接触。进一步地，第四导电插塞804还贯穿部分栅极结构700，以增大第四导电插塞804与栅极结构700的接触面积，从而减小第四导电插塞804与栅极结构700之间的接触电阻。
相比于相关技术而言，通过形成垂直设置的第一导电通道层和第二导电通道层，即形成垂直设置的两个导电沟道，导电沟道垂直设置，栅极结构在水平方向上环绕第一导电沟道和第二导电沟道，从而避免导电沟道在水平方向上占用很大的面积。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系， 都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (20)

  1. 一种半导体结构，包括：
    基底，以及位于所述基底上的导电通道结构，所述导电沟道结构包括依次堆叠设置的第一导电沟道层，导电缓冲层和第二导电沟道层；
    所述第一导电通道层包括第一导电沟道以及位于所述第一导电沟道两端的第一掺杂区和第二掺杂区，其中，所述第一掺杂区靠近所述第二导电通道层；
    所述第二导电通道层包括第二导电沟道以及位于所述第二导电沟道两端的第三掺杂区和第四掺杂区，其中，所述第三掺杂区靠近所述第一导电通道层；
    所述导电缓冲层用于降低所述第一掺杂区和所述第三掺杂区之间的电干扰；
    第一导线层，位于所述基底上，在第一方向上延伸，且与所述第一方向上的所述第二掺杂区相接触；
    第二导线层，在第二方向上延伸，且与所述第二方向的所述第一掺杂区和所述第三掺杂区相接触；
    栅极结构，环绕所述第一导电沟道和所述第二导电沟道设置。
  2. 根据权利要求1所述的半导体结构，其中，所述导电通道结构分立设置在所述基底上；
    所述第一导线层与第一方向上设置的所有所述导电通道结构的所述第二掺杂区相接触；
    所述第二导线层与第二方向上设置的所有所述导电通道结构的所述第一掺杂区和所述第三掺杂区相接触；
    所述栅极结构还填充所述第一导线层所在平面和第二导线层所在平面的空隙。
  3. 根据权利要求1或2所述的半导体结构，其中，所述基底包括结构区和连线区，所述连线区设置在所述结构区外围；
    所述连线区的基底上设置有外围绝缘结构，所述第一导线层和所述第二导线层延伸至所述连线区的所述外围绝缘结构中；
    还包括：第一导电插塞和第二导电插塞；
    所述第一导电插塞贯穿所述外围绝缘结构与所述第一导线层相接触；
    所述第二导电插塞贯穿部分所述外围绝缘结构与所述第二导线层相接触。
  4. 根据权利要求3所述的半导体结构，其中，所述第一方向和所述第二方向的延伸夹角大于0°。
  5. 根据权利要求3所述的半导体结构，还包括：
    第三导电插塞，与所述第四掺杂区相接触；
    第四导电插塞，与所述栅极结构顶部相接触。
  6. 根据权利要求1所述的半导体结构，包括：
    所述导电缓冲层与所述第一掺杂区的接触面的高度低于所述第二导线层中心厚度位置的高度，且高于所述第二导线层底部表面的高度；
    所述导电缓冲层与所述第一掺杂区的接触面的高度高于所述第二导线层中心厚度位置的高度，且低于所述第二导线层顶部表面的高度。
  7. 根据权利要求6所述的半导体结构，其中，所述导电缓冲层的厚度小于所述第二导线层厚度的1/3。
  8. 根据权利要求1所述的半导体结构，其中，所述基底包括衬底和隔离层，所述第一导线层位于所述衬底内，所述隔离层位于所述衬底顶部表面，所述第一导电通道层贯穿所述隔离层和部分所述衬底，以使所述第二掺杂区与所述第一导线层相接触。
  9. 根据权利要求1所述的半导体结构，其中，所述基底包括衬底和隔离层，所述隔离层位于所述衬底顶部表面，所述第一导线层位于所述隔离层顶部表面。
  10. 根据权利要求9所述的半导体结构，还包括：包围所述第一导线层设置的第一绝缘层。
  11. 根据权利要求1所述的半导体结构，还包括：包围所述第二导线层设置的第二绝缘层。
  12. 根据权利要求1所述的半导体结构，还包括：保护层，嵌套设置在分立的所有导电沟道结构顶部，与所述第四掺杂区相接触，在垂直于所述基底表面方向上，所述保护层中具有贯穿所述保护层的连通孔，所述栅极结构还填充所述连通孔。
  13. 根据权利要求12所述的半导体结构，其中，所述保护层顶部表面与所述第二导电沟道层的顶部表面齐平。
  14. 根据权利要求1所述的半导体结构，其中，所述第一导电沟道层和所述第二导电沟道层的其中一者为N型导电沟道，另一者为P型导电沟道。
  15. 一种半导体结构的形成方法，包括：
    提供包括结构区和连线区的基底，所述基底包括衬底、第一导线层和隔离层，所述第一导线层在第一方向上延伸；
    在所述结构区的所述基底上形成第一牺牲层，在所述连线区的所述基底上形成外围绝缘结构；
    图形化所述第一牺牲层，形成贯穿所述第一牺牲层的第一通道；
    形成填充所述第一通道且部分位于所述第一牺牲层上的第二导线层，所述第二导线层延伸至所述连线区的所述外围绝缘结构中，且所述第二导线层在第二方向上延伸；
    在所述结构区的所述基底上依次形成第二牺牲层和保护层；
    图形化所述第二牺牲层，形成贯穿所述第二牺牲层和第二通道，所述第一通道和第二通道在所述基底上的投影重合；
    形成填充所述第二通道的第二导电通道层；
    图形化部分所述保护层，直至暴露出所述第二牺牲层，去除所述第二牺牲层和所述第一牺牲层；
    形成填充空隙的栅极结构。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，提供包括结构区和连线区的基底，包括：提供包括结构区和连线区的衬底，在所述结构区的所述衬底上形成隔离层，并在所述隔离层上形成所述第一导线层。
  17. 根据权利要求15所述的半导体结构的形成方法，其中，提供包括结构区和连线区的基底，包括：提供包括结构区和连线区的衬底，在所述结构区的所述衬底中掺杂形成所述第一导线层，并在所述结构区的所述衬底上形成所述隔离层。
  18. 一种半导体结构的形成方法，包括：
    提供包括结构区和连线区的基底，所述基底包括衬底、第一导线层和隔离层，所述第一导线层在第一方向上延伸；
    在所述结构区的所述基底上形成第一牺牲层，在所述连线区的所述基底上形成外围绝缘结构；
    在所述第一牺牲层上形成第二导线层，所述第二导线层延伸至所述连线区的所述外围绝缘结构中，且所述第二导线层在第二方向上延伸；
    在所述结构区的所述基底上依次形成第二牺牲层和保护层；
    图形化所述保护层，所述第二牺牲层和所述第一牺牲层，形成开口，并填充所述开口形成导电通道结构；
    图形化部分所述保护层，直至暴露出所述第二牺牲层，去除所述第二牺牲层和所述第一牺牲层；
    形成填充空隙的栅极结构。
  19. 根据权利要求18所述的半导体结构的形成方法，其中，提供包括结构区和连线区的基底，包括：提供包括结构区和连线区的衬底，在所述结构区的所述衬底上形成隔离层，并在所述隔离层上形成所述第一导线层。
  20. 根据权利要求18所述的半导体结构的形成方法，其中，提供包括结构区和连线区的基底，包括：提供包括结构区和连线区的衬底，在所述结构区的所述衬底中掺杂形成所述第一导线层，并在所述结构区的所述衬底上形成所述隔离层。
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JP2007250652A (ja) * 2006-03-14 2007-09-27 Sharp Corp 半導体装置
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