WO2020224018A1 - 互连结构、电路及包括该互连结构或电路的电子设备 - Google Patents

互连结构、电路及包括该互连结构或电路的电子设备 Download PDF

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WO2020224018A1
WO2020224018A1 PCT/CN2019/089286 CN2019089286W WO2020224018A1 WO 2020224018 A1 WO2020224018 A1 WO 2020224018A1 CN 2019089286 W CN2019089286 W CN 2019089286W WO 2020224018 A1 WO2020224018 A1 WO 2020224018A1
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layer
semiconductor device
interconnection
source
substrate
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PCT/CN2019/089286
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US17/594,753 priority Critical patent/US20220246520A1/en
Priority to DE112019007288.9T priority patent/DE112019007288T5/de
Publication of WO2020224018A1 publication Critical patent/WO2020224018A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors

Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to interconnect structures between device layers, circuits including interconnections between device layers, and electronic devices including such interconnect structures or circuits.
  • the interconnection between the device layers can reduce parasitic resistance and capacitance, thereby reducing the resistance and capacitance (RC) delay and power consumption of the integrated circuit (IC).
  • RC resistance and capacitance
  • IC integrated circuit
  • it is difficult to interconnect between device layers because the interconnection process is not compatible with the device integration process.
  • the purpose of the present disclosure is at least partly to provide an interconnection structure between device layers, a circuit including the interconnection between device layers, and an electronic device including such an interconnection structure or circuit.
  • an interconnection structure for a plurality of semiconductor devices formed on a substrate the interconnection structure is provided under the plurality of semiconductor devices, and includes: At least one via layer and at least one interconnection layer are alternately arranged in the direction of the device toward the substrate, wherein each via layer includes via holes respectively provided under at least a part of the plurality of semiconductor devices, each The interconnection layer includes conductive nodes respectively disposed under at least a part of the semiconductor devices among the plurality of semiconductor devices, wherein, in the same interconnection layer, there is a conductive channel between at least one conductive node and at least another node, and each via The vias in the layers and the corresponding conductive nodes in each interconnection layer at least partially overlap each other in the direction from the semiconductor device to the substrate.
  • a circuit including: a substrate; an interconnection structure provided on the substrate, the interconnection structure including at least one alternately arranged in a direction substantially perpendicular to the surface of the substrate A via layer and at least one interconnection layer, the uppermost layer of the interconnection structure is a via layer; and a plurality of semiconductor devices arranged on the interconnection structure, wherein each via layer includes arranged in rows and columns Via holes at least a part of the points in the two-dimensional lattice, each interconnection layer includes a main body part provided at at least a part of the points in the two-dimensional lattice, and a line or For the extensions extending in the direction of the columns, at least a portion of the adjacent main body portions are in contact with the extensions facing each other, and at least a portion of the source/drain regions of the semiconductor device are in contact with corresponding via holes in the uppermost via layer.
  • a method of manufacturing an interconnection structure for a semiconductor device including: providing at least one first sacrificial layer and at least one second sacrificial layer alternately stacked on a substrate.
  • Stack wherein the uppermost layer of the first stack is the first sacrificial layer; the device active material layer is arranged on the first stack; the first hard mask layer is arranged on the device active material layer, and the first hard mask
  • the mold layer has a grid pattern defined by lines extending in a first direction and a second direction that cross each other, including nodes defined by intersections between the lines and bridging portions between the nodes; using the first hard mask layer , Define the active area for the semiconductor device in the device active material layer; use the first hard mask layer to pattern the first stack, so that each layer in the first stack has the same value as the first hard mask layer Corresponding grid patterns, and therefore include nodes and bridging portions between nodes; and defining an interconnect structure in the first stack, including: for each first
  • an electronic device including the above interconnection structure or circuit.
  • an interconnection structure under the device layer (relative to the substrate) and a manufacturing method thereof are proposed.
  • This structure may be a three-dimensional (3D) structure, and more specifically, the interconnection may be constructed on a 3D grid to realize the interconnection between device layers.
  • This structure can be fabricated by the etch-fill-etch-fill (EFEF) method detailed below to be compatible with the device integration process.
  • EFEF etch-fill-etch-fill
  • the source/drain regions of the device and the vias in the interconnect structure can be self-aligned, and the vias between different layers in the interconnect structure can be self-aligned.
  • the active area of the device can be made of a single crystal semiconductor, so that the device performance can be improved.
  • the technology according to the present disclosure can be well applied under extreme ultraviolet (EUV) lithography.
  • EUV extreme ultraviolet
  • Figures 1 to 52(d) show schematic diagrams of some stages in the process of manufacturing a vertical semiconductor device according to an embodiment of the present disclosure, in which Figures 2(a), 8(a), 9(a), 12(a) ), 14(a), 15(a), 23(a), 25(a), 27(a), 32(a), 35(a), 43(a), 49(a), 52(a ) Is the top view, Figure 1, 2(b), 3, 4(b), 5(b), 6(b), 7(b), 8(b), 10(b), 11(b), 12 (c), 13(b), 14(c), 15(c), 16(b), 17(b), 18(b), 19(b), 20(b), 21(b), 22 (b), 23(c), 24(b), 25(c) are cross-sectional views along the line BB', Figure 4(a), 5(a), 6(a), 7(a), 9( b), 10(a), 11(a), 12(b), 13(a), 14(b), 15(b), 16
  • FIGS. 53 to 66(b) show schematic diagrams of some stages in the process of manufacturing a FinFET according to an embodiment of the present disclosure, in which FIGS. 54(a), 59(a), 60(a) , 62(a), 63(a), 64(a), 65(a), 66(a) are top views, Figures 53, 54(b), 55(b), 56, 59(c), 60( c), 63(c), 64(c) are cross-sectional views along the line BB', Figure 55(a), 57(a), 59(b), 60(b), 61, 62(b), 63 (b), 64(b), 65(b), 66(b) are cross-sectional views along the line AA', Figure 57(b) is the cross-sectional view along the line FF', Figure 57(d), 58, 59 (d) is a cross-sectional view along the line GG', Figure 65(c) is a cross-sectional view along the line HH
  • FIGS. 67 to 70(b) show schematic diagrams of some stages in the process of manufacturing a planar semiconductor device according to an embodiment of the present disclosure, in which FIGS. 68(a), 69(a), 70(a) are top views, and FIG. 67 It is a cross-sectional view along the line BB', and Figures 68(b), 69(b), and 70(b) are cross-sectional views along the line GG'.
  • a layer/element when referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element may be located “under” the other layer/element when the orientation is reversed.
  • an interconnection structure is proposed. Different from forming an interconnection structure such as a metallization above the device after forming a semiconductor device on a substrate in the conventional technology, the interconnection structure according to an embodiment may be disposed under the device, for example, between the device and the substrate.
  • the interconnect structure may include at least one via layer and at least one interconnect layer that are alternately stacked. Each via layer is provided with a via hole, so as to realize electrical connection between the layer below the via hole layer and the layer above (both interconnect layers). Conductive channels are provided in each interconnection layer, so as to realize routing within the interconnection layer.
  • the side of the interconnect structure closest to the device is the via layer, so that electrical connections can be drawn from the corresponding device.
  • the via holes may be respectively located below the corresponding semiconductor device (especially its active region, such as the source/drain region). For example, this is because they can be defined with substantially the same pattern as described below.
  • the via hole and the corresponding semiconductor device especially its active area, such as the source/drain area
  • each via layer not all semiconductor devices, more specifically, have via holes formed under the source/drain regions, but only a part of the source/drain regions (which can be referred to as the "first group of source/drain regions") A via hole is formed below the drain region"), and an insulating part may be formed below another part of the source/drain region (which may be referred to as a “second group of source/drain regions”).
  • the layout of the vias and the insulating parts in the via layer can be determined according to the connection layout required by the circuit design.
  • each interconnection layer there may be conductive nodes under the corresponding semiconductor device (especially its active region, such as source/drain region). Likewise, for example, this is because they can be defined with substantially the same pattern as described below. Thus, the conductive node and the corresponding semiconductor device (especially its active region, such as source/drain region) (and the corresponding via) along the etching direction can at least partially overlap, or even be substantially aligned, for example Center alignment. Similarly, in each interconnection layer, not all semiconductor devices, more specifically, have conductive nodes formed under the source/drain regions, but only a part of the source/drain regions may have conductive nodes formed under them.
  • conductive channels extend between corresponding conductive nodes.
  • the conductive channel can extend hop-by-hop between adjacent conductive nodes, and there is no conductive channel directly connecting non-adjacent conductive nodes (the so-called "direct connection” refers to not passing through other conductive nodes) .
  • the upper layer and the lower layer may have corresponding conductive nodes and be in contact with them, so as to realize the electrical connection between the upper and lower layers.
  • the conductive node there may be no corresponding vias on the upper and lower layers, so that the conductive node can be used as an intermediate node on the conductive channel; or, the upper and/or the next layer can Corresponding vias exist and are in contact with them to achieve electrical connections between layers.
  • each layer in the interconnect structure can present a layout similar to that of a semiconductor device.
  • the layout is called “array”, such as a two-dimensional array arranged in rows and columns (of course, other forms of arrays are also possible), and elements in the layout (for example, semiconductor devices in the device layer, vias) Vias in layers, or conductive nodes in interconnect layers) are called “nodes”.
  • the array of each via layer and the array of the device layer may be basically the same, but some nodes may be missing (as described below, insulating parts may be provided at these nodes).
  • the array of each interconnection layer and the array of the device layer may be basically the same, but some nodes may be missing.
  • conductive nodes may be formed at all nodes.
  • insulating parts can be provided at corresponding positions in the via layer above and below, and the conductive paths between the conductive nodes and the adjacent conductive nodes can be cut off to make them an isolated dummy node. This can make the treatment of conductive nodes in the interconnect layer uniform, thereby making the process easier to perform.
  • the interconnect structure can be a three-dimensional (3D) grid structure as a whole.
  • the conductive channels in each interconnection layer may extend along the sides (e.g., in the row or column direction) of the grid in the array.
  • the vertical type semiconductor device may include an active region extending in a vertical direction (for example, a direction substantially perpendicular to the surface of the substrate).
  • Each node in the interconnect structure may be located below the active region of each vertical semiconductor device in the vertical direction, and may be aligned in the vertical direction, such as centered.
  • the vertical active region may include source/drain regions at the upper and lower ends and a channel region between the source/drain regions.
  • a conductive channel can be formed between the source/drain regions through the channel region.
  • Such an active region can be provided by, for example, a first source/drain layer, a channel layer, and a second source/drain layer that are sequentially stacked.
  • the source/drain region may be formed substantially in the first and second source/drain layers, and the channel region may be formed substantially in the channel layer.
  • the active region, especially the channel layer can take the shape of a nanowire, thereby obtaining a nanowire device.
  • the active region, especially the channel layer may take the shape of a nanosheet, thereby obtaining a nanosheet device.
  • the channel layer may be composed of a single crystal semiconductor material to improve device performance.
  • the first and second source/drain layers can also be made of single crystal semiconductor materials.
  • the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source/drain layer may be eutectic.
  • such a semiconductor device may be a conventional field effect transistor (FET).
  • FET field effect transistor
  • the source/drain regions on both sides of the channel region may have doping of the same conductivity type (for example, n-type or p-type).
  • a conductive channel can be formed between the source/drain regions located at both ends of the channel region through the channel region.
  • such a semiconductor device may be a tunneling FET.
  • the source/drain regions on both sides of the channel region may have doping of different conductivity types (for example, n-type and p-type, respectively).
  • the gate electrode may be formed around at least part of the periphery of the channel region.
  • the gate electrode may be self-aligned to the channel layer.
  • the sidewall on the side of the gate electrode close to the channel layer may be aligned with the outer peripheral sidewall of the channel layer so as to occupy substantially the same range in the vertical direction. In this way, the overlap of the gate electrode and the source/drain region can be reduced or even avoided, which helps to reduce the parasitic capacitance between the gate and the source/drain.
  • the gate electrode may include an extension part extending outward from the main part in addition to surrounding the main body of the channel region.
  • the extension may also extend along the side (for example, the row or column direction) of the grid in the array. At least a part of the extensions of adjacent gate electrodes facing each other may be in contact with each other to be electrically connected to each other.
  • contact plugs for introducing electrical signals into the interconnection structure may also be provided.
  • the contact plugs are in contact with corresponding via holes in the uppermost via layer in the interconnect structure, so as to apply electrical signals to the interconnect structure.
  • the contact plugs can also be located at corresponding nodes in the array.
  • the contact plug may be formed by converting the active area at the corresponding node into a conductive material (for example, a silicide obtained by silicidation), so the contact plug may be self-aligned to the corresponding node ( In other words, the vias at the corresponding nodes). That is, in the array of the device layer, some nodes may be real device active regions, while other nodes may be contact plugs.
  • a contact plug for applying an electric signal to the gate electrode may also be provided.
  • this contact plug can also be formed by converting the active region at the corresponding node into a conductive material ("body portion") as described above.
  • the contact plug may further include an extension portion extending from the body portion so as to be in contact with the gate electrode. The extension may also extend along the side (for example, the row or column direction) of the grid in the array.
  • the semiconductor device may also be in other forms, such as fin field effect transistors (FinFET) or planar semiconductor devices, and their fins or active regions may be along the lateral direction (for example, substantially parallel to the substrate).
  • the direction of the bottom surface extends, for example, it may extend along the side (for example, the direction of the row or the column) of the grid in the array.
  • the source/drain regions of the device can be located at the nodes of the array. In this way, through the interconnection structure formed below, electrical connection to at least part of the source/drain regions in the device array can be achieved.
  • Such an interconnection structure can be manufactured as follows, for example.
  • a first stack of alternately stacked first sacrificial layers and second sacrificial layers may be provided on a substrate.
  • the first stack is then used to form the interconnect structure.
  • the sacrificial layer defining the position of the via layer is referred to as the first sacrificial layer
  • the sacrificial layer defining the position of the interconnection layer is referred to as the second sacrificial layer. Therefore, the uppermost sacrificial layer of the first stack may be one of the first sacrificial layers.
  • the first sacrificial layer and the second sacrificial layer may have etching selectivity relative to each other.
  • a semiconductor material that is subsequently used to form the active region of the device can be provided on the first stack.
  • a second stack of a first source/drain layer, a channel layer, and a second source/drain layer that are sequentially stacked may be provided.
  • the channel layer may have etching selectivity with respect to the first and second source/drain layers.
  • the first source/drain layer and the second source/drain layer may include the same semiconductor material.
  • At least adjacent layers between the first stack and the second stack ie, the topmost layer of the first stack and the bottommost layer of the second stack
  • these layers can be formed by epitaxial growth.
  • each layer especially each layer in the second stack, may be doped separately, so that at least a pair of adjacent layers may have a doping concentration interface.
  • a hard mask layer may be provided on top of the semiconductor material of the active region, such as the second stack.
  • the hard mask layer may have a grid shape.
  • the hard mask layer may include lines arranged in rows and columns. Here, the intersections of rows and columns in the hard mask layer are called “nodes", and the lines between nodes are called “bridging portions”. If a grid pattern is formed in other layers, it can also be called this way.
  • the nodes of the mesh pattern of the hard mask layer may define the body position of the vertical active region, and the line width of the nodes may be increased to be thicker than the bridge portion.
  • the approximate middle of the bridge portion of the mesh pattern of the hard mask layer may define the channel region, and the portions on both sides of the channel region (the node and the surrounding bridge portion) may define the source /Drain area.
  • the hard mask layer can be used to define the active region in the active region semiconductor material, such as the second stack.
  • the pattern of the hard mask layer can be transferred to the second stack.
  • the active region may be located at a position corresponding to each node.
  • the part corresponding to the bridging part in the second stack can be removed (it can be replaced by a supporting material to provide structural support), and the part corresponding to the node in the second stack can be retained to form a plurality of separated structures. Source area.
  • Some active regions can be used to form devices, and other active regions can be subsequently converted into conductive contact plugs, for example by silicidation.
  • the mask layer can be used to define the frame of the interconnect structure in the first stack. This can be achieved by transferring the pattern of the hard mask layer to the first stack, and trimming the pattern in each layer according to the connection design of the interconnect structure.
  • the nodes of the hard mask layer can be used to define the pattern of the via holes therein.
  • the layout of nodes can be transferred to the first sacrificial layer.
  • the bridge portion in the first sacrificial layer may be removed, leaving the nodes in the first sacrificial layer.
  • the nodes in the corresponding first sacrificial layer can be removed or retained according to the via layout in each via layer to achieve the required via layout.
  • the bridge portion in the hard mask layer can be used to define the direction of the conductive channel therein.
  • the pattern of the hard mask layer may be transferred to the second sacrificial layer, and the nodes in the second sacrificial layer may serve as relay points between bridging portions as conductive channels.
  • the nodes in the second sacrificial layer may also be in contact with corresponding nodes in the first sacrificial layer to achieve interconnection between the upper and lower layers.
  • the bridging part in the corresponding second sacrificial layer can be cut off or reserved to realize the required route selection.
  • the trimming of the patterns in the first stack can be performed layer by layer, for example, sequentially from top to bottom.
  • the shielding layer can be used to shield the first laminate, and the shielding layer is gradually etched back downward to expose each layer in the first laminate one by one.
  • the layer below it can be shielded by the shielding layer to avoid being affected.
  • the design between the layers in the interconnect structure is not necessarily the same.
  • the shielding layer is gradually etched back, when the lower layer is processed, the upper layer may be exposed and affected.
  • the part that needs to be retained in the first or second sacrificial layer can be replaced with a different material. This can be achieved by an etch-fill-etch-fill (EFEF) method, which will be described in detail below.
  • EFEF etch-fill-etch-fill
  • the present disclosure can be presented in various forms, some examples of which will be described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.
  • 1 to 52(d) show schematic diagrams of some stages in the process of manufacturing a vertical semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • a well region (not shown) may be formed. If a p-type device is to be formed, the well region may be an n-type well; if an n-type device is to be formed, the well region may be a p-type well.
  • the well region may be formed, for example, by injecting corresponding conductivity type dopants (p-type dopants such as B or In, or n-type dopants such as As or P) into the substrate 1001 and then thermal annealing.
  • p-type dopants such as B or In, or n-type dopants such as As or P
  • a first stack of alternately arranged first sacrificial layers 1003a-1, 1003a-2, 1003a-3 and second sacrificial layers 1003b-1, 1003b-2 can be formed by, for example, epitaxial growth.
  • the first sacrificial layer and the second sacrificial layer may have etching selectivity with respect to each other. Since the material of the active region (generally a semiconductor material) will be formed on the first stack later, the first stack can be formed of semiconductor material to achieve high-quality active region growth.
  • each of the first sacrificial layers 1003a-1, 1003a-2, and 1003a-3 may include SiGe, the atomic percentage of Ge is about 10-40%, and the thickness is about 20-100 nm; the second sacrificial layers 1003b-1, 1003b- 2 may each include Si with a thickness of about 20-100 nm.
  • Each of the first sacrificial layer and the second sacrificial layer may have substantially the same thickness.
  • the number of layers of the first sacrificial layer and the second sacrificial layer may be determined according to the number of via layers and interconnection layers in the interconnect structure to be formed, and is not limited to the number of layers shown in the figure.
  • the lowermost first sacrificial layer 1003a-1 will then be replaced with an isolation layer in order to achieve electrical isolation between the interconnect structure and the substrate.
  • a second stack of the first source/drain layer 1005, the channel layer 1007, and the second source/drain layer 1009 can be formed by, for example, epitaxial growth. These can all be semiconductor materials. As described above, the channel layer and the first and second source/drain layers may have etching selectivity with respect to each other. In addition, in order to facilitate the separate processing of the first stack and the second stack, at least adjacent layers between them may have etching selectivity with respect to each other.
  • the channel layer 1007 may include SiGe, the atomic percentage of Ge may be about 10-40%, and the thickness may be about 20-100 nm; the first source/drain layer 1005 and the second source/drain layer 1009 may include Si with a thickness of About 20-100nm.
  • a contact layer may also be provided.
  • a contact interface layer (not shown) may be formed by, for example, epitaxial growth.
  • the contact interface layer may include, for example, silicon, and may be doped into n-type or p-type by, for example, in-situ doping, preferably the same as the doping type described below in conjunction with FIG. 25, and the doping concentration is about 1E19-5E21cm ⁇ 3 . This can reduce the resistance between the source/drain and the interconnect structure.
  • the contact interface layer since the contact interface layer includes the same material (Si) as the first source/drain layer 1005, it can be subsequently processed like the first source/drain layer 1005.
  • a contact layer (not shown) is formed on the substrate by, for example, epitaxial growth.
  • the contact layer may include, for example, silicon, and may be doped into n-type or p-type by, for example, in-situ doping, preferably the same as the doping type described below in conjunction with FIG. 25, and the doping concentration is about 1E19- 5E21cm -3 .
  • the hard mask layer may include a stacked layer structure, such as a first sublayer 1011 and a second sublayer 1013.
  • the first sub-layer 1011 can be used for protection and/or etch stop.
  • it can include oxide (for example, silicon oxide) with a thickness of about 2-5 nm. It can be formed by deposition or thermal oxidation (formed by thermal oxidation). The oxide quality is better).
  • the second sub-layer 1013 can be used for masking and/or isolation purposes.
  • the hard mask layer can include nitride (e.g., silicon nitride) or low-k dielectric material (e.g., silicon carbide-based material), with a thickness of about 10-100 nm, Can be formed by deposition.
  • nitride e.g., silicon nitride
  • low-k dielectric material e.g., silicon carbide-based material
  • the material of the hard mask layer is not limited to this, but may include materials that can be retained in various subsequent etching processes.
  • the hard mask layer may also include more sub-layers to provide better etching selectivity.
  • the hard mask layer can be patterned into a desired pattern. As described above, a grid pattern can be formed. To this end, as shown in FIGS. 2(a) and 2(b), a photoresist 1015 may be formed on the hard mask layer. The photoresist 1015 is patterned into a grid pattern by photolithography (exposure and development). The nodes of the grid can be thickened to define the location of the active area. Here, the nodes of the mesh are roughly circular, so that nanowire devices can be formed later.
  • the shape of the grid node is not limited to this, but can be any other suitable shape, such as ellipse, rectangle, square, etc., or even a combination of different shapes (some nodes are of one shape, while others Is another shape). In the case of forming rectangular or square nodes, cross-sidewall pattern transfer (xSIT) technology can be used, and then nanosheet devices can be formed.
  • xSIT cross-sidewall pattern transfer
  • the active area can be defined. For example, this can be done as follows.
  • the pattern of photoresist 1015 can be transferred to the hard mask layer and then to the second stack below. Specifically, as shown in FIG. 3, the patterned photoresist 1015 can be used as a mask, and the hard mask layer (1013, 1011), the second source/drain layer 1009, the channel layer 1007 and the first source/drain layer 1009 can be sequentially applied as a mask.
  • the drain layer 1005 is selectively etched such as reactive ion etching (RIE). RIE may be performed in a direction substantially perpendicular to the surface of the substrate, for example, so that the pattern formed in the second stack and the pattern of the hard mask layer may be substantially aligned in the vertical direction.
  • RIE reactive ion etching
  • the etching of the first source/drain layer 1005 does not proceed to the bottom surface of the first source/drain layer 1005.
  • a thin layer of Si was left on the top surface of the first stack.
  • This Si thin layer can then protect the first sacrificial layer 1003a-3 in the first stack when the channel layer 1007 is selectively etched, because in this example the first sacrificial layer 1003a-3 and the channel layer 1007 Both include SiGe.
  • the etching of the first source/drain layer 1005 can also be performed to the bottom surface of the first source/drain layer 1005.
  • the second stack presents the same grid pattern as the hard mask layer. It is desirable to separate the second stack into active regions for individual devices at each node.
  • the first source/drain layer 1005, the channel layer 1007, and the second source/drain layer 1009 may be further selectively etched to remove the bridge portion, leaving the node portion. This is possible because the line width of the node part is relatively thick as described above.
  • the channel layer 1007 may be further selectively etched relative to the first source/drain layer 1005 and the second source/drain layer 1009 (Si) .
  • the amount of etching is controlled so that the bridge portion in the channel layer 1007 is removed (see FIG. 4(b)), and the node portion is retained (see FIG. 4(a)).
  • the channel layer 1007 is separated into a plurality of parts located at each node, and the channel of the device will be formed in these parts. The outer peripheries of these separated parts have a certain concave inward with respect to the outer peripheries of the corresponding nodes in the hard mask layer.
  • atomic layer etching can be used. Due to the existence of the continuous bottom of the first source/drain layer 1005, the first sacrificial layer 1003a-3, which is the same SiGe as the channel layer 1007, may not be affected.
  • a position holding layer 1017 may be formed in the gap of the second stack under the hard mask layer.
  • a dielectric material can be deposited on the structure shown in Figures 4(a) and 4(b) in an amount sufficient to fill the voids in the second stack, and the hard mask layer is used as a mask to deposit The deposited dielectric material is etched back such as RIE. The RIE can be performed in a direction substantially perpendicular to the surface of the substrate, so the dielectric material can be left under the hard mask layer to form the position holding layer 1017.
  • the position holding layer 1017 is filled in the original position of the bridge portion in the channel layer and the node portion is self-aligned to the channel layer and surrounds the outer periphery of the channel layer in the recess formed by the further selective etching. Protect the channel layer.
  • the material of the position holding layer 1017 is selected so that it has etching selectivity with respect to the hard mask layer, such as oxynitride (for example, silicon oxynitride).
  • the first source/drain layer 1005 and the second Two source/drain layers 1009 Si
  • the amount of etching is controlled so that the bridge portion in the first source/drain layer 1005 and the second source/drain layer 1009 is removed (see FIG. 6(b)), while the node portion is retained (see FIG. 6(a)) .
  • the first source/drain layer 1005 and the second source/drain layer 1009 are separated into multiple parts located at each node, and the source/drain regions of the device will be formed in these parts. .
  • the outer peripheries of these separated parts have a certain concave inward with respect to the outer peripheries of the corresponding nodes in the hard mask layer.
  • ALE can be used.
  • the thickness of the continuous thin layer at the bottom of the first source/drain layer 1005 is small, so that it can be removed during this further etching process to expose the first sacrificial layer 1003a-3 for subsequent processing of the first stack.
  • a position holding layer 1019 may be formed in the gap of the second stack under the hard mask layer.
  • the position holding layer 1019 can be formed by the method of forming the position holding layer 1017.
  • the position holding layer 1019 is filled in the positions where the bridge portions of the first source/drain layer 1005 and the second source/drain layer 1009 are originally located and the recesses formed by the further selective etching of the node portions, self-aligning It is aligned with the first source/drain layer 1005 and the second source/drain layer 1009, and surrounds the outer periphery of the first source/drain layer 1005 and the second source/drain layer 1009 to protect the source/drain layer.
  • the material of the position holding layer 1019 is selected so that it has an etching selectivity with respect to the hard mask layer and the position holding layer 1017, such as SiC.
  • the respective separated portions of the etched first source/drain layer 1005, channel layer 1007, and second source/drain layer 1009 form a columnar shape (in this example, the cross-section is a substantially circular columnar shape), which defines Source area.
  • the columnar active region may extend substantially perpendicular to the surface of the substrate.
  • the position of the conductive portion of the interconnect structure (the above-mentioned via, conductive node, conductive channel) can be defined in the first stack.
  • the pattern of the hard mask layer can be transferred to the first stack. Since the second laminate (together with the support material) above the first laminate as described above has been patterned as the hard mask layer, this pattern transfer is possible.
  • the hard mask layer (1013, 1011) can be used as a mask, and the first sacrificial layer 1003a-3, the second sacrificial layer 1003b-2, and the A sacrificial layer 1003a-2, a second sacrificial layer 1003b-1 and a first sacrificial layer 1003a-1 are selectively etched such as RIE.
  • RIE may be performed in a direction substantially perpendicular to the surface of the substrate, for example, so that the pattern formed in the first stack and the pattern of the hard mask layer may be substantially aligned in the vertical direction.
  • the first stack presents the same grid pattern as the hard mask layer.
  • the bridge portion can be removed. This removal can be achieved by further selective etching of the first sacrificial layer as in the above separation of the active region.
  • the remaining nodes in this case are smaller (as described above, the nodes are recessed inward with respect to the hard mask layer).
  • photolithography can be used to make the remaining nodes larger.
  • a photoresist 1021 can be formed on the structure shown in Figures 8(a) and 8(b), and the photoresist 1021 can be patterned with a hard mask.
  • the nodes of the photoresist 1021 can be larger than the nodes of the hard mask layer, so that the nodes left in the subsequent first sacrificial layer can be larger, and can also cover the separate active Area to prevent it from being affected when the first sacrificial layer is etched.
  • a thin layer may be deposited as the hard mask layer, and then the hard mask layer may be patterned using the above photoresist.
  • the first sacrificial layer (SiGe) may be further selectively etched relative to the second sacrificial layer (Si). Then, the bridging portion of the first sacrificial layer exposed by the photoresist 1021 is removed (see FIG. 10(b)), and the node is retained (see FIG. 10(a)) (due to the above-mentioned photoresist 1021 node It is relatively large, so a certain length of bridging part may remain on the periphery of the node of the first sacrificial layer). Subsequently, the photoresist 1021 may be removed.
  • the frame of the interconnect structure is defined in the first stack, and then the patterns in the first stack (node patterns in the first sacrificial layer, and node patterns in the second sacrificial layer) can be adjusted according to the connection design of the interconnect structure. Grid pattern) for trimming. This trimming can be done layer by layer.
  • a dielectric layer may be formed in the gap between the first stack and the second stack.
  • a dielectric layer 1023 (for example, oxide) may be formed on the substrate 1001 by, for example, deposition.
  • the deposited dielectric layer 1023 may be planarized, such as chemical mechanical polishing (CMP), and the CMP may stop at the second sub-layer 1013 of the hard mask layer.
  • CMP chemical mechanical polishing
  • the top surface of the dielectric layer 1023 may be substantially coplanar with the top surface of the second sub-layer 1013.
  • the top surface (in a specific area) of the dielectric layer 1023 can be gradually lowered to sequentially expose the layers in the first stack, so as to achieve layer-by-layer trimming.
  • each second sacrificial layer there is a bridge between each node.
  • the bridging part between some nodes can be cut off, so as to define a path that conforms to the connection design in the corresponding interconnection layer.
  • a processing channel to the bridge part is required.
  • an opening exposing the bridge portion may be formed in the dielectric layer 1023.
  • This can be achieved by using an additional hard mask layer.
  • another hard mask layer may be formed on the top surface of the dielectric layer 1023 and the top surface of the hard mask layer (1011/1013).
  • the hard mask layer may also include, for example, a first sublayer 1025 having a thickness of about 2-10 nm, and a second sublayer having a thickness of about 10-150 nm, such as nitride or low-k dielectric material. 1027 stacks. Regarding the first sublayer 1025 and the second sublayer 1027, see also the description of the first sublayer 1011 and the second sublayer 1013 above.
  • the hard mask layer can be patterned into a desired pattern, as described above, to expose the bridge portion.
  • a photoresist 1029 may be formed on the hard mask layer.
  • the photoresist 1029 is patterned by photolithography (exposure and development) to include a series of openings, which are respectively located at each bridge portion, such as the middle of each bridge portion.
  • the opening is shown as an ellipse, but the present disclosure is not limited to this, and may also be in various shapes suitable for processing, such as a circle.
  • the photoresist 1029 can be used as a mask to selectively etch the second sub-layer 1027 (nitride), such as RIE.
  • RIE may be performed in a direction substantially perpendicular to the surface of the substrate, and may stop at the first sub-layer 1025 (oxide).
  • the first sub-layer 1025 and the dielectric layer 1023 may be selectively etched such as RIE.
  • RIE can be performed in a direction substantially perpendicular to the surface of the substrate, and can be performed until the uppermost second sacrificial layer 1003b-2 is exposed, thereby forming a processing channel T1, as shown in FIG. 14(c).
  • the bottom surface of the processing channel T1 may be located between the top surface and the bottom surface of the first sacrificial layer 1003a-2 under the second sacrificial layer 1003b-2 that needs to be exposed, on the one hand, to ensure that the second sacrificial layer 1003b-2 is fully exposed, On the other hand, avoid exposing the second sacrificial layer 1003b-1 underneath.
  • ALE can be used. After that, the photoresist 1029 may be removed.
  • each processing channel T1 is located approximately in the middle of each bridge portion, and each node (hence, the active area and the first sacrificial layer located at each node) are shielded.
  • the remaining exposed material layers are all dielectric materials (hard mask layers of oxide and nitride, oxynitride The object position holding layer 1017, the SiC position holding layer 1019, and the oxide dielectric layer 1023).
  • All current bridging parts (specifically the middle part) are exposed in the corresponding processing channel T1. Among these bridge parts, some bridge parts need to be cut off, while other bridge parts need to be retained. The bridged parts that need to be cut off and the bridged parts that need to be reserved can be processed separately.
  • the routing in each interconnection layer is not necessarily the same.
  • the bridging part of one layer for example, the upper layer
  • the bridging part of the other layer for example, the lower layer
  • Need to be cut off when the bridge portion of the next layer is cut through the processing channel T1, the bridge portion of the upper layer that can also be exposed in the processing channel T1 because it is located above (including the same material as the next layer, both The second sacrificial layer) can also be cut off.
  • the bridge portion that needs to be retained can be replaced with a material having etching selectivity with respect to the second sacrificial layer to avoid being affected when the second sacrificial layer is processed below.
  • FIGS. 15(a), 15(b), and 15(c) you can use the structure shown in FIGS. 14(a), 14(b), and 14(c) (with the photoresist 1029 removed) A photoresist 1031 is formed, and the photoresist 1031 is patterned by photolithography to expose the processing channel T1 where the bridge portion needs to be reserved, and cover the processing channel T1 where the bridge portion needs to be cut.
  • the second sacrificial layer 1003b-2 (Si) is selectively etched (first etching). In this way, the part of the second sacrificial layer 1003b-2 in these exposed processing channels T1 will be removed. Thus, a gap is formed where a portion of the second sacrificial layer 1003b-2 bridges the portion. After that, the photoresist 1031 can be removed.
  • the position holding layer 1033-2b can be filled (first filling) into the gap of the bridge portion of the second sacrificial layer 1003b-2 through the processing channel T1.
  • the position maintaining layer 1033-2b may include a material having etching selectivity with respect to the second sacrificial layer (Si), such as SiGe, and the atomic percentage of Ge may be about 25-75%.
  • This filling can be achieved by depositing SiGe through the processed channel T1, and then etching back the deposited SiGe (relative to the surrounding dielectric material) such as RIE. RIE can be performed in a direction substantially perpendicular to the surface of the substrate. Due to the existence of the hard mask layer 1011/1013, the etched back SiGe can be completely filled in the gap of the bridge portion and extend along the corresponding bridge portion.
  • the processing channel T1 can be used to compare other material layers exposed in the processing channel T1 (for example, the above-mentioned dielectric material and the SiGe position holding layer 1033-2b),
  • the second sacrificial layer 1003b-2 (Si) is selectively etched (second etching).
  • second etching the portion of the second sacrificial layer 1003b-2 in the processing channel T1 originally covered by the photoresist 1031 will be removed.
  • the bridge portion replaced by the position holding layer 1033-2b above is also exposed in the processing channel T1, it may be basically unaffected here due to the etching selectivity.
  • the insulating portion 1035-2b may be filled (second filling).
  • the insulating portion 1035-2b may include, for example, SiC. This filling can be achieved by deposition and then etch back as described above. Similarly, the insulating portion 1035-2b can be completely filled in the gap of the bridge portion and extend along the corresponding bridge portion.
  • the second sacrificial layer 1003b-2 is passed through the insulating portion 1035-2b through the above-mentioned first etching-first filling-second etching-second filling (EFEF) process
  • EFEF first etching-first filling-second etching-second filling
  • the dielectric layer 1023 may be selectively etched, such as RIE, to deepen the processing channel T1, thereby exposing the second sacrificial layer 1003b- 1.
  • the bottom surface of the processing channel T1 may be located between the top surface and the bottom surface of the first sacrificial layer 1003a-1 under the second sacrificial layer 1003b-1 to be exposed.
  • ALE can be used. Then, the above-mentioned EFEF process can be performed through the deepened processing channel T1 to realize the desired route selection on the second sacrificial layer 1003b-1.
  • the structure shown in Figures 18(a) and 18(b) can be used (the processing channel T1 has been deepened as described above)
  • a photoresist (not shown) is formed thereon, and is patterned to expose the processing channel T1 where the bridge portion needs to be retained, and cover the processing channel T1 where the bridge portion needs to be cut.
  • the pattern of the photoresist may be different from the pattern of the above-mentioned photoresist 1031, such as exposing/covering different processing channels T1.
  • the exposed bridging portion of the second sacrificial layer 1003b-1 can be replaced with the position maintaining layer 1033-1b through etching and filling processing.
  • the position holding layer 1033-1b see the above description about the position holding layer 1033-2b.
  • the photoresist can be removed.
  • the bridge portion of the second sacrificial layer 1003b-1 in the processing channel T1 originally covered by the photoresist can be replaced with the insulating portion 1035-1b through etching and filling processing.
  • the insulating portion 1035-1b refer to the above description of the insulating portion 1035-2b.
  • the position holding layer 1033-2b and the insulating portion 1035-2b formed above for the second sacrificial layer 1003b-2 are also exposed in the processing channel T1, due to the etching selectivity, they may be basically unaffected here.
  • the structure shown in Figs. 19(a) and 19(b) is obtained.
  • the second sacrificial layer 1003b-1 is isolated into different parts by the insulating portion 1035-1b, and these parts can then form (a part of) different conductive channels.
  • the position holding layers 1033-1b and 1033-2b (also SiGe in this example, the Ge atomic percentage may be different) may be caused As a result, the position holding layers 1033-1b and 1033-2b can be replaced with new position holding layers having etching selectivity with respect to the first sacrificial layer.
  • the position holding layers 1033-1b, 1033-2b can be processed relative to the second sacrificial layer (Si) and the surrounding dielectric material through the processing channel T1. SiGe) is selectively etched to remove it.
  • new position maintaining layers 1037-1b, 1037-2b can be filled at the original positions of position maintaining layers 1033-1b, 1033-2b by a method of deposition and then etch back.
  • the position maintaining layers 1037-1b, 1037-2b may include Si, such as polysilicon or amorphous silicon formed by deposition such as chemical vapor deposition (CVD).
  • the processing channel T1 can be shielded to prevent the corresponding bridge part from being affected in the subsequent processing.
  • an oxide can be deposited on the structure shown in Figs. 20(a) and 20(b) in an amount sufficient to fill the voids in the structure .
  • the deposited oxide can be planarized, such as CMP, and the CMP can be stopped at the second sub-layer 1027 of nitride.
  • the respective layers 1011, 1023, 1025 that are also oxides and the oxide formed here are collectively shown as 1039.
  • the previously formed hard mask layer 1025/1027 is used to define the processing channel T1 to the bridge portion, which can be removed here.
  • hot phosphoric acid is used to select the second sub-layer 1027 of nitride Etch to remove it.
  • a planarization treatment such as CMP can be performed on the resulting structure, and the CMP can stop at the second sub-layer 1013 of nitride. In this way, the hard mask layer 1025/1027 defining the processing channel T1 is removed, and the hard mask layer 1011/1013 with a grid pattern still exists.
  • pattern trimming can be performed on the first sacrificial layer.
  • each node exists in each first sacrifice layer. Some nodes can be removed according to the layout design of each via layer. In order to remove the node, a processing channel to the node is required.
  • the trimming of the first sacrificial layer can be performed in substantially the same manner as the trimming of the second sacrificial layer, except that the location of the processing channel is different.
  • an opening exposing the node may be formed in the dielectric layer 1039.
  • This can be achieved by using an additional hard mask layer.
  • another hard mask can be formed on the top surface of the dielectric layer 1039 and the top surface of the hard mask layer (1011/1013).
  • Mask layer may also include, for example, a first sublayer 1041 having a thickness of about 2-10 nm, and a second sublayer having a thickness of about 10-150 nm, such as nitride or low-k dielectric material. 1043 stacks. Regarding the first sub-layer 1041 and the second sub-layer 1043, see also the description of the first sub-layer 1011 and the second sub-layer 1013 above.
  • the hard mask layer can be patterned into a desired pattern, as described above, to expose the nodes.
  • a photoresist 1045 may be formed on the hard mask layer.
  • the photoresist 1045 is patterned by photolithography (exposure and development) to include a series of openings, which are respectively located at each node, for example approximately centered at each node.
  • the outer periphery of the opening may protrude outward relative to the outer periphery of the node in the hard mask layer 1011/1013.
  • the size of the opening may be larger than the node size of the photoresist 1021 used to define the node in the first sacrificial layer as described above with reference to FIG. 9(a).
  • the opening is shown as a circular shape, but the present disclosure is not limited to this, and may also be various shapes suitable for processing, such as an oval shape.
  • the processing channel can be formed.
  • the photoresist 1045 can be used as a mask, and the second sub-layer 1043 (nitride) can be selectively etched such as RIE.
  • RIE may be performed in a direction substantially perpendicular to the surface of the substrate, for example, and may stop at the first sub-layer 1041 (oxide).
  • the first sub-layer 1041 and the dielectric layer 1039 may be selectively etched such as RIE.
  • RIE can be performed in a direction substantially perpendicular to the surface of the substrate, and can be performed until the uppermost first sacrificial layer 1003a-3 is exposed, thereby forming a processing channel T2, as shown in FIG. 24(c).
  • the bottom surface of the processing channel T2 may be located between the top surface and the bottom surface of the second sacrificial layer 1003b-2 under the first sacrificial layer 1003a-3 that needs to be exposed, on the one hand, to ensure that the first sacrificial layer 1003a-3 is fully exposed, On the other hand, avoid exposing the underlying first sacrificial layer 1003a-2.
  • ALE can be used. After that, the photoresist 1045 can be removed.
  • each processing channel T2 is roughly centered at each node, and each bridge part is basically shielded (some part of it may be exposed in the processing channel T2, which is also the above pair of position holding layers 1033-1b, 1033-
  • the reason for the replacement of 2b is that the position holding layers 1033-1b and 1033-2b may be exposed from the processing channel T2, especially in the case of device miniaturization).
  • the remaining exposed material layers are all dielectric materials (hard mask layers of oxides and nitrides, oxynitride
  • the position holding layer 1037-2b is also exposed in the processing channel T2. Note that in the cross-section of FIG. 24(c), the first sacrificial layer 1003a-3 is not seen, because the position of the CC' line is at the bridging part (see FIG. 23(a)), and the first sacrificial layer 1003a-3 is not seen as described above.
  • the bridging part of a sacrificial layer has been basically removed.
  • All current nodes are exposed in the corresponding processing channel T2. Among these nodes, some nodes need to be removed (replaced with insulating parts), and some nodes need to be retained.
  • the nodes that need to be removed and the nodes that need to be retained can be processed separately. As described above, in order to avoid the mutual interference of the processing of the various layers, the nodes that need to be retained can be replaced with materials that have etching selectivity with respect to the first sacrificial layer.
  • photolithography can be formed on the structure shown in FIGS. 24(a), 24(b), and 24(c) (with the photoresist 1045 removed).
  • the photoresist 1047 is patterned by photolithography to expose the processing channel T2 where the nodes need to be retained, and cover the processing channel T2 where the nodes need to be removed.
  • the processing channel T2 that can be exposed through the photoresist 1047 can replace the first sacrificial layer 1003a-3 with the position maintaining layer 1037-3a by a method similar to the above-mentioned first etching and first filling.
  • the position maintaining layer 1037-a may include a material having etching selectivity with respect to the first sacrificial layer, such as Si.
  • FIG. 25(f-1) to 25(f-4) show this process in detail.
  • FIG. 25(f-1) shows a processing channel T2 where the photoresist 1047 is exposed.
  • the exposed first sacrificial layer 1003a-3 SiGe here
  • the photoresist 1047 may be removed.
  • FIG. 25(f-3) through the processing channel T2, (polycrystalline or amorphous) silicon 1037p can be deposited (which can be doped into n-type or p-type by, for example, in-situ doping.
  • the impurity concentration is about 1E19-5E21cm -3 ), and the deposited silicon 1037p is etched back, such as RIE, to fill the position holding layer 1037-3a where the node of the first sacrificial layer 1003a-3 was removed. . Multiple depositions and etch-backs can be performed to better fill the position maintaining layer 1037-3a.
  • part of the nodes of the first sacrificial layer 1003a-3 is removed.
  • This part of the node of the first sacrificial layer 1003a-3 can be replaced with an insulating part by a method similar to the above-mentioned second etching and second filling.
  • the first sacrificial layer 1003a-3 SiGe
  • the first sacrificial layer 1003a-3 can be selectively etched through the processing channel T2. In this way, the part of the first sacrificial layer 1003a-3 in the processing channel T2 originally covered by the photoresist 1047 will be removed.
  • the insulating portion 1035-3a can be filled.
  • the insulating portion 1035-3a may include the same dielectric material such as SiC as the previous insulating portions 1035-1b, 1035-2b. This filling can be achieved by etchback after deposition as described above.
  • the dielectric layer 1039 may be selectively etched, such as RIE, to deepen the processing channel T2, thereby exposing the first sacrificial layer 1003a-2.
  • the bottom surface of the processing channel T2 may be located between the top surface and the bottom surface of the second sacrificial layer 1003b-1 under the first sacrificial layer 1003a-2 to be exposed. Then, the above-mentioned EFEF process can be performed through the deepened processing channel T2 to realize the desired via layout in the first sacrificial layer 1003a-2.
  • a photoresist 1053 can be formed on the structure of FIG. 26 (the processing channel T2 has been deepened), and the pattern is The processing channel T2 in which the node needs to be retained is exposed, and the processing channel T2 in which the node needs to be removed is covered.
  • the pattern of the photoresist 1053 may be different from the pattern of the photoresist 1047 described above.
  • the exposed nodes of the first sacrificial layer 1003a-2 can be replaced with position retention through etching and filling processes.
  • Layer 1037-2a Regarding the position holding layer 1037-2a, refer to the description of the position holding layer 1037-3a above.
  • the photoresist 1053 can be removed.
  • FIGS. 29(a) and 29(b) through the processing channel T2, the first sacrificial layer 1003a-2 can be placed in the processing channel T2 originally covered by the photoresist 1053 through etching and filling processing.
  • the node in is replaced with insulating part 1035-2a.
  • the insulating portion 1035-2a refer to the above description of the insulating portion 1035-3a.
  • FIG. 30 shows that the layers in the first stack are aligned as described above (in fact, in this example, since the bottommost first sacrificial layer 1003a-1 is finally used to define the isolation layer, there is no need to pattern it (Further modification) The structure obtained after EFEF processing. As indicated by the arrows in the figure, in the first stack, different interconnection paths are defined.
  • the lowermost first sacrificial layer 1003a-1 can be replaced with an insulating material to achieve isolation between the interconnection structure and the substrate.
  • the processing channel T2 can be further deepened to expose the first sacrificial layer 1003a-1.
  • the etch back of the dielectric layer 1039 may stop at the surface of the substrate 1001, so that the bottom surface of the processing channel T2 may be defined by the top surface of the substrate 1001.
  • the exposed first sacrificial layer 1003a-1 is selectively etched to remove it.
  • a dielectric material such as an oxide can be filled in the voids of the resulting structure to achieve electrical isolation.
  • the amount deposited is sufficient to fill the voids in the structure.
  • a planarization treatment such as CMP may be performed on the deposited oxide, and the CMP may stop at the second sub-layer 1043 of nitride.
  • all oxides in the structure are collectively shown as 1055.
  • the previously formed hard mask layer 1041/1043 is used to define the processing channel T2, which can be removed here.
  • the second sub-layer 1043 of nitride can be selectively etched by hot phosphoric acid to remove it.
  • a planarization process such as CMP may be performed on the resulting structure, and the CMP may stop at the second sub-layer 1013 of nitride.
  • the hard mask layer 1041/1043 defining the processing channel T2 is removed, and the hard mask layer 1011/1013 of the grid pattern still exists, as shown in FIGS. 32(a) and 32(b).
  • the second sacrificial layer is trimmed layer by layer, and then the first sacrificial layer is trimmed layer by layer.
  • the present disclosure is not limited to this.
  • the first sacrificial layer may be trimmed layer by layer, and then the second sacrificial layer may be trimmed layer by layer.
  • a vertical device can be fabricated based on each active region in the second stack.
  • the dielectric layer 1055 can be etched back to expose the second stack.
  • the dielectric layer 1055 may be etched back such as RIE.
  • RIE can be performed in a direction substantially perpendicular to the surface of the substrate, and can be performed until the second stack is exposed.
  • the top surface of the dielectric layer 1055 after etch back can be between the top and bottom surfaces of the uppermost layer in the first stack. between.
  • ALE can be used. Due to the presence of the hard mask layer 1011/1013, the exposed second laminate layer presents a grid pattern. Then, as shown in FIGS. 33(a) and 33(b-2), the position holding layer 1019 may be selectively etched to remove it, thereby exposing the first source/drain layer 1005 and the second source/drain layer 1009.
  • the exposed first source/drain layer 1005 and second source/drain layer 1009 may be doped to form source/drain regions therein. According to an embodiment of the present disclosure, doping may be performed by a solid-state dopant source. However, the present disclosure is not limited to this.
  • the first source/drain layer 1005 and the second source/drain layer 1009 can be doped in situ when they are grown, or they can be doped by ion implantation or the like.
  • a solid dopant source layer 1057 may be formed on the surfaces of the first source/drain layer 1005 and the second source/drain layer 1009.
  • the solid dopant source layer 1057 may include an oxide film containing n-type dopants with a thickness of about 0.5-5 nm.
  • the n-type dopant may include P or As, and the content is about 0.01-3%.
  • the solid dopant source layer 1057 can be formed on the structure shown in FIGS.
  • a diffusion barrier layer 1059 may be formed on the solid dopant source layer 1057.
  • the diffusion barrier layer 1059 may include SiC with a thickness of about 1-5 nm.
  • the diffusion barrier layer 1059 may be formed on the solid dopant source layer 1057 in a substantially conformal manner by deposition such as CVD or ALD.
  • the solid dopant source layer 1057 for the n-type device is formed above.
  • a solid dopant source layer for the p-type device may be additionally formed.
  • a photoresist 1061 may be formed on the structure shown in FIGS. 34(a) and 34(b). Photolithography can be used to mask the region where the n-type device is to be formed by the photoresist 1061 and therefore the n-type solid dopant source layer 1057 in the region, thereby exposing the region where the p-type device is to be formed and therefore the region The n-type solid dopant source layer 1057.
  • the exposed diffusion barrier layer 1059 and the n-type solid dopant source layer 1057 can be sequentially etched by selective etching, such as by gas phase HF, to remove them. During the etching process, the exposed part of the first sub-layer 1011 of the oxide in the hard mask layer may also be removed. After that, the photoresist 1061 may be removed.
  • a solid dopant source layer 1063 for p-type devices can be formed.
  • the p-type solid dopant source layer 1063 may include an oxide film containing p-type dopants with a thickness of about 0.5-5 nm.
  • the p-type dopant may include B in an amount of about 0.01-3%.
  • the solid dopant source layer 1063 may be formed in a substantially conformal manner by deposition such as CVD or ALD.
  • the present disclosure is not limited to this, and their formation order can be exchanged.
  • the dopants in the dopant source layer can be driven into the corresponding first source/drain layer 1005 and second source/drain layer 1009 by annealing to form source/drain regions therein.
  • n-type doping and p-type doping are shown in different gray scales.
  • the concentration of the n-type doping may be about 1E18-1E21 cm ⁇ 3
  • the concentration of the p-type doping may be about 1E18-1E21 cm ⁇ 3 .
  • each solid dopant source layer and diffusion barrier layer can be removed by selective etching such as gas phase HF.
  • a gate electrode can be formed around the outer circumference of the channel layer to complete the fabrication of the device.
  • the original position holding layer around the source/drain layer can be restored.
  • a position holding layer 1065 may be formed in the void of the second stack under the hard mask layer.
  • the position holding layer 1065 refer to the description of the position holding layer 1019 above.
  • a silicide layer may be formed on the surfaces of the first source/drain layer 1005 and the second source/drain layer 1009.
  • a metal such as NiPt, Co, or Ti with a thickness of about 0.5-5 nm can be deposited in a substantially conformal manner, and annealed to make the deposited metal and the first source/drain layer 1005 and the second
  • the second source/drain layer 1009 (Si) reacts to form a silicide (not shown). After that, unreacted metals can be removed.
  • a gate stack can be formed.
  • different gate stacks for example, with different equivalent work functions
  • the gate dielectric layer 1067 can be formed around the surface of the channel layer 1007 by deposition.
  • the gate dielectric layer 1067 may be formed on the structure shown in FIGS. 38(a) and 38(b) in a substantially conformal manner, and the thickness is, for example, about 1-5 nm.
  • the gate dielectric layer 1067 may include a high-k gate dielectric such as HfO 2 .
  • an interface layer may be formed on the surface of the channel layer 1007, such as an oxide formed by thermal oxidation, with a thickness of about 0.3-2 nm.
  • a gate electrode material can be formed on the structure shown in Figs. 39(a) and 39(b).
  • work function adjustment metal for n-type devices can be deposited, and optionally gate conductive metal can also be deposited to completely fill voids in the structure.
  • the deposited gate electrode material is etched back, such as RIE, to obtain a gate electrode 1069.
  • RIE can be performed in a direction substantially perpendicular to the surface of the substrate. Due to the existence of the hard mask layer 1011/1013, the gate electrode 1069 after etch back also has a grid pattern. That is, the gate electrode 1069 may be located at the original position of the position holding layer 1017, and thus self-aligned to the channel layer 1007.
  • the gate electrode 1069 for the n-type device is formed above. It is also possible to additionally form a gate electrode for a p-type device.
  • a photoresist 1071 may be formed on the structure shown in FIGS. 40(a) and 40(b).
  • the photoresist 1071 can mask the area where the n-type device is to be formed and therefore the gate electrode 1069 in the area, while exposing the area where the p-type device is to be formed and therefore the gate electrode 1069 in the area.
  • the exposed gate electrode 1069 can be etched by selective etching to remove it. After that, the photoresist 1071 can be removed.
  • the gate electrode 1073 for the p-type device may be formed in the space freed by the removal of the gate electrode 1069.
  • the gate electrode 1073 may be formed in the same manner as the gate electrode 1069, but may include different materials (for example, having different work functions). Similarly, the gate electrode 1073 may be self-aligned to the channel layer 1007.
  • the gate stacks of the n-type device and the p-type device share the same gate dielectric layer 1067.
  • the present disclosure is not limited to this.
  • the gate dielectric layer 1067 can also be removed in the p-type device region, and another gate dielectric layer for the p-type device is formed.
  • the order of forming the gate stack of the n-type device and the stack of the p-type device can be exchanged.
  • the gate electrodes 1069 and 1073 exhibit the same grid pattern as the hard mask layer 1011/1013 as a whole, so the gate electrodes are connected as a whole on the plane where the channel layer 1007 is located by the bridge portion.
  • the unnecessary connections between the gate electrodes can be cut off according to the connection design of the circuit.
  • a photoresist 1075 may be formed on the structure shown in FIGS. 42(a) and 42(b).
  • the photoresist 1075 can be patterned by photolithography to cover the connections between the gate electrodes that need to be retained, and expose the connections between the gate electrodes that need to be cut. Then, the exposed gate electrode can be etched by selective etching to remove them. As shown in Fig. 43(b), the gate electrode is cut. Then, the photoresist 1075 can be removed.
  • a dielectric material such as SiC may be filled to form an insulating portion 1077 to realize isolation between the gate electrodes. The filling of the insulating portion 1077 can be achieved by the method of deposition and then etch back as described above, and therefore can be consistent with the pattern of the hard mask 1011/1013, at the position where the gate electrode was removed.
  • interconnect fabrication includes forming conductive paths in the first stack, forming contact plugs for applying electrical signals to the conductive channels or gate electrodes in the first stack, and the like.
  • the interconnection channels have been defined by the semiconductor material (in this example, silicon) (the other parts in the first stack are dielectric materials to achieve electrical isolation).
  • These semiconductor materials in the first stack can be replaced or converted into conductive materials to form an interconnect structure.
  • these semiconductor materials can be converted into conductive silicides through a silicidation reaction.
  • these semiconductor materials can be replaced with other conductive materials.
  • the silicidation reaction is described as an example.
  • a protective layer 1079 can be formed to cover and thereby protect the gate electrode.
  • the protective layer 1079 in the form of a side wall can be formed by a side wall forming process.
  • a layer of SiC with a thickness of about 1-5 nm can be deposited on the structure shown in FIG. 44 in a substantially conformal manner, and the deposited SiC may be subjected to RIE in a direction substantially perpendicular to the surface of the substrate to remove it.
  • the laterally extending part is left, and the vertically extending part is left, thereby obtaining the protective layer 1079.
  • the protective layer 1079 may be formed around the outer periphery of each node and the bridge portion in the second stack, so as to cover the gate electrode formed around the channel layer.
  • the first stack is currently covered by a dielectric layer 1055.
  • the dielectric layer 1055 such as RIE can be etched back (of course, after the dielectric layer 1055 is etched back, the gate dielectric layer 1067 on the surface needs to be selectively etched. Such as RIE).
  • ALE can be used.
  • the dielectric layer 1055 may be further selectively etched to expose the sidewalls of the semiconductor material in the first stack.
  • the amount of etching can be controlled so that the bottom of the dielectric layer 1005 still remains covering the substrate 1001.
  • ALE can be used.
  • silicidation can be performed through their exposed sidewalls.
  • a metal such as NiPt, Co, or Ti with a thickness of about 1-10 nm can be deposited, and annealed to cause the deposited metal to react with the semiconductor material (Si) in the first stack to form a silicide 1081. After that, unreacted metals can be removed.
  • the first source/drain layer 1005 can be connected to the silicide 1081 through the contact interface layer, so that reduced contact resistance can be obtained.
  • the silicidation of the semiconductor material in the first stack is performed after the gate electrode is formed. This is because the high-k metal gate can adapt to a larger range of heat treatment (temperature), which can give a larger process window.
  • the present disclosure is not limited to this.
  • the device can be fabricated in the second stack.
  • the dielectric layer can be supplemented to achieve electrical isolation.
  • an oxide can be deposited on the structures shown in FIGS. 47(a), 47(b) and 47(c), and the deposited oxide can be etched back to form a dielectric layer 1055' .
  • the deposited oxide may be planarized, such as CMP, and the CMP may stop at the second sub-layer 1013 of nitride.
  • the top surface of the etched back dielectric layer 1055 ′ may be located near the boundary between the first stack and the second stack to expose the protective layer 1079.
  • the contact plug can be made.
  • Such contact plugs may be connected to the interconnect structure in the first stack, or may be connected to the gate electrodes in order to apply electrical signals to them.
  • this contact plug can be formed by replacing or converting part of the active area into a conductive material, so that it can be self-aligned to the gate electrode to be connected or the via hole in the interconnect structure.
  • each active area is covered by a protective layer 1079.
  • the contact plug can be formed by removing the protective layer 1079 around the active region that needs to be converted or replaced with a contact plug, and silicidating the active region exposed thereby.
  • a photoresist 1083 may be formed on the structure shown in FIG. 48.
  • a series of openings can be formed in the photoresist 1083 by photolithography, and these openings are located at nodes where contact plugs need to be formed.
  • the exposed protective layer 1079 can be removed by selective etching through the opening in the photoresist 1083, and the gate dielectric layer, gate electrode, etc. exposed due to the removal of the protective layer 1079 can be sequentially removed to expose the corresponding active area Side wall. After that, the photoresist 1083 may be removed.
  • the gate electrodes between the active regions with exposed sidewalls and the adjacent active regions that might otherwise be connected together are also cut off.
  • the connection between the gate electrodes is determined according to the connection layout of the circuit.
  • the gaps of the first stack can be filled under the hard mask layer.
  • the semiconductor materials 1085 such as deposited polysilicon or amorphous silicon, can also be replaced or converted into conductive materials later.
  • silicidation can be performed to convert the semiconductor material not covered by the protective layer 1079 into conductive silicide to serve as a contact Plug 1087.
  • silicidation process please refer to the previous description, which will not be repeated here.
  • a part of the contact plug may be in contact with the interconnect structure below to apply an electrical signal to the interconnect structure.
  • part of the contact plugs are electrically isolated from the interconnection structure below by the insulating portion 1035-3a, and these contact plugs can be used to connect the gate electrode Apply electrical signals.
  • the contact plug 1087 contacts the gate electrode 1073 through the laterally extending portion. As described above, this laterally extending portion is aligned with the bridging portion in the grid pattern of the hard mask layer and is located at the original position of the gate electrode.
  • contact portions may be formed above the device.
  • a dielectric layer such as an oxide (here, still shown as 1055') can be deposited to fill the structure To achieve electrical isolation between devices.
  • a contact 1091 penetrating the hard mask layer and/or the dielectric layer 1055' may be formed to apply electrical signals to the upper source/drain regions and the contact plugs. These contacts can be formed by etching holes and filling them with conductive materials such as metals.
  • FIGS. 53 to 66(b) show schematic diagrams of some stages in the process of manufacturing FinFET according to an embodiment of the present disclosure.
  • differences from the above-mentioned embodiment will be mainly described, and the description overlapping with the above-mentioned embodiment will be simplified or omitted.
  • a first stack of alternately disposed first sacrificial layers 2003a-1, 2003a-2, 2003a-3 and second sacrificial layers 2003b-1, 2003b-2 may be formed on the substrate 2001.
  • the substrate 2001 and the first sacrificial layers 2003a-1, 2003a-2, 2003a-3 and the second sacrificial layers 2003b-1, 2003b-2 please refer to the above about the substrate 1001 and the first sacrificial layer 1003a-1 , 1003a-2, 1003a-3 and the second sacrificial layer 1003b-1, 1003b-2.
  • a contact layer may be provided on the substrate.
  • the fin precursor layer 2005 may be formed by, for example, epitaxial growth.
  • the fin precursor layer 2005 may include a suitable semiconductor material such as Si in order to subsequently form a fin serving as an active region of the FinFET.
  • the fin precursor layer 2005 may be formed to have a certain height, such as about 20-100 nm.
  • a hard mask layer may be formed, for example, including a first sublayer 2011 and a second sublayer 2013.
  • first sublayer 2011 and the second sublayer 2013, please refer to the above description of the first sublayer 1011 and the second sublayer 1013.
  • a grid pattern may be defined in the first stack and the fin precursor layer 2005.
  • a photoresist 2015 having a grid pattern may be formed.
  • the photoresist 2015 and its grid pattern please refer to the above details of the photoresist 1015 and its grid pattern.
  • the photoresist 2015 is shown as the node part in the grid pattern is thicker than the bridge part, which is similar to the photoresist 1015 described above. This is advantageous for making subsequent contacts to the source/drain regions formed at the nodes.
  • the line width of the node part may be substantially the same as the line width of the bridge part.
  • the grid pattern can be defined by straight lines that cross each other with uniform thickness.
  • the active area can be defined.
  • the pattern of the photoresist 2015 may be transferred to the hard mask layer, and then transferred to the fin precursor layer 2005 below.
  • the patterned photoresist 2015 can be used as a mask, and the hard mask layer (2013, 2011) and the fin precursor layer 2005 can be selectively selected in sequence.
  • Etching is like RIE.
  • RIE may be performed in a direction substantially perpendicular to the surface of the substrate, and may stop at the top surface of the first stack.
  • the fin precursor layer 2005 may exhibit the same grid pattern as the hard mask layer. The edges of the grid (lines extending in the row or column direction) can define the location of the fins.
  • substantially the middle of the bridging portion of the fin precursor layer 2005 can be used as a channel region, and portions on both sides of the channel region (a node portion and a bridging portion with a certain length around it) can be used as source/drain regions. After that, the photoresist 2015 can be removed.
  • the surface of the fin precursor layer 2005 A protective layer is formed on it.
  • a protective layer 2101 may be formed on the sidewall of the fin precursor layer 2005 according to the sidewall formation process.
  • the protective layer 2101 may include nitride with a thickness of about 1-10 nm.
  • the interconnect structure can be defined in the first stack according to the EFEF process described above.
  • the processes related to the source/drain doping and the formation of the metal gate described above in conjunction with FIGS. 33(a) to 45 can be omitted here.
  • a silicide interconnection via 2081 is formed in the first stack, which includes a via in the via layer and a conductive channel in the interconnect layer.
  • the figure also shows the insulating portions 2035-2a, 2035-3a, 2035-1b, 2035-2b, and the dielectric layer 2055 in the first stack.
  • the insulating portion 1035-2a above.
  • 1035-3a, 1035-1b, 1035-2b and the description of the dielectric layer 1055.
  • the device After defining the interconnect structure, the device can be fabricated. To this end, as shown in FIG. 58, the protective layer 2101 can be removed by selective etching. When the protective layer 2101 is removed, the second sublayer 2013, which is also nitride in this example, may also be removed.
  • a dielectric layer can be supplemented to achieve electrical isolation.
  • an oxide can be deposited and the deposited oxide can be etched back to form the dielectric layer 2055'. Before etch-back, the deposited oxide can be planarized, such as CMP.
  • the top surface of the etched back dielectric layer 2055' may be located near the boundary between the first stack and the second stack, for example, lower than the boundary.
  • the fin precursor layer 2005 extends vertically relative to the structure below, similar to a fin.
  • the fin precursor layer 2005 is continuous, that is, the active regions of the devices are connected together.
  • the fin precursor layer 2005 can be separated into different active regions according to the device layout design. It is possible to form gate electrodes that intersect these active regions (fins) to fabricate devices. According to the embodiments of the present disclosure, the separation between the active regions of the device and the fabrication of the gate electrode can be combined.
  • a sacrificial gate intersecting each bridge portion of the fin precursor layer 2005 may be formed on the dielectric layer 2055'.
  • the sacrificial gate dielectric layer 2103 and the sacrificial gate electrode layer 2105 can be formed on the dielectric layer 2055', for example, by deposition.
  • the sacrificial gate dielectric layer 2103 may include oxide with a thickness of about 1-5 nm; the sacrificial gate electrode layer 2105 may include amorphous silicon or polysilicon, and its top surface may be higher than the top surface of the fin precursor layer 2005 so as to cover the bridges.
  • a hard mask layer 2107 can be formed on the sacrificial gate electrode layer 2105, for example, by deposition.
  • the hard mask layer 2107 may include nitride with a thickness of about 10-150 nanometers.
  • the hard mask layer 2107 and the sacrificial gate electrode layer 2105 can be patterned into a desired shape by photoresist (not shown), by selective etching such as RIE, for example, a shape that intersects (for example, vertical) with each bridge portion Bar. The etching can stop at the sacrificial gate dielectric layer 2103 of oxide.
  • a sacrificial gate intersecting it is formed. According to the layout design, part of the sacrificial gate can be connected together. It should be pointed out here that these sacrificial gates are not necessarily replaced by real gates in the future, but some of them can define the isolation position between active regions.
  • FIG. 59(b) the structure in the first laminate is not shown only for the convenience of illustration.
  • gate spacers 2109 may be formed on the sidewalls of the sacrificial gate.
  • the gate spacer 2109 may include nitride.
  • the gate sidewall spacer 2109 may also be formed on the vertical sidewall of the fin precursor layer 2005, but it is not shown in the figure for convenience.
  • ion implantation may be used to dope the fin precursor layer 2005 (especially the part not shielded by the sacrificial gate, mainly each node and a certain length of the bridge around it) to form the source/drain region.
  • the fin precursor layer 2005 especially the part not shielded by the sacrificial gate, mainly each node and a certain length of the bridge around it
  • different conductivity types can be doped respectively.
  • strain source/drain technology may be utilized.
  • the portion of the fin precursor layer 2005 that is not shielded by the sacrificial gate may be selectively etched, such as RIE, to partially remove it, and a portion may be left as a seed layer.
  • source/drain regions can be formed on the remaining seed layer, for example, by epitaxial growth.
  • the grown source/drain regions may have a different material from the fin precursor layer 2005 (for example, have a different lattice constant) in order to apply stress to the channel region formed in the fin precursor layer 2005.
  • the source/drain region 2111 may include Si:C; for a p-type device, the source/drain region 2113 may include SiGe.
  • the source/drain regions can be doped in-situ during growth.
  • annealing may be performed to diffuse the dopant, thereby improving the electrical connection between the source/drain region and the via hole under the source/drain region.
  • active region separation and sacrificial gate replacement can be performed.
  • oxide can be deposited on the structures shown in Figures 60 (a), 60 (b) and 60 (c), and the deposited oxide can be planarized, such as CMP ( It can stop at the sacrificial gate 2105) to fill the gaps between the devices.
  • CMP It can stop at the sacrificial gate 2105
  • the deposited oxide and the dielectric layer 2055' are still integrally shown as 2055'.
  • a photoresist 2111 can be formed on the dielectric layer 2055', and patterned according to the layout design to cover the sacrificial gate that needs to be replaced with a real gate, and expose the limit Sacrificial gates in isolation positions between active regions.
  • the photoresist 2111 can be used as a mask to selectively etch the sacrificial gate 2105 and the sacrificial gate dielectric layer 2103 to expose the underlying Fin precursor layer 2005 (the middle of the corresponding bridge portion).
  • the exposed fin precursor layer 2005 may be selectively etched such as RIE, and the RIE may be stopped at the underlying dielectric layer 2055', so that the fin precursor layer 2005 is cut off at a corresponding position. After that, the photoresist 2111 may be removed.
  • a dielectric such as oxide can be filled by deposition and then CMP to achieve electrical isolation.
  • the filled dielectric and the dielectric layer 2055' are integrally shown as 2113.
  • gate replacement can be performed.
  • the sacrificial gate electrode layer 2105 and the sacrificial gate dielectric layer 2103 can be removed by selective etching, and the sacrificial gate electrode layer 2105 and the sacrificial gate In the space left by the removal of the dielectric layer 2103, a gate dielectric layer 2067 and gate electrode layers 2069 and 2073 are formed.
  • the gate dielectric layer 2067 and the gate electrode layers 2069 and 2073 please refer to the above description of the gate dielectric layer 1067 and the gate electrode layers 1069 and 1073. There are various ways to perform gate replacement in the art, which will not be repeated here.
  • part of the source/drain regions may define contact plugs.
  • a photoresist 2083 can be formed and patterned to have openings where contact plugs need to be formed.
  • the dielectric layer 2113 can be recessed through the opening in the photoresist 2083 by selective etching such as RIE to expose the source/drain regions at the corresponding positions.
  • the exposed source/drain regions can be converted into contact plugs 2087 through silicidation. For details of the silicidation process, refer to the above description.
  • part of the source/drain region of the device is connected with the interconnect structure.
  • a contact portion may be formed above the device.
  • a dielectric such as oxide (here, shown as 2113' together with the dielectric layer 2113) can be deposited to fill the gaps in the structure to achieve inter-device Electrical isolation.
  • a contact 2091 penetrating the dielectric layer 2113' may be formed. Since the electrical connection to part of the source/drain regions can be realized through the interconnection structure under the device, the area of the metal interconnection above the device can be made more abundant, which is beneficial to the miniaturization of the device.
  • 67 to 70(b) show schematic diagrams of some stages in the process of manufacturing a planar semiconductor device according to an embodiment of the present disclosure.
  • the differences from the above-mentioned embodiment will be mainly described, and the overlapping description with the above-mentioned embodiment will be simplified or omitted.
  • a first stack of alternately arranged first sacrificial layers 3003a-1, 3003a-2, 3003a-3 and second sacrificial layers 3003b-1, 3003b-2 may be formed on a substrate 3001.
  • the substrate 3001 and the first sacrificial layers 3003a-1, 3003a-2, 3003a-3 and the second sacrificial layers 3003b-1, 3003b-2 please refer to the above about the substrate 1001 and the first sacrificial layer 1003a-1 , 1003a-2, 1003a-3 and the second sacrificial layer 1003b-1, 1003b-2.
  • the active layer 3005 can be formed by, for example, epitaxial growth.
  • the active layer 3005 may include a suitable semiconductor material such as Si.
  • the active layer 3005 may be relatively thin, for example, about 5-70 nm.
  • a grid pattern may be defined in the first stack and the active layer 3005.
  • the protective layer on the sidewalls of the mesh pattern of the active layer 3005 may be removed, and the dielectric layer 3055 may be formed.
  • CMP can stop on the top surface of the active layer 3005, and the dielectric layer 3055 is not etched back again, so as to obtain Figures 68(a) and 68( b) The structure shown. That is, in this embodiment, the active layer 3005 does not need to be relatively protruding as in FinFET.
  • the 3081 and 3035-2a shown in the figure please refer to the above description about 1081 and 1035-2a.
  • a device can be fabricated based on the active layer 3005.
  • the process of making the device can be basically the same as the process of making the FinFET above, except for the different form of the active region.
  • the active The protective layer 3101 on the sidewall of the grid pattern of the layer 3005.
  • the protective layer 3101 refer to the description of the protective layer 2101 above.
  • the dielectric layer 3055 is formed.
  • CMP may stop at the second sub-layer 3013 of the hard mask layer. This can reduce damage to the active layer 3005 by CMP. Afterwards, as shown in FIGS.
  • the second sub-layer 3013 and the protective layer 3101 of nitride can be etched back by selective etching to expose the first sub-layer 3011 below.
  • ALE can be used.
  • the first sub-layer 3013 may be selectively etched to expose the surface of the active layer 3005.
  • a device can be fabricated based on the active layer 3005.
  • the first sublayer 3011 and the second sublayer 3013 refer to the description of the first sublayer 1011 and the second sublayer 1013 above.
  • the interconnection structure and circuit according to the embodiments of the present disclosure can be applied to various electronic devices.
  • an integrated circuit IC
  • an electronic device can be constructed therefrom. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device.
  • the electronic device may also include components such as a display screen matched with an integrated circuit and a wireless transceiver matched with an integrated circuit.
  • Such electronic devices include smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and so on.
  • SoC system on chip
  • a method of manufacturing an interconnect structure for a semiconductor device comprising:
  • a first hard mask layer is provided on the device active material layer.
  • the first hard mask layer has a grid pattern defined by lines extending in a first direction and a second direction crossing each other, including intersections between the lines. Point-limited nodes and the bridge between nodes;
  • the first stack is patterned so that each layer in the first stack has a grid pattern corresponding to the first hard mask layer, and therefore includes nodes and bridges between nodes Part;
  • the interconnection structure defined in the first stack includes:
  • each first sacrificial layer at least partially remove the bridge portions of the first sacrificial layer so that the nodes of the first sacrificial layer are separated from each other; according to the layout of the interconnect structure, remove one or more of the first sacrificial layers Nodes, and
  • each second sacrificial layer according to the layout of the interconnect structure, cut off one or more bridge portions in the second sacrificial layer, and form at the area of the remaining portion of each first sacrificial layer and each second sacrificial layer Conductive material.
  • the removal process is performed on each first sacrificial layer according to the layout of the interconnect structure, and then the cutting process is performed on each second sacrificial layer according to the layout of the interconnect structure.
  • the method further includes: shielding the first stack with the first shielding layer; and gradually etching back the first shielding layer downward to expose each of the first sacrificial layers one by one,
  • the method further includes: shielding the first stack with a second shielding layer; and gradually etching back the second shielding layer downward to expose each second sacrificial layer one by one.
  • the method further includes: forming a second hard mask layer on the first shielding layer, and the second hard mask layer has a pattern corresponding to the node portion of the mesh pattern. And using the second hard mask layer to form a first processing channel to the node of each first sacrificial layer in the first shielding layer, wherein etching back the first shielding layer includes etching back the first processing channel through the first processing channel Masking layer,
  • the method further includes: forming a third hard mask layer on the second shielding layer, the third hard mask layer having a substantially middle portion of the bridge portion with the mesh pattern Corresponding openings; and using the third hard mask layer to form a second processing channel to the bridging portion of each second sacrificial layer in the second masking layer, wherein etching back the second masking layer includes passing through the second processing channel Etch back the second shielding layer.
  • the first insulating portion is filled.
  • the second insulating portion is filled.
  • first sacrificial layer and the second sacrificial layer include semiconductor materials
  • first position holding layer and the second position holding layer include semiconductor materials
  • forming of the conductive material includes:
  • the metal reacts with the semiconductor material to generate a conductive metal semiconductor compound.
  • the first sacrificial layer in the lowermost layer is replaced with an insulating layer.
  • the semiconductor device is a vertical semiconductor device
  • the defining the active area includes defining the device active area at each node, respectively.
  • the device active material layer includes a second stack of a first source/drain layer, a channel layer, and a second source/drain layer stacked in sequence, the active region being defined include:
  • the second stack is patterned so that each layer in the first stack has a grid pattern corresponding to the first hard mask layer, and therefore includes nodes and bridges between nodes section;
  • the first source/drain layer and the second source/drain layer are further selectively etched to at least partially remove the respective bridge portions of the first source/drain layer and the second source/drain layer so that the first source/drain layer The respective nodes of the layer and the second source/drain layer are separated from each other.
  • a first position holding layer with a pattern corresponding to the hard mask layer is formed around the separated nodes of the channel layer;
  • first source/drain layer and the second source/drain layer are further selectively etched, a pattern and the hard mask layer are formed around the separated nodes of the first source/drain layer and the second source/drain layer.
  • the corresponding second position holding layer is formed around the separated nodes of the first source/drain layer and the second source/drain layer.
  • the dopants in the dopant source layer are driven into the respective nodes of the first source/drain layer and the second source/drain layer.
  • a gate electrode is formed around the node of the channel layer.
  • a contact plug is formed at one or more node positions.
  • the metal reacts with the active region at the one or more node positions to generate a conductive metal semiconductor compound.
  • the structure where the outer periphery of the active region is removed is filled with semiconductor material, wherein the metal also reacts with the filled semiconductor material to generate a conductive metal-semiconductor compound.
  • the semiconductor device is a fin-type field effect transistor or a planar semiconductor device
  • the defining an active area includes:
  • the device active material layer is patterned so that the device active material layer has a grid pattern corresponding to the first hard mask layer, and thus includes nodes and bridge portions between nodes.
  • One or more sacrificial gates are removed by selective etching
  • sacrificial gate and the gate sidewall as a mask, selectively etch the active material layer to remove part of the device active material layer exposed by the sacrificial gate and the gate sidewall;
  • the remaining part of the device active material layer is used as a seed to grow epitaxial source/drain.

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Abstract

一种互连结构、电路及包括这种互连结构或电路的电子设备。一种用于在衬底上形成的多个半导体器件的互连结构可以设置在所述多个半导体器件之下。该互连结构可以包括：沿从半导体器件向着衬底的方向交替设置的至少一个过孔层和至少一个互连层，其中，每一过孔层包括分别设于所述多个半导体器件中至少一部分半导体器件下方的过孔，每一互连层包括分别设于所述多个半导体器件中至少一部分半导体器件下方的导电节点，其中，在同一互连层中，至少一个导电节点与至少另一个节点之间具有导电通道，各过孔层中的过孔与各互连层中的相应导电节点在从半导体器件向着衬底的方向上彼此至少部分地交迭。

Description

互连结构、电路及包括该互连结构或电路的电子设备
相关申请的引用
本申请要求于2019年5月5日递交的题为“互连结构、电路及包括该互连结构或电路的电子设备”的中国专利申请201910369630.9的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及器件层之间的互连结构、包括器件层之间的互连的电路及包括这种互连结构或电路的电子设备。
背景技术
器件层之间的互连能够降低寄生电阻和电容，从而可以降低集成电路(IC)的电阻电容(RC)延迟和功耗。另外，还可以增加IC的集成密度并因此降低IC的制造成本。但是，难以在器件层之间进行互连，因为互连工艺与器件集成工艺并不兼容。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种器件层之间的互连结构、包括器件层之间的互连的电路以及包括这种互连结构或电路的电子设备。
根据本公开的一个方面，提供了一种用于在衬底上形成的多个半导体器件的互连结构，所述互连结构设置在所述多个半导体器件之下，且包括：沿从半导体器件向着衬底的方向交替设置的至少一个过孔层和至少一个互连层，其中，每一过孔层包括分别设于所述多个半导体器件中至少一部分半导体器件下方的过孔，每一互连层包括分别设于所述多个半导体器件中至少一部分半导体器件下方的导电节点，其中，在同一互连层中，至少一个导电节点与至少另一个节点之间具有导电通道，各过孔层中的过孔与各互连层中的相应导电节点在从半导体器件向着衬底的方向上彼此至少部分地交迭。
根据本公开的另一方面，提供了一种电路，包括：衬底；设于衬底上的互 连结构，所述互连结构包括沿实质上垂直于衬底表面的方向交替设置的至少一个过孔层和至少一个互连层，互连结构的最上层是过孔层；以及设于互连结构上的多个半导体器件，其中，每一过孔层包括设于按行和列排列的二维点阵中的至少一部分点之处的过孔，每一互连层包括设于所述二维点阵中的至少一部分点之处的主体部以及从所述主体部沿所述行或列的方向延伸的延伸部，至少一部分相邻主体部各自彼此相向的延伸部相接触，至少一部分半导体器件的源/漏区与最上层的过孔层中的相应过孔相接触。
根据本公开的另一方面，提供了一种制造用于半导体器件的互连结构的方法，包括：在衬底上设置交替堆叠的至少一个第一牺牲层和至少一个第二牺牲层的第一叠层，其中，第一叠层的最上层是第一牺牲层；在第一叠层上设置器件有源材料层；在器件有源材料层上设置第一硬掩模层，第一硬掩模层具有由沿彼此交叉的第一方向和第二方向延伸的线条限定的网格图案，包括由线条之间的交叉点限定的节点以及节点之间的桥接部分；利用第一硬掩模层，在器件有源材料层中限定针对半导体器件的有源区；利用第一硬掩模层，对第一叠层进行构图，从而第一叠层中的各层具有与第一硬掩模层相对应的网格图案，并因此包括节点以及节点之间的桥接部分；以及在第一叠层中限定互连结构，包括：针对各第一牺牲层：将该第一牺牲层的各桥接部分至少部分地去除从而该第一牺牲层的节点彼此分离；根据互连结构的布局，去除该第一牺牲层中的一个或多个节点，以及针对各第二牺牲层：根据互连结构的布局，将该第二牺牲层中的一个或多个桥接部分切断，以及在各第一牺牲层和各第二牺牲层的残留部分的区域处形成导电材料。
根据本公开的另一方面，提供了一种电子设备，包括上述互连结构或电路。
根据本公开的实施例，提出了器件层之下(相对于衬底而言)的互连结构及其制作方法。这种结构可以是三维(3D)结构，更具体地，互连可以在3D网格上构建，实现器件层之间的互连。这种结构可以通过以下详述的刻蚀-填充-刻蚀-填充(etch-fill-etch-fill，EFEF)的方法来制作，以便与器件集成工艺相兼容。器件的源/漏区与互连结构中的过孔可以自对准，而且互连结构中不同层之间的过孔可以自对准。器件的有源区可以由单晶半导体制成，从而可以改进器件性能。根据本公开的技术在极紫外(EUV)光刻下可以有很好的应用。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至52(d)示出了根据本公开实施例的制造竖直半导体器件的流程中部分阶段的示意图，其中，图2(a)、8(a)、9(a)、12(a)、14(a)、15(a)、23(a)、25(a)、27(a)、32(a)、35(a)、43(a)、49(a)、52(a)是俯视图，图1、2(b)、3、4(b)、5(b)、6(b)、7(b)、8(b)、10(b)、11(b)、12(c)、13(b)、14(c)、15(c)、16(b)、17(b)、18(b)、19(b)、20(b)、21(b)、22(b)、23(c)、24(b)、25(c)是沿BB′线的截面图，图4(a)、5(a)、6(a)、7(a)、9(b)、10(a)、11(a)、12(b)、13(a)、14(b)、15(b)、16(a)、17(a)、18(a)、19(a)、20(a)、21(a)、22(a)、23(b)、24(a)、25(b)、30、31(a)、32(b)、33(a)、34(a)、35(b)、36、37、38(a)、39(a)、40(a)、41、42(a)、43(b)、44、47(a)、49(b)、50(a)、51(a)、52(b)是沿AA′线的截面图，图23(d)、24(c)、25(d)是沿CC′线的截面图，图25(e)、26、47(b)、49(c)、50(b)、51(b)、52(c)是沿FF′线的截面图，图25(f-1)、25(f-2)、25(f-3)、25(f-4)、27(b)、28(a)、29(a)、31(b-1)、31(b-2)、33(b-1)、33(b-2)、34(b)、38(b)、39(b)、40(b)是沿DD′线的截面图，图27(c)、28(b)、29(b)、49(d)、50(c)、51(c)是沿EE′线的截面图，图42(b)、45、46、47(c)、48是沿GG′线的截面图，图50(d)、51(d)、52(d)是沿1-1′线的截面图；
图53至66(b)示出了根据本公开实施例的制造鳍式场效应晶体管(FinFET)的流程中部分阶段的示意图，其中，图54(a)、59(a)、60(a)、62(a)、63(a)、64(a)、65(a)、66(a)是俯视图，图53、54(b)、55(b)、56、59(c)、60(c)、63(c)、64(c)是沿BB′线的截面图，图55(a)、57(a)、59(b)、60(b)、61、62(b)、63(b)、64(b)、65(b)、66(b)是沿AA′线的截面图，图57(b)是沿FF′线的截面图，图57(d)、58、59(d)是沿GG′线的截面图，图65(c)是沿HH′线的截面图，图57(c)是沿1-1′线的截面图；
图67至70(b)示出了根据本公开实施例的制造平面半导体器件的流程中部分阶段的示意图，其中，图68(a)、69(a)、70(a)是俯视图，图67是沿BB′线的截面图，图68(b)、69(b)、70(b)是沿GG′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提出了一种互连结构。与常规技术中在衬底上形成半导体器件之后在器件上方形成互连结构如金属化叠层(metallization)不同，根据实施例的互连结构可以设置在器件下方，例如器件与衬底之间。互连结构可以包括交替堆叠的至少一个过孔层和至少一个互连层。各过孔层中设置有过孔，以便实现该过孔层之下的层与之上的层(均为互连层)之间的电连接。各互连层中设置有导电通道，以便实现该互连层之内的路线选择(routing)。一般而言，互连结构最靠近器件一侧是过孔层，以便从相应器件引出电连接。
在各过孔层中，过孔可以分别处于相应半导体器件(特别是其有源区，例如源/漏区)的下方。例如，这是由于如下所述它们可以采用实质上相同的图案来限定。于是，过孔可以和相应半导体器件(特别是其有源区，例如源/漏区)沿着刻蚀方向可以至少部分地交迭，甚至可以实质上对准，例如中心对准。当然，在各过孔层中，并非一定是所有半导体器件更具体地其源/漏区下方都形成有过孔，而是可以仅有一部分源/漏区(可以称作“第一组源/漏区”)下方 形成有过孔，而另一部分源/漏区(可以称作“第二组源/漏区”)下方可以形成有绝缘部。过孔层中过孔和绝缘部的布局可以根据电路设计所需的连接布局而定。
类似地，在各互连层中，可以存在处于相应半导体器件(特别是其有源区，例如源/漏区)下方的导电节点。同样地，例如这是由于如下所述它们可以采用实质上相同的图案来限定。于是，导电节点可以和相应半导体器件(特别是其有源区，例如源/漏区)(以及相应的过孔)沿着刻蚀方向可以至少部分地交迭，甚至可以实质上对准，例如中心对准。同样地，在各互连层中，并非一定是所有半导体器件更具体地其源/漏区下方都形成有导电节点，而是可以仅有一部分源/漏区下方形成有导电节点。
在各互连层中，导电通道在相应导电节点之间延伸。根据本公开的实施例，导电通道可以在相邻导电节点之间逐跳延伸，而并不存在直接连接非相邻导电节点的导电通道(所谓“直接连接”，是指不经过其他导电节点)。
对于每一过孔而言，其上一层和下一层均可以存在相应的导电节点并与之相接触，以便实现上下两层之间的电连接。对于每一导电节点而言，其上一层和下一层可以均不存在相应过孔，从而该导电节点可以作为导电通道上的中间节点；或者，其上一层和/或下一层可以存在相应过孔并与之相接触，以实现层之间的电连接。
于是，互连结构中各层可以呈现与半导体器件相似的布局。在此，将布局称为“阵列”，例如按行和列排列的二维阵列(当然也可以是其他形式的阵列)，并将布局中的元素(例如，器件层中的半导体器件、过孔层中的过孔、或互连层中的导电节点)称为“节点”。各过孔层的阵列与器件层的阵列可以基本相同，但可能缺失了某些节点(如下所述，这些节点处可以设置有绝缘部)。各互连层的阵列与器件层的阵列可以基本相同，但可能缺失了某些节点。
在某些实施例中，在各互连层中，可以在所有节点处均形成导电节点。对于不需要的导电节点，可以在其上、下方的过孔层中的相应位置处设置绝缘部，并切断其与相邻导电节点之间的导电通道，使其成为孤立的虚设节点。这可以使对于互连层中导电节点的处理一致化，从而使工艺易于进行。
因此，互连结构可以整体上成为一种三维(3D)网格结构。各互连层中 的导电通道可以沿着阵列中的网格的边(例如，行或列的方向)延伸。
这种互连结构特别适用于竖直型半导体器件。竖直型半导体器件可以包括在竖直方向(例如，基本上垂直于衬底表面的方向)上延伸的有源区。互连结构中的各节点可以沿竖直方向处于各竖直型半导体器件的有源区下方，并可以在竖直方向上对准，例如中心对准。
竖直有源区可以包括分处于上下两端的源/漏区和位于源/漏区之间的沟道区。源/漏区之间可以通过沟道区形成导电通道。这种有源区例如可以通过依次叠置的第一源/漏层、沟道层和第二源/漏层来提供。源/漏区可以基本上形成在第一和第二源/漏层中，沟道区可以基本上形成在沟道层中。有源区特别是沟道层可以呈现纳米线的形状，从而得到纳米线器件。或者，有源区特别是沟道层可以呈现纳米片的形状，从而得到纳米片器件。
沟道层可以由单晶半导体材料构成，以改善器件性能。当然，第一、第二源/漏层也可以由单晶半导体材料构成。这种情况下，沟道层的单晶半导体材料与源/漏层的单晶半导体材料可以是共晶体。
根据本公开的实施例，这种半导体器件可以是常规场效应晶体管(FET)。在FET的情况下，沟道区两侧的源/漏区可以具有相同导电类型(例如，n型或p型)的掺杂。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。或者，这种半导体器件可以是隧穿FET。在隧穿FET的情况下，沟道区两侧的源/漏区)可以具有不同导电类型(例如，分别为n型和p型)的掺杂。这种情况下，带电粒子如电子可以从源区隧穿通过沟道区而进入漏区，从而使源区和漏区之间形成导通路径。尽管常规FET和隧穿FET中的导通机制并不相同，但是它们均表现出可通过栅来控制源/漏区之间导通与否的电学性能。因此，对于常规FET和隧穿FET，统一以术语“源/漏层(源/漏区)”和“沟道层(沟道区)”来描述，尽管在隧穿FET中并不存在通常意义上的“沟道”。
栅电极可以绕沟道区的至少部分外周形成。栅电极可以自对准于沟道层。例如，栅电极靠近沟道层一侧的侧壁可以与沟道层的外周侧壁对准从而在竖直方向上占据实质上相同的范围。这样，可以减少或甚至避免栅电极与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
为便于不同器件之间栅电极的连接以及向栅电极施加电信号，栅电极除了绕沟道区的主体部之外，还可以包括从主体部向外延伸的延伸部。延伸部也可以沿着阵列中的网格的边(例如，行或列的方向)延伸。至少一部分相邻栅电极各自彼此相向的延伸部可以接触，从而彼此电连接。
根据本公开的实施例，还可以设置用于将电信号引入互连结构中的接触插塞。例如，接触插塞与互连结构中最上层的过孔层中的相应过孔相接触，以便将电信号施加到互连结构中。于是，接触插塞也可以位于阵列中的相应节点处。根据本公开的实施例，接触插塞可以通过将相应节点处的有源区转换为导电材料(例如，通过硅化处理得到的硅化物)来形成，于是接触插塞可以自对准于相应节点(或者说，相应节点处的过孔)。也即，器件层的阵列中，部分节点可以是真正的器件有源区，而另外一些节点可以是接触插塞。
根据本公开的实施例，还可以设置用于将电信号施加到栅电极的接触插塞。出于工艺一致性的目的，这种接触插塞也可以如上所述通过相应节点处的有源区转换为导电材料来形成(“主体部”)。另外，接触插塞除了节点处的主体部之外，还可以包括从主体部延伸以便与栅电极相接触的延伸部。延伸部也可以沿着阵列中的网格的边(例如，行或列的方向)延伸。
根据本公开的实施例，半导体器件也可以是其他的形式，例如鳍式场效应晶体管(FinFET)或平面型半导体器件，它们的鳍或有源区可以沿横向方向(例如，基本上平行于衬底表面的方向)延伸，例如可以沿着阵列中的网格的边(例如，行或列的方向)延伸。器件的源/漏区可以位于阵列的节点处。这样，通过在下方形成的互连结构，可以实现到器件阵列中至少部分源/漏区的电连接。
这种互连结构例如可以如下制造。
根据本公开的实施例，可以在衬底上设置交替堆叠的第一牺牲层和第二牺牲层的第一叠层。第一叠层随后用于形成互连结构。在此，为便于描述，将限定过孔层位置的牺牲层称作第一牺牲层，而将限定互连层位置的牺牲层称作第二牺牲层。因此，第一堆叠最上方的牺牲层可以是第一牺牲层之一。第一牺牲层和第二牺牲层可以相对于彼此具备刻蚀选择性。
在第一叠层上，可以设置随后用于形成器件有源区的半导体材料。例如， 在形成竖直半导体器件的情况下，可以设置依次堆叠的第一源/漏层、沟道层、第二源/漏层的第二叠层。沟道层相对于第一和第二源/漏层可以具备刻蚀选择性。另外，第一源/漏层和第二源/漏层可以包括相同的半导体材料。第一叠层和第二叠层之间至少相邻的层(即，第一叠层的最顶层和第二叠层的最底层)相对于彼此具备刻蚀选择性。例如，这些层可以通过外延生长来形成。由于分别外延生长，至少一对相邻层之间可以具有清晰的晶体界面。另外，可以对各层特别是第二叠层中的各层分别进行掺杂，于是至少一对相邻层之间可以具有掺杂浓度界面。
为便于构图，可以在有源区半导体材料例如第二叠层的顶部上设置硬掩模层。硬掩模层可以呈网格状。例如，硬掩模层可以包括按行和列设置的线条。在此，将硬掩模层中的行和列的交叉点称为“节点”，节点之间的线条称为“桥接部分”。其他层中如果形成网格图案的话，也可以如此称呼。在竖直半导体器件的情况下，硬掩模层的网格图案的节点可以限定竖直有源区的主体位置，而且节点的线宽可以增大以粗于桥接部分。在FinFET或平面半导体器件的情况下，硬掩模层的网格图案的桥接部分的大致中部可以限定沟道区，且沟道区两侧的部分(节点及其周围的桥接部分)可以限定源/漏区。
可以利用硬掩模层，在有源区半导体材料例如第二叠层中限定有源区。例如，可以将硬掩模层的图案转移到第二叠层中。在竖直半导体器件的情况下，有源区可以位于各节点相对应的位置处。此时，可以去除第二叠层中与桥接部分相对应的部分(可以代之以支撑材料以提供结构支撑)，而保留第二叠层中与节点相对应的部分，形成多个分离的有源区。一些有源区可以用来形成器件，另一些有源区可以在随后例如通过硅化处理而转化为导电接触插塞。
接下来，可以利用掩模层，在第一叠层中限定互连结构的框架。这可以通过将硬掩模层的图案转移到第一叠层中，并在每一层中根据互连结构的连接设计对图案进行修整来实现。
在过孔层中，需要设置穿透过孔层的过孔以实现上下互连层之间的连接。这种过孔可以沿竖直方向延伸，而无需在过孔层内的横向延伸配置。因此，对于第一牺牲层而言，可以利用硬掩模层的节点来在其中限定过孔的图案。具体地，可以将节点的布局转移到第一牺牲层中。例如，在将硬掩模层的图案转移 到第一牺牲层中之后，可以去除第一牺牲层中的桥接部分，而留下第一牺牲层中的节点。可以根据各过孔层中的过孔布局，对相应第一牺牲层中的节点进行去除或保留，以实现所需的过孔布局。
在互连层中，需要设置在互连层内横向延伸的导电通道，以实现路线选择。因此，对于第二牺牲层而言，可以利用硬掩模层中的桥接部分来在其中限定导电通道的走向。具体地，可以将硬掩模层的图案转移到第二牺牲层中，第二牺牲层中的节点可以充当作为导电通道的桥接部分之间的中继点。另外，第二牺牲层中的节点还可以与第一牺牲层中的相应节点接触，以实现上下层之间的互连。可以根据各互连层中的连接设计，对相应第二牺牲层中的桥接部分进行切断或保留，以实现所需的路线选择。
对于第一叠层中图案的修整，可以逐层进行，例如从上向下依次进行。可以利用遮蔽层来遮蔽第一叠层，并逐渐向下回蚀遮蔽层以逐一露出第一叠层中的各层。在对第一叠层中的某一层进行处理时，其下方的层可以被遮蔽层所遮蔽以免受影响。
通常互连结构中各层之间的设计并不一定是一样的。随着遮蔽层的逐渐回蚀，在对下方的层进行处理时，其上方的层可能露出而受到影响。为避免在对下层进行处理时对上层造成影响，可以将第一或第二牺牲层中需要保留的部分替换为不同的材料。这可以通过刻蚀-填充-刻蚀-填充(EFEF)的方法来实现，以下将对此进行详细描述。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至52(d)示出了根据本公开实施例的制造竖直半导体器件的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括 但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001中，可以形成阱区(未示出)。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。阱区例如可以通过向衬底1001中注入相应导电类型掺杂剂(p型掺杂剂如B或In，或n型掺杂剂如As或P)且随后进行热退火来形成。本领域存在多种方式来设置这种阱区，在此不再赘述。
在衬底1001上，可以通过例如外延生长，形成交替设置的第一牺牲层1003a-1、1003a-2、1003a-3和第二牺牲层1003b-1、1003b-2的第一叠层。如上所述，第一牺牲层和第二牺牲层相对于彼此可以具备刻蚀选择性。因为随后将在第一叠层上形成有源区的材料(一般地为半导体材料)，故而第一叠层可以采用半导体材料形成，以实现高质量的有源区生长。例如，第一牺牲层1003a-1、1003a-2、1003a-3各自可以包括SiGe，Ge的原子百分比为约10-40％，厚度为约20-100nm；第二牺牲层1003b-1、1003b-2可以各自包括Si，厚度为约20-100nm。第一牺牲层和第二牺牲层各自可以具有基本上相同的厚度。第一牺牲层和第二牺牲层的层数可以根据将要形成的互连结构中过孔层和互连层的数目来定，而不限于图中所示的层数。在此，最下面的第一牺牲层1003a-1随后将被替换为隔离层，以便实现互连结构与衬底之间的电隔离。
在第一叠层上，可以通过例如外延生长，形成第一源/漏层1005、沟道层1007和第二源/漏层1009的第二叠层。这些都可以是半导体材料。如上所述，沟道层与第一、第二源/漏层相对于彼此可以具备刻蚀选择性。另外，为了便于对第一叠层和第二叠层的分别处理，它们之间至少相邻的层相对于彼此可以具备刻蚀选择性。例如，沟道层1007可以包括SiGe，Ge的原子百分比可以为约10-40％，厚度为约20-100nm；第一源/漏层1005和第二源/漏层1009可以包括Si，厚度为约20-100nm。
根据实施例，还可以设置接触层。例如，在第一叠层与第二叠层之间，可以通过例如外延生长，形成接触界面层(未示出)。接触界面层可以包括例如硅，并且可以通过例如原位掺杂而被掺杂为n型或者p型，优选地与以下结合 图25描述的掺杂类型相同，掺杂浓度为约1E19-5E21cm -3。这可以降低源/漏与互连结构之间的电阻。在此，该接触界面层由于同第一源/漏层1005包括相同的材料(Si)，随后可以同第一源/漏层1005一样被处理。备选地或者另外，在形成第一叠层之前，在衬底上通过例如外延生长，形成接触层(未示出)。同样地，接触层可以包括例如硅，并且可以通过例如原位掺杂而被掺杂为n型或者p型，优选地与以下结合图25描述的掺杂类型相同，掺杂浓度为约1E19-5E21cm -3。
在第二叠层上，可以形成硬掩模层。硬掩模层可以包括叠层结构，例如第一子层1011和第二子层1013。第一子层1011可以用于保护和/或刻蚀停止等目的，例如可以包括氧化物(例如，氧化硅)，厚度为约2-5nm，可以通过淀积或热氧化形成(热氧化形成的氧化物质量较好)。第二子层1013可以用于掩模和/或隔离等目的，例如可以包括氮化物(例如，氮化硅)或低k电介质材料(例如，碳化硅系材料)，厚度为约10-100nm，可以通过淀积形成。当然，硬掩模层的材料不限于此，而是可以包括在随后的各种刻蚀工艺中能够保留下来的材料。另外，硬掩模层还可以包括更多子层，以提供更好的刻蚀选择性。
可以将硬掩模层构图为所需的图案。如上所述，可以形成网格图案。为此，如图2(a)和2(b)所示，可以在硬掩模层上形成光刻胶1015。通过光刻(曝光和显影)将光刻胶1015构图为网格图案。网格的节点可以增粗，以便限定有源区的位置。在此，网格的节点呈大致圆形，从而随后可以形成纳米线器件。当然，网格节点的形状不限于此，而可以是其他各种合适的形状，例如椭圆形、矩形、方形等，甚至可以是不同形状的组合(某些节点是一种形状，而另一些节点是另一种形状)。在形成矩形或方形节点的情况下，可以利用交叉侧墙图形转移(xSIT)技术，且随后可以形成纳米片器件。
接下来，可以限定有源区。例如，这可以如下进行。
可以将光刻胶1015的图案转移到硬掩模层中，并继而转移到下方的第二叠层中。具体地，如图3所示，可以构图后的光刻胶1015为掩模，依次对硬掩模层(1013、1011)、第二源/漏层1009、沟道层1007和第一源/漏层1005进行选择性刻蚀如反应离子刻蚀(RIE)。RIE例如可以按大致垂直于衬底表面的方向进行，从而第二叠层中形成的图案与硬掩模层的图案可以在竖直方向上 基本上对准。
在该示例中，对第一源/漏层1005的刻蚀并未进行到第一源/漏层1005的底面处。于是，在第一叠层的顶面上留下了一薄层的Si。该Si薄层随后可以在对沟道层1007进行选择性刻蚀时保护第一叠层中的第一牺牲层1003a-3，因为在该示例中第一牺牲层1003a-3和沟道层1007均包括SiGe。在第一牺牲层1003a-3相对于沟道层1007具备刻蚀选择性的情况下，对第一源/漏层1005的刻蚀也可以进行到第一源/漏层1005的底面处。
当前，第二叠层呈现同硬掩模层一样的网格图案。希望将第二叠层分离为各个节点处针对单独器件的有源区。为此，可以对第一源/漏层1005、沟道层1007和第二源/漏层1009进一步进行选择性刻蚀以去除桥接部分，而留下节点部分。这是可能的，因为如上所述节点部分的线宽较粗。
例如，如图4(a)和4(b)所示，可以相对于第一源/漏层1005和第二源/漏层1009(Si)，进一步选择性刻蚀沟道层1007(SiGe)。控制刻蚀的量，使得沟道层1007中的桥接部分被去除(参见图4(b))，而节点部分得以保留(参见图4(a))。如图4(a)所示，沟道层1007被分离为分处于各节点处的多个部分，这些部分中随后将形成器件的沟道。这些分离部分的外周相对于硬掩模层中的相应节点的外周向内侧有一定凹入。为便于对刻蚀量的控制，可以采用原子层刻蚀(ALE)。由于第一源/漏层1005的连续底部的存在，与沟道层1007同为SiGe的第一牺牲层1003a-3可以不受影响。
出于结构支撑及保护沟道层等目的，如图5(a)和5(b)所示，可以在硬掩模层下方第二叠层的空隙中形成位置保持层1017。例如，可以在图4(a)和4(b)所示的结构上淀积电介质材料，淀积的量足以填满第二叠层中的空隙，并以硬掩模层为掩模对淀积的电介质材料进行回蚀如RIE。RIE可以沿大致垂直于衬底表面的方向进行，于是电介质材料可以留于硬掩模层下方而形成位置保持层1017。因此，位置保持层1017填充在沟道层中的桥接部分原本所在的位置以及节点部分由于上述进一步选择性刻蚀而形成的凹入中，自对准于沟道层，环绕沟道层外周以保护沟道层。在此，选择位置保持层1017的材料，使得其相对于硬掩模层具备刻蚀选择性，例如氮氧化物(例如，氮氧化硅)。
类似地，如图6(a)和6(b)所示，可以相对于沟道层1007和第一牺牲层 1003a-3(SiGe)，进一步选择性刻蚀第一源/漏层1005和第二源/漏层1009(Si)。控制刻蚀的量，使得第一源/漏层1005和第二源/漏层1009中的桥接部分被去除(参见图6(b))，而节点部分得以保留(参见图6(a))。如图6(a)所示，第一源/漏层1005和第二源/漏层1009均被分离为分处于各节点处的多个部分，这些部分中随后将形成器件的源/漏区。这些分离部分的外周相对于硬掩模层中的相应节点的外周向内侧有一定凹入。为便于对刻蚀量的控制，可以采用ALE。另外，第一源/漏层1005底部的连续薄层的厚度较小，从而在该进一步刻蚀过程中可以被去除，以露出第一牺牲层1003a-3以便随后对第一堆叠进行处理。
同样地，出于结构支撑及保护源/漏层等目的，如图7(a)和7(b)所示，可以在硬掩模层下方第二叠层的空隙中形成位置保持层1019。位置保持层1019可以按形成位置保持层1017的方法来形成。因此，位置保持层1019填充在第一源/漏层1005和第二源/漏层1009各自的桥接部分原本所在的位置以及节点部分由于上述进一步选择性刻蚀而形成的凹入中，自对准于第一源/漏层1005和第二源/漏层1009，环绕第一源/漏层1005和第二源/漏层1009外周以保护源/漏层。在此，选择位置保持层1019的材料，使得其相对于硬掩模层和位置保持层1017具备刻蚀选择性，例如SiC。
刻蚀后的第一源/漏层1005、沟道层1007和第二源/漏层1009各自的相应分离部分形成柱状(在本示例中，截面为大致圆形的圆柱状)，限定了有源区。该柱状有源区可以大致垂直于衬底表面延伸。
随后，可以在第一叠层中限定互连结构的导电部分(上述过孔、导电节点、导电通道)的位置。
例如，可以将硬掩模层的图案转移到第一叠层中。由于如上所述处于第一叠层上方的第二叠层(连同支撑材料)已按硬掩模层构图，故而这种图案转移是可能的。具体地，如图8(a)和8(b)所示，可以硬掩模层(1013、1011)为掩模，依次对第一牺牲层1003a-3、第二牺牲层1003b-2、第一牺牲层1003a-2、第二牺牲层1003b-1和第一牺牲层1003a-1进行选择性刻蚀如RIE。RIE例如可以按大致垂直于衬底表面的方向进行，从而第一叠层中形成的图案与硬掩模层的图案可以在竖直方向上基本上对准。
当前，第一叠层呈现同硬掩模层一样的网格图案。对于针对过孔层的第一 牺牲层而言，如上所述，可以去除其中的桥接部分。这种去除可以如同以上分离有源区那样，通过对第一牺牲层进一步选择性刻蚀来实现。但是，这种情况下留下的节点较小(如上所述，相对于硬掩模层的节点向内凹入)。为确保工艺裕度并降低接触电阻，可以使用光刻技术，以使留下的节点较大。例如，如图9(a)和9(b)所示，可以在图8(a)和8(b)所示的结构上形成光刻胶1021，并将光刻胶1021构图为与硬掩模层的图案相对应的分离节点，以覆盖第一牺牲层中的各节点而露出节点之间的桥接部分。如图9(a)所示，光刻胶1021的各节点可以大于硬掩模层的节点从而可以使随后第一牺牲层中留下的节点较大，而且也可以覆盖上述分离的各有源区以避免其在对第一牺牲层刻蚀时受到影响。备选地，可以淀积一薄层作为硬掩模层，然后利用上述光刻胶对硬掩模层进行构图。
然后，如图10(a)和10(b)所示，可以相对于第二牺牲层(Si)，进一步选择性刻蚀第一牺牲层(SiGe)。于是，被光刻胶1021露出的第一牺牲层的桥接部分被去除(参见图10(b))，而节点得以保留(参见图10(a))(由于如上所述光刻胶1021的节点相对较大，故而在第一牺牲层的节点外周，可能残留一定长度的桥接部分)。随后，可以去除光刻胶1021。
于是，在第一叠层中限定了互连结构的框架，之后可以根据互连结构的连接设计，对第一叠层中的图案(第一牺牲层中为节点图案，第二牺牲层中为网格图案)进行修整。这种修整可以逐层进行。
为了使逐层修整更好地进行，可以在第一叠层和第二叠层的空隙中形成电介质层。如图11(a)和11(b)所示，可以通过例如淀积，在衬底1001上形成电介质层1023(例如，氧化物)。可以对淀积的电介质层1023进行平坦化处理如化学机械抛光(CMP)，CMP可以停止于硬掩模层的第二子层1013。于是，电介质层1023的顶面可以与第二子层1013的顶面基本共面。之后，可以通过使电介质层1023的(在特定区域中的)顶面逐步降低来依次露出第一叠层中的各层，以便实现逐层修整。
下文中，以先对第二牺牲层进行图案修整为例进行描述。当前在各第二牺牲层中，各节点之间均存在桥接部分。可以根据各互连层的连接设计，切断某些节点之间的桥接部分，从而在相应互连层中限定与连接设计相符的路径。为 了对桥接部分进行切断，需要到桥接部分的加工通道。
例如，可以在电介质层1023中形成露出桥接部分的开口。这可以通过利用另外的硬掩模层来实现。如图12(a)、12(b)和12(c)所示，可以在电介质层1023的顶面以及硬掩模层(1011/1013)的顶面上形成另一硬掩模层。类似地，该硬掩模层也可以包括例如为氧化物、厚度为约2-10nm的第一子层1025和例如为氮化物或低k电介质材料、厚度为约10-150nm的第二子层1027的叠层。关于第一子层1025和第二子层1027，也可以参见以上针对第一子层1011和第二子层1013的描述。
可以将硬掩模层构图为所需的图案，如上所述，以露出桥接部分。为此，可以在硬掩模层上形成光刻胶1029。通过光刻(曝光和显影)将光刻胶1029构图为包括一系列开口，这些开口分别处于各桥接部分处，例如各桥接部分的中部。在该示例中，将开口示出为椭圆形，但本公开不限于此，还可以是各种适合加工的形状，例如圆形等。
接下来，可以形成加工通道。例如，如图13(a)和13(b)，可以光刻胶1029为掩模，对第二子层1027(氮化物)进行选择性刻蚀如RIE。RIE例如可以按大致垂直于衬底表面的方向进行，并可以停止于第一子层1025(氧化物)。然后，如图14(a)、14(b)和14(c)所示，可以对第一子层1025和电介质层1023(在此均为氧化物)进行选择性刻蚀如RIE。RIE例如可以按大致垂直于衬底表面的方向进行，并可以进行至露出最上的第二牺牲层1003b-2，从而形成了加工通道T1，如图14(c)所示。例如，加工通道T1的底面可以位于需要露出的第二牺牲层1003b-2之下的第一牺牲层1003a-2的顶面和底面之间，一方面确保充分露出第二牺牲层1003b-2，另一方面避免露出之下的第二牺牲层1003b-1。为了准确控制刻蚀量，可以使用ALE。之后，可以去除光刻胶1029。
如图14(a)所示，各加工通道T1分别位于各桥接部分的大致中部，而各节点(因此，位于各节点处的有源区和第一牺牲层)被遮蔽。如图14(c)所示，在各加工通道T1中，除了第二牺牲层1003b-2之外，其余露出的材料层均是电介质材料(氧化物和氮化物的硬掩模层、氮氧化物的位置保持层1017、SiC的位置保持层1019和氧化物的电介质层1023)。
当前所有的桥接部分(具体地其中部)均在相应加工通道T1中露出。在 这些桥接部分中，一些桥接部分需要切断，而另一些桥接部分需要保留。对于需要切断的桥接部分和需要保留的桥接部分，可以分别进行处理。
另外，通常互连结构中存在多层互连层(因此，多层第二牺牲层)，而各互连层中的路线选择并不一定是一样的。例如，对于上下两层第二牺牲层而言，在同一加工通道T1处，可能一层(例如，上面一层)的桥接部分需要保留，而另一层(例如，下面一层)的桥接部分需要切断。于是，在通过加工通道T1对下一层的桥接部分进行切断处理时，因处于上方而同样可以在加工通道T1中露出的上一层的桥接部分(与下一层包括相同的材料，均为第二牺牲层)也可以被切断。根据本公开的实施例，对于需要保留的桥接部分，可以将其替换为相对于第二牺牲层具备刻蚀选择性的材料，以避免在对下方的第二牺牲层进行处理时受到影响。
例如，如图15(a)、15(b)和15(c)所示，可以在图14(a)、14(b)和14(c)所示的结构(去除光刻胶1029)上形成光刻胶1031，并通过光刻将光刻胶1031构图为露出其中桥接部分需要保留的加工通道T1，而覆盖其中桥接部分需要切断的加工通道T1。
然后，如图16(a)和16(b)所示，可以通过由光刻胶1031露出的加工通道T1，相对于加工通道T1中露出的电介质材料(如上所述的氧化物、氮化物、氮氧化物、SiC)，对第二牺牲层1003b-2(Si)进行选择性刻蚀(第一刻蚀)。这样，第二牺牲层1003b-2处于这些露出的加工通道T1中的部分将被去除。于是，在第二牺牲层1003b-2的部分桥接部分之处形成了间隙。之后，可以去除光刻胶1031。
接着，如图17(a)和17(b)所示，可以通过加工通道T1，向第二牺牲层1003b-2的桥接部分的间隙之中填充(第一填充)位置保持层1033-2b。位置保持层1033-2b可以包括相对于第二牺牲层(Si)具备刻蚀选择性的材料如SiGe，Ge的原子百分比可以为约25-75％。这种填充可以通过经加工通道T1淀积SiGe，然后对淀积的SiGe(相对于周围的电介质材料)进行回蚀如RIE来实现。RIE可以通过沿大致垂直于衬底表面的方向进行。由于硬掩膜层1011/1013的存在，回蚀后的SiGe可以完全填充在桥接部分的间隙之中，沿着相应的桥接部分延伸。
然后，对第二牺牲层1003b-2的部分桥接部分进行切断。
例如，如图18(a)和18(b)所示，可以通过加工通道T1，相对于加工通道T1中露出的其他材料层(例如，上述电介质材料以及SiGe的位置保持层1033-2b)，对第二牺牲层1003b-2(Si)进行选择性刻蚀(第二刻蚀)。这样，第二牺牲层1003b-2处于原本被光刻胶1031所覆盖的加工通道T1中的部分将被去除。对于以上被替换为位置保持层1033-2b的桥接部分，尽管也在加工通道T1中露出，但由于刻蚀选择性，在此可以基本不受影响。于是，在第二牺牲层1003b-2的部分桥接部分之处形成了间隙。在这些间隙中，可以填充(第二填充)绝缘部1035-2b。考虑到随后工艺中所需的刻蚀选择性(例如，相对于电介质层1023的刻蚀选择性)，绝缘部1035-2b可以包括例如SiC。这种填充可以如上所述通过淀积然后回蚀来实现。同样地，绝缘部1035-2b可以完全填充在桥接部分的间隙之中，沿着相应的桥接部分延伸。
于是，如图18(a)中所示，通过上述第一刻蚀-第一填充-第二刻蚀-第二填充(EFEF)工艺，将第二牺牲层1003b-2通过绝缘部1035-2b而隔离为不同的部分，这些部分随后可以形成不同的导电通道(的一部分)。
接下来，可以对下方的第二牺牲层1003b-1进行类似的处理。
例如，如以上结合图14(a)、14(b)和14(c)所述，可以对电介质层1023进行选择性刻蚀如RIE，以加深加工通道T1，从而露出第二牺牲层1003b-1。例如，加工通道T1的底面可以位于需要露出的第二牺牲层1003b-1之下的第一牺牲层1003a-1的顶面和底面之间。为准确控制刻蚀深度，可以使用ALE。然后，可以通过加深的加工通道T1，执行上述EFEF工艺，以在第二牺牲层1003b-1实现所需的路线选择。
具体地，如以上结合图15(a)、15(b)和15(c)所述，可以在图18(a)和18(b)所示的结构(加工通道T1如上所述已经加深)上形成光刻胶(未示出)，并将其构图为露出其中桥接部分需要保留的加工通道T1，而覆盖其中桥接部分需要切断的加工通道T1。该光刻胶的图案可以不同于上述光刻胶1031的图案，例如露出/覆盖不同的加工通道T1。
通过由光刻胶露出的加工通道T1，可以通过刻蚀和填充处理，将其中露出的第二牺牲层1003b-1的桥接部分替换为位置保持层1033-1b。关于位置保 持层1033-1b，可以参见以上关于位置保持层1033-2b的描述。之后，可以去除光刻胶。然后，通过加工通道T1，可以通过刻蚀和填充处理，将第二牺牲层1003b-1处于原本被光刻胶所覆盖的加工通道T1中的桥接部分替换为绝缘部1035-1b。关于绝缘部1035-1b，可以参见以上关于绝缘部1035-2b的描述。另外，尽管以上针对第二牺牲层1003b-2形成的位置保持层1033-2b和绝缘部1035-2b也在加工通道T1中露出，但是由于刻蚀选择性，在此可以基本不受影响。
于是，得到如图19(a)和19(b)所示的结构。如图19(a)中所示，通过EFEF工艺，将第二牺牲层1003b-1通过绝缘部1035-1b而隔离为不同的部分，这些部分随后可以形成不同的导电通道(的一部分)。
为避免在随后对第一牺牲层(在该示例中为SiGe)的处理过程中可能对位置保持层1033-1b、1033-2b(在该示例中同样为SiGe，Ge原子百分比可能不同)造成的影响，在此将可以将位置保持层1033-1b、1033-2b替换为相对于第一牺牲层具备刻蚀选择性的新的位置保持层。例如，如图20(a)和20(b)所示，可以通过加工通道T1，相对于第二牺牲层(Si)及其周围的电介质材料，对位置保持层1033-1b、1033-2b(SiGe)进行选择性刻蚀以将其去除。然后，可以通过淀积然后回蚀的方法，在位置保持层1033-1b、1033-2b原本所在的位置处填充新的位置保持层1037-1b、1037-2b。例如，位置保持层1037-1b、1037-2b可以包括Si，例如通过淀积如化学气相淀积(CVD)而形成的多晶硅或非晶硅。
另外，可以遮蔽加工通道T1，以避免相应的桥接部分在随后的处理中受影响。例如，如图21(a)和21(b)所示，可以在图20(a)和20(b)所示的结构上，淀积氧化物，淀积的量足以填充该结构中的空隙。然后，可以对淀积的氧化物进行平坦化处理如CMP，CMP可以停止于氮化物的第二子层1027。在此，将同样为氧化物的各层1011、1023、1025以及在此形成的氧化物一体示出为1039。
另外，之前形成的硬掩模层1025/1027用来限定到桥接部分的加工通道T1，在此可以被去除。例如，如图22(a)和22(b)所示，可以在图21(a)和21(b)所示的结构中，例如通过热磷酸，对氮化物的第二子层1027进行选择性刻蚀，以将其去除。接着，可以对得到的结构进行平坦化处理如CMP，CMP可以停 止于氮化物的第二子层1013。这样，去除了限定加工通道T1的硬掩模层1025/1027，另外网格图案的硬掩模层1011/1013仍然存在。
接下来，可以对第一牺牲层进行图案修整。当前在各第一牺牲层中，各节点均存在。可以根据各过孔层的布局设计，去除某些节点。为了对节点进行去除，需要到节点的加工通道。对第一牺牲层的修整可以与对第二牺牲层的修整按基本相同的方式进行，除了加工通道所在的位置不同之外。
例如，可以在电介质层1039中形成露出节点的开口。这可以通过利用另外的硬掩模层来实现。如图23(a)、23(b)、23(c)和23(d)所示，可以在电介质层1039的顶面以及硬掩模层(1011/1013)的顶面上形成另一硬掩模层。类似地，该硬掩模层也可以包括例如为氧化物、厚度为约2-10nm的第一子层1041和例如为氮化物或低k电介质材料、厚度为约10-150nm的第二子层1043的叠层。关于第一子层1041和第二子层1043，也可以参见以上针对第一子层1011和第二子层1013的描述。
可以将硬掩模层构图为所需的图案，如上所述，以露出节点。为此，可以在硬掩模层上形成光刻胶1045。通过光刻(曝光和显影)将光刻胶1045构图为包括一系列开口，这些开口分别处于各节点处，例如大致居中位于各节点。在此，为确保能形成向下的通道，开口的外周相对于硬掩模层1011/1013中节点的外周可以向外伸出。另外，为了确保能够完全去除第一牺牲层中希望去除的节点，开口的尺寸可以大于以上结合图9(a)所述的用来限定第一牺牲层中节点的光刻胶1021的节点尺寸。在该示例中，将开口示出为圆形，但本公开不限于此，还可以是各种适合加工的形状，例如椭圆形等。
接下来，可以形成加工通道。例如，如图24(a)、24(b)和24(c)所示，可以光刻胶1045为掩模，对第二子层1043(氮化物)进行选择性刻蚀如RIE。RIE例如可以按大致垂直于衬底表面的方向进行，并可以停止于第一子层1041(氧化物)。然后，可以对第一子层1041和电介质层1039(在此均为氧化物)进行选择性刻蚀如RIE。RIE例如可以按大致垂直于衬底表面的方向进行，并可以进行至露出最上的第一牺牲层1003a-3，从而形成了加工通道T2，如图24(c)所示。例如，加工通道T2的底面可以位于需要露出的第一牺牲层1003a-3之下的第二牺牲层1003b-2的顶面和底面之间，一方面确保充分露出第一牺牲层 1003a-3，另一方面避免露出之下的第一牺牲层1003a-2。为了准确控制刻蚀量，可以使用ALE。之后，可以去除光刻胶1045。
参照图25(a)，各加工通道T2分别大致居中位于各节点处，而各桥接部分基本被遮蔽(可能有一部分在加工通道T2中露出，这也是以上对位置保持层1033-1b、1033-2b进行替换的原因所在，因为位置保持层1033-1b、1033-2b有可能从加工通道T2中露出，特别是在器件小型化的情况下)。如图24(c)所示，在各加工通道T2中，除了第一牺牲层1003a-3之外，其余露出的材料层均是电介质材料(氧化物和氮化物的硬掩模层、氮氧化物的位置保持层1017、SiC的位置保持层1019、氧化物的电介质层1039、SiC的绝缘部1035-2b)。另外，在该示例中，示出了位置保持层1037-2b也在加工通道T2中露出。注意，在图24(c)的截面中，并未看到第一牺牲层1003a-3，因为CC′线所在的位置处于桥接部分处(参见图23(a))，而如上所述在第一牺牲层中桥接部分已被基本去除。
当前所有的节点均在相应加工通道T2中露出。在这些节点中，一些节点需要去除(替换为绝缘部)，而另一些节点需要保留。对于需要去除的节点和需要保留的节点，可以分别进行处理。如上所述，为了避免各层处理的相互干扰，对于需要保留的节点，可以将其替换为相对于第一牺牲层具备刻蚀选择性的材料。
例如，如图25(a)至25(f-4)所示，可以在图24(a)、24(b)和24(c)所示的结构(去除光刻胶1045)上形成光刻胶1047，并通过光刻将光刻胶1047构图为露出其中节点需要保留的加工通道T2，而覆盖其中节点需要去除的加工通道T2。可以经光刻胶1047露出的加工通道T2，通过类似于上述第一刻蚀和第一填充的方法，将第一牺牲层1003a-3替换为位置保持层1037-3a。位置保持层1037-a可以包括相对于第一牺牲层具备刻蚀选择性的材料例如Si。
图25(f-1)至25(f-4)详细示出了这种过程。具体地，图25(f-1)示出了光刻胶1047露出的一个加工通道T2。如图25(f-2)所示，可以通过该加工通道T2，对其中露出的第一牺牲层1003a-3(在此为SiGe)进行选择性刻蚀以将其去除。之后，可以去除光刻胶1047。然后，如图25(f-3)所示，可以经加工通道T2，淀积(多晶或非晶)硅1037p(可以通过例如原位掺杂而被掺杂为n型或者p 型，掺杂浓度为约1E19-5E21cm -3)，并对淀积的硅1037p进行回蚀如RIE，来在被去除的第一牺牲层1003a-3的节点原本所在的位置处填充位置保持层1037-3a。可以进行多次淀积和回蚀，以更好地填充位置保持层1037-3a。
然后，将第一牺牲层1003a-3的部分节点去除。可以通过类似于上述第二刻蚀和第二填充的方法，将第一牺牲层1003a-3的这部分节点替换为绝缘部。例如，如图26所示，可以通过加工通道T2，对第一牺牲层1003a-3(SiGe)进行选择性刻蚀。这样，第一牺牲层1003a-3处于原本被光刻胶1047所覆盖的加工通道T2中的部分将被去除。对于以上被替换为位置保持层1037-3a的节点，尽管也在加工通道T2中露出，但由于刻蚀选择性，在此可以基本不受影响。于是，在第一牺牲层1003a-3的部分节点之处形成了间隙。在这些间隙中，可以填充绝缘部1035-3a。绝缘部1035-3a可以与之前的绝缘部1035-1b、1035-2b包括相同的电介质材料如SiC。这种填充可以如上所述通过淀积后回蚀来实现。
于是，如图26所示，通过上述EFEF工艺，将第一牺牲层1003a-3中的部分节点替换为绝缘部1035-3a，而其余节点保留(事实上，为了刻蚀选择性，替换为位置保持层1037-3a)以便随后限定过孔。
接下来，可以对下方的第一牺牲层1003a-2进行类似的处理。
例如，可以对电介质层1039进行选择性刻蚀如RIE，以加深加工通道T2，从而露出第一牺牲层1003a-2。例如，加工通道T2的底面可以位于需要露出的第一牺牲层1003a-2之下的第二牺牲层1003b-1的顶面和底面之间。然后，可以通过加深的加工通道T2，执行上述EFEF工艺，以在第一牺牲层1003a-2实现所需的过孔布局。
具体地，如图27(a)、27(b)和27(c)所示，可以在图26的结构(加工通道T2上所述已经加深)上形成光刻胶1053，并将其构图为露出其中节点需要保留的加工通道T2，而覆盖其中节点需要去除的加工通道T2。该光刻胶1053的图案可以不同于上述光刻胶1047的图案。
如图28(a)和28(b)所示，通过由光刻胶露出的加工通道T2，可以通过刻蚀和填充处理，将其中露出的第一牺牲层1003a-2的节点替换为位置保持层1037-2a。关于位置保持层1037-2a，可以参见以上关于位置保持层1037-3a的 描述。之后，可以去除光刻胶1053。然后，如图29(a)和29(b)所示，通过加工通道T2，可以通过刻蚀和填充处理，将第一牺牲层1003a-2处于原本被光刻胶1053所覆盖的加工通道T2中的节点替换为绝缘部1035-2a。关于绝缘部1035-2a，可以参见以上关于绝缘部1035-3a的描述。
图30示出了通过如上所述对第一叠层中的各层(事实上，在该示例中由于最底层的第一牺牲层1003a-1最终用来限定隔离层，故而无需对它的图案进行进一步修整)进行EFEF处理之后得到的结构。如图中的箭头所示，在第一叠层中，限定了不同的互连通路。
接下来，如图31(a)所示，可以将最下的第一牺牲层1003a-1替换为绝缘材料，以实现互连结构与衬底之间的隔离。例如，如图31(b-1)所示，可以进一步加深加工通道T2，以露出第一牺牲层1003a-1。例如，对电介质层1039的回蚀可以停止于衬底1001的表面，从而加工通道T2的底面可以由衬底1001的顶面限定。然后，对露出的第一牺牲层1003a-1进行选择性刻蚀，以将其去除。接着，如图31(b-2)所示，可以在所得结构的空隙中填充电介质材料例如氧化物，实现电隔离。淀积的量足以填充结构中的空隙。然后，可以对淀积的氧化物进行平坦化处理如CMP，CMP可以停止于氮化物的第二子层1043。在此，将结构中的所有氧化物一体示出为1055。
另外，之前形成的硬掩模层1041/1043用来限定加工通道T2，在此可以被去除。例如，可以通过热磷酸对氮化物的第二子层1043进行选择性刻蚀，以将其去除。接着，可以对得到的结构进行平坦化处理如CMP，CMP可以停止于氮化物的第二子层1013。这样，去除了限定加工通道T2的硬掩模层1041/1043，另外网格图案的硬掩模层1011/1013仍然存在，如图32(a)和32(b)所示。
在以上示例中，先对第二牺牲层进行逐层修整，然后对第一牺牲层进行逐层修整。但是本公开不限于此。例如，也可以先对第一牺牲层进行逐层修整，然后对第二牺牲层进行逐层修整。
然后，可以第二叠层中的各有源区为基础，制作竖直型器件。
为此，可以回蚀电介质层1055，以露出第二叠层。例如，如图33(b-1)所示，可以对电介质层1055进行回蚀如RIE。RIE可以沿大致垂直于衬底表面 的方向进行，并且可以进行至露出第二叠层，例如回蚀后电介质层1055的顶面可以在第一叠层中最上方的层的顶面与底面之间。为准确控制回蚀量，可以使用ALE。由于硬掩膜层1011/1013的存在，露出的第二叠层呈现网格图案。然后，如图33(a)和33(b-2)所示，可以对位置保持层1019进行选择性刻蚀以将其去除，从而露出第一源/漏层1005和第二源/漏层1009。
可以对露出的第一源/漏层1005和第二源/漏层1009进行掺杂，以在其中形成源/漏区。根据本公开的实施例，可以通过固态掺杂剂源来进行掺杂。但是，本公开不限于此。例如，可以在生长第一源/漏层1005和第二源/漏层1009时对它们进行原位掺杂，或者可以通过离子注入等方式来进行掺杂。
如图34(a)和34(b)所示，可以在第一源/漏层1005和第二源/漏层1009的表面上形成固态掺杂剂源层1057。例如，为了形成n型器件，固态掺杂剂源层1057可以包括含n型掺杂剂的氧化物薄膜，厚度为约0.5-5nm。n型掺杂剂可以包括P或As，含量为约0.01-3％。固态掺杂剂源层1057可以通过淀积如CVD或原子层淀积(ALD)以大致共形的方式形成在图33(a)和33(b-2)所示的结构上，以充分覆盖第一源/漏层1005和第二源/漏层1009的表面。为避免交叉污染，在固态掺杂剂源层1057上可以形成扩散阻挡层1059。例如，扩散阻挡层1059可以包括SiC，厚度为约1-5nm。扩散阻挡层1059可以通过淀积如CVD或ALD以大致共形的方式形成在固态掺杂剂源层1057上。
以上形成了针对n型器件的固态掺杂剂源层1057。在衬底上还形成p型器件的情况下，还可以另外形成针对p型器件的固态掺杂剂源层。
例如，如图35(a)和35(b)所示，可以在图34(a)和34(b)所示的结构上形成光刻胶1061。可以通过光刻，将光刻胶1061遮蔽要形成n型器件的区域且因此遮蔽该区域中的n型固态掺杂剂源层1057，而露出要形成p型器件的区域且因此露出该区域中的n型固态掺杂剂源层1057。
然后，如图36所示，可以通过选择性刻蚀，例如通过气相HF，依次刻蚀露出的扩散阻挡层1059和n型固态掺杂剂源层1057，以将其去除。在刻蚀过程中，硬掩模层中氧化物的第一子层1011的露出部分也可以被去除。之后，可以去除光刻胶1061。
接着，如图37所示，可以形成针对p型器件的固态掺杂剂源层1063。例 如，p型固态掺杂剂源层1063可以包括含p型掺杂剂的氧化物薄膜，厚度为约0.5-5nm。p型掺杂剂可以包括B，含量为约0.01-3％。固态掺杂剂源层1063可以通过淀积如CVD或ALD以大致共形的方式形成。
尽管在此描述了先形成n型固态掺杂剂源层1057然后再形成p型固态掺杂剂源层1063，但是本公开不限于此，它们的形成顺序可以交换。
之后，可以通过退火，将掺杂剂源层中的掺杂剂驱入相应的第一源/漏层1005和第二源/漏层1009中，以在其中形成源/漏区。在附图中，以不同的灰度分别示出了n型掺杂和p型掺杂。根据实施例，n型掺杂的浓度可以为约1E18-1E21cm -3，p型掺杂的浓度可以为约1E18-1E21cm -3。之后，可以通过选择性刻蚀如气相HF，去除各固态掺杂剂源层和扩散阻挡层。
随后，可以绕沟道层的外周形成栅电极，即可完成器件的制作。为了形成能够自对准于沟道层的栅电极，可以恢复原本在源/漏层周围的位置保持层。例如，如图38(a)和38(b)所示，可以在硬掩模层下方第二叠层的空隙中形成位置保持层1065。关于位置保持层1065，可以参见以上关于位置保持层1019的描述。
另外，为了降低接触电阻，可以在第一源/漏层1005和第二源/漏层1009的表面上形成硅化物层。例如，在形成位置保持层1065之前，可以大致共形的方式淀积约0.5-5nm厚的金属如NiPt、Co或Ti，并进行退火使淀积的金属与第一源/漏层1005和第二源/漏层1009(Si)发生反应以形成硅化物(未示出)。之后，可以去除未反应的金属。
随后，可以形成栅堆叠。针对n型器件和p型器件，可以分别形成不同的栅堆叠(例如，具备不同的等效功函数)。
为此，如图39(a)和39(b)所示，可以通过选择性刻蚀，去除位置保持层1017。于是，露出沟道层1007的表面。可以通过淀积，绕沟道层1007的表面形成栅介质层1067。栅介质层1067可以大致共形的方式形成在图38(a)和38(b)所示的结构上，厚度例如为约1-5nm。例如，栅介质层1067可以包括高k栅介质如HfO 2。在形成高k栅介质之前，还可以在沟道层1007的表面上形成界面层，例如通过热氧化形成的氧化物，厚度为约0.3-2nm。
接着，如图40(a)和40(b)所示，可以在图39(a)和39(b)所示的结构上形成 栅电极材料。例如，可以淀积针对n型器件的功函数调节金属，并且可选地还可以淀积栅导电金属，以完全填充结构中的空隙。对所淀积的栅电极材料进行回蚀如RIE，得到栅电极1069。RIE可以沿大致垂直于衬底表面的方向进行。由于硬掩模层1011/1013的存在，回蚀后的栅电极1069同样呈网格图案。也即，栅电极1069可以位于位置保持层1017原本所在的位置处，且因此自对准于沟道层1007。
以上形成了针对n型器件的栅电极1069。还可以另外形成针对p型器件的栅电极。
例如，如图41所示，可以在图40(a)和40(b)所示的结构上形成光刻胶1071。可以通过光刻，将光刻胶1071遮蔽要形成n型器件的区域且因此遮蔽该区域中的栅电极1069，而露出要形成p型器件的区域且因此露出该区域中的栅电极1069。可以通过选择性刻蚀，刻蚀露出的栅电极1069，以将其去除。之后，可以去除光刻胶1071。
然后，如图42(a)和42(b)所示，可以在由于栅电极1069的去除而释放的空间中，形成针对p型器件的栅电极1073。栅电极1073可以按形成栅电极1069的相同方式形成，但可以包括不同的材料(例如，具备不同的功函数)。同样地，栅电极1073可以自对准于沟道层1007。
在该示例中，n型器件和p型器件的栅堆叠共用相同的栅介质层1067。但是本公开不限于此。例如，在p型器件区域也可以去除栅介质层1067，并另外形成针对p型器件的栅介质层。同样地，n型器件的栅堆叠和p型器件的堆叠的形成顺序可以交换。
如上所述，栅电极1069和1073整体上呈现同硬掩模层1011/1013一样的网格图案，因此栅电极整体上在沟道层1007所在的平面上通过桥接部分而连接成一体。可以根据电路的连接设计，将栅电极之间不需要的连接切断。
例如，如图43(a)和43(b)所示，可以在图42(a)和42(b)所示的结构上形成光刻胶1075。可以通过光刻，将光刻胶1075构图为覆盖需要保留的栅电极之间的连接，而露出需要切断的栅电极之间的连接。然后，可以通过选择性刻蚀，对露出的栅电极进行刻蚀，以将它们去除。如图43(b)所示，栅电极被切断。然后，可以去除光刻胶1075。然后，如图44所示，在栅电极被切断而释放的 空间中，可以填充电介质材料如SiC以形成绝缘部1077，以实现栅电极之间的隔离。绝缘部1077的填充可以通过如上所述的淀积然后回蚀的方法来实现，且因此可以与硬掩模1011/1013的图案保持一致，处于栅电极被去除部分原本所在的位置处。
在完成器件制作之后，可以进行互连制作。互连制作包括在第一叠层中形成导电通路、形成向第一叠层中的导电通道或栅电极施加电信号的接触插塞等。
如上所述，在第一叠层中，已经通过半导体材料(在该示例中，为硅)限定了互连通道(第一叠层中的其他部分为电介质材料，实现电隔离)。可以将第一叠层中的这些半导体材料替换或转换为导电材料来形成互连结构。例如，可以通过硅化反应，将这些半导体材料转换为导电硅化物。或者，可以将这些半导体材料替换为其他导电材料。在此，以硅化反应为例进行描述。
为例避免在硅化处理时栅电极中的金属被侵蚀，如图45所示，可以形成保护层1079来覆盖并因此保护栅电极。根据实施例，可以通过侧墙形成工艺，来形成侧墙形式的保护层1079。例如，可以在图44所示的结构上以大致共形的方式淀积一层约1-5nm厚的SiC，并对淀积的SiC沿大致垂直于衬底表面的方向进行RIE，以去除其横向延伸部分，而留下其竖直延伸部分，从而得到保护层1079。保护层1079可以绕第二叠层中各节点以及桥接部分的外周形成，从而覆盖绕沟道层形成的栅电极。
另外，第一叠层当前被电介质层1055所覆盖。为了对其中的半导体材料进行硅化处理，如图46所示，可以回蚀如RIE电介质层1055(当然，在回蚀电介质层1055之后，需要先对其表面的栅介质层1067进行选择性刻蚀如RIE)。为准确控制回蚀量，可以使用ALE。
然后，如图47(a)、47(b)和47(c)所示，可以进一步选择性刻蚀电介质层1055，以露出第一叠层中的半导体材料的侧壁。可以控制刻蚀的量，使得电介质层1005的底部仍然保持覆盖衬底1001。为准确控制刻蚀量，可以使用ALE。
对于第一叠层中的半导体材料，可以通过它们露出的侧壁，进行硅化处理。例如，可以淀积约1-10nm厚的金属如NiPt、Co或Ti，并进行退火使淀积的金属与第一叠层中的半导体材料(Si)发生反应以形成硅化物1081。之后，可以去除未反应的金属。
在如上所述在第一叠层与第二叠层之间形成接触界面层的情况下，第一源/漏层1005可以通过接触界面层连接到硅化物1081，从而可以获得降低的接触电阻。
在以上示例中，对第一叠层中的半导体材料进行硅化处理在形成栅电极之后进行。这是因为高k金属栅可以适应较大范围的热处理(温度)，从而可以给出较大的工艺窗口。但是，本公开不限于此。例如，可以在第一叠层中完成互连结构之后再在第二叠层中进行器件制作。
对于第一叠层，可以补充其中的电介质层，以实现电隔离。例如，如图48所示，可以在图47(a)、47(b)和47(c)所示的结构上淀积氧化物，并对淀积的氧化物回蚀，形成电介质层1055′。在回蚀之前，可以对淀积的氧化物进行平坦化处理如CMP，CMP可以停止于氮化物的第二子层1013。回蚀后的电介质层1055′的顶面可以位于第一叠层和第二叠层之间的边界附近，以露出保护层1079。
接下来，可以制作接触插塞。这种接触插塞可以连接到第一叠层中的互连结构，或者可以连接到栅电极，以便向它们施加电信号。如上所述，这种接触插塞可以通过将部分有源区替换或转换为导电材料来形成，从而可以自对准于其需要连接的栅电极或者互连结构中的过孔。
当前，各有源区周围被保护层1079所覆盖。可以通过去除需要转换或替换为接触插塞的有源区周围的保护层1079，并对由此露出的有源区进行硅化处理来形成接触插塞。
例如，如图49(a)、49(b)、49(c)和49(d)所示，可以在图48所示的结构上形成光刻胶1083。可以通过光刻，在光刻胶1083中形成一系列开口，这些开口位于需要形成接触插塞的节点处。可以经光刻胶1083中的开口，通过选择性刻蚀，去除露出的保护层1079，并依次去除由于保护层1079的去除而露出的栅介质层、栅电极等，以露出相应有源区的侧壁。之后，可以去除光刻胶1083。
由于这种刻蚀，这些露出侧壁的有源区与相邻有源区之间原本可能连接在一起的栅电极也被切断。如前所述，栅电极之间的连接是根据电路的连接布局确定的。为了弥补这种栅电极的切断，如图50(a)、50(b)、50(c)和50(d)所示， 可以在硬掩模层下方、在第一叠层的空隙中填充半导体材料1085，例如淀积多晶硅或非晶硅，它们随后也可以被替换或转换为导电材料。
之后，如图51(a)、51(b)、51(c)和51(d)所示，可以进行硅化处理，以将未被保护层1079覆盖的半导体材料转换为导电硅化物以充当接触插塞1087。关于硅化处理，可以参考之前的描述，在此不再赘述。
如图51(a)所示，部分接触插塞可以与下方的互连结构接触，以向互连结构施加电信号。例外，如图51(b)、51(c)和51(d)所示，部分接触插塞通过绝缘部1035-3a与下方的互连结构电隔离，这些接触插塞可以用于向栅电极施加电信号。如图51(d)所示，接触插塞1087通过横向延伸部分而接触栅电极1073。如上所述，这种横向延伸部分与硬掩模层网格图案中的桥接部分相对准，处于原本栅电极所在的位置处。
通过以上处理，实现了器件下部源/漏区、栅电极的连接。另外，对于器件的上部源/漏区以及接触插塞，可以在器件上方形成接触部。例如，如图52(a)、52(b)、52(c)和52(d)所示，可以淀积电介质层如氧化物(在此，仍然示出为1055′)以填满结构中的间隙，以实现器件间电隔离。另外可以形成穿透硬掩模层和/或电介质层1055′的接触部1091，以向上部源/漏区以及接触插塞施加电信号。这些接触部可以通过刻蚀孔洞，并在其中填充导电材料如金属来形成。
尽管以上以竖直型半导体器件为例进行了描述，但是本公开不限于此，而是可以应用于其他形式的器件，例如FinFET或平面型半导体器件。
图53至66(b)示出了根据本公开实施例的制造FinFET的流程中部分阶段的示意图。在以下，将主要描述与上述实施例之间的不同之处，而简化或省略与上述实施例重复的描述。
如图53所示，可以在衬底2001上形成交替设置的第一牺牲层2003a-1、2003a-2、2003a-3和第二牺牲层2003b-1、2003b-2的第一叠层。关于衬底2001以及第一牺牲层2003a-1、2003a-2、2003a-3和第二牺牲层2003b-1、2003b-2的详情，可以参见以上关于衬底1001以及第一牺牲层1003a-1、1003a-2、1003a-3和第二牺牲层1003b-1、1003b-2的描述。另外，如上所述，在形成第一叠层之前，可以在衬底上设置接触层。
在第一叠层上，可以通过例如外延生长，形成鳍前体层2005。鳍前体层 2005可以包括合适的半导体材料如Si，以便在后继形成充当FinFET的有源区的鳍。鳍前体层2005可以形成为具有一定的高度如约20-100nm。
在鳍前体层2005上，可以形成硬掩模层，例如包括第一子层2011和第二子层2013。关于第一子层2011和第二子层2013的详情，可以参见以上关于第一子层1011和第二子层1013的描述。
与上述实施例类似，可以在第一叠层和鳍前体层2005中限定网格图案。为此，如图54(a)和54(b)所示，可以形成具有网格图案的光刻胶2015。关于光刻胶2015及其网格图案的详情，可以参见以上关于光刻胶1015及其网格图案的详情。
这里需要指出的是，在该示例中，将光刻胶2015示出为其网格图案中的节点部分粗于桥接部分，与上述光刻胶1015相似。这对于随后制作到节点处形成的源/漏区的接触是有利的。但是，本公开不限于此。节点部分的线宽可以与桥接部分的线宽实质上相同。例如，可以通过粗细均匀的相互交叉直线条来限定网格图案。
接下来，可以限定有源区。
与上述实施例相似，可以将光刻胶2015的图案转移到硬掩模层中，并继而转移到下方的鳍前体层2005中。具体地，如图55(a)和55(b)所示，可以构图后的光刻胶2015为掩模，依次对硬掩模层(2013、2011)、和鳍前体层2005进行选择性刻蚀如RIE。RIE例如可以按大致垂直于衬底表面的方向进行，并可以停止于第一叠层的顶面。于是，鳍前体层2005可以呈现同硬掩模层一样的网格图案。网格的边(沿行或列方向延伸的线条)可以限定鳍的位置。更具体地，鳍前体层2005的桥接部分的大致中部可以用作沟道区，沟道区两侧的部分(节点部分及其周围一定长度的桥接部分)可以用作源/漏区。之后，可以去除光刻胶2015。
另外，为了在随后对第一叠层进行处理时影响鳍前体层2005(在该示例中，与第一叠层中的第二牺牲层均为Si)，可以在鳍前体层2005的表面上形成保护层。例如，如图56所示，可以按侧墙形成工艺，在鳍前体层2005的侧壁上形成保护层2101。例如，保护层2101可以包括氮化物，厚度为约1-10nm。
接下来，可以按照以上描述的EFEF工艺，在第一叠层中限定互连结构。 对此，可以参见以上结合图8(a)至47(c)的描述。但是，在此可以省略以上结合图33(a)至45描述的与源/漏掺杂和金属栅的形成有关的工艺。
于是，可以得到如图57(a)、57(b)、57(c)和57(d)所示的结构。如图所示，在第一叠层中形成了硅化物的互连通路2081，其包括过孔层中的过孔以及互连层中的导电通道。关于互连通路2081的详情，可以参见以上关于硅化物1081的描述。另外，图中还示出了第一叠层中的绝缘部2035-2a、2035-3a、2035-1b、2035-2b以及电介质层2055，关于它们的详情，可以参见以上关于绝缘部1035-2a、1035-3a、1035-1b、1035-2b以及电介质层1055的描述。
在限定了互连结构之后，可以进行器件的制作。为此，如图58所示，可以通过选择性刻蚀，去除保护层2101。在去除保护层2101时，在该示例中也为氮化物的第二子层2013也可以被去除。
另外，对于第一叠层，可以补充其中的电介质层，以实现电隔离。例如，可以淀积氧化物，并对淀积的氧化物回蚀，形成电介质层2055′。在回蚀之前，可以对淀积的氧化物进行平坦化处理如CMP。回蚀后的电介质层2055′的顶面可以位于第一叠层和第二叠层之间的边界附近，例如低于该边界。
鳍前体层2005相对于下方的结构竖直伸出，类似于鳍。本领域存在各种各样的技术来基于鳍制造FinFET，以下描述仅作为示例。
当前，鳍前体层2005是连续的，也即各器件的有源区连接在一起。可以根据器件布局设计，将鳍前体层2005分离为不同的有源区。可以形成与这些有源区(鳍)相交的栅电极，从而制作器件。根据本公开的实施例，器件有源区之间的分离与栅电极的制作可以结合在一起。
例如，如图59(a)、59(b)、59(c)和59(d)所示，可以在电介质层2055′上，形成与鳍前体层2005的各桥接部分相交的牺牲栅。例如，可以在电介质层2055′上例如通过淀积，依次形成牺牲栅介质层2103和牺牲栅电极层2105。例如，牺牲栅介质层2103可以包括氧化物，厚度为约1-5nm；牺牲栅电极层2105可以包括非晶硅或多晶硅，其顶面可以高于鳍前体层2005的顶面以便覆盖各桥接部分的侧壁和顶面。为构图方便，可以在牺牲栅电极层2105上例如通过淀积，形成硬掩模层2107。例如，硬掩模层2107可以包括氮化物，厚度为约10-150纳米。可以通过光刻胶(未示出)，通过选择性刻蚀如RIE，将硬掩模层2107 和牺牲栅电极层2105构图为所需的形状，例如与各桥接部分相交(例如，垂直)的条形。刻蚀可以停止于氧化物的牺牲栅介质层2103。
如图59(a)所示，在鳍前体层2005的各桥接部分的大致中部，均形成了与之相交的牺牲栅。根据布局设计，部分牺牲栅可以连接在一起。这里需要指出的是，这些牺牲栅在随后并不一定被全部替换为真正的栅，而是有部分可以限定有源区之间的隔离位置。
在图59(b)中，仅为了图示方便起见，没有示出第一叠层中的构造。关于第一叠层中的构造，可以参见上述实施例中的相关描述。
然后，如图60(a)、60(b)和60(c)所示，可以在牺牲栅的侧壁上，形成栅侧墙2109。例如，栅侧墙2109可以包括氮化物。本领域存在多种方式来形成栅侧墙，在此不再赘述。这里需要指出的是，栅侧墙2109也可能形成在鳍前体层2005的竖直侧壁上，但是图中为方便起见并未示出。
可以通过例如离子注入，对鳍前体层2005(特别是未被牺牲栅遮蔽的部分，主要是各节点及其周围一定长度的桥接部分)进行掺杂，以形成源/漏区。对于n型器件和p型器件，可以分别进行不同导电类型的掺杂。
根据本公开的另一实施例，可以利用应变源/漏技术。例如，可以对鳍前体层2005未被牺牲栅遮蔽的部分进行选择性刻蚀如RIE以将其部分地去除，可以留有一部分用作种子层。然后，可以在留下的种子层上，例如通过外延生长，形成源/漏区。生长的源/漏区可以具有与鳍前体层2005不同的材料(例如，具有不同的晶格常数)，以便向鳍前体层2005中形成的沟道区施加应力。例如，对于n型器件，源/漏区2111可以包括Si：C；对于p型器件，源/漏区2113可以包括SiGe。源/漏区可以在生长时原位掺杂。
另外，可以进行退火，以使得掺杂剂扩散，从而改善源/漏区与源/漏区下方的过孔之间的电连接。
接下来，可以进行有源区分离和牺牲栅替换。
为此，如图61所示，可以在图60(a)、60(b)和60(c)所示的结构上淀积氧化物，并对淀积的氧化物进行平坦化处理如CMP(可以停止于牺牲栅2105)，以填充各器件之间的间隙。在此，将淀积的氧化物与电介质层2055′仍然一体示出为2055′。
然后，如图62(a)和62(b)所示，可以在电介质层2055′上形成光刻胶2111，并根据布局设计将其构图为覆盖需要替换为真正栅的牺牲栅，并露出限定有源区之间隔离位置的牺牲栅。接着，如图63(a)、63(b)和63(c)所示，可以光刻胶2111为掩模，对牺牲栅2105、牺牲栅介质层2103进行选择性刻蚀，以露出下方的鳍前体层2005(相应桥接部分的中部)。对露出的鳍前体层2005可以进行选择性刻蚀如RIE，RIE可以停止于下方的电介质层2055′，从而使得鳍前体层2005在相应位置处被切断。之后，可以去除光刻胶2111。在相应牺牲栅侧墙的内侧，可以通过淀积然后CMP来填充电介质如氧化物，以实现电隔离。在此，将填充的电介质与电介质层2055′一体示出为2113。
接着，可以进行栅替换。如图64(a)、64(b)和64(c)所示，可以通过选择性刻蚀，去除牺牲栅电极层2105和牺牲栅介质层2103，并在由于牺牲栅电极层2105和牺牲栅介质层2103的去除而留下的空间中，形成栅介质层2067和栅电极层2069、2073。关于栅介质层2067和栅电极层2069、2073的详情，可以参见以上关于栅介质层1067和栅电极层1069、1073的描述。本领域存在各种方式来进行栅替换，在此不再赘述。
与上述实施例中类似，部分源/漏区可以限定接触插塞。如图65(a)、65(b)和65(c)所示，可以形成光刻胶2083，并将其构图为在需要形成接触插塞处具有开口。可以经光刻胶2083中的开口，通过选择性刻蚀如RIE，使电介质层2113下凹，以露出相应位置处的源/漏区。可以通过硅化处理，使露出的源/漏区转换为接触插塞2087。关于硅化处理的详情，可以参见以上描述。
通过以上处理，实现了器件的部分源/漏区与互连结构的连接。另外，对于器件的一些源/漏区和栅电极以及接触插塞，可以在器件上方形成接触部。例如，如图66(a)和66(b)所示，可以淀积电介质如氧化物(在此，与电介质层2113一起示出为2113′)以填满结构中的间隙，以实现器件间电隔离。另外可以形成穿透电介质层2113′的接触部2091。由于到部分源/漏区的电连接可以通过器件下方的互连结构来实现，因此可以使器件上方金属互连的面积更充裕，利于器件的小型化。
图67至70(b)示出了根据本公开实施例的制造平面半导体器件的流程中部分阶段的示意图。在以下，将主要描述与上述实施例之间的不同之处，而简化 或省略与上述实施例重复的描述。
如图67所示，可以在衬底3001上形成交替设置的第一牺牲层3003a-1、3003a-2、3003a-3和第二牺牲层3003b-1、3003b-2的第一叠层。关于衬底3001以及第一牺牲层3003a-1、3003a-2、3003a-3和第二牺牲层3003b-1、3003b-2的详情，可以参见以上关于衬底1001以及第一牺牲层1003a-1、1003a-2、1003a-3和第二牺牲层1003b-1、1003b-2的描述。
在第一叠层上，可以通过例如外延生长，形成有源层3005。有源层3005可以包括合适的半导体材料如Si。相比于鳍前体层2005，有源层3005可以相对较薄，例如为约5-70nm。
与上述实施例类似，可以在第一叠层和有源层3005中限定网格图案。对此，可以参见以上结合图54(a)至57(d)的描述。然后，如以上结合图58所述，可以去除有源层3005的网格图案的侧壁上的保护层，并形成电介质层3055。与上述实施例的不同之处在于，在形成电介质层3055时，CMP可以停止于有源层3005的顶面，而并不对电介质层3055再回蚀，从而得到如图68(a)和68(b)所示的结构。也即，在该实施例中，有源层3005并不需要像FinFET中那样相对突出。关于图中示出的3081、3035-2a，可以参见以上关于1081、1035-2a的描述。
之后，可以有源层3005为基础制作器件。制作器件的过程可以与以上制作FinFET的过程基本相同，除了有源区的形式不同之外。
根据本公开的另一实施例，如图69(a)和69(b)所示，在如以上结合图54(a)至57(d)所述限定网格图案之后，并不去除有源层3005的网格图案的侧壁上的保护层3101。关于保护层3101，可以参见以上关于保护层2101的描述。在保留保护层3101的情况下，形成电介质层3055。在形成电介质层3055时，CMP可以停止于硬掩模层的第二子层3013。这可以降低CMP对于有源层3005的损伤。之后，如图70(a)和70(b)所示，可以通过选择性刻蚀，对氮化物的第二子层3013和保护层3101进行回蚀，以露出下方的第一子层3011。为准确控制回蚀量，可以使用ALE。然后，可以选择性刻蚀第一子层3013，以露出有源层3005的表面。之后，可以有源层3005为基础制作器件。关于第一子层3011和第二子层3013，可以参见以上关于第一子层1011和第二子层1013的 描述。
根据本公开实施例的互连结构和电路可以应用于各种电子设备。例如，可以基于这样的互连结构或电路形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
根据本公开的实施例，还提供了以下方面。
1.一种制造用于半导体器件的互连结构的方法，包括：
在衬底上设置交替堆叠的至少一个第一牺牲层和至少一个第二牺牲层的第一叠层，其中，第一叠层的最上层是第一牺牲层；
在第一叠层上设置器件有源材料层；
在器件有源材料层上设置第一硬掩模层，第一硬掩模层具有由沿彼此交叉的第一方向和第二方向延伸的线条限定的网格图案，包括由线条之间的交叉点限定的节点以及节点之间的桥接部分；
利用第一硬掩模层，在器件有源材料层中限定针对半导体器件的有源区；
利用第一硬掩模层，对第一叠层进行构图，从而第一叠层中的各层具有与第一硬掩模层相对应的网格图案，并因此包括节点以及节点之间的桥接部分；以及
在第一叠层中限定互连结构，包括：
针对各第一牺牲层：将该第一牺牲层的各桥接部分至少部分地去除从而该第一牺牲层的节点彼此分离；根据互连结构的布局，去除该第一牺牲层中的一个或多个节点，以及
针对各第二牺牲层：根据互连结构的布局，将该第二牺牲层中的一个或多个桥接部分切断，以及在各第一牺牲层和各第二牺牲层的残留部分的区域处形成导电材料。
2.根据方面1所述的方法，其中，在第一叠层中限定互连结构时，
先根据互连结构的布局对各第一牺牲层进行所述去除处理，然后根据互连结构的布局对各第二牺牲层进行所述切断处理，或者
先根据互连结构的布局对各第一牺牲层进行所述去除处理，然后根据互连结构的布局对各第二牺牲层进行所述切断处理。
3.根据方面1或2所述的方法，其中，从上至下依次对第一叠层中的各层进行处理。
4.根据方面3所述的方法，其中，
在对各第一牺牲层进行所述去除处理时，该方法还包括：利用第一遮蔽层遮蔽第一叠层；以及逐渐向下回蚀第一遮蔽层以逐一露出各第一牺牲层，
在对各第二牺牲层进行所述切断处理时，该方法还包括：利用第二遮蔽层遮蔽第一叠层；以及逐渐向下回蚀第二遮蔽层以逐一露出各第二牺牲层。
5.根据方面4所述的方法，其中，
在对各第一牺牲层进行所述去除处理时，该方法还包括：在第一遮蔽层上形成第二硬掩模层，第二硬掩模层具有与网格图案的节点部相对应的开口；以及利用第二硬掩模层，在第一遮蔽层中形成到各第一牺牲层的节点的第一加工通道，其中，回蚀第一遮蔽层包括经由第一加工通道回蚀第一遮蔽层，
在对各第二牺牲层进行所述切断处理时，该方法还包括：在第二遮蔽层上形成第三硬掩模层，第三硬掩模层具有与网格图案的桥接部分的大致中部相对应的开口；以及利用第三硬掩模层，在第二遮蔽层中形成到各第二牺牲层的桥接部分的第二加工通道，其中，回蚀第二遮蔽层包括经由第二加工通道回蚀第二遮蔽层。
6.根据方面5所述的方法，其中，对各第一牺牲层进行所述去除处理包括：
遮挡到该第一牺牲层中要去除的所述一个或多个节点的第一加工通道，而露出到该第一牺牲层中的其余节点的第一加工通道；
经由露出的第一加工通道，通过选择性刻蚀，去除该第一牺牲层中的相应节点；
在被去除的节点处，填充第一位置保持层；
经由所有的第一加工通道，通过选择性刻蚀，去除该第一牺牲层中的其余节点；
在被去除的节点处，填充第一绝缘部。
7.根据方面5所述的方法，其中，对各第二牺牲层进行所述切断处理包括：
遮挡到该第二牺牲层中要切断的所述一个或多个桥接部分的第二加工通道，而露出到该第二牺牲层中的其余桥接部分的第二加工通道；
经由露出的第二加工通道，通过选择性刻蚀，切断该第二牺牲层中的相应桥接部分；
在被切断的桥接部分处，填充第二位置保持层；
经由所有的第二加工通道，通过选择性刻蚀，切断该第二牺牲层中的其余桥接部分；
在被切断的桥接部分处，填充第二绝缘部。
8.根据方面6或7所述的方法，其中，第一牺牲层和第二牺牲层包括半导体材料，且第一位置保持层和第二位置保持层包括半导体材料，所述形成导电材料包括：
使金属与所述半导体材料发生反应，生成导电的金属半导体化合物。
9.根据方面1所述的方法，其中，所述网格图案的节点的线宽粗于桥接部分的线宽。
10.根据方面1所述的方法，其中，第一叠层的最下层是第一牺牲层，该方法还包括：
将最下层的第一牺牲层替换为绝缘层。
11.根据方面1所述的方法，其中，所述半导体器件是竖直半导体器件，所述限定有源区包括：限定分别处于各节点之处的器件有源区。
12.根据方面1所述的方法，其中，器件有源材料层包括依次堆叠的第一源/漏层、沟道层和第二源/漏层的第二叠层，所述限定有源区包括：
利用第一硬掩模层，对第二叠层进行构图，从而第一叠层中的各层具有与第一硬掩模层相对应的网格图案，并因此包括节点以及节点之间的桥接部分；
对沟道层进行进一步选择性刻蚀，以将沟道层的各桥接部分至少部分地去 除从而沟道层的节点彼此分离；
对第一源/漏层和第二源/漏层进一步选择性刻蚀，以将第一源/漏层和第二源/漏层各自的各桥接部分至少部分地去除从而第一源/漏层和第二源/漏层各自的节点彼此分离。
13.根据方面12所述的方法，还包括：
在对沟道层进行进一步选择性刻蚀之后，在沟道层的分离的节点周围形成图案与硬掩模层相对应的第一位置保持层；
在对第一源/漏层和第二源/漏层进一步选择性刻蚀之后，在第一源/漏层和第二源/漏层各自的分离的节点周围形成图案与硬掩模层相对应的第二位置保持层。
14.根据方面13所述的方法，还包括：
通过选择性刻蚀，去除第二位置保持层，以露出第一源/漏层和第二源/漏层各自的节点；
在第一源/漏层和第二源/漏层各自的节点的表面上形成掺杂剂源层；
通过热处理，将掺杂剂源层中的掺杂剂驱入第一源/漏层和第二源/漏层各自的节点中。
15.根据方面13所述的方法，还包括：
通过选择性刻蚀，去除第一位置保持层，以露出沟道层的节点；
绕沟道层的节点形成栅电极。
16.根据方面15所述的方法，还包括：
在一个或多个节点位置处形成接触插塞。
17.根据方面16所述的方法，其中，所述形成接触插塞包括：
在所述一个或多个节点位置处，通过选择性刻蚀，去除有源区外周的结构；
使金属与所述一个或多个节点位置处的有源区发生反应，生成导电的金属半导体化合物。
18.根据方面17所述的方法，还包括：
在有源区外周被去除的结构之处，填充半导体材料，其中，所述金属也与填充的半导体材料发生反应而生成导电的金属半导体化合物。
19.根据方面11所述的方法，其中，所述半导体器件是鳍式场效应晶体 管或平面半导体器件，所述限定有源区包括：
利用第一掩模层，对器件有源材料层进行构图，从而器件有源材料层具有与第一硬掩模层相对应的网格图案，并因此包括节点以及节点之间的桥接部分。
20.根据方面19所述的方法，还包括：
形成与器件有源材料层的各桥接部分相交的牺牲栅；
在牺牲栅的侧壁上形成侧墙；
通过选择性刻蚀，去除一个或多个牺牲栅；
通过牺牲栅的去除而在相应侧墙内留下的空间，切断器件有源材料层的相应桥接部分；
在侧墙内的空间中填充绝缘材料；
将其余牺牲栅替换为栅电极。
21.根据方面19所述的方法，还包括：
以牺牲栅和栅侧墙为掩模，对有源材料层进行选择性刻蚀，以去除被牺牲栅和栅侧墙露出的器件有源材料层的一部分；
以器件有源材料层的残留部分为种子，生长外延源/漏。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (48)

  1. 一种用于在衬底上形成的多个半导体器件的互连结构，所述互连结构设置在所述多个半导体器件之下，且包括：
    沿从半导体器件向着衬底的方向交替设置的至少一个过孔层和至少一个互连层，其中，
    每一过孔层包括分别设于所述多个半导体器件中至少一部分半导体器件下方的过孔，
    每一互连层包括分别设于所述多个半导体器件中至少一部分半导体器件下方的导电节点，其中，在同一互连层中，至少一个导电节点与至少另一个节点之间具有导电通道，
    各过孔层中的过孔与各互连层中的相应导电节点在从半导体器件向着衬底的方向上彼此至少部分地交迭。
  2. 根据权利要求1所述的互连结构，其中，各过孔层中的过孔与各互连层中的相应导电节点在从半导体器件向着衬底的方向上彼此实质上对准。
  3. 根据权利要求1所述的互连结构，其中，所述多个半导体器件包括竖直半导体器件、平面半导体器件或者鳍式场效应晶体管中的至少一种。
  4. 根据权利要求1所述的互连结构，其中，各过孔层中的至少一个过孔、各互连层中的相应导电节点与相应的半导体器件的源/漏区在从半导体器件向着衬底的方向上彼此实质上对准。
  5. 根据权利要求1所述的互连结构，其中，从半导体器件向着衬底的方向是实质上垂直于衬底表面的方向。
  6. 根据权利要求1所述的互连结构，其中，各过孔层中的过孔实质上共面，各互连层中的导电节点、导电通道实质上共面。
  7. 根据权利要求1所述的互连结构，其中，在每一过孔层中，在所述多个半导体器件之中的第一组源/漏区下方设置有过孔，在所述多个半导体器件之中的第二组源/漏区下方设置有绝缘部，各过孔层中的绝缘部与各互连层中的相应导电节点在从半导体器件向着衬底的方向上彼此至少部分地交迭。
  8. 根据权利要求7所述的互连结构，其中，各过孔层中的过孔与各互连 层中的相应导电节点在从半导体器件向着衬底的方向上彼此实质上对准，且各过孔层中的绝缘部与各互连层中的相应导电节点在半导体器件向着衬底的方向上彼此实质上对准。
  9. 根据权利要求7所述的互连结构，其中，各过孔层中的过孔、各互连层中的相应导电节点与相应的半导体器件的源/漏区在从半导体器件向着衬底的方向上彼此实质上对准，且各过孔层中的绝缘部、各互连层中的相应导电节点与相应的半导体器件的源/漏区在从半导体器件向着衬底的方向上彼此实质上对准。
  10. 根据权利要求7所述的互连结构，其中，各过孔层中的过孔和绝缘部的布局与各互连层中的导电节点的布局实质上相同。
  11. 根据权利要求7所述的互连结构，其中，各过孔层中的过孔、绝缘部实质上共面，各互连层中的导电节点、导电通道实质上共面。
  12. 根据权利要求7所述的互连结构，其中，所述绝缘部与所述互连结构中的层间电介质层具有不同的绝缘材料。
  13. 根据权利要求7所述的互连结构，其中，所述过孔和所述绝缘部具有实质上相同的横向尺寸。
  14. 根据权利要求1所述的互连结构，其中，在每一互连层中，各导电节点具有设于相应半导体器件下方的主体部以及从主体部向着其相邻导电节点延伸的延伸部，其中每一对相邻的导电节点的彼此相向的延伸部实质上沿相同直线延伸，其中至少一对相邻的导电节点的彼此相向的延伸部延伸为彼此连接在一起从而构成所述导电通道的至少一部分。
  15. 根据权利要求14所述的互连结构，其中，所述延伸部细于所述主体部。
  16. 根据权利要求14所述的互连结构，其中，至少一对相邻的导电节点的彼此相向的延伸部之间具有绝缘部，所述绝缘部与所述延伸部实质上沿着相同直线延伸。
  17. 根据权利要求16所述的互连结构，其中，所述绝缘部与所述互连结构中的层间电介质层具有不同的绝缘材料。
  18. 根据权利要求16所述的互连结构，其中，所述绝缘部与所述延伸部 在所述直线的方向上实质上对准。
  19. 根据权利要求16所述的互连结构，其中，所述绝缘部与所述延伸部各自垂直于所述直线的截面具有基本相同的形状。
  20. 根据权利要求16所述的互连结构，其中，所述绝缘部位于其两侧的主体部之间的基本上中心位置。
  21. 根据权利要求14所述的互连结构，其中，各互连层中的至少一个主体部与相应的半导体器件的源/漏区在从半导体器件向着衬底的方向上实质上对准。
  22. 根据权利要求14所述的互连结构，其中，所述半导体器件是竖直半导体器件，且在俯视图中，所述延伸部延伸超出相应的半导体器件的有源区的外周。
  23. 根据权利要求14所述的互连结构，其中，
    在每一过孔层中，所述过孔分别处于按行和列排列的二维点阵中的至少一部分点之处，
    在每一互连层中，所述主体部分别处于所述二维点阵中的至少一部分点之处，且所述延伸部在所述行或列的方向上延伸。
  24. 根据权利要求23所述的互连结构，其中，在俯视图中，各互连层具有由所述行和列限定的网格图案。
  25. 根据权利要求1所述的互连结构，其中，所述过孔、所述导电节点和所述导电通道包括金属硅化物。
  26. 根据权利要求1所述的互连结构，其中，各半导体器件中的至少部分器件的沟道材料是单晶半导体材料。
  27. 一种电路，包括：
    衬底；
    设于衬底上的互连结构，所述互连结构包括沿实质上垂直于衬底表面的方向交替设置的至少一个过孔层和至少一个互连层，互连结构的最上层是过孔层；以及
    设于互连结构上的多个半导体器件，其中，
    每一过孔层包括设于按行和列排列的二维点阵中的至少一部分点之处的 过孔，
    每一互连层包括设于所述二维点阵中的至少一部分点之处的主体部以及从所述主体部沿所述行或列的方向延伸的延伸部，至少一部分相邻主体部各自彼此相向的延伸部相接触，
    至少一部分半导体器件的源/漏区与最上层的过孔层中的相应过孔相接触。
  28. 根据权利要求27所述的电路，其中，在每一互连层中，从至少一部分相邻主体部分别彼此相向延伸的延伸部之间设置有与所述延伸部沿相同方向延伸且实质上共面的绝缘部。
  29. 根据权利要求27所述的电路，其中，每一互连层中的主体部粗于延伸部。
  30. 根据权利要求27所述的电路，其中，在每一过孔层中，所述二维点阵之中的第一组点之处设置有过孔，在所述二维点阵之中的不同于第一组点的第二组点之处设置有绝缘部，所述绝缘部与所述过孔实质上共面。
  31. 根据权利要求27所述的电路，其中，
    至少一部分所述半导体器件是竖直半导体器件，包括在所述二维点阵的至少一部分点之处沿实质上垂直于衬底表面的方向延伸的竖直有源区；或者
    至少一部分所述半导体器件是平面半导体器件或鳍式场效应晶体管，包括沿着所述行或列的方向延伸的水平有源区或鳍。
  32. 根据权利要求27所述的电路，还包括：在所述互连结构上设置于所述二维点阵之中的一部分点之处的接触插塞。
  33. 根据权利要求32所述的电路，还包括：在所述半导体器件上设置于所述二维点阵之中的至少一部分点之处的接触部，所述接触部向下延伸至接触相应的半导体器件的源/漏区或接触插塞。
  34. 根据权利要求32所述的电路，其中，
    至少一部分所述半导体器件是竖直半导体器件，包括在所述二维点阵的至少一部分点之处沿实质上垂直于衬底表面的方向延伸的竖直有源区，所述接触插塞与所述竖直有源区实质上共面；或者
    至少一部分所述半导体器件是平面半导体器件或鳍式场效应晶体管，包括沿着所述行或列的方向延伸的水平有源区或鳍，所述接触插塞与所述水平有源 区或鳍中的源/漏区实质上共面。
  35. 根据权利要求32所述的电路，其中，至少一部分接触插塞与最上层的过孔相接触。
  36. 根据权利要求32所述的电路，其中，
    至少一部分所述半导体器件是竖直半导体器件，包括在所述二维点阵的至少一部分点之处沿实质上垂直于衬底表面的方向延伸的竖直有源区，每一竖直半导体器件包括绕竖直有源区中的沟道区形成的栅电极，
    至少一部分接触插塞与相邻的竖直半导体器件的栅电极相接触。
  37. 根据权利要求36所述的电路，其中，所述至少一部分接触插塞各自包括设于所述二维点阵中的相应点之处的主体部以及从所述主体部沿所述行或列的方向向着所述相邻的竖直半导体器件延伸的延伸部，所述延伸部与所述相邻的竖直半导体器件的栅电极相接触且彼此实质上共面。
  38. 根据权利要求31所述的电路，其中，每一竖直半导体器件包括绕竖直有源区中的沟道区形成的栅电极，各栅电极包括设于所述二维点阵中的相应点之处的主体部以及从所述主体部沿所述行或列的方向延伸的延伸部，至少一部分相邻栅电极各自彼此相向的延伸部相接触。
  39. 根据权利要求38所述的电路，其中，各栅电极实质上共面。
  40. 根据权利要求32所述的电路，其中，所述过孔包括金属硅化物，所述互连层的主体部和延伸部包括金属硅化物，以及所述接触插塞包括金属硅化物。
  41. 根据权利要求31所述的电路，其中，每一平面半导体器件或鳍式场效应晶体管各自的水平有源区或鳍包括位于所述二维点阵中的相邻点之间的位置处的沟道区以及位于沟道区两侧的源/漏区。
  42. 根据权利要求41所述的电路，其中，每一平面半导体器件或鳍式场效应晶体管包括沿与相应水平有源区或鳍的延伸方向交叉的方向延伸、与相应沟道区在竖直方向上重叠的栅电极。
  43. 根据权利要求42所述的电路，其中，
    至少一部分相邻的平面半导体器件或鳍式场效应晶体管各自的有源区通过彼此之间的隔离部而电隔离，
    所述电路还包括绕各栅电极以及个隔离部的至少上部侧壁形成的电介质侧墙。
  44. 根据权利要求27所述的电路，还包括：设于所述有源区上方的硬掩模层，所述硬掩模层具有以所述行和列限定的网格图案。
  45. 根据权利要求27所述的电路，其中，有源区包括单晶半导体材料。
  46. 根据权利要求27所述的电路，其中，所述半导体器件的沟道区包括单晶半导体材料。
  47. 一种电子设备，包括如权利要求1至26中任一项所述的互连结果或如权利要求27至46中任一项所述的电路。
  48. 根据权利要求47所述的电子设备，其中，该电子设备包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或移动电源。
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