WO2020082405A1 - 半导体器件及其制造方法及包括该器件的电子设备 - Google Patents

半导体器件及其制造方法及包括该器件的电子设备 Download PDF

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WO2020082405A1
WO2020082405A1 PCT/CN2018/113049 CN2018113049W WO2020082405A1 WO 2020082405 A1 WO2020082405 A1 WO 2020082405A1 CN 2018113049 W CN2018113049 W CN 2018113049W WO 2020082405 A1 WO2020082405 A1 WO 2020082405A1
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layer
source
drain
channel layer
semiconductor
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PCT/CN2018/113049
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US17/261,862 priority Critical patent/US11652103B2/en
Publication of WO2020082405A1 publication Critical patent/WO2020082405A1/zh

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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to vertical semiconductor devices and methods of manufacturing the same, and electronic equipment including such semiconductor devices.
  • a horizontal type device such as a metal oxide semiconductor field effect transistor (MOSFET)
  • MOSFET metal oxide semiconductor field effect transistor
  • the source, gate, and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, reducing the area occupied by horizontal devices generally requires that the area occupied by the source, drain, and gate be reduced, which will degrade device performance (eg, increased power consumption and resistance). The area of the device is not easy to shrink further.
  • the source, gate, and drain are arranged in a direction substantially perpendicular to the surface of the substrate. Therefore, compared with the horizontal type device, the area occupied by the vertical type device is easier to shrink.
  • an object of the present disclosure is, at least in part, to provide a vertical semiconductor device capable of reducing the occupied area well, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.
  • a semiconductor device including: a substrate; a first device and a second device stacked on the substrate in sequence, each of the first device and the second device includes: from bottom to top The stacked first source / drain layer, channel layer, and second source / drain layer, and the gate stack formed around at least part of the outer periphery of the channel layer, and the sidewalls of the channel layer of the first device and the second device At least partly extends along different crystal planes or crystal plane families.
  • a method of manufacturing a semiconductor device comprising: sequentially stacking a first source / drain layer, a channel layer, and a second source / drain of a first device on a substrate from bottom to top Layer and the first source / drain layer, channel layer and second source / drain layer of the second device; the first source / drain layer, channel layer and second source / drain layer of the first device and the second semiconductor
  • the first source / drain layer, the channel layer, and the second source / drain layer of the device define the active regions of the corresponding semiconductor devices such that the side wall of the channel layer of the first device and the side of the channel layer of the second device At least part of the walls extend along different crystal planes or families of planes; and a gate stack of each of the first device and the second device is formed around at least a portion of the periphery of the channel layer of the first device and the second device, respectively.
  • an electronic device including an integrated circuit formed at least in part by the above-described semiconductor device.
  • the semiconductor device includes vertical type devices stacked on top of each other, which can greatly reduce the area and save space.
  • the gate stack is formed around at least part of the outer periphery of the channel layer and the channel is formed in the channel layer, so that the gate length can be determined by the thickness of the channel layer, and better control of the gate length can be achieved.
  • at least a part of the sidewalls of the channel layer of different devices may be arranged to extend along different crystal planes or crystal plane families. Since the carriers can have different mobilities in different crystal planes or plane family directions, the carrier mobility in the channel layer of different devices can be adjusted, thereby adjusting the conduction effect of different devices to optimize The overall performance of semiconductor devices.
  • 1 to 25 are schematic diagrams showing the flow of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • 26 to 35 are schematic diagrams showing some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • 36 to 39 show schematic diagrams showing the flow of patterning a hard mask layer according to an embodiment of the present disclosure.
  • a layer / element when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / between element.
  • the layer / element may be "below” the other layer / element.
  • the semiconductor device of the embodiment of the present disclosure may include a first device and a second device that are sequentially stacked on the substrate.
  • the first device and the second device are both vertical type devices.
  • Such a vertical type device may include a first source / drain layer, a channel layer, and a second source / drain layer that are sequentially stacked.
  • the source / drain regions of the device may be formed in the first source / drain layer and the second source / drain layer, and the channel region of the device may be formed in the channel layer.
  • a conductive channel can be formed through the channel region between the source / drain regions that are located at both ends of the channel region.
  • the stacking configuration of the active regions of different vertical devices may be the same or different.
  • the sidewalls of the channel layer of different devices may extend along different crystal planes or families of crystal planes. Since the carriers can have different mobilities in different crystal planes or plane family directions, the carrier mobility in the channel layer of different devices can be adjusted, thereby adjusting the conduction effect of different devices to optimize The overall performance of semiconductor devices.
  • the channel layer is a single crystal semiconductor material or one of Si, SiGe, or Ge crystals
  • at least part of the sidewalls of the channel layer of the n-type device may be along the (100) crystal plane or ⁇ 100 ⁇ crystal plane Family extension, because the crystal plane or crystal plane family is conducive to electron mobility; and at least part of the sidewall layer of the channel layer of the p-type device can extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family, because the crystal The face or crystal face family favors the mobility of holes.
  • CMOS complementary metal oxide semiconductor
  • not all sidewalls of the channel layer may be optimized (ie, they are extended along a desired crystal plane or family of crystal planes), but only a part of the sidewalls may be optimized.
  • the channel layer may be chamfered.
  • the rounded portion of the side wall may not extend along the desired crystal plane or plane family.
  • the side wall of the channel layer with a larger area can be optimized, and the influence of the side wall with a smaller area can be ignored, for example, in the case of nanosheets.
  • the crystal plane of the sidewall is not a single crystal plane family.
  • the first source / drain layer of the device may point in the direction of its second source / drain layer in the [100] crystal direction or in the ⁇ 100> crystal direction group, which is parallel to the ⁇ 100 ⁇ crystal plane Family and ⁇ 110 ⁇ crystal plane family, that is, the ⁇ 100 ⁇ crystal plane family and ⁇ 110 ⁇ crystal plane family are perpendicular to the substrate, so that the channel layer side wall extending along the ⁇ 100 ⁇ crystal plane family or ⁇ 110 ⁇ crystal plane family Perpendicular to the substrate.
  • the channel layer may be chamfered so that the corner formed by the adjacent sidewalls of the channel layer may be relatively gentle rounded.
  • the channel layer may be composed of a semiconductor single crystal material to improve device performance, such as reducing channel resistance.
  • the semiconductor single crystal materials of the channel layers of different devices may have the same crystal orientation, and / or may have the same crystal structure. In this way, the channel layer of these devices can be manufactured with the same substrate, which is convenient to manufacture and has fewer defects.
  • the first and second source / drain layers may also be composed of semiconductor single crystal materials.
  • the semiconductor single crystal material of the channel layer and the semiconductor single crystal material of the source / drain layer may be eutectic.
  • the electron or hole mobility of the semiconductor single crystal material of the channel layer may be greater than the electron or hole mobility of the first and second source / drain layers.
  • the forbidden band width of the first and second source / drain layers may be greater than the forbidden band width of the channel single-crystal semiconductor single crystal material.
  • the gate stack may be formed around at least part of the periphery of the channel layer. Therefore, the gate length can be determined by the thickness of the channel layer itself, rather than depending on the etching time as in the conventional technique.
  • the channel layer can be formed by epitaxial growth, for example, so that its thickness can be well controlled. Therefore, the gate length can be well controlled.
  • the gate stack may be self-aligned to the channel layer.
  • the gate stack may be substantially coplanar with the channel layer.
  • the space occupied by the gate stack may be defined by the interface between the channel layer and the first and second source / drain layers.
  • at least part of the upper surface of the gate stack may be substantially coplanar with the upper surface of the channel layer
  • at least part of the lower surface of the gate stack may be substantially coplanar with the lower surface of the channel layer.
  • the channel layer may have an etch selectivity with respect to the source / drain layer, for example, including different semiconductor materials. In this way, it is advantageous to process the channel layer and the source / drain layer separately, such as selective etching.
  • the first source / drain layer and the second source / drain layer may include the same semiconductor material.
  • the lateral dimensions of the first and second source / drain layers may be greater than the lateral dimensions of the channel layer, such that the outer circumference of the channel layer is concave inward relative to the outer circumferences of the first and second source / drain layers
  • the formed gate stack may be embedded in the recess of the channel layer relative to the first and second source / drain layers.
  • the lateral dimensions of the first and second source / drain layers may not be greater than the lateral dimensions of the channel layer, so that the area facing the gate stack and the source / drain regions formed may be reduced, Helps reduce the overlap capacitance between gate and source / drain.
  • the first source / drain layer, the channel layer, and the second source / drain layer of the second device may be within the range of the second source / drain layer of the first device.
  • the first device and the second device may be electrically connected to each other.
  • such an electrical connection may be achieved by the second source / drain layer of the first device and the first source / drain layer of the second device being adjacent to each other, ie in direct physical contact.
  • the second source / drain layer of the first device and the first source / drain layer of the second device may even be integrated, that is, they may be provided through the same semiconductor layer.
  • the first device and the second device are both vertical type devices and are stacked on each other, in addition to the second source / drain layer of the second device at the top, the remaining source / drain layers (where the source / drain Drain region) and the gate stack formed around the channel layer cannot form electrical contacts directly above each. Therefore, in order to form an electrical connection to them, electrical contacts that are offset in the lateral direction can be formed and electrically connected to it by means of laterally extending components.
  • the gate stack formed around the periphery of the channel layer may include a laterally extending portion extending laterally outward from the corresponding recess, and the laterally extending portion may extend beyond the defined periphery of the active region In order to be able to form electrical contacts in contact therewith.
  • an electrical contact layer adjacent thereto may be provided for the second source / drain layer of the first device and the first source / drain layer of the second device.
  • the electrical contact layer may surround the second source / drain layer of the first device and the outer periphery of the first source / drain layer of the second device to reduce contact resistance.
  • a portion of the electrical contact layer may extend laterally relative to the remaining portion, and may extend beyond the defined active area so that electrical contact with it can then be formed over it Contact.
  • the first source / drain layer of the first device at the bottom it can be patterned such that the lower part extends beyond the outer periphery of the upper part, so that the electrical contact portion in contact therewith can then be formed above the lower part.
  • laterally extending portions may laterally extend in different directions to avoid mutual interference between the corresponding electrical contacts. If at least some of these laterally extending portions overlap in the vertical direction, among these overlapping laterally extending portions, the laterally extending portions below may extend beyond the laterally extending portions above to avoid mutual interference of corresponding electrical contacts .
  • Such a semiconductor device can be manufactured as follows, for example. Specifically, the first source / drain layer, the channel layer and the second source / drain layer of the first device and the first source / drain layer and the channel layer of the second device may be sequentially stacked on the substrate from bottom to top And the second source / drain layer. For example, these layers can be provided by epitaxial growth, and during epitaxial growth, the thickness of the grown channel layer can be controlled. In addition, as described above, the second source / drain layer of the first device and the first source / drain layer of the second device may be integrated, that is, the same layer. Due to the respective epitaxial growth, at least a pair of adjacent layers may have a clear crystal interface. In addition, each layer may be doped differently, so that at least a pair of adjacent layers may have a doping concentration interface.
  • an active region may be defined therein.
  • they can be selectively etched into desired shapes in sequence.
  • the order of etching can be performed sequentially from top to bottom for each layer.
  • the The etching of the layer may be directed only to the upper part of the layer, so that the lower part of the layer may extend beyond the periphery of the upper part.
  • a gate stack may be formed around the outer periphery of the channel layer.
  • the sidewall of the channel layer may be formed along a certain crystal plane or family of crystal planes.
  • the same mask is usually used when defining the active region, so the sidewalls of the first source / drain layer and the second source / drain layer can also extend along the same crystal plane or family of crystal planes. Therefore, the active region may have a square column shape.
  • the first device and the second device especially when they have different conductivity types, at least part of the sidewalls of their respective channel layers may extend along different crystal planes or crystal plane families.
  • the active region of the second device may be patterned with a first mask that extends at least part of the sidewalls along the desired crystal plane or family of crystal planes, and may use at least part of the sidewalls along different desired crystal planes Or a second mask extended by the crystal plane family to pattern the active region of the first device. Since the patterning is performed from top to bottom, in order to prevent the active region of the second device above from obstructing the patterning of the active region of the first device below, the boundary of the first mask may be at the boundary of the second mask Within range.
  • the outer periphery of the channel layer of each device may be recessed inwardly with respect to the outer periphery of the corresponding first and second source / drain layers, so as to define a space for accommodating the gate stack. For example, this can be achieved by selective etching.
  • the gate stack can be embedded in the recess.
  • the recess of the channel layer can be achieved by isotropic etching.
  • the sharp corners formed between the adjacent sidewalls of the channel layer can be treated as relatively gentle rounded corners.
  • Source / drain regions can be formed in the first and second source / drain layers of each device. For example, this can be achieved by doping the first and second source / drain layers. For example, ion implantation, plasma doping, or in-situ doping when growing the first and second source / drain layers can be performed.
  • a sacrificial gate may be formed in the recess formed by the outer periphery of the channel layer relative to the outer periphery of the first and second source / drain layers, and then on the surfaces of the first and second source / drain layers A dopant source layer is formed, and the dopant in the dopant source layer enters the active region through the first and second source / drain layers by, for example, annealing.
  • the sacrificial gate can prevent the dopant in the dopant source layer from directly entering the channel layer.
  • some dopants may enter the channel layer near the ends of the first source / drain layer and the second source / drain layer through the first and second source / drain layers, thereby approaching the first in the channel layer
  • the ends of the source / drain layer and the second source / drain layer form a doping distribution, which helps to reduce the resistance between the source / drain region and the channel region when the device is turned on, thereby improving device performance.
  • the operation of forming the source / drain regions may be performed together (for example, in the case where their respective source / drain regions have the same or similar doping characteristics), or may be performed separately (for example, in (The case where their respective source / drain regions have different doping characteristics).
  • the sacrificial gate in the recess formed by the outer periphery of the channel layer relative to the outer periphery of the first and second source / drain layers may be removed, and a gate stack for the corresponding device may be formed in the corresponding recess.
  • the source / drain layer may be silicided to reduce the contact resistance.
  • 1 to 25 are schematic diagrams showing the flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • the substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is taken as an example for description.
  • the substrate 1001 may be (100) single crystal silicon, single crystal silicon germanium, or single crystal germanium wafer. At this time, there are both ⁇ 100 ⁇ crystal planes and ⁇ 110 ⁇ crystal planes among the crystal planes perpendicular to the (100) crystal plane, which is advantageous for the manufacture of the following devices.
  • a first source / drain layer 1003, a first channel layer 1005, a second source / drain layer 1007, a second channel layer 1009, and a third source / drain layer may be sequentially formed by, for example, epitaxial growth 1011.
  • the first source / drain layer 1003 may include a suitable semiconductor material such as SiGe (the atomic percentage of Ge may be about 10-40%) and the thickness is about 20-50 nm;
  • the first channel layer 1005 may A semiconductor material such as Si, which is different from the first source / drain layer 1003 and the second source / drain layer 1007, has a thickness of about 10-100 nm;
  • the second source / drain layer 1007 may include the same material as the first source / drain layer 1003 A material such as SiGe (the atomic percentage of Ge may be about 10-40%);
  • the second channel layer 1009 may include a semiconductor material such as Si different from the second source / drain layer 1007 and the third source / drain layer 1011, and the thickness is About 10-100 nm;
  • the third source / drain layer 1011 may include the same material as the second source / drain layer 1007 such as SiGe (the atomic percentage of Ge may be about 10-40%), and the thickness is about 20-50 nm.
  • each channel layer may include the same composition as the source / drain layer below or above, but different semiconductor materials (e.g., all SiGe, but with different atomic percentages of Ge) as long as the trench
  • the channel layer has etch selectivity relative to the source / drain layers below and above.
  • the first source / drain layer 1003, the first channel layer 1005, and the lower portion 1007-1 of the second source / drain layer 1007 are used to define the first device Source region, and an upper portion 1007-2 of the second source / drain layer 1007 (for example, a thickness of about 10-50 nm), a second channel layer 1009, and a third source / drain layer 1011 are used to define the activeness of the second device Area.
  • the first device and the second device are adjacent to each other and share the same source / drain layer 1007. But the present disclosure is not limited to this.
  • the source / drain layer 1007-1 for the first device and the source / drain layer 1007-2 for the second device may be grown separately, and they may have the same or different semiconductor materials. Even, the first device and the second device are not adjacent, but have a dielectric layer therebetween so as to be electrically isolated from each other, for example, the source / drain layer 1007-1 for the first device and the second device A dielectric layer is additionally deposited between the source / drain layer 1007-2.
  • the source / drain layers 1003, 1007, and 1011 can be doped in situ to subsequently form source / drain regions. For example, for n-type devices, n-type doping can be performed; for p-type devices, p-type doping can be performed.
  • the channel layers 1005 and 1009 when they are grown, they can also be doped in situ to adjust the device threshold voltage (V t ).
  • V t device threshold voltage
  • p-type doping can be performed at a doping concentration of about 1E17-1E19cm -3 ; for p-type devices, n-type doping can be performed at a doping concentration of about 1E17-1E19cm -3 .
  • the first source / drain layer 1003 is additionally grown on the substrate 1001.
  • the present disclosure is not limited to this.
  • the first source / drain layer may be formed by the substrate 1001 itself.
  • the source / drain regions may be formed by forming a well region in the substrate 1001.
  • a hard mask 1013 may be formed on the semiconductor layers grown for the purpose of convenience in patterning in subsequent processing and provision of appropriate stop layers.
  • the hard mask 1013 may include a first hard mask layer 1013-1, a second hard mask layer 1013-2, and a third hard mask layer 1013-3 that are sequentially stacked.
  • the first hard mask layer 1013-1 may include an oxide (such as silicon oxide) with a thickness of about 2-10 nm;
  • the second hard mask layer 1013-2 may include a nitride (such as silicon nitride) with a thickness of About 10-100 nm;
  • the third hard mask layer 1013-3 may include oxide, and the thickness is about 20-100 nm.
  • the stack configuration of the hard mask 1013 is mainly for providing suitable etching selectivity in subsequent processing, and those skilled in the art may conceive other configurations.
  • the active area of the device can be defined. For example, this can be done as follows. Specifically, as shown in FIGS. 2 (a) and 2 (b) (FIG. 2 (a) is a cross-sectional view, and FIG. 2 (b) is a top view, where the line AA ′ shows the location of the cross-section), it can be A photoresist (not shown) is formed on the hard mask 1013, and the photoresist is patterned into a desired shape by photolithography (exposure and development) (in this example, approximately rectangular).
  • the photoresist pattern may be etched according to different crystal planes or crystal plane family directions according to the type of the device.
  • the second device is an n-type device
  • the corresponding photoresist can be patterned to at least partially Or all the sidewalls extend along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family of the substrate 1001 (because the channel layer is epitaxially grown on the substrate 1001, so also along the (100) crystal plane or ⁇ 100 of the channel layer ⁇ Crystal plane family extended) roughly rectangular pattern.
  • the shape of the patterned photoresist may be transferred to the hard mask 1013.
  • the third hard mask layer 1013-3, the second hard mask layer 1013-2, and the first hard mask layer 1013-1 may be selectively etched such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • the third source / drain layer 1011, the second channel layer 1009, and the second source / drain layer 1007 may be selectively etched, such as RIE.
  • the etching proceeds to the second source / drain layer 1007, but does not proceed to the bottom surface of the second source / drain layer 1007, so that the upper portion 1007-2 of the second source / drain layer is patterned to correspond to the hard mask Shape, and its lower part 1007-1 is basically unchanged.
  • the third source / drain layer 1011, the second channel layer 1009, and the upper portion 1007-2 of the second source / drain layer form a square column shape.
  • RIE can be performed, for example, in a direction substantially perpendicular to the surface of the substrate, so that the rectangular column shape is also substantially perpendicular to the surface of the substrate.
  • the photoresist can be removed.
  • the second device may also be a p-type device.
  • the photoresist may be patterned such that at least part of the side walls extend parallel to the (110) crystal plane or ⁇ 110 ⁇ crystal plane family. Therefore, after etching, at least part of the sidewalls of the third source / drain layer 1011, the second channel layer 1009, and the upper portion 1007-2 of the second source / drain layer are along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family extend.
  • FIGS. 3 (a) and 3 (b) are a front cross-sectional view
  • FIG. 3 (b) is a top cross-sectional view
  • line 11 ′ shows the cut-away position of the top cross-section
  • AA ′ The line shows the cross-sectional position of the cross section of the front view). In this example, it is recessed in a lateral direction substantially parallel to the substrate surface).
  • the concave upper and lower side walls are respectively defined by the interfaces between the second channel layer 1009 and the second source / drain layer 1007 and between the second channel layer 1009 and the third source / drain layer 1011.
  • this can be achieved by further isotropically selectively etching the second channel layer 1009 with respect to the second source / drain layer 1007 and the third source / drain layer 1011.
  • atomic layer etching (ALE) or digital etching can be used to perform selective etching in order to more precisely control the amount of etching.
  • the active region of the second device (the upper portion 1007-2 of the etched second source / drain layer, the second channel layer 1009, and the third source / drain layer 1011) is defined.
  • the active region has a substantially square column shape.
  • the upper portion of the second source / drain layer 1007-2 and the outer periphery of the third source / drain layer 1011 may be substantially aligned, and the second trench The outer periphery of the track layer 1009 is relatively concave. As shown in FIG.
  • the second channel layer 1009 remains substantially conformal before and after the etching, so that it has a square column shape with a smaller lateral dimension, and at least part of its side walls remains Keep extending along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family.
  • the sidewalls of the second channel layer 1009 extend along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family, so that sharp corners are formed between adjacent sidewalls thereof.
  • Such sharp corners may be damaged in subsequent processes, resulting in process instability, device reliability degradation, and device performance fluctuations.
  • such sharp corners can be chamfered to make them smooth.
  • such sharp corners can be processed into rounded corners by oxidation (and subsequent removal of the oxide layer).
  • a gate stack will subsequently be formed.
  • a material layer may be filled in the recess to occupy the space of the gate stack (thus, This material layer may be referred to as a "sacrificial gate"). For example, this can be done by depositing nitride on the structure shown in FIGS. 3 (a) and 3 (b), and then etching back the deposited nitride such as RIE.
  • the RIE can be performed in a direction substantially perpendicular to the surface of the substrate, and the nitride can be left only in the recess to form a sacrificial gate 1015, as shown in FIG. 4.
  • the sacrificial gate 1015 may substantially fill the above-mentioned recess.
  • the upper portion 1007-2 of the second source / drain layer and the third source / drain layer 1011 may be further doped, especially if the in-situ doping concentration is insufficient.
  • a dopant source layer 1017 may be formed on the structure shown in FIG. 4.
  • the dopant source layer 1017 may include an oxide such as silicon oxide, which contains a dopant.
  • oxide such as silicon oxide, which contains a dopant.
  • n-type dopants can be included; for p-type devices, p-type dopants can be included.
  • the dopant source layer 1017 may be formed in the form of a spacer on the sidewall of the active region of the second device (due to the presence of the sacrificial gate 1015, the spacer In fact, it is formed on the upper portion 1007-2 of the second source / drain layer and the side wall of the third source / drain layer 1011).
  • a thin film can be deposited substantially conformally on the surface of the structure shown in FIG.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the dopant contained in the dopant source layer 1017 may be further activated into the active region by, for example, annealing to activate the in-situ doped impurities, thereby forming a doped region therein, such as The shaded part in the figure shows. More specifically, one of the source / drain regions S / D-t1 of the second semiconductor device may be formed in the third source / drain layer 1011, and the second semiconductor may be formed in the upper portion 1007-2 of the second source / drain layer Another source / drain region S / D-t2 of the device. Thereafter, the dopant source layer 1017 may be removed.
  • the dopant can also enter the second channel layer 1009 via the upper portion 1007-2 of the second source / drain layer and the third source / drain layer 1011, so that A certain doping distribution is formed at the upper and lower ends of the track layer 1009 (not shown in the figure).
  • This doping profile can reduce the resistance between the source / drain regions when the device is turned on, thereby improving device performance.
  • oxide 1013-4 is deposited around and above the active region of the second device, and a planarization process such as CMP is performed on it, and the planarization process can be stopped at the second hard mask layer 1013 -3, it is integrated with the previously existing third hard mask layer 1013-3 (hereinafter collectively marked as 1013-3).
  • the oxide layer can then protect the active area of the second device during the patterning of the active area of the first device.
  • FIGS. 7 (b) and 7 (c) are cross-sectional views
  • FIG. 7 (c) is a top view, where the line AA ′ shows the cross-sectional cut position
  • a photoresist can be formed (Not shown), the photoresist is patterned into a desired shape (in this example, it is roughly rectangular, but the orientation of the previous photoresist pattern is different).
  • the first device and the second device are different in type, such as a p-type device
  • the corresponding The photoresist pattern is that at least part or all of the sidewalls extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family of the substrate 1001 (because the channel layer is epitaxially grown on the substrate 1001, it also extends along the channel layer ( 110)
  • a substantially rectangular pattern of crystal planes or ⁇ 110 ⁇ crystal plane family extensions ).
  • the range occupied by the patterned photoresist is such that the active region of the second device is completely within the range. In this way, the pattern of the photoresist can be transferred to the layer below the active region of the second device.
  • the oxide layer 1013-3, the lower portion 1007-1 of the second source / drain layer 1007, the first channel layer 1005, and the first source / drain layer 1003 may be selectively etched, such as RIE. Etching may be performed into the first source / drain layer 1003, but not to the bottom surface of the first source / drain layer 1003, so that the upper portion of the first source / drain layer 1003 is etched and the lower portion is substantially unchanged.
  • the lower portion 1007-1 of the second source / drain layer 1007, the first channel layer 1005, and the first source / drain layer 1003 (or the upper portion thereof) are patterned to correspond to the shape of the photoresist.
  • it is square columnar.
  • RIE can be performed, for example, in a direction substantially perpendicular to the substrate surface, so that the columnar shape is also substantially perpendicular to the substrate surface. After that, the photoresist can be removed.
  • a protective layer may be formed on the periphery thereof 1019, as shown in Figure 7 (b). For this reason, when RIE is performed on the oxide layer 1013-3, it may stop at the lower portion 1007-1 of the second source / drain layer 1007. On the side wall of the oxide layer 1013-3 after RIE, a protective layer 1019 may be formed. This protective layer 1019 may also be formed in the form of a side wall, for example, may be SiC or the like. Then, the lower portion 1007-1 of the second source / drain layer 1007, the first channel layer 1005, and the first source / drain layer 1003 are etched.
  • the photoresist is patterned such that at least part or all of the sidewalls extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family.
  • FIG. 7 (c) at least part of the side walls of the upper portion of the lower portion 1007-1 of the second source / drain layer 1007, the first channel layer 1005, and the first source / drain layer 1003 after etching (110 )
  • the crystal plane or ⁇ 110 ⁇ crystal plane family extends.
  • the third source / drain layer 1011 of the second device and the upper portion 1007-2 of the second source / drain layer that have been formed may also be possible Affected, the upper portion 1007-2 of the third source / drain layer 1011 and the second source / drain layer (shown by dotted lines in the figure) is changed from a substantially square cylinder to a substantially octahedral cylinder, and the second channel layer 1009 (Shown by the dotted line in the figure) Since it is a rectangular column with a small lateral dimension, it can be unaffected, and its side walls still extend along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family.
  • the first device may also be an n-type device.
  • the photoresist may be patterned such that at least the sidewalls extend in the direction of the (100) crystal plane or ⁇ 100 ⁇ crystal plane family, so the lower portion of the second source / drain layer 1007 after etching 1007-1, at least part of the sidewalls of the upper part of the first channel layer 1005 and the first source / drain layer 1003 extend along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family.
  • FIGS. 8 (a) and 8 (b) are a front cross-sectional view
  • FIG. 8 (b) is a top cross-sectional view
  • the line AA ′ shows the cut position of the front cross-section.
  • the line 22 ' shows the cross-sectional position of the cross-section in a plan view).
  • the outer periphery of the first channel layer 1005 relative to the lower part 1007-1 of the second source / drain layer 1007 and the first source / drain layer 1003
  • the outer periphery of the upper part thereof is recessed (in this example, it is recessed in a lateral direction substantially parallel to the surface of the substrate).
  • the concave upper and lower side walls are respectively defined by the interface between the first channel layer 1005 and the second source / drain layer 1007 and the first channel layer 1005 and the first source / drain layer 1003. For example, this may be achieved by further isotropically selectively etching the channel layer 1005 with respect to the second source / drain layer 1007 and the first source / drain layer 1003.
  • atomic layer etching (ALE) or digital etching can be used to perform selective etching in order to more precisely control the amount of etching.
  • the active region of the first device (the lower portion 1007-1 of the etched second source / drain layer, the first channel layer 1005, and the first source / drain layer 1003) is defined.
  • the active region has a substantially square column shape.
  • the lower portion 1007-1 of the second source / drain layer and the outer periphery of the first source / drain layer 1003 may be substantially aligned, while the first trench The outer periphery of the track layer 1005 is relatively concave. As shown in FIG.
  • the first channel layer 1005 remains substantially conformal before and after the etching, so that it has a square column shape with a smaller lateral dimension, and at least part of its sidewalls remains Keep extending along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family.
  • the sidewalls of the first channel layer 1005 extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family, so that sharp corners are formed between adjacent sidewalls thereof.
  • Such sharp corners may be damaged in subsequent processes, resulting in process instability, device reliability degradation, and device performance fluctuations.
  • such sharp corners can be chamfered to make them smooth.
  • such sharp corners can be processed into rounded corners by oxidation (and subsequent removal of the oxide layer).
  • the sacrificial gate 1021 may be formed in the recess formed by the lower portion 1007-1 of the first channel layer 1005 with respect to the second source / drain layer and the first source / drain layer 1003, as shown in FIG. 9.
  • the sacrificial gate 1021 may include nitride, for example. As mentioned above, this can be achieved by depositing nitride and etching back.
  • a thin layer of oxide for example, a thickness of about 1-5 nm, not shown in the figure may be deposited before the nitride is deposited.
  • the lower portion 1007-1 of the second source / drain layer and the first source / drain layer 1003 may optionally be further doped, especially if the above-mentioned in-situ doping concentration is insufficient.
  • a dopant source layer 1023 may be formed on the structure shown in FIG.
  • the dopant source layer 1023 may include an oxide such as silicon oxide, which contains a dopant.
  • the dopant source layer 1023 may be a thin film, so that it can be deposited substantially conformally on the surface of the structure shown in FIG. 9 by, for example, CVD or ALD.
  • the dopants contained in the dopant source layer 1023 can be activated into the active region by, for example, annealing, in-situ doped impurities or further dopants contained in the dopant source layer 1023, thereby forming a doped region therein, such as This is shown in the shaded area in Figure 11. More specifically, one of the source / drain regions S / D-b1 of the first semiconductor device may be formed in the lower portion 1007-1 of the second source / drain layer, and the first semiconductor may be formed in the first source / drain layer 1003 Another source / drain region S / D-b2 of the device.
  • the dopant in the dopant source layer 1023 can be suppressed from entering the active region of the second device.
  • the dopant source layer 1023 and the protective layer 1019 can be removed by, for example, selective etching, and the oxide 1013-3 can also be removed together.
  • the dopant source layer 1023 includes a portion that extends along the horizontal surface of the lower portion (unetched portion) of the first source / drain layer 1003 so that it can even be located below the first source / drain layer 1003
  • a doped region is formed at the horizontal surface (unetched portion), and the doped region extends beyond the outer periphery of the columnar active region. In this way, it can be easily electrically connected to the source / drain region S / D-b2 through the doped region in the subsequent process.
  • the source / drain regions are formed by driving the dopant into the active region from the dopant source layer, but the present disclosure is not limited thereto.
  • the source / drain regions can be formed by ion implantation, plasma doping, and the like.
  • silicide 1025 may be formed at the surface of the source / drain regions, as shown in FIG. 12. For example, this can be achieved by depositing a metal layer (for example, Ni, NiPt, or Co) on the structure shown in FIG. 11 and annealing to cause the metal layer and the semiconductor material to undergo silicidation reaction to generate silicide 1025.
  • a metal layer for example, Ni, NiPt, or Co
  • silicide 1025 is also formed on the horizontal surface of the lower portion (unetched portion) of the first source / drain layer 1003. Subsequently, the unreacted remaining metal can be removed.
  • An isolation layer may be formed around the active area to achieve electrical isolation.
  • the isolation layer is formed in multiple layers.
  • oxide 1027 can be deposited on the structure shown in FIG. 12 and subjected to planarization treatment such as chemical mechanical polishing (CMP). CMP may stop at the second hard mask layer 1013-2 (nitride). Then, as shown in FIG. 14, the planarized oxide may be etched back to form the first isolation layer 1027.
  • the top surface of the isolation layer 1027 may be located between the top surface and the bottom surface of the first channel layer 1005, which helps to form a self-aligned gate stack. Due to the existence of the sacrificial gates 1015, 1021, the material of the isolation layer 1027 can be prevented from entering the above-mentioned recess to accommodate the gate stack.
  • the sacrificial gate 1021 may be removed to release the recessed space of the first channel layer 1005.
  • the sacrificial gate 1021 nitride
  • the sacrificial gate 1015 and the second hard mask layer 1013-2 are also nitrides, they are also removed.
  • cleaning may also be performed to clean the surfaces of the channel layers 1005 and 1009 (for example, to remove an oxide layer that may exist on the surface).
  • the first hard mask layer 1013-1 may also be removed.
  • a gate stack may be formed in the recess of the first channel layer 1005.
  • a first gate dielectric layer 1029 and a first gate conductor layer 1031 can be deposited in sequence on the structure shown in FIG. 15, and the deposited first gate conductor layer 1031 (and optionally the first gate dielectric The layer 1029) is etched back so that the top surface of the portion outside the recess is not higher than and preferably lower than the top surface of the first channel layer 1005.
  • the first gate dielectric layer 1029 may include a high-K gate dielectric such as HfO 2 ; the first gate conductor layer 1031 may include a metal gate conductor.
  • a function adjustment layer can also be formed between the first gate dielectric layer 1029 and the first gate conductor layer 1031.
  • an interface layer such as oxide may also be formed.
  • the gate stack of the first device can be embedded and self-aligned into the recess of the first channel layer 1005 so as to overlap the entire height of the first channel layer 1005.
  • a stack of the first gate dielectric layer 1029 and the first gate conductor layer 1031 is also embedded.
  • the shape of the gate stack can be adjusted to facilitate subsequent interconnect fabrication.
  • a photoresist (not shown) may be formed on the structure shown in FIG.
  • the photoresist is patterned, for example, by photolithography to cover a portion of the gate stack exposed outside the recess (in this example, the left half of the figure), and to expose another portion of the gate stack exposed outside the recess (in this In the example, the right half of the figure).
  • photoresist can be used as a mask to selectively etch the first gate conductor layer 1031, such as RIE. In this way, the portion of the first gate conductor layer 1031 that is blocked by the photoresist is retained except for the portion that remains in the recess, as shown in FIG. 17. Subsequently, electrical connection to the gate stack can be achieved through this portion.
  • the first gate dielectric layer 1029 may be further selectively etched, such as RIE (not shown). After that, the photoresist can be removed.
  • oxide may be deposited on the structure shown in FIG. 17 and etched back to form a second isolation layer 1033.
  • the deposited oxide may be subjected to a planarization process such as CMP.
  • the top surface of the isolation layer 1033 may be located between the top surface and the bottom surface of the second source / drain layer 1007 (preferably, between the top surface and the bottom surface of the lower portion 1007-1 of the second source / drain layer), This helps to form an electrical contact layer adjacent to the source / drain region S / D-b1 of the first device and the source / drain region S / D-t2 of the second device.
  • an electrical contact layer 1037 can be formed on the structure shown in FIG. 18 by depositing and etching back a conductive material.
  • the electrical contact layer 1037 may include metal such as W.
  • the top surface of the electrical contact layer 1037 may be lower than the top surface of the second source / drain layer 1007 (preferably, not lower than the bottom surface of the upper portion 1007-2 of the second source / drain layer).
  • the exposed high-K gate dielectric layer 1029 may be removed, and a barrier layer 1035 such as TiN may also be deposited first.
  • the shape of the electrical contact layer 1037 can be adjusted to facilitate subsequent interconnect fabrication.
  • photolithography can be used to pattern the electrical contact layer 1037 as a part of it (in this example, the right part in the figure) extends laterally with respect to the rest.
  • the electrical connection to the electrical contact layer 1037 can be achieved through the protruding portion.
  • the electrical contact layer 1037 surrounds the second source / drain layer 1007, which helps reduce contact resistance.
  • barrier layer 1039 such as TiN can be further deposited. In this way, the barrier layers 1035 and 1039 can encapsulate the electrical contact layer 1037 to block its diffusion.
  • excess portions other than the portions of the barrier layers 1035 and 1039 used to encapsulate the electrical contact layer 1037 can also be removed to avoid affecting the device performance (for example, the presence of a conductive barrier layer in the isolation layer may cause errors Electrical connection, parasitic capacitance, etc.). For example, this can be done as follows. As shown in FIG. 21, a part of the laterally extending portion of the barrier layers 1035, 1039 on the second isolation layer 1031 can be removed using, for example, photolithography. Then, as shown in FIG. 22, a third isolation layer 1041 may be formed on the structure shown in FIG. 21 by, for example, depositing an oxide and etching it back.
  • the top surface of the third isolation layer 1041 may be higher than the top surface of the electrical contact layer 1037, but lower than the bottom surface of the second channel layer 1009. After that, the barrier layers 1035, 1039 exposed by the third isolation layer 1041 may be removed. In this way, the barrier layers 1035, 1039 basically only extend over the outer periphery of the electrical contact layer 1037 (slightly beyond to ensure a margin) so as to encapsulate the electrical contact layer 1037.
  • a common electrical contact layer 1037 is formed for the first device and the second device.
  • the present disclosure is not limited to this. Separate electrical contact layers can be formed for them, for example, where the opposing source / drain layers in the first device and the second device are not electrically connected.
  • the gate stack of the second device can be similarly formed.
  • an oxide may be deposited on the structure shown in FIG. 22 and etched back to form a fourth isolation layer 1043.
  • the deposited oxide may be subjected to a planarization process such as CMP.
  • the CMP may stop at the third source / drain layer 1011 or the silicide 1025.
  • the top surface of the isolation layer 1043 may be located between the top surface and the bottom surface of the second channel layer 1009, which helps to form a self-aligned gate stack. Due to the presence of the first gate dielectric layer 1029 and the first gate conductor layer 1031, the material of the isolation layer 1043 can be prevented from entering the above-mentioned recess to accommodate the gate stack.
  • the first gate dielectric layer 1029 and the first gate conductor layer 1031 can be removed to release the recessed space of the second channel layer 1009 and form the gate of the second device in the space
  • the stack includes a second gate dielectric layer 1045 and a second gate conductor layer 1047.
  • the shape of the gate stack can be adjusted to facilitate subsequent interconnect fabrication.
  • the materials of the first gate dielectric layer and the second gate conductor layer and their forming processes please refer to the description above in conjunction with FIGS. 14-17. It should be noted here that the second gate dielectric layer 1045 and the first gate dielectric layer 1029 may be the same or different. When the second gate dielectric layer 1045 is the same as the first gate dielectric layer 1029, FIG.
  • the dielectric layer 1029 removes the first gate conductor layer 1031 and forms a second gate conductor layer 1047 in the released recessed space.
  • the second gate conductor layer 1047 and the first gate conductor layer 1031 may be the same or different.
  • the gate stack of the second semiconductor device can be embedded and self-aligned into the recess so as to overlap the entire height of the second channel layer 1009.
  • an interlayer dielectric layer 1049 may be formed on the structure shown in FIG.
  • an interlayer dielectric layer 1049 can be formed by depositing oxide and planarizing it such as CMP.
  • electrical contacts 1051-1 to 1051-5 to the respective source / drain regions and gate conductor layers of the first device and the second device may be formed. These contacts can be formed by etching holes in the interlayer dielectric layer 1049 and the isolation layer and filling them with a conductive material such as metal.
  • the corresponding contact portions 1051-2 to 1051-4 can be easily formed.
  • the doped region in the substrate 1001 extends beyond the active region, the corresponding contact 1051-5 can be easily formed.
  • 26 to 35 are schematic diagrams showing some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • the second hard mask layer 1013-2 may include a material that can be retained in the subsequent processing without being etched away, such as SiC, so that the hard mask is set in the entire processing process 1013 (especially the second hard mask layer 1013-2 and the first hard mask layer 1013-1 below) can remain.
  • the third source / drain layer 1011 of the second device and the upper portion 1007-2 of the second source / drain layer are refined so that the third source / drain
  • the lateral dimensions of the upper portion 1007-2 of the layer 1011 and the second source / drain layer are reduced (even smaller than the second channel layer 1009), and the refined third source / drain layer 1011 and the second source / drain layer
  • the outer periphery of the upper portion 1007-2 can be substantially aligned.
  • the lower part 1007-1 of the second source / drain layer 1007 and the upper part of the first source / drain layer 1003 of the first device are refined so that the lower part 1007-1 of the second source / drain layer 1007 and the first
  • the lateral size of the upper part of a source / drain layer 1003 is reduced (it may even be smaller than that of the first channel layer 1005), and the lower part 1007-1 of the second source / drain layer and the first source / drain layer 1003 undergoing refinement
  • the periphery can be substantially aligned.
  • the thinning process of the source / drain layer of the first device and the thinning process of the source / drain layer of the second device may be performed simultaneously.
  • the thinning process can effectively reduce the facing area between the gate and the source / drain, and thus can reduce the overlapping capacitance between the gate and the source / drain, and improve the reliability of the semiconductor device.
  • the refined source / drain layer may be silicided to form a silicide 1025 at the surface of the source / drain layer.
  • the silicidation process has been described above in conjunction with FIG. 12 and will not be repeated here.
  • An isolation layer may be formed around the active area to achieve electrical isolation.
  • the isolation layer is formed in multiple layers.
  • oxide 1027 may be deposited on the structure shown in FIG. 26, planarized and stopped at the second hard mask layer 1013-2 (SiC). Then, as shown in FIG. 28, the planarized oxide may be etched back to form the first isolation layer 1027.
  • the top surface of the isolation layer 1027 may be located between the top surface and the bottom surface of the first channel layer 1005, which helps to form a self-aligned gate stack. Due to the existence of the sacrificial gates 1015, 1021, the material of the isolation layer 1027 can be prevented from entering the above-mentioned recess to accommodate the gate stack.
  • the oxide in the recesses of the sidewalls of the second source / drain layer 1007 and the third source / drain layer 1011 relative to the outer periphery of the hard mask layer is retained, forming a shadow Layer 1053.
  • the shielding layer 1053 is substantially coplanar with the corresponding source / drain layer, which facilitates the subsequent formation of a gate stack that is self-aligned to the channel layer.
  • the sacrificial gate 1021 may be removed to release the space in the recess of the first channel layer 1005 relative to the shielding layer 1053.
  • the sacrificial gate 1015 is also removed.
  • a gate stack may be formed in the recess of the first channel layer 1005.
  • the first gate dielectric layer 1029 and the first gate conductor layer 1031 can be deposited in sequence, and the deposited first gate conductor layer 1031 can be etched back so that the top surface of the portion outside the recess is not high It is preferably lower than the top surface of the first channel layer 1005.
  • the gate stack of the first device can be embedded in the recess of the first channel layer 1005 relative to the shielding layer 1053 and self-aligned with the first channel layer 1005 so as to be the entire height of the first channel layer 1005 Overlap.
  • a stack of the first gate dielectric layer 1029 and the first gate conductor layer 1031 is also embedded.
  • the shape of the gate stack can be adjusted to facilitate subsequent interconnect fabrication.
  • a photoresist (not shown) may be formed on the structure shown in FIG.
  • the photoresist is patterned, for example, by photolithography to cover a portion of the gate stack exposed outside the recess (in this example, the left half of the figure), and to expose another portion of the gate stack exposed outside the recess (in this In the example, the right half of the figure).
  • photoresist can be used as a mask to selectively etch the first gate conductor layer 1031, such as RIE.
  • the portion of the first gate conductor layer 1031 except for the portion left in the recess is retained by the photoresist, as shown in FIG. 30, and then the photoresist can be removed. Subsequently, electrical connection to the gate stack can be achieved through this portion.
  • oxide is deposited and etched back to form a second isolation layer 1033. Before the etch back, the deposited oxide can be planarized.
  • the top surface of the isolation layer 1033 may be located between the top surface and the bottom surface of the second source / drain layer 1007, which helps to form the source / drain regions S / D-b1 of the first device and the second device The electrical contact layer adjacent to the source / drain region S / D-t2.
  • an electrical contact layer 1037 can be formed by depositing a conductive material and etching it back.
  • the electrical contact layer 1037 may include metal such as W.
  • the top surface of the electrical contact layer 1037 may be lower than the top surface of the second source / drain layer 1007.
  • a barrier layer (not shown) may be deposited. In this regard, reference may be made to the above description in conjunction with FIGS. 18 and 19, which will not be repeated.
  • the shape of the electrical contact layer 1037 can be adjusted to facilitate subsequent interconnect fabrication.
  • photolithography can be used to pattern the electrical contact layer 1037 as a part of it (in this example, the right part in the figure) extends laterally with respect to the rest.
  • the electrical connection to the electrical contact layer 1037 can be achieved through the protruding portion.
  • the electrical contact layer 1037 surrounds the second source / drain layer 1007, which helps reduce contact resistance.
  • a barrier layer (not shown) can be further deposited. In this way, the barrier layer deposited this time and the barrier layer previously deposited can encapsulate the electrical contact layer 1037 to block its diffusion.
  • a third isolation layer (not shown in the figure) may also be formed, and the barrier layer exposed by the third isolation layer is removed by photolithography so that the barrier layer extends substantially only on the outer periphery of the electrical contact layer 1037 (slightly Beyond to ensure a margin) in order to encapsulate the electrical contact layer 1037. In this regard, reference may be made to the above description in conjunction with FIGS. 20 and 22, which will not be repeated.
  • the gate stack of the second device can be similarly formed.
  • the oxide is continuously deposited and etched back to form the fourth isolation layer 1043.
  • the deposited oxide can be planarized, such as CMP, so that the top surface of the isolation layer 1043 can be located between the top surface and the bottom surface of the second channel layer 1009, which helps to form a self-alignment
  • the isolation layer 1043 fills the recess of the third source / drain layer 1011 relative to the hard mask layer to form another shielding layer 1054.
  • the shielding layer 1054 is substantially coplanar with the corresponding source / drain layer, which facilitates the subsequent formation of a gate stack that is self-aligned to the channel layer.
  • the first gate dielectric layer 1029 and the first gate conductor layer 1031 can be removed to release the space in the recess of the second channel layer 1009 relative to the shielding layer 1054 and form in the space
  • the gate stack of the second device includes a second gate dielectric layer 1045 and a second gate conductor layer 1047, and the gate conductor layer 1047 is etched back so that the top surface of the portion of the gate conductor layer 1047 outside the recess is lower than the second channel The top surface of layer 1009.
  • the shape of the gate stack can be adjusted to facilitate subsequent interconnect fabrication. It should be pointed out here that the second gate dielectric layer 1045 and the first gate dielectric layer 1029 may be the same or different.
  • FIG. 34 may also retain the first gate
  • the dielectric layer 1029 removes the first gate conductor layer 1031 and forms a second gate conductor layer 1047 in the released recessed space.
  • the second gate conductor layer 1047 and the first gate conductor layer 1031 may be the same or different.
  • the gate stack of the second device can be embedded in the recess of the second channel layer 1009 relative to the shielding layer 1054, self-aligned to the second channel layer 1009, and thus intersect the entire height of the second channel layer 1009 Stack.
  • an interlayer dielectric layer 1049 may be formed on the structure shown in FIG.
  • an interlayer dielectric layer 1049 can be formed by depositing oxide and planarizing it such as CMP.
  • electrical contacts 1051-1 to 1051-5 to the respective source / drain regions and gate conductor layers of the first device and the second device may be formed. These contacts can be formed by etching holes in the interlayer dielectric layer 1049 and the isolation layer and filling them with a conductive material such as metal. Since the gate conductor layers 1031, 1047 and the electrical contact layer 1037 extend beyond the outer periphery of the active region, the corresponding contact portions 1051-2 to 1051-4 can be easily formed. In addition, since the doped region in the substrate 1001 extends beyond the active region, the corresponding contact 1051-5 can be easily formed.
  • the semiconductor device may include the first device and the second device stacked in the vertical direction.
  • the first device includes a first source / drain layer 1003, a first channel layer 1005, and a second source / drain layer 1007 (or a lower portion 1007-1 thereof) stacked in the vertical direction.
  • At least part of the sidewalls of the first channel layer 1005 extend along the first crystal plane or crystal plane family, and a gate stack (1029/1031) is formed around the outer periphery of the first channel layer 1005.
  • the second device includes a second source / drain layer 1007 (or an upper portion 1007-2 thereof) stacked in the vertical direction, a second channel layer 1009, and a third source / drain layer 1011. At least part of the side walls of the second channel layer 1009 extend along the second crystal plane or crystal plane family, and a gate stack (1045/1047) is formed around the outer periphery of the first channel layer 1005.
  • patterning is performed using photoresist.
  • a pattern transfer technique or the like can also be used.
  • 36 to 39 show schematic diagrams showing the flow of patterning a hard mask layer according to an embodiment of the present disclosure.
  • the semiconductor stack shown in FIG. 1 is still used.
  • a hard mask layer 1013 may also be formed, and the hard mask layer 1013 may include a first hard mask layer 1013-1 and a second hard mask layer 1013 that are sequentially stacked 2 ⁇ third hard mask layer 1013-3.
  • the hard mask 1013 may also be provided in other ways.
  • a first sacrificial layer 1055 is formed on the hard mask layer 1013.
  • the first sacrificial layer 1055 may include amorphous silicon ( ⁇ -Si).
  • the first sacrificial layer 1055 includes a first side wall extending in the first direction (the side wall shown on the left side in the figure).
  • the first direction extends in the direction of the crystal plane or family of crystal planes, such as the (100) crystal plane or the ⁇ 100 ⁇ crystal plane family.
  • the first sidewall 1056 extending in the first direction may be formed on the first sidewall of the first sacrificial layer 1055.
  • the first spacer 1056 may include nitride.
  • the first sacrificial layer 1055 may be removed.
  • the pattern of the first sidewall spacer 1056 may be transferred into the hard mask layer 1013, and the first sidewall spacer is removed.
  • FIGS. 37 (a) -37 (c) FIGS. 37 (a) is a front sectional view before removing the first side wall 1056
  • FIG. 37 (b) is a front sectional view after removing the first side wall 1056.
  • the pattern of the first sidewall spacer 1056 can be transferred to the third hard mask layer 1013 of the hard mask layer 1013 -3.
  • this may be performed by selectively etching the third hard mask layer 1013-3, such as RIE. RIE may stop at the second hard mask layer 1013-2.
  • the first sidewall spacer 1056 can be removed by selective etching (of course, 1056 can also be left).
  • the third hard mask layer 1013-3 has a strip shape extending in the first direction.
  • a second sacrificial layer is formed on the hard mask layer 1013, and the second sacrificial layer includes a second sidewall extending in the second direction.
  • the second direction may also extend in the direction of the crystal plane or family of crystal planes, such as the (100) crystal plane or the ⁇ 100 ⁇ crystal plane family. That is, the second direction may extend along the same crystal family direction as the first direction.
  • the second direction may be different from the first direction, for example crossing the first direction (e.g., perpendicular) in order to subsequently define a closed pattern.
  • a second side wall extending along the second direction may be formed on the second side wall. The second side wall intersects the pattern of the first side wall, thereby defining the desired pattern where they intersect.
  • the formation of the second sacrificial layer and the second side wall may be the same as the formation of the first sacrificial layer and the first side wall, only the extending direction is different, and will not be repeated here.
  • the pattern of the second sidewall spacer may be transferred into the third hard mask layer 1013-3 of the hard mask layer 1013, and the second sidewall spacer is removed.
  • the third hard mask layer 1013-3 is rectangular in a plan view, as shown in FIG. 38.
  • the third hard mask layer 1013-3 has a rectangular column shape with sidewalls extending along the (100) crystal plane.
  • the third hard mask layer 1013-3 can be used as a mask to define the active area of the n-type device.
  • the third hard mask layer 1013-3 may be patterned into a square pillar shape whose sidewalls extend along the (110) crystal plane ⁇ 110 ⁇ crystal plane family, and a top view thereof is shown in FIG. 39.
  • the pattern transfer technology can at least partially overcome the limitations of lithography technology, and the pattern size can be more precise.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating multiple such semiconductor devices and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and an electronic device constructed therefrom. Therefore, the present disclosure also provides an electronic device including the above semiconductor arrangement.
  • the electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and the like.
  • a method of manufacturing a system on chip is also provided.
  • the method may include the method of manufacturing a semiconductor device described above.
  • various devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

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Abstract

一种半导体器件及其制造方法及包括该半导体器件的电子设备，半导体器件包括：衬底（1001）、依次叠置在衬底（1001）上的第一器件和第二器件，第一器件和第二器件各自均包括：从下至上依次叠置的第一源/漏层（1003、1007-2）、沟道层（1005、1009）和第二源/漏层（1007-1、1011），以及绕沟道层（1005、1009）的至少部分外周形成的栅堆叠（1029/1031、1045/1047），第一器件和第二器件各自的沟道层（1005、1009）的侧壁中至少部分沿不同的晶体晶面或晶面族延伸。

Description

半导体器件及其制造方法及包括该器件的电子设备
相关申请的引用
本申请要求于2018年10月26日递交的题为“半导体器件及其制造方法及包括该器件的电子设备”的中国专利申请201811265733.2的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，缩小水平型器件所占的面积，一般要求源极、漏极和栅极所占的面积缩小，这样会使器件性能变差(例如，功耗和电阻增加)，故水平型器件的面积不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件所占的面积更容易缩小。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种能够很好地缩小所占面积的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；依次叠置在衬底上的第一器件和第二器件，第一器件和第二器件各自均包括：从下至上依次叠置的第一源/漏层、沟道层和第二源/漏层，以及绕沟道层的至少部分外周形成的栅堆叠，第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上从下至上依次叠置第一器件的第一源/漏层、沟道层和第二源/漏层以及第 二器件的第一源/漏层、沟道层和第二源/漏层；在第一器件的第一源/漏层、沟道层和第二源/漏层以及第二半导体器件的第一源/漏层、沟道层和第二源/漏层中限定相应半导体器件的有源区，使得第一器件的沟道层的侧壁与第二器件的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸；以及分别绕第一器件和第二器件各自的沟道层的至少部分外周形成第一器件和第二器件各自的栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括至少部分地由上述半导体器件形成的集成电路。
根据本公开的实施例，半导体器件包括彼此叠置的竖直型器件，能够大幅度地缩小面积，节省空间。栅堆叠绕沟道层的至少部分外周形成且沟道形成于沟道层中，从而栅长可以由沟道层的厚度确定，可以实现对栅长的较好控制。另外，可以将不同器件的沟道层的至少一部分侧壁设置为沿不同晶体晶面或晶面族延伸。由于载流子在不同晶体晶面或晶面族方向上可以具有不同的迁移率，于是可以调节不同器件的沟道层中的载流子迁移率，进而调节不同器件的导通效果，以优化半导体器件的整体性能。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至25示出了根据本公开实施例的制造半导体器件的流程的示意图；
图26至35示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图；
图36至39示出示出了根据本公开实施例对硬掩膜层进行构图的流程的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知 结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
本公开实施例的半导体器件可以包括依次叠置在衬底上的第一器件和第二器件。第一器件和第二器件均为竖直型器件。这种竖直型器件可以包括依次叠置的第一源/漏层、沟道层和第二源/漏层。在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。不同竖直器件的有源区叠层配置可以相同，也可以不同。
根据本公开的实施例，不同器件特别是不同导电类型的器件的沟道层的至少一部分侧壁可以沿不同的晶体晶面或晶面族延伸。由于载流子在不同晶体晶面或晶面族方向上可以具有不同的迁移率，于是可以调节不同器件的沟道层中的载流子迁移率，进而调节不同器件的导通效果，以优化半导体器件的整体性能。例如，在沟道层为单晶半导体材料或者为Si、SiGe或Ge晶体之一的情况下，n型器件的沟道层侧壁中至少部分可以沿(100)晶面或{100}晶面族延伸，因为该晶面或晶面族有利于电子的迁移率；而p型器件的沟道层侧壁中至少部分可以沿(110)晶面或{110}晶面族延伸，因为该晶面或晶面族有利于空穴的迁移率。另外，在器件为不同导电类型时，可以形成互补金属氧化物半导体(CMOS)配置。
根据本公开的实施例，可以并非对沟道层的所有侧壁进行优化(即，使它们均沿期望的晶体晶面或晶面族延伸)，而是只对部分侧壁进行优化。例如， 为提升器件可靠性和降低工艺波动，可以对沟道层进行倒角处理。此时，侧壁的圆角部分可能并非沿着期望的晶体晶面或晶面族延伸。又如，可以对沟道层的侧壁中面积较大的侧壁进行优化，而忽略面积较小的侧壁的影响，例如在纳米片的情况下。此种情况下，侧壁的晶面不是单一晶面族。
根据本公开的实施例，器件的第一源/漏层可以沿[100]晶向或沿<100>晶向族指向其第二源/漏层的方向，该指向平行于{100}晶面族和{110}晶面族，即{100}晶面族和{110}晶面族垂直于衬底，使得沿{100}晶面族或{110}晶面族延伸的沟道层侧壁垂直于衬底。
在沟道层的侧壁沿晶体晶面或晶面族延伸时，沟道层的相邻侧壁之间可能形成尖角。这种尖角并不稳定，可能降低器件的可靠性和造成器件性能的波动。为此，可以对沟道层进行倒角处理，使得沟道层的相邻侧壁所形成的角可以为相对和缓的圆角。
沟道层可以由半导体的单晶材料构成，以改善器件性能，例如降低沟道电阻。不同器件的沟道层的半导体单晶材料可以具有相同的晶向，和/或可以具有相同的晶体结构。这样，这些器件的沟道层可以用同样的基体制造，制造方便且缺陷较少。
当然，第一、第二源/漏层也可以由半导体的单晶材料构成。这种情况下，沟道层的半导体单晶材料与源/漏层的半导体单晶材料可以是共晶体。沟道层半导体单晶材料的电子或空穴迁移率可以大于第一、第二源/漏层的电子或空穴迁移率。另外，第一、第二源/漏层的禁带宽度可以大于沟道层半导体单晶材料的禁带宽度。
栅堆叠可以绕沟道层的至少部分外周形成。于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于刻蚀时间来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。
根据本公开的实施例，栅堆叠可以自对准于沟道层。例如，栅堆叠可以与沟道层实质上共面。特别是，栅堆叠所占据的空间可以由沟道层与第一、第二源/漏层之间的界面来限定。这种情况下，栅堆叠的至少部分上表面可以与沟道层的上表面实质上共面，且栅堆叠的至少部分下表面可以与沟道层的下表面 实质上共面。这样，可以减少或甚至避免栅堆叠与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
根据本公开的实施例，沟道层可以相对于源/漏层具有刻蚀选择性，例如包括不同的半导体材料。这样，有利于分别对沟道层和源/漏层进行处理例如选择性刻蚀。另外，第一源/漏层和第二源/漏层可以包括相同的半导体材料。
根据本公开的实施例，第一、第二源/漏层的横向尺寸可以大于沟道层的横向尺寸，使得沟道层的外周相对于第一、第二源/漏层的外周向内凹入，所形成的栅堆叠可以嵌于沟道层相对于第一、第二源/漏层的凹入中。根据本公开的其他实施例，第一、第二源/漏层的横向尺寸可以不大于沟道层的横向尺寸，从而可以减小所形成的栅堆叠与源/漏区的正对面积，有助于降低栅与源/漏之间的重叠电容。在俯视图中，第二器件的第一源/漏层、沟道层和第二源/漏层可以处于第一器件的第二源/漏层的范围之内。
第一器件和第二器件可以是彼此电连接的。例如，这种电连接可以通过第一器件的第二源/漏层与第二器件的第一源/漏层彼此邻接即直接物理接触来实现。这种情形下，第一器件的第二源/漏层与第二器件的第一源/漏层甚至可以是一体的，也即，它们可以通过同一半导体层来提供。
由于第一器件和第二器件均是竖直型器件且彼此叠置，因此除了处于最上方的第二器件的第二源/漏层之外，其余源/漏层(其中形成器件的源/漏区)以及绕沟道层形成的栅堆叠无法直接在各自的上方形成电接触部。因此，为了形成到它们的电连接，可以形成在横向上偏移的电接触部，并通过横向延伸的部件而与之电连接。例如，绕沟道层外周形成的栅堆叠(具体地，其中的栅导体)可以包括从相应的凹入横向向外延伸的横向延伸部分，该横向延伸部分可以延伸超出所限定的有源区外周，以便随后能够在其上方形成与之相接触的电接触部。对于第一器件的第二源/漏层及第二器件的第一源/漏层，可以提供与之邻接的电接触层。电接触层可以环绕第一器件的第二源/漏层及第二器件的第一源/漏层的外周，以降低接触电阻。电接触层的一部分(称作“横向延伸部分”)可以相对于其余部分横向伸出，且可以伸出到所限定的有源区之外，以便随后能够在其上方形成与之相接触的电接触部。对于处于最下方的第一器件的第一源/漏层，可以将其构图为下部延伸超出上部的外周，从而随后能够在其下部 的上方形成与之相接触的电接触部。
由于存在多个这样的横向延伸部分，这些横向延伸部分中的至少一些可以向着不同的方向横向延伸，以避免相应的电接触部之间相互干扰。如果这些横向延伸部分中至少一些在竖直方向上交迭，则在这些交迭的横向延伸部分中，位于下方的横向延伸部分可以延伸超出位于上方的横向延伸部分，以避免相应电接触相互干扰。
这种半导体器件例如可以如下制造。具体地，可以在衬底上从下至上依次叠置第一器件的第一源/漏层、沟道层和第二源/漏层以及第二器件的第一源/漏层、沟道层和第二源/漏层。例如可以通过外延生长来提供这些层，在外延生长时，可以控制所生长的沟道层的厚度。另外，如上所述，第一器件的第二源/漏层与第二器件的第一源/漏层可以是一体的，即，同一层。由于分别外延生长，至少一对相邻层之间可以具有清晰的晶体界面。另外，可以分别对各层进行不同掺杂，于是至少一对相邻层之间可以具有掺杂浓度界面。
对于叠置的上述各层，可以在其中限定有源区。例如，可以将它们依次选择性刻蚀为所需的形状。刻蚀的顺序可以从上至下对各层依次进行，如上所述，为了便于在后继工艺中连接处于最下方的第一器件的第一源/漏层中形成的源/漏区，对该层的刻蚀可以只针对该层的上部，从而该层的下部可以延伸超出其上部的外周。然后，可以绕沟道层的外周形成栅堆叠。
根据本公开的实施例，可以沿一定的晶体晶面或晶面族来形成沟道层的侧壁。当然，在限定有源区时通常利用相同的掩模，于是第一源/漏层和第二源/漏层的侧壁也可以沿相同的晶体晶面或晶面族延伸。于是，有源区可以呈方柱状。另外，对于第一器件和第二器件，特别是在它们具有不同导电类型时，它们各自的沟道层的侧壁中至少部分可以沿不同的晶体晶面或晶面族延伸。
在第一器件和第二器件的沟道层的至少部分侧壁沿不同的晶体晶面或晶面族延伸时，可以分别利用不同的掩模来对它们进行构图。例如，可以利用至少部分侧壁沿期望的晶体晶面或晶面族延伸的第一掩模来对第二器件的有源区进行构图，并可以利用至少部分侧壁沿不同的期望晶体晶面或晶面族延伸的第二掩模来对第一器件的有源区进行构图。由于构图从上至下进行，为避免处于上方的第二器件的有源区阻碍对处于下方的第一器件的有源区的构图，第一 掩模的边界可以处于第二掩模的边界的范围之内。
另外，可以使各器件的沟道层的外周相对于相应的第一、第二源/漏层的外周向内凹入，以便限定容纳栅堆叠的空间。例如，这可以通过选择性刻蚀来实现。于是，栅堆叠可以嵌入该凹入中。为了保持沟道层的侧壁仍然沿相应晶面或晶面族延伸，沟道层的凹入可以通过各向同性刻蚀来实现。
为了提高器件的可靠性，可以将沟道层的相邻侧壁之间形成的尖角处理为相对和缓的圆角。
在各器件的第一、第二源/漏层中可以形成源/漏区。例如，这可以通过对第一、第二源/漏层掺杂来实现。例如，可以进行离子注入、等离子体掺杂，或者在生长第一、第二源/漏层时原位掺杂。根据一有利实施例，可以在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅，然后在第一、第二源/漏层的表面上形成掺杂剂源层，并通过例如退火使掺杂剂源层中的掺杂剂经第一、第二源/漏层进入有源区中。牺牲栅可以阻止掺杂剂源层中的掺杂剂直接进入沟道层中。但是，可以有部分掺杂剂经由第一、第二源/漏层而进入沟道层靠近第一源/漏层和第二源/漏层的端部，由此在沟道层靠近第一源/漏层和第二源/漏层的端部形成掺杂分布，这有助于降低器件导通时源/漏区与沟道区之间的电阻，从而提升器件性能。对于第一器件和第二器件，形成源/漏区的操作可以一起进行(例如，在它们各自的源/漏区具有相同或相似掺杂特性的情况下)，或者可以分开进行(例如，在它们各自的源/漏区具有不同的掺杂特性的情况下)。在后续制作过程中，可以去除沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中的牺牲栅，在相应凹入中形成针对相应器件的栅堆叠。
在上述从上至下的刻蚀过程中，在形成第二器件的牺牲栅之后且在限定第一器件的有源区之前，为了保护已形成的第二器件有源区不受后续处理的影响，还可以在第二器件的第一、第二源/漏层的表面上形成保护层。另外，在形成第一器件和第二器件的牺牲栅之后，还可以对源/漏层进行硅化处理，以降低接触电阻。
本公开可以各种形式呈现，以下将描述其中一些示例。
图1至25示出了根据本公开实施例的制造半导体器件的流程的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。根据本公开的实施例，衬底1001可以是(100)单晶硅、单晶锗硅或单晶锗晶圆。此时，与(100)晶面垂直的晶面中既有{100}晶面族的晶面又有{110}晶面族的晶面，有利于下述器件的制造。
在衬底1001上，可以通过例如外延生长，依次形成第一源/漏层1003、第一沟道层1005、第二源/漏层1007、第二沟道层1009以及第三源/漏层1011。例如，对于p型器件，第一源/漏层1003可以包括合适的半导体材料如SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm；第一沟道层1005可以包括不同于第一源/漏层1003、第二源/漏层1007的半导体材料如Si，厚度为约10-100nm；第二源/漏层1007可以包括与第一源/漏层1003相同的材料如SiGe(Ge的原子百分比可以为约10-40％)；第二沟道层1009可以包括不同于第二源/漏层1007、第三源/漏层1011的半导体材料如Si，厚度为约10-100nm；第三源/漏层1011可以包括与第二源/漏层1007相同的材料如SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm。源/漏层和沟道层的材料选择不限于此，可以包括能够提供适当刻蚀选择性的其他半导体材料。例如，各沟道层可以包括与之下或之上的源/漏层相同的组分，但是组分含量不同的半导体材料(例如，都是SiGe，但是其中Ge的原子百分比不同)，只要沟道层相对于之下及之上的源/漏层具备刻蚀选择性。
在该示例中，第一源/漏层1003、第一沟道层1005以及第二源/漏层1007的下部1007-1(例如，厚度为约10-50nm)用于限定第一器件的有源区，且第二源/漏层1007的上部1007-2(例如，厚度为约10-50nm)、第二沟道层1009以及第三源/漏层1011用于限定第二器件的有源区。在此，第一器件和第二器件彼此邻接，且共享相同的源/漏层1007。但是本公开不限于此。例如，可以分别生长用于第一器件的源/漏层1007-1以及用于第二器件的源/漏层1007-2，它们可以具有相同或不同的半导体材料。甚至，第一器件和第二器件并不邻接，而是在之间具有电介质层从而彼此电隔离，例如，可以在用于第一器件的源/漏层1007-1以及用于第二器件的源/漏层1007-2之间另外沉积电介质层。
在生长各源/漏层1003、1007、1011时，可以对它们进行原位掺杂，以便随后形成源/漏区。例如，对于n型器件，可以进行n型掺杂；对于p型器件，可以进行p型掺杂。
另外，在生长沟道层1005、1009时，也可以对它们进行原位掺杂，以调节器件阈值电压(V t)。例如，对于n型器件，可以进行p型掺杂，掺杂浓度为约1E17-1E19cm -3；对于p型器件，可以进行n型掺杂，掺杂浓度为约1E17-1E19cm -3。
另外，对于无结器件，可以对各源/漏层1003、1007、1011以及沟道层1005、1009进行相同类型的掺杂。
在该示例中，第一源/漏层1003是另外生长在衬底1001上的。但是，本公开不限于此。例如，可以通过衬底1001自身来形成第一源/漏层。在这种情况下，可以通过在衬底1001中形成阱区，以便在其中形成源/漏区。
另外，为了后继处理中构图的方便以及提供适当的停止层等目的，在所生长的这些半导体层之上，还可以形成硬掩模1013。在该示例中，硬掩模1013可以包括依次叠置的第一硬掩模层1013-1、第二硬掩模层1013-2和第三硬掩模层1013-3。例如，第一硬掩模层1013-1可以包括氧化物(如氧化硅)，厚度为约2-10nm；第二硬掩模层1013-2可以包括氮化物(如氮化硅)，厚度为约10-100nm；第三硬掩模层1013-3可以包括氧化物，厚度为约20-100nm。硬掩模1013的叠层配置主要是为了在后继处理中提供合适的刻蚀选择性，本领域技术人员可以设想其他配置。
接下来，可以限定器件的有源区。例如，这可以如下进行。具体地，如图2(a)和2(b)(图2(a)是截面图，图2(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在硬掩模1013上形成光刻胶(未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状(在该示例中，大致矩形)。在此，为了增强半导体器件的性能，可以根据器件的类型，按照不同的晶体晶面或晶面族方向来对光刻胶构图进行刻蚀。在本例中，假设第二器件为n型器件，期望其沟道的至少部分侧壁沿着(100)晶面或{100}晶面族延伸，故而可以将相应光刻胶构图为至少部分或者全部侧壁沿衬底1001的(100)晶面或{100}晶面族延伸(由于沟道层外延生长在衬底1001上，故而也沿沟道层的(100)晶面或 {100}晶面族延伸)的大致矩形图案。
然后，可以将构图后的光刻胶的形状转移到硬掩模1013。例如，可以依次对第三硬掩模层1013-3、第二硬掩模层1013-2和第一硬掩模层1013-1进行选择性刻蚀如反应离子刻蚀(RIE)。然后，可以依次对第三源/漏层1011、第二沟道层1009和第二源/漏层1007进行选择性刻蚀如RIE。刻蚀进行到第二源/漏层1007中，但并未进行到第二源/漏层1007的底面处，从而第二源/漏层的上部1007-2被构图为对应于硬掩模的形状，而其下部1007-1基本未变。于是，刻蚀后第三源/漏层1011、第二沟道层1009和第二源/漏层的上部1007-2形成方柱状。RIE例如可以按大致垂直于衬底表面的方向进行，从而该方柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
如图2(b)所示，刻蚀后第三源/漏层1011、第二沟道层1009和第二源/漏层的上部1007-2的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
当然，在其他实施例中，第二器件也可以是p型器件。当第二器件为p型器件时，可以将光刻胶构图为至少部分侧壁平行于(110)晶面或{110}晶面族延伸。于是，刻蚀后第三源/漏层1011、第二沟道层1009和第二源/漏层的上部1007-2的侧壁中至少部分沿(110)晶面或{110}晶面族延伸。
然后，如图3(a)和3(b)(图3(a)是正视截面图，图3(b)是俯视截面图，其中的11′线示出了俯视截面的截取位置，AA′线示出了正视截面的截取位置)所示，可以使第二沟道层1009的外周相对于第二源/漏层的上部1007-2和第三源/漏层1011的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。该凹入的上下侧壁分别由第二沟道层1009与第二源/漏层1007以及第二沟道层1009与第三源/漏层1011之间的界面限定。例如，这可以通过相对于第二源/漏层1007和第三源/漏层1011，进一步各向同性地选择性刻蚀第二沟道层1009来实现。例如，可以使用原子层刻蚀(ALE)或数字化刻蚀，来进行选择性刻蚀，以便更精确地控制刻蚀的量。
这样，就限定了第二器件的有源区(刻蚀后的第二源/漏层的上部1007-2、第二沟道层1009和第三源/漏层1011)。在该示例中，有源区大致呈方柱状，在有源区中，第二源/漏层的上部1007-2和第三源/漏层1011的外周可以实质上对准，而第二沟道层1009的外周相对凹入。如图3(b)所示，由于采用各向 同性刻蚀，第二沟道层1009在刻蚀前后基本保持共形，从而呈横向尺寸较小的方柱状，且其侧壁中至少部分依然保持沿(100)晶面或{100}晶面族延伸。
如图3(b)所示，第二沟道层1009的侧壁沿(100)晶面或{100}晶面族延伸，从而其相邻侧壁之间形成尖角。这种尖角在随后的工艺中可能损坏，导致工艺的不稳地性、器件可靠性的下降和器件性能的波动。为此，可以对这种尖角进行倒角处理，以使其圆滑。例如，可以通过氧化(且随后去除氧化层)，来将这种尖角处理为圆角。
在第二沟道层1009相对于第二源/漏层的上部1007-2和第三源/漏层1011的凹入中，随后将形成栅堆叠。为避免后继处理对于沟道层1009造成影响或者在该凹入中留下不必要的材料从而影响后继栅堆叠的形成，可以在该凹入中填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过在图3(a)和3(b)所示的结构上淀积氮化物，然后对淀积的氮化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮化物可仅留在凹入内，形成牺牲栅1015，如图4所示。这种情况下，牺牲栅1015可以基本上填满上述凹入。
可选地，还可以对第二源/漏层的上部1007-2和第三源/漏层1011进一步掺杂，特别是在上述原位掺杂浓度不够的情况下。具体地，如图5所示，可以在图4所示的结构上形成掺杂剂源层1017。例如，掺杂剂源层1017可以包括氧化物如氧化硅，其中含有掺杂剂。对于n型器件，可以包含n型掺杂剂；对于p型器件，可以包含p型掺杂剂。在此，为了减少掺杂剂源层1017对用于另一器件(第一器件)的第二源/漏层下部1007-1的影响(特别是在第一器件和第二器件的源/漏区具有不同掺杂特性的情况下)，掺杂剂源层1017可以形成为第二器件的有源区的侧壁上的侧墙(spacer)的形式(由于牺牲栅1015的存在，该侧墙事实上形成于第二源/漏层的上部1007-2和第三源/漏层1011的侧壁上)。例如，可以通过例如化学气相淀积(CVD)或原子层淀积(ALD)等大致共形地在图4所示结构的表面上淀积一薄膜，然后沿大致垂直于衬底表面的方向对该薄膜进行RIE，来得到侧墙形式的掺杂剂源层1017。
然后，如图6所示，可以通过例如退火，激活原位掺杂的杂质或者进一步使掺杂剂源层1017中包含的掺杂剂进入有源区中，从而在其中形成掺杂区， 如图中的阴影部分所示。更具体地，可以在第三源/漏层1011中形成第二半导体器件的源/漏区之一S/D-t1，且在第二源/漏层的上部1007-2中形成第二半导体器件的另一源/漏区S/D-t2。之后，可以去除掺杂剂源层1017。
另外，尽管有牺牲栅1015存在，但是掺杂剂也可以经由第二源/漏层的上部1007-2和第三源/漏层1011而进入第二沟道层1009中，从而在第二沟道层1009的上下两端处形成一定的掺杂分布(图中未示出)。这种掺杂分布可以降低器件导通时源/漏区之间的电阻，从而提升器件性能。
接下来，可以针对第一器件进行类似处理。如图7(a)所示，在第二器件的有源区周围和上方淀积氧化物1013-4，对其进行平坦化处理如CMP，平坦化处理可以停止于第二硬掩膜层1013-3，与原先存在的第三硬掩膜层1013-3形成一体(之后共同标记为1013-3)。该氧化物层随后可以对第一器件的有源区进行构图的过程中保护第二器件的有源区。
然后，可以限定第一器件的有源区。如图7(b)和7(c)(图7(b)是截面图，图7(c)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以形成光刻胶(未示出)，将光刻胶构图为所需形状(在该示例中，大致矩形，但是与先前的光刻胶图案的取向不同)。在本例中，假设第一器件与第二器件类型不同例如为p型器件，期望其沟道的至少部分侧壁沿着(110)晶面或{110}晶面族延伸，故而可以将相应光刻胶构图为至少部分或者全部侧壁沿衬底1001的(110)晶面或{110}晶面族延伸(由于沟道层外延生长在衬底1001上，故而也沿沟道层的(110)晶面或{110}晶面族延伸)的大致矩形图案。
另外，为避免与先前形成的第二器件的有源区相干扰，构图后的光刻胶所占据的范围使第二器件的有源区完全处于该范围之内。这样，可以将光刻胶的图案转移到第二器件的有源区下方的层中。
然后，将构图后的光刻胶的形状转移到下方的层中。可以依次对氧化物层1013-3、第二源/漏层1007的下部1007-1、第一沟道层1005和第一源/漏层1003进行选择性刻蚀如RIE。刻蚀可以进行到第一源/漏层1003中，但并未进行到第一源/漏层1003的底面处，从而第一源/漏层1003的上部被刻蚀，而下部基本未变。于是，刻蚀后第二源/漏层1007的下部1007-1、第一沟道层1005和第一源/漏层1003(或其上部)被构图为对应于光刻胶的形状，在本例中为方 柱状。RIE例如可以按大致垂直于衬底表面的方向进行，从而该柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
根据本公开的实施例，为了保护第二器件的有源区(特别是源/漏区)在后继处理中不受影响(特别是为了抑制掺杂剂交叉污染)，可以在其外周形成保护层1019，如图7(b)所示。为此，在对氧化物层1013-3进行RIE时，可以停止于第二源/漏层1007的下部1007-1。在RIE后的氧化物层1013-3的侧壁上，可以形成保护层1019。这种保护层1019也可以形成为侧墙形式，例如可以是SiC等。然后再接着刻蚀第二源/漏层1007的下部1007-1、第一沟道层1005和第一源/漏层1003。
如上所述，在该示例中，光刻胶构图为至少部分或者全部侧壁沿(110)晶面或{110}晶面族延伸。如图7(c)所示，刻蚀后第二源/漏层1007的下部1007-1、第一沟道层1005和第一源/漏层1003的上部的侧壁中至少部分沿(110)晶面或{110}晶面族延伸。
另外，如图7(c)所示，在限定第一器件的有源区时，已经形成的第二器件的第三源/漏层1011和第二源/漏层的上部1007-2也可能受到影响，使得第三源/漏层1011和第二源/漏层的上部1007-2(图中虚线所示)从大致方柱体变为大致八面柱体，而第二沟道层1009(图中点状线所示)由于是横向尺寸较小的方柱体，可以没有受到影响，其侧壁依然保持沿(100)晶面或{100}晶面族延伸。
根据其他实施例，第一器件也可以是n型器件。当第一器件为n型器件时，可以将光刻胶构图为其至少侧壁沿(100)晶面或{100}晶面族方向延伸，于是刻蚀后第二源/漏层1007的下部1007-1、第一沟道层1005和第一源/漏层1003的上部的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
然后，如图8(a)和8(b)(图8(a)是正视截面图，图8(b)是俯视截面图，其中的AA′线示出了正视截面的截取位置，其中的22′线示出了俯视截面的截取位置)所示，同样可以使第一沟道层1005的外周相对于第二源/漏层1007的下部1007-1和第一源/漏层1003(或其上部)的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。该凹入的上下侧壁分别由第一沟道层1005与第二源/漏层1007以及第一沟道层1005与第一源/漏层1003之间的界 面限定。例如，这可以通过相对于第二源/漏层1007和第一源/漏层1003，进一步各向同性地选择性刻蚀沟道层1005来实现。例如，可以使用原子层刻蚀(ALE)或数字化刻蚀，来进行选择性刻蚀，以便更精确地控制刻蚀的量。
这样，就限定了第一器件的有源区(刻蚀后的第二源/漏层的下部1007-1、第一沟道层1005和第一源/漏层1003)。在该示例中，有源区大致呈方柱状，在有源区中，第二源/漏层的下部1007-1和第一源/漏层1003的外周可以实质上对准，而第一沟道层1005的外周相对凹入。如图8(b)所示，由于采用各向同性刻蚀，第一沟道层1005在刻蚀前后基本保持共形，从而呈横向尺寸较小的方柱状，且其侧壁中至少部分依然保持沿(110)晶面或{110}晶面族延伸。
如图8(b)所示，第一沟道层1005的侧壁沿(110)晶面或{110}晶面族延伸，从而其相邻侧壁之间形成尖角。这种尖角在随后的工艺中可能损坏，导致工艺的不稳地性、器件可靠性的下降和器件性能的波动。为此，可以对这种尖角进行倒角处理，以使其圆滑。例如，可以通过氧化(且随后去除氧化层)，来将这种尖角处理为圆角。
如上所述，在第一沟道层1005相对于第二源/漏层的下部1007-1和第一源/漏层1003所形成的凹入中可以形成牺牲栅1021，如图9所示。牺牲栅1021例如可以包括氮化物。如上所述，这可以通过淀积氮化物并回蚀来实现。可选地，为了改善选择性或工艺控制，在淀积氮化物之前，还可以淀积一层薄氧化物(例如，厚度为约1-5nm，图中未示出)。
类似地，可以可选地对第二源/漏层的下部1007-1和第一源/漏层1003进一步掺杂，特别是在上述原位掺杂浓度不够的情况下。具体地，如图10所示，可以在图9所示的结构上形成掺杂剂源层1023。例如，掺杂剂源层1023可以包括氧化物如氧化硅，其中含有掺杂剂。对于n型器件，可以包含n型掺杂剂；对于p型器件，可以包含p型掺杂剂。在此，掺杂剂源层1023可以是一薄膜，从而可以通过例如CVD或ALD等大致共形地淀积在图9所示结构的表面上。
然后，如图11所示，可以通过例如退火，激活原位掺杂的杂质或者进一步使掺杂剂源层1023中包含的掺杂剂进入有源区中，从而在其中形成掺杂区，如图11中的阴影部分所示。更具体地，可以在第二源/漏层的下部1007-1中形成第一半导体器件的源/漏区之一S/D-b1，且在第一源/漏层1003中形成第一 半导体器件的另一源/漏区S/D-b2。由于保护层1019的存在，可以抑制掺杂剂源层1023中的掺杂剂进入第二器件的有源区中。之后，可以通过例如选择性刻蚀，去除掺杂剂源层1023和保护层1019，氧化物1013-3也可以一并被去除。
在该示例中，掺杂剂源层1023包括沿第一源/漏层1003的下部(未被刻蚀的部分)的水平表面延伸的部分，从而甚至可以在第一源/漏层1003的下部(未被刻蚀的部分)的水平表面处形成掺杂区，该掺杂区延伸超出柱状有源区的外周。这样，在后继工艺中可以容易地通过该掺杂区电连接到源/漏区S/D-b2。
在以上示例中，通过从掺杂剂源层向有源区中驱入(drive in)掺杂剂来形成源/漏区，但是本公开不限于此。例如，可以通过离子注入、等离子体掺杂等方式，来形成源/漏区。
可选地，为了降低接触电阻，可以在源/漏区的表面处形成硅化物1025，如图12所示。例如，这可以通过在图11所示的结构上淀积一层金属层(例如，Ni、NiPt或Co)，并进行退火以使该金属层与半导体材料发生硅化反应，来生成硅化物1025。在该示例中，硅化物1025还形成在第一源/漏层1003的下部(未被刻蚀的部分)的水平表面上。随后，可以去除未反应的剩余金属。
可以在有源区周围形成隔离层，以实现电隔离。在此，为配合下述栅堆叠和电接触层的形成，隔离层分多层形成。
例如，如图13所示，可以在图12所示的结构上淀积氧化物1027，并对其进行平坦化处理如化学机械抛光(CMP)。CMP可以停止于第二硬掩膜层1013-2(氮化物)。然后，如图14所示，可以回蚀平坦化的氧化物，以形成第一隔离层1027。在此，隔离层1027的顶面可以位于第一沟道层1005的顶面与底面之间，这有助于形成自对准的栅堆叠。由于牺牲栅1015、1021的存在，可以避免隔离层1027的材料进入要容纳栅堆叠的上述凹入中。
之后，如图15所示，可以去除牺牲栅1021，以释放第一沟道层1005的凹入中的空间。例如，可以通过选择性刻蚀，来去除牺牲栅1021(氮化物)。在该示例中，由于牺牲栅1015以及第二硬掩模层1013-2同样是氮化物，故而其也被去除。此外，在去除牺牲栅1021、1015之后，还可以进行清洗，以清洁沟道层1005、1009的表面(例如，去除表面可能存在的氧化层)。在清洗过程中，第一硬掩模层1013-1也可以被去除。
然后，如图16所示，可以在第一沟道层1005的凹入中形成栅堆叠。具体地，可以在图15所示的结构上依次淀积第一栅介质层1029和第一栅导体层1031，并对所淀积的第一栅导体层1031(以及可选地第一栅介质层1029)进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于第一沟道层1005的顶面。例如，第一栅介质层1029可以包括高K栅介质如HfO 2；第一栅导体层1031可以包括金属栅导体。另外，在第一栅介质层1029和第一栅导体层1031之间，还可以形成功函数调节层。在形成第一栅介质层1029之前，还可以形成例如氧化物的界面层。
这样，第一器件的栅堆叠可以嵌入并自对准到第一沟道层1005的凹入中，从而与第一沟道层1005的整个高度相交迭。另外，在第二沟道层1009的凹入中，也嵌入了第一栅介质层1029和第一栅导体层1031的叠层。
接下来，可以对栅堆叠的形状进行调整，以便于后继互连制作。例如，可以在图16所示的结构上形成光刻胶(未示出)。该光刻胶例如通过光刻构图为覆盖栅堆叠露于凹入之外的一部分(在该示例中，图中左半部)，且露出栅堆叠露于凹入之外的另一部分(在该示例中，图中右半边)。然后，可以光刻胶为掩模，对第一栅导体层1031进行选择性刻蚀如RIE。这样，第一栅导体层1031除了留于凹入之内的部分之外，被光刻胶遮挡的部分得以保留，如图17所示。随后，可以通过该部分来实现到栅堆叠的电连接。
根据另一实施例，也可以进一步对第一栅介质层1029进行选择性刻蚀如RIE(图中未示出)。之后，可以去除光刻胶。
然后，如图18所示，可以在图17所示的结构上淀积氧化物，并对其回蚀，以形成第二隔离层1033。在回蚀之前，可以对淀积的氧化物进行平坦化处理如CMP。在此，隔离层1033的顶面可以位于第二源/漏层1007的顶面与底面之间(优选地，位于第二源/漏层的下部1007-1的顶面与底面之间)，这有助于形成与第一器件的源/漏区S/D-b1以及第二器件的源/漏区S/D-t2相邻接的电接触层。
接着，如图19所示，可以在图18所示的结构上，通过淀积导电材料并对其回蚀，来形成电接触层1037。例如，电接触层1037可以包括金属如W。电接触层1037的顶面可以低于第二源/漏层1007的顶面(优选地，不低于第二 源漏层的上部1007-2的底面)。优选地，在淀积导电材料之前，可以去除暴露在外的高K栅介质层1029，并且还可以先淀积一层阻挡层1035如TiN。
接下来，可以对电接触层1037的形状进行调整，以便于后继互连制作。例如，如图20所示，可以利用光刻，将电接触层1037构图为其一部分(在该示例中，图中右侧部分)相对于其余部分横向伸出。随后，可以通过该伸出部分来实现到电接触层1037的电连接。优选地，电接触层1037环绕第二源/漏层1007，这有助于减小接触电阻。
同样地，还可以进一步淀积阻挡层1039如TiN。这样，阻挡层1035和1039可以将电接触层1037包封在内，以阻挡其扩散。
另外，还可以去除阻挡层1035、1039用于包封电接触层1037的部分之外的多余部分，以避免其对器件性能造成影响(例如，在隔离层中存在导电的阻挡层可能会导致错误的电连接、寄生电容等问题)。例如，这可以如下进行。如图21所示，可以利用例如光刻，去除阻挡层1035、1039在第二隔离层1031上的一部分横向延伸部分。然后，如图22所示，可以在图21所示的结构上，通过例如淀积氧化物并对其回蚀，形成第三隔离层1041。第三隔离层1041的顶面可以高于电接触层1037的顶面，但是低于第二沟道层1009的底面。之后，可以去除被第三隔离层1041暴露在外的阻挡层1035、1039。这样，阻挡层1035、1039基本上只在电接触层1037的外周上延伸(稍有超出，以确保余量)以便包封电接触层1037。
在该示例中，针对第一器件和第二器件，形成了公共的电接触层1037。当然，本公开不限于此。可以针对它们形成分离的电接触层，例如在第一器件和第二器件中相对的源/漏层并不电连接的情况下。
接下来，可以类似地形成第二器件的栅堆叠。例如，如图23所示，可以在图22所示的结构上淀积氧化物，并对其回蚀，以形成第四隔离层1043。在回蚀之前，可以对淀积的氧化物进行平坦化处理如CMP。CMP可以停止于第三源/漏层1011或硅化物1025。在此，隔离层1043的顶面可以位于第二沟道层1009的顶面与底面之间，这有助于形成自对准的栅堆叠。由于第一栅介质层1029和第一栅导体层1031的存在，可以避免隔离层1043的材料进入要容纳栅堆叠的上述凹入中。
之后，如图24所示，可以去除第一栅介质层1029和第一栅导体层1031，以释放第二沟道层1009的凹入中的空间，并在该空间中形成第二器件的栅堆叠，包括第二栅介质层1045和第二栅导体层1047。同样地，可以对可以对栅堆叠的形状进行调整，以便于后继互连制作。关于第一栅介质层和第二栅导体层的材料以及它们的形成工艺，可以参见以上结合图14～17的描述。这里需要指出的是，第二栅介质层1045与第一栅介质层1029可以相同也可以不同，当第二栅介质层1045与第一栅介质层1029相同时，图24也可以保留第一栅介质层1029而去除第一栅导体层1031，并在释放的凹入空间中形成第二栅导体层1047，第二栅导体层1047与第一栅导体层1031可以相同也可以不同。
这样，第二半导体器件的栅堆叠可以嵌入且自对准到凹入中，从而与第二沟道层1009的整个高度相交迭。
然后，可以如图25所示，在图24所示的结构上形成层间电介质层1049。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1049。在层间电介质层1049中，可以形成到第一器件和第二器件各自的源/漏区以及栅导体层的电接触部1051-1至1051-5。这些接触部可以通过在层间电介质层1049以及隔离层中刻蚀孔洞，并在其中填充导电材料如金属来形成。
由于栅导体层1031、1047以及电接触层延1037伸超出有源区外周，从而可以容易地形成相应的接触部1051-2至1051-4。另外，由于衬底1001中的掺杂区延伸超出有源区之外，从而可以容易地形成相应接触部1051-5。
图26至35示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图。
例如，可以按照以上实施例中结合图1至11所描述的流程进行，在此不再赘述。需要说明的是，在本实施例中，第二硬掩模层1013-2可以包括在后继处理中可以保留而未被刻蚀掉的材料，例如SiC，这样设置使得整个处理过程中硬掩模1013(特别是第二硬掩模层1013-2及下方的第一硬掩模层1013-1)能够保留。
如图26所示，在图11所示的结构上，对第二器件的第三源/漏层1011和第二源/漏层的上部1007-2进行细化处理，使得第三源/漏层1011和第二源/漏层的上部1007-2的横向尺寸减小(甚至可以小于第二沟道层1009)，经过细化 处理的第三源/漏层1011和第二源/漏层的上部1007-2的外周可以实质上对准。同样地，对第一器件的第二源/漏层1007的下部1007-1和第一源/漏层1003的上部进行细化处理，使得第二源/漏层1007的下部1007-1和第一源/漏层1003的上部的横向尺寸减小(甚至可以小于第一沟道层1005)，经过细化处理的第二源/漏层的下部1007-1和第一源/漏层1003的外周可以实质上对准。对第一器件的源/漏层的细化处理和对第二器件的源/漏层的细化处理可以同时进行。通过细化处理可以有效减小栅与源/漏之间的正对面积，进而可以降低栅与源/漏之间的重叠电容，提高半导体器件的可靠性。可选地，为了降低接触电阻，可以对细化处理后的源/漏层进行硅化处理，在源/漏层的表面处形成硅化物1025。硅化处理的过程在上文中结合图12已说明，在此不再赘述。
可以在有源区周围形成隔离层，以实现电隔离。在此，为配合下述栅堆叠和电接触层的形成，隔离层分多层形成。
例如，如图27所示，可以在图26所示的结构上淀积氧化物1027，对其进行平坦化处理并停止于第二硬掩膜层1013-2(SiC)。然后，如图28所示，可以回蚀平坦化的氧化物，以形成第一隔离层1027。在此，隔离层1027的顶面可以位于第一沟道层1005的顶面与底面之间，这有助于形成自对准的栅堆叠。由于牺牲栅1015、1021的存在，可以避免隔离层1027的材料进入要容纳栅堆叠的上述凹入中。此外，在回蚀氧化物的过程中，在第二源/漏层1007、第三源/漏层1011的侧壁相对于硬掩模层的外周的凹入中的氧化物被保留，形成遮蔽层1053。遮蔽层1053与相应的源/漏层实质上共面，有助于随后形成自对准于沟道层的栅堆叠。
之后，如图29所示，可以去除牺牲栅1021，以释放第一沟道层1005相对于遮蔽层1053的凹入中的空间。牺牲栅1015也同样被去除。然后，可以在第一沟道层1005的凹入中形成栅堆叠。具体可以通过依次淀积第一栅介质层1029和第一栅导体层1031，并对所淀积的第一栅导体层1031进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于第一沟道层1005的顶面。对此，可以参照以上结合图15和16的描述，不再赘述。
这样，第一器件的栅堆叠可以嵌入到第一沟道层1005相对于遮蔽层1053的凹入中，并自对准于第一沟道层1005，从而与第一沟道层1005的整个高度 相交迭。另外，在第二沟道层1009相对于遮蔽层1053的凹入中，也嵌入了第一栅介质层1029和第一栅导体层1031的叠层。
接下来，可以对栅堆叠的形状进行调整，以便于后继互连制作。例如，可以在图29所示的结构上形成光刻胶(未示出)。该光刻胶例如通过光刻构图为覆盖栅堆叠露于凹入之外的一部分(在该示例中，图中左半部)，且露出栅堆叠露于凹入之外的另一部分(在该示例中，图中右半边)。然后，可以光刻胶为掩模，对第一栅导体层1031进行选择性刻蚀如RIE。这样，第一栅导体层1031除了留于凹入之内的部分之外，被光刻胶遮挡的部分得以保留，如图30所示，之后可以去除光刻胶。随后，可以通过该部分来实现到栅堆叠的电连接。
继续在图30中，淀积氧化物并对其回蚀，以形成第二隔离层1033。在回蚀之前，可以对淀积的氧化物进行平坦化处理。在此，隔离层1033的顶面可以位于第二源/漏层1007的顶面与底面之间，这有助于形成与第一器件的源/漏区S/D-b1以及第二器件的源/漏区S/D-t2相邻接的电接触层。
接着，如图31所示，可以去除暴露在外的高K栅介质层1029，并且可以至少部分地去除遮蔽层1053，以至少部分地露出第二源/漏层1007和第三源/漏层1011。在此结构上，如图32，可以通过淀积导电材料并对其回蚀，来形成电接触层1037。例如，电接触层1037可以包括金属如W。电接触层1037的顶面可以低于第二源/漏层1007的顶面。优选地，在淀积导电材料之前，可以先淀积一层阻挡层(图中未示出)。对此，可以参照以上结合图18和19的描述，不再赘述。
接下来，可以对电接触层1037的形状进行调整，以便于后继互连制作。例如，如图33所示，可以利用光刻，将电接触层1037构图为其一部分(在该示例中，图中右侧部分)相对于其余部分横向伸出。随后，可以通过该伸出部分来实现到电接触层1037的电连接。优选地，电接触层1037环绕第二源/漏层1007，这有助于减小接触电阻。
同样地，还可以进一步淀积阻挡层(图中未示出)。这样，此次淀积的阻挡层和与之前淀积的阻挡层可以将电接触层1037包封在内，以阻挡其扩散。此外，还可以形成第三隔离层(图中未示出)，通过光刻去除被第三隔离层暴露在外的阻挡层，使得阻挡层基本上只在电接触层1037的外周上延伸(稍有 超出，以确保余量)以便包封电接触层1037。对此，可以参照以上结合图20和22的描述，不再赘述。
继续在图33中，可以类似地形成第二器件的栅堆叠。例如，继续淀积氧化物，并对其回蚀，以形成第四隔离层1043。在回蚀之前，可以对淀积的氧化物进行平坦化处理如CMP，使得隔离层1043的顶面可以位于第二沟道层1009的顶面与底面之间，这有助于形成自对准的栅堆叠，且隔离层1043填充第三源/漏层1011相对于硬掩模层的凹入从而形成另一遮蔽层1054。遮蔽层1054与相应的源/漏层实质上共面，有助于随后形成自对准于沟道层的栅堆叠。
之后，如图34所示，可以去除第一栅介质层1029和第一栅导体层1031，以释放第二沟道层1009相对于遮蔽层1054的凹入中的空间，并在该空间中形成第二器件的栅堆叠，包括第二栅介质层1045和第二栅导体层1047，回蚀栅导体层1047，使栅导体层1047在凹入之外的部分的顶面低于第二沟道层1009的顶面。同样地，可以对可以对栅堆叠的形状进行调整，以便于后继互连制作。这里需要指出的是，第二栅介质层1045与第一栅介质层1029可以相同也可以不同，当第二栅介质层1045与第一栅介质层1029相同时，图34也可以保留第一栅介质层1029而去除第一栅导体层1031，并在释放的凹入空间中形成第二栅导体层1047，第二栅导体层1047与第一栅导体层1031可以相同也可以不同。
这样，第二器件的栅堆叠可以嵌入到第二沟道层1009相对于遮蔽层1054的凹入中，自对准于第二沟道层1009，从而与第二沟道层1009的整个高度相交迭。
然后，可以如图35所示，在图34所示的结构上形成层间电介质层1049。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1049。在层间电介质层1049中，可以形成到第一器件和第二器件各自的源/漏区以及栅导体层的电接触部1051-1至1051-5。这些接触部可以通过在层间电介质层1049以及隔离层中刻蚀孔洞，并在其中填充导电材料如金属来形成。由于栅导体层1031、1047以及电接触层延1037伸超出有源区外周，从而可以容易地形成相应的接触部1051-2至1051-4。另外，由于衬底1001中的掺杂区延伸超出有源区之外，从而可以容易地形成相应接触部1051-5。
根据上述实施例，如图25、35所示，半导体器件可以包括沿竖直方向叠置的第一器件和第二器件。第一器件包括沿竖直方向叠置的第一源/漏层1003、第一沟道层1005和第二源/漏层1007(或其下部1007-1)。第一沟道层1005的侧壁中至少部分沿第一晶体晶面或晶面族延伸，栅堆叠(1029/1031)绕第一沟道层1005的外周形成。同样地，第二器件包括沿竖直方向叠置的第二源/漏层1007(或其上部1007-2)、第二沟道层1009和第三源/漏层1011。第二沟道层1009的侧壁中至少部分沿第二晶体晶面或晶面族延伸，栅堆叠(1045/1047)绕第一沟道层1005的外周形成。
在以上实施例中，在限定半导体器件的有源区的过程中，利用光刻胶进行构图。但是本公开不限于此，例如还可以使用图案转移技术等。
图36至39示出示出了根据本公开实施例对硬掩膜层进行构图的流程的示意图。
在本实施例中，仍然沿用图1所示的半导体叠层。如图1所示，在这些半导体层上，还可以形成硬掩模层1013，硬掩模层1013可以包括依次叠置的第一硬掩模层1013-1、第二硬掩模层1013-2和第三硬掩模层1013-3。在其他实施例中，硬掩膜1013也可以以其他方式设置。
如图36所示，在硬掩膜层1013上形成第一牺牲层1055。考虑刻蚀选择性，例如第一牺牲层1055可以包括非晶硅(α-Si)。第一牺牲层1055包括沿第一方向延伸的第一侧壁(图中所示为左侧的侧壁)。在此，第一方向沿晶体晶面或晶面族例如(100)晶面或{100}晶面族的方向延伸。通过侧墙形成工艺，可以在第一牺牲层1055的第一侧壁上形成沿第一方向延伸的第一侧墙1056。考虑到刻蚀选择性，例如第一侧墙1056可以包括氮化物。在形成第一侧墙1056之后，可以去除第一牺牲层1055。然后，可以将第一侧墙1056的图案转移到硬掩膜层1013中，并去除第一侧墙。具体地，如图37(a)-37(c)(图37(a)是去除第一侧墙1056之前的正视截面图，图37(b)是去除第一侧墙1056之后的正视截面图，图37(c)是俯视图，其中的AA′线示出了截面的截取位置)所示，首先可以将第一侧墙1056的图案转移到硬掩膜层1013的第三硬掩模层1013-3中。例如，这可以通过对第三硬掩模层1013-3进行选择性刻蚀如RIE来进行。RIE可以停止于第二硬掩模层1013-2。随后，可以通过选择性刻蚀，去除第一 侧墙1056(当然，也可以保留1056)。如图37(c)所示，第三硬掩模层1013-3呈沿第一方向延伸的条状。
进一步，在硬掩膜层1013上形成第二牺牲层，第二牺牲层包括沿第二方向延伸的第二侧壁。在此，第二方向也可以沿晶体晶面或晶面族例如(100)晶面或{100}晶面族的方向延伸。也即，第二方向可以与第一方向沿着相同的晶面族方向延伸。第二方向可以与第一方向不同，例如与第一方向交叉(例如，垂直)，以便随后限定闭合图案。在第二侧壁上可以形成沿第二方向延伸的第二侧墙。该第二侧墙与第一侧墙的图案相交，从而在它们相交之处限定了所需图案。第二牺牲层和第二侧墙的形成可以与第一牺牲层和第一侧墙的形成相同，仅延伸方向不同，在此不再赘述。然后，可以将第二侧墙的图案转移到硬掩膜层1013的第三硬掩模层1013-3中，并去除第二侧墙。于是，第三硬掩模层1013-3在俯视图中呈矩形，如图38所示。在该示例中，第三硬掩模层1013-3为侧壁沿(100)晶面延伸的方柱状。可以此第三硬掩模层1013-3为掩膜来限定n型器件的有源区。
类似地，限定p型器件的有源区时，也可以分别形成沿(110)晶面或{110}晶面族方向延伸、且彼此相交(例如，垂直)的两个侧墙，并通过这两个侧墙来限定有源区的图案。于是，第三硬掩模层1013-3可以被构图为侧壁沿(110)晶面会{110}晶面族延伸延伸的方柱状，其俯视图如图39所示。
通过图案转移技术，可以至少部分地克服光刻技术的限制，图案尺寸可以更加精确。
在该示例中，示出了两个器件彼此叠置。但是，本公开不限于此，可以有更多器件在竖直方向上彼此叠置。
根据本公开实施例的半导体设置可以应用于各种电子设备。例如，通过集成多个这样的半导体设置以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体设置的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方 法可以包括上述制造半导体设置的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (39)

  1. 一种半导体器件，包括：
    衬底；
    依次叠置在衬底上的第一器件和第二器件，第一器件和第二器件各自均包括：从下至上依次叠置的第一源/漏层、沟道层和第二源/漏层，以及绕沟道层的至少部分外周形成的栅堆叠，
    第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸。
  2. 根据权利要求1所述的半导体器件，其中，
    第一器件的沟道层是半导体的单晶材料和/或第二器件的沟道层是半导体的单晶材料。
  3. 根据权利要求2所述的半导体器件，其中，
    第一器件为n型器件，其沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族，而第二器件为n型器件，其沟道层的侧壁至少部分沿(100)晶面或{100}晶面族延伸。
  4. 根据权利要求1所述的半导体器件，其中，
    第一器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，而第二器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
  5. 根据权利要求4所述的半导体器件，其中，所述第一器件的第一源/漏 层指向第二源/漏层的方向沿[100]晶向或沿<100>晶向族，和/或所述第二器件的第一源/漏层指向第二源/漏层的方向沿[100]晶向或沿<100>晶向族。
  6. 根据权利要求1所述的半导体器件，其中，第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶向与第二器件的沟道层的晶向相同。
  7. 根据权利要求1所述的半导体器件，其中，第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶体结构与第二器件的沟道层的晶体结构相同。
  8. 根据权利要求1所述的半导体器件，其中：
    第一器件的沟道层的相邻侧壁所形成的角为圆角；并且/或者
    第二器件的沟道层的相邻侧壁所形成的角为圆角。
  9. 根据权利要求1所述的半导体器件，其中：
    在俯视图中，第二器件的第一源/漏层、沟道层和第二源/漏层处于第一器件的第二源/漏层的范围之内。
  10. 根据权利要求1所述的半导体器件，其中，第一器件的第二源/漏层与第二器件的第一源/漏层彼此邻接。
  11. 根据权利要求10所述的半导体器件，其中，第一器件的第二源/漏层与第二器件的第一源/漏层是一体的。
  12. 根据权利要求10或11所述的半导体器件，还包括：
    与第一器件的第二源/漏层及第二器件的第一源/漏层二者电连接的电接触层。
  13. 根据权利要求12所述的半导体器件，其中，电接触层环绕第一器件的第二源/漏层及第二器件的第一源/漏层的外周。
  14. 根据权利要求12所述的半导体器件，其中：
    第一器件的栅堆叠包括从沟道层的侧壁横向向外延伸的横向延伸部分；
    电接触层包括相对于其余部分在横向上伸出的横向延伸部分；
    第二器件的栅堆叠包括从沟道层的侧壁横向向外延伸的横向延伸部分；
    第一器件的栅堆叠的横向延伸部分、电接触层的横向延伸部分以及第二器件的栅堆叠的横向延伸部分中的至少一些向着不同的方向横向延伸。
  15. 根据权利要求14所述的半导体器件，其中，如果第一半导体器件的栅堆叠的横向延伸部分、电接触层的横向延伸部分以及第二半导体器件的栅堆叠的横向延伸部分中的至少一些在竖直方向上交迭，则在这些交迭的横向延伸部分中，位于下方的横向延伸部分延伸超出位于上方的横向延伸部分。
  16. 根据权利要求11所述的半导体器件，其中：
    第一器件的第一源/漏层是在衬底上外延生长的半导体层，第一器件的沟道层是在第一器件的第一源/漏层上外延生长的半导体层；
    第一器件的第二源/漏层和第二器件的第一源/漏层二者是在第一器件的沟道层上外延生长的半导体层；
    第二器件的沟道层是在第二器件的第一源/漏层上外延生长的半导体层，且第二器件的第二源/漏层是在第二器件的沟道层上外延生长的半导体层。
  17. 根据权利要求1所述的半导体器件，其中，第一器件的栅堆叠和第二器件的栅堆叠具有不同的叠层配置。
  18. 一种制造半导体器件的方法，包括：
    在衬底上从下至上依次叠置第一器件的第一源/漏层、沟道层和第二源/漏层以及第二器件的第一源/漏层、沟道层和第二源/漏层；
    在第一器件的第一源/漏层、沟道层和第二源/漏层以及第二半导体器件的第一源/漏层、沟道层和第二源/漏层中限定相应器件的有源区，使得第一器件的沟道层的侧壁与第二器件的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸；以及
    分别绕第一器件和第二器件各自的沟道层的至少部分外周形成第一器件和第二器件各自的栅堆叠。
  19. 根据权利要求18所述的方法，其中，所述第一器件的第一源/漏层指向第二源/漏层的方向是沿[100]晶向或沿<100>晶向族，和/或所述第二器件的第一源/漏层指向第二源/漏层的方向是沿[100]晶向或沿<100>晶向族。
  20. 根据权利要求18所述的方法，其中，
    第一器件的沟道层是半导体的单晶材料和/或第二器件的沟道层是半导体的单晶材料。
  21. 根据权利要求20所述的方法，其中，
    第一器件为n型器件，其沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族，而第二器件为n型器件，其沟道层的侧壁至少部分沿(100)晶面或{100}晶面族延伸。
  22. 根据权利要求18所述的方法，其中，
    第一器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，而第二器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
  23. 根据权利要求18所述的方法，其中，第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶向与第二器件的沟道层的晶向相同。
  24. 根据权利要求18所述的方法，其中，第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶体结构与第二器件的沟道层的晶体结构相同。
  25. 根据权利要求18所述的方法，其中，限定半导体器件的有源区包括：
    依次对第二器件的第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀以形成侧壁沿第一晶体晶面或晶面族延伸的图案，并通过各向同性刻蚀使得沟道层的外周相对于第一、第二源/漏层的外周凹入；
    在第二器件的沟道层相对于第一、第二源/漏层的凹入中形成第二器件的牺牲栅；
    依次对第一器件的第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀以形成侧壁沿第二晶体晶面或晶面族延伸的图案，并通过各向同性刻蚀使得沟道 层的外周相对于第一、第二源/漏层的外周凹入；以及
    在第一器件的沟道层相对于第一、第二源/漏层的凹入中形成第一器件的牺牲栅。
  26. 根据权利要求25所述的方法，其中，限定半导体器件的有源区还包括：
    在对第二器件的沟道层进行各向同性刻蚀后，将第二器件的沟道层的相邻侧壁形成的尖角处理为圆角；并且/或者
    在对第一器件的沟道层进行各向同性刻蚀后，将第一器件的沟道层的相邻侧壁形成的尖角处理为圆角。
  27. 根据权利要求25所述的方法，其中，在形成第二器件的牺牲栅之后且在限定第一器件的有源区之前，该方法还包括：在第二器件的第一、第二源/漏层的表面上形成保护层。
  28. 根据权利要求25所述的方法，其中，在形成第二器件的牺牲栅之后且在限定第一器件的有源区之前，该方法还包括：
    在第二器件的第一源/漏层和第二源/漏层的表面上形成掺杂剂源层；以及
    使掺杂剂源层中的掺杂剂进入第二器件的第一、第二源/漏层中。
  29. 根据权利要求25或28所述的方法，其中，在形成第一器件的牺牲栅之后，该方法还包括：
    在第一器件的第一源/漏层和第二源/漏层的表面上形成另一掺杂剂源层；以及
    使另一掺杂剂源层中的掺杂剂进入第一器件的第一、第二源/漏层中。
  30. 根据权利要求25所述的方法，其中，在形成第一器件的牺牲栅之后，该方法还包括：
    在第二器件的第一、第二源/漏层的表面上形成硅化物；和/或
    在第一器件的第一、第二源/漏层的表面上形成硅化物。
  31. 根据权利要求25所述的方法，其中：
    形成第一器件的栅堆叠包括：
    在衬底上有源区的周围形成第一隔离层，其中第一隔离层的顶面处于第一器件的沟道层和顶面与底面之间；
    去除第一器件的牺牲栅，以释放第一器件的沟道层相对于第一、第二源/漏层的凹入中的空间；
    在第一隔离层上依次形成第一器件的栅介质层和栅导体层；以及
    回蚀栅导体层，使栅导体层在所述凹入之外的部分的顶面低于第一器件的沟道层的顶面；
    该方法还包括：
    在第一隔离层上形成第二隔离层，其中第二隔离层的顶面处于第一器件的第二源/漏层的顶面与底面之间；
    在第二隔离层上形成与第一器件的第二源/漏层及第二器件的第一源/漏层电连接的电接触层，其中电接触层的顶面位于第二器件的第一源/漏层的顶面与底面之间；以及
    形成第二器件的栅堆叠包括：
    在第二隔离层上形成第三隔离层，其中第三隔离层的顶面处于第二器件的沟道层的顶面与底面之间；
    去除第二器件的牺牲栅，以释放第二器件的沟道层相对于第一、第二源/漏层的凹入中的空间；
    在第三隔离层上依次形成第二器件的栅介质层和栅导体层；以及
    回蚀栅导体层，使栅导体层在所述凹入之外的部分的顶面低于第二器件的沟道层的顶面。
  32. 根据权利要求25所述的方法，其中，限定半导体器件的有源区还包括：
    在形成第二器件的牺牲栅后，对第二器件的第一、第二源/漏层进行细化处理，使得第二器件的第一、第二源/漏层的横向尺寸减小；并且/或者
    在形成第一器件的牺牲栅后，对第一器件的第一、第二源/漏层进行细化处理，使得第一器件的第一、第二源/漏层的横向尺寸减小。
  33. 根据权利要求32所述的方法，还包括：
    在第二器件的经过细化处理的第一、第二源/漏层的表面上形成硅化物；和/或
    在第一器件的经过细化处理的第一、第二源/漏层的表面上形成硅化物。
  34. 根据权利要求32所述的方法，其中：
    该方法还包括：在第一器件的第一源/漏层、第二源/漏层以及第二器件的第一源/漏层、第二源/漏层的侧壁中相对于第二器件的牺牲栅凹入的侧壁上形成遮蔽层，该遮蔽层的侧壁与第二器件的牺牲栅的侧壁实质上共面；
    形成第一器件的栅堆叠包括：
    在衬底上有源区的周围形成第一隔离层，其中第一隔离层的顶面处于第一器件的沟道层和顶面与底面之间；
    去除第一器件的牺牲栅，以释放第一器件的沟道层相对于遮蔽层的凹入中的空间；
    在第一隔离层上依次形成第一器件的栅介质层和栅导体层；以及
    回蚀栅导体层，使栅导体层在所述凹入之外的部分的顶面低于第一器件的沟道层的顶面；
    该方法还包括：
    在第一隔离层上形成第二隔离层，其中第二隔离层的顶面处于第一器件的第二源/漏层的顶面与底面之间；
    至少部分地去除遮蔽层，以至少部分地露出第一器件的第二源/漏层和/或第二器件的第一源/漏层；
    在第二隔离层上形成与第一器件的第二源/漏层及第二器件的第一源/漏层电连接的电接触层，其中电接触层的顶面位于第二器件的第一源/漏层的顶面与底面之间；以及
    形成第二器件的栅堆叠包括：
    在第二隔离层上形成第三隔离层，其中第三隔离层的顶面处于第二器件的沟道层的顶面与底面之间，第三隔离层填充第二器件的第二源/漏层相对于第二器件的牺牲栅的凹入从而形成另一遮蔽层；
    去除第二器件的牺牲栅，以释放第二器件的沟道层相对于所述另一遮蔽层的凹入中的空间；
    在第三隔离层上依次形成第二器件的栅介质层和栅导体层；以及
    回蚀栅导体层，使栅导体层在所述凹入之外的部分的顶面低于第二器件的沟道层的顶面。
  35. 根据权利要求31或34所述的方法，还包括：
    在形成第一器件的栅堆叠的操作中，将第一器件的栅导体层构图为其一部分从相应凹入横向向外延伸；
    在形成电接触层的操作中，将电接触层构图为其一部分相对于其余部分在横向上伸出；
    在形成第二器件的栅堆叠的操作中，将第二器件的栅导体构图为其一部分从相应凹入横向向外延伸；
    其中，第一器件的栅堆叠的向外延伸的部分、电接触层伸出的部分、以及第二器件的栅堆叠的向外延伸的部分中的至少一些向着不同的方向横向延伸，且如果这些部分中的至少一些在竖直方向上交迭，则在这些交迭的部分中，位于下方的部分延伸超出位于上方的部分。
  36. 根据权利要求25所述的方法，其中，限定有源区包括：
    形成硬掩膜层；
    在硬掩膜层上形成第一牺牲层，第一牺牲层包括沿第一方向延伸的第一侧壁；
    在第一侧壁上形成沿第一方向延伸的第一侧墙，并去除第一牺牲层；
    将第一侧墙的图案转移到硬掩膜层中，并去除第一侧墙；
    在硬掩膜层上形成第二牺牲层，第二牺牲层包括沿与第一方向垂直的第二方向延伸的第二侧壁；
    在第二侧壁上形成沿第二方向延伸的第二侧墙，该第二侧墙与第一侧墙的图案相交；
    将第二侧墙的图案转移到硬掩膜层中，并去除第二侧墙；
    以硬掩膜层为掩膜来限定有源区。
  37. 一种电子设备，包括至少部分地由如权利要求1至17中任一项所述的半导体器件形成的集成电路。
  38. 根据权利要求37所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
  39. 根据权利要求37所述的电子设备，该电子设备包括以下至少一个：智能电话、计算机、平板电脑、可穿戴设备、和/或移动电源。
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CN117135923B (zh) * 2023-10-23 2024-01-26 北京超弦存储器研究院 半导体结构及其制备方法、电子设备

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