WO2021248973A1 - 带导电层的竖直型半导体器件及其制造方法及电子设备 - Google Patents

带导电层的竖直型半导体器件及其制造方法及电子设备 Download PDF

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WO2021248973A1
WO2021248973A1 PCT/CN2021/082329 CN2021082329W WO2021248973A1 WO 2021248973 A1 WO2021248973 A1 WO 2021248973A1 CN 2021082329 W CN2021082329 W CN 2021082329W WO 2021248973 A1 WO2021248973 A1 WO 2021248973A1
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layer
source
drain
semiconductor device
metallic
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PCT/CN2021/082329
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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    • B82—NANOTECHNOLOGY
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Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to a vertical semiconductor device with a conductive layer, especially a metallic layer, a manufacturing method thereof, and electronic equipment including such a semiconductor device.
  • the source, gate, and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the area occupied by the horizontal device is not easy to be further reduced or the manufacturing cost is not easy to be further reduced. Unlike this, in a vertical device, the source, gate, and drain are arranged in a direction substantially perpendicular to the surface of the substrate. Therefore, compared to horizontal devices, vertical devices are easier to shrink or to reduce manufacturing costs.
  • MOSFET metal oxide semiconductor field effect transistor
  • a vertical device it is desirable to use a single crystal material for the channel, because compared to a polycrystalline material, the channel resistance can be reduced and therefore a plurality of vertical devices can be stacked to achieve high integration density.
  • the gate length on the one hand, it is difficult to control the gate length, on the other hand, it is difficult to provide low resistance in the source/drain region.
  • the purpose of the present disclosure is at least partly to provide a vertical semiconductor device having a conductive layer, particularly a metallic layer, to provide low resistance in the source/drain region, a manufacturing method thereof, and an electronic device including such a semiconductor device. equipment.
  • a semiconductor device including: a substrate; a first metallic layer, a channel layer, and a second metallic layer sequentially disposed on the substrate; and at least part of the channel layer In the gate stack formed on the outer periphery, the first metallic layer, the second metallic layer and the channel layer have a single crystal structure.
  • a semiconductor device including: a substrate; a first conductive layer, a first source/drain layer, a channel layer, a second source/drain layer, and A second conductive layer; and a gate stack formed around at least part of the outer periphery of the channel layer, wherein the first conductive layer and the second conductive layer, the first source/drain layer and the second source/drain layer, and the channel layer are single ⁇ Crystal structure.
  • the conductive layer may include a doped semiconductor material.
  • a method of manufacturing a semiconductor device including: sequentially forming a first metallic layer, a channel layer, and a second metallic layer on a substrate; The channel layer and the second metallic layer are patterned into a predetermined shape; and a gate stack is formed around at least part of the outer circumference of the channel layer.
  • a method of manufacturing a semiconductor device including: sequentially forming a first conductive layer, a first source/drain layer, a channel layer, a second source/drain layer, and a first conductive layer on a substrate. Two conductive layers; patterning the first conductive layer, the first source/drain layer, the channel layer, the second source/drain layer, and the second conductive layer into a predetermined shape; and forming a gate stack around at least part of the periphery of the channel layer.
  • an electronic device including an integrated circuit formed of the above-mentioned semiconductor device.
  • the gate stack is formed around at least a part of the periphery of the channel layer and the channel may be formed in the channel layer, so that the gate length is substantially determined by the thickness of the channel layer.
  • the channel layer can be formed by epitaxial growth, for example, so that its thickness can be well controlled. Therefore, the gate length can be well controlled.
  • conductive layers, especially metallic layers, are provided on both sides of the channel layer, which may be part of the source/drain region or the source/drain region, thereby reducing the source/drain resistance.
  • FIG. 1(a) to 8(c) show schematic diagrams of a process of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • 9 to 12 show schematic diagrams of a process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element may be located "under” the other layer/element when the orientation is reversed.
  • a vertical semiconductor device may include a first conductive layer, a channel layer, and a second conductive layer sequentially stacked on a substrate.
  • the layers may be adjacent to each other, of course, there may also be other semiconductor layers in between, such as a leakage suppression layer and an on-state current enhancement layer (a semiconductor layer with a band gap larger or smaller than the adjacent layer).
  • the first conductive layer and the second conductive layer themselves may respectively form source/drain regions of the device (may be referred to as “first source/drain regions” and “second source/drain regions”, respectively).
  • the first source/drain layer may be between the first conductive layer and the channel layer
  • the second source/drain layer may be between the second conductive layer and the channel layer.
  • the first source/drain region and the second source/drain region may also be formed in the first source/drain layer and the second source/drain layer.
  • the channel region of the device can be formed in the channel layer.
  • the first conductive layer and the second conductive layer may be layers of highly conductive materials, such as metallic layers or doped semiconductor layers.
  • the first conductive layer and the second conductive layer may respectively form ohmic contacts with the first source/drain layer and the second source/drain layer to reduce resistance.
  • the first conductive layer and the second conductive layer, especially the metallic layer can form a Schottky junction with the channel layer, and thus can form a Schottky junction. Turki devices.
  • Each of the first conductive layer, the first source/drain layer, the channel layer, the second source/drain layer, and the second conductive layer may be a single crystal material, which may have high carrier mobility and low leakage current, And therefore, the device performance can be improved.
  • These layers can be formed by growth such as epitaxial growth. Due to the epitaxial growth, at least a part of adjacent layers may have a clear crystal interface, and at least a part or all of at least some of the interfaces may be coherent interfaces.
  • the gate stack may be formed around at least a part of the outer periphery of the channel layer, and may control the on/off of the channel region.
  • the gate stack particularly its end close to the channel layer, may be self-aligned to the channel layer.
  • the outer peripheral sidewall of the channel layer may be relatively inwardly recessed.
  • the end of the formed gate stack can be embedded in the relative recess of the channel layer, reducing the overlap with the source/drain region, and helping to reduce the parasitic capacitance between the gate and the source/drain. Therefore, the gate length can be determined by the thickness of the channel layer itself, instead of relying on the etching timing as in the conventional technology.
  • the channel layer can be formed by epitaxial growth, for example, so that its thickness can be well controlled. Therefore, the gate length can be well controlled.
  • Such a semiconductor device can be manufactured as follows, for example.
  • the first conductive layer, the channel layer, and the second conductive layer may be sequentially formed on the substrate.
  • a first source/drain layer may be formed between the first conductive layer and the channel layer
  • a second source/drain layer may be formed between the channel layer and the second conductive layer.
  • each layer can be formed by epitaxial growth on the substrate, and each layer can be kept in a single crystal system. During growth, the thickness of the grown layers, especially the channel layer, can be controlled.
  • an active region may be defined therein. For example, they can be selectively etched into a desired shape in sequence. Generally, the active region may have a columnar shape (for example, a cylindrical shape).
  • the etching of the first conductive layer may only target the upper part of the first conductive layer, so that the lower part of the first conductive layer may extend beyond the upper part of the first conductive layer. Peripheral. Then, a gate stack may be formed around the outer periphery of the channel layer.
  • the outer periphery of the channel layer (and optionally, the outer periphery of the first source/drain layer and the second source/drain layer) may be recessed inwardly with respect to the outer periphery of the first and second conductive layers, so as to define the accommodation Grid stack space. For example, this can be achieved by selective etching. In this case, the gate stack can be embedded in the recess.
  • the present disclosure can be presented in various forms, some examples of which will be described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this kind of etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.
  • FIG. 1(a) to 8(c) show schematic diagrams of a process of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • a well region can be formed by, for example, ion implantation or diffusion doping.
  • a p-type device is to be formed, an n-type well region can be formed; and if an n-type device is to be formed, a p-type well region can be formed.
  • the well regions of different conductivity types can be formed by impurities of corresponding conductivity types (p-type impurities such as B or BF2, etc., n-type impurities such as P or As, etc.). Annealing can be performed to activate the implanted impurities.
  • the doping concentration in the well region may be, for example, about 1E17-1E19 cm ⁇ 3 .
  • a material layer for arranging the active region can be formed (all of these material layers can be formed as a single crystal structure to ensure that the channel layer in the active region can have a single crystal structure to reduce the channel structure. resistance).
  • a leakage suppression layer may be formed before forming the material layer for the active region.
  • the leakage suppression layer may include a semiconductor material such as Si, as shown at 1003 in FIG. 1(a).
  • the leakage suppression layer 1003 of semiconductor material may be formed by, for example, epitaxial growth, and may be doped to a conductivity type opposite to the well region by ion implantation or in-situ doping during epitaxial growth.
  • the leakage suppression layer 1003 and the well region can form a pn junction.
  • the pn junction leakage is relatively small compared to the Schottky junction leakage that will be formed later.
  • the leakage suppression layer may include an insulating material, as shown at 1003' in FIG. 1(c).
  • the leakage suppression layer 1003' of an insulating material may be formed by growth such as chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the difference between the lattice constant of the leakage suppression layer 1003' and the lattice constant of the substrate 1001 may be within about +/-2%.
  • the leakage suppression layer 1003' may include SrTiO 3 , (LaY) 2 O 3 , LaAlO 3 or LaLuO 3 , but the present disclosure is not limited thereto.
  • a first conductive layer 1005, a first source/drain layer 1007, a channel layer 1009, a second source/drain layer 1011, and a second conductive layer 1013 may be sequentially formed.
  • the first conductive layer 1005 and the second conductive layer 1013 may have high conductivity.
  • the first conductive layer 1005 and the second conductive layer 1013 may include metallic materials such as NiSi 2 or CoSi 2 and may be formed by growth such as CVD.
  • the first conductive layer 1005 and the second conductive layer 1013 may also include semiconductor materials, may be formed by, for example, epitaxial growth, and may be doped (for example, doped in-situ during growth) to have high conductivity, such as doping.
  • the first conductive layer 1005 and the second conductive layer 1013 may include the same material, of course, may also include different materials.
  • the lattice constants of the first conductive layer 1005 and the second conductive layer 1013 may differ from the lattice constant of the substrate 1001 within about +/-2%.
  • the first conductive layer 1005 and the second conductive layer 1013 may form a source/drain region or a part of the source/drain region (for example, used as a contact part of the source/drain region and the interconnection), and the thickness is, for example, about 5nm-50nm .
  • the first source/drain layer 1007, the channel layer 1009, and the second source/drain layer 1011 may be semiconductor material layers formed by, for example, epitaxial growth.
  • the first source/drain layer 1007 and the second source/drain layer 1011 can be used to form (a part of) the source/drain regions, so they can be doped (for example, doped in-situ during growth) to match the device that needs to be formed
  • the conductivity type corresponding to the type of is, for example, p-type devices are doped to be p-type, and n-type devices are doped to be n-type, the doping concentration is about 1E19-1E21cm-3, and the thickness may be, for example, about 2nm-5nm.
  • the first source/drain layer 1007 and the second source/drain layer 1011 are thinner than the first conductive layer 1005 and the second conductive layer 1013, so that most of the source/drain regions formed later have high conductivity, To reduce resistance.
  • the first source/drain layer 1007 and the second source/drain layer 1011 may include the same material, but the present disclosure is not limited thereto.
  • the trench bottom layer 1009 may be unintentionally doped, or lightly doped (for example, doped in situ during growth) to adjust the threshold voltage of the device, and the thickness may be, for example, about 10 nm-200 nm.
  • the first source/drain layer 1007, the channel layer 1009, and the second source/drain layer 1011 may include various suitable semiconductor materials, such as Si, SiGe, Ge, group III-V compound semiconductors such as GaAs, and the like.
  • the lattice constant of each of the first source/drain layer 1007, the channel layer 1009, and the second source/drain layer 1011 may differ from the lattice constant of the substrate 1001 within about +/-2%.
  • the first source/drain layer 1007, the channel layer 1009, and the second source/drain layer 1011 may include the same material such as Si.
  • adjacent layers of the first source/drain layer 1007, the channel layer 1009, and the second source/drain layer 1011 may have etch selectivity, such as the first source/drain layer 1007 and the second source/drain layer 1007.
  • the source/drain layer 1011 may include Si
  • the channel layer 1009 may include SiGe.
  • a highly doped semiconductor layer (1007, 1011) and a conductive layer (1005, 1013) are respectively provided to Form source/drain regions.
  • An ohmic contact can be formed between the highly doped semiconductor layer (1007, 1011) and the conductive layer (1005, 1013) to reduce resistance.
  • the present disclosure is not limited to this.
  • the highly doped semiconductor layer can be omitted, and conductive layers 1005 and 1013 are directly provided on the upper and lower sides of the channel layer 1009.
  • the conductive layers 1005 and 1013 include metallic layers, they can form a Schottky junction with the channel layer 1009, and thus can form a Schottky device together with the channel layer 1009.
  • These layers formed on the substrate 1001 are respectively grown from the lower layer to maintain the single crystal system. There may be a crystal interface and/or a doping concentration interface between adjacent layers. In addition, at least part of the interface between at least some adjacent layers may be a coherent interface.
  • Figures 1(a), 1(b) and 1(c) respectively show different situations, they can be combined in different ways.
  • the leakage suppression layer 1003 in FIG. 1(b) may be formed as an insulating material as shown in 1003' in FIG. 1(c), or the source/drain layers 1007 and 1011 may also be omitted in FIG. 1(c).
  • the situation shown in Figure 1(a) is mainly used as an example for description. However, these descriptions can also be applied to other situations such as those shown in Figures 1(b) and 1(c).
  • the active area of the device can be defined. For example, this can be done as follows. Specifically, as shown in Figures 2(a) and 2(b) ( Figure 2(a) is a cross-sectional view, Figure 2(b) is a top view, in which the AA' line shows the cut position of the cross section), it can be formed Photoresist (not shown), the photoresist is patterned into the desired shape (in this example, roughly circular) by photolithography (exposure and development), and the patterned photoresist is used as a mask, in turn
  • the second conductive layer 1013, the second source/drain layer 1011, the channel layer 1009, the first source/drain layer 1007, and the first conductive layer 1005 are selectively etched such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • the etching may be performed into the first conductive layer 1005, but not to the bottom surface of the first conductive layer 1005. This is to facilitate the contact portion formed later to easily land on the first conductive layer 1005.
  • the upper portions of the second conductive layer 1013, the second source/drain layer 1011, the channel layer 1009, the first source/drain layer 1007, and the first conductive layer 1005 form a columnar shape (in this example, a columnar shape) , They define the active area.
  • RIE may be performed in a direction substantially perpendicular to the surface of the substrate, so that the columnar shape is also substantially perpendicular to the surface of the substrate. After that, the photoresist can be removed.
  • an active region having a substantially circular shape will result in the formation of nanowire devices.
  • the present disclosure is not limited to this.
  • the active region may be patterned into a rectangle (length, for example, about 10 nm-10 ⁇ m to provide sufficient device current, and width, for example, about 10 nm-100 nm to achieve good control of the short channel effect), so that nanosheet devices can be formed.
  • the shape of the active region is not limited to this.
  • the outer peripheral sidewall of the channel layer 1009 may be relatively recessed (in this example, recessed in a lateral direction substantially parallel to the substrate surface).
  • the channel layer 1009 may be selectively etched relative to the first conductive layer 1005 and the second conductive layer 1013, for example, by wet etching using a TMAH solution.
  • the etching of the channel layer 1009 may be performed by atomic layer etching (ALE). Around the outer circumference of the channel layer 1009, the etching depth may be approximately the same.
  • the channel layer 1009 can be kept substantially aligned with the second conductive layer 1013, and the shape can be kept substantially the same (but reduced).
  • the first source/drain layer 1007 and the second source/drain layer 1011 also include Si, so they can also be etched, and the etched shape can be approximately the same as the channel layer 1009 and approximately center-aligned .
  • a gate stack will be formed subsequently.
  • a material layer can be filled in the recess to occupy the space of the gate stack (therefore, This material layer can be called a "sacrificial gate"). For example, this can be done by depositing nitride and then etching back the deposited nitride such as RIE.
  • RIE can be performed in the vertical direction, so that the nitride can only remain in the recess to form a sacrificial gate 1015, as shown in FIG. 4.
  • the sacrificial gate 1015 can substantially fill the above-mentioned recess.
  • An isolation layer can be formed around the active region to achieve electrical isolation.
  • an oxide may be deposited on the structure shown in FIG. 4 and etched back to form an isolation layer 1017. Before etch back, the deposited oxide can be planarized, such as chemical mechanical polishing (CMP) or sputtering.
  • CMP chemical mechanical polishing
  • the top surface of the isolation layer 1017 may be between the top surface and the bottom surface of the channel layer 1009.
  • the sacrificial gate 1015 can be removed by selective etching to release the space in the recess.
  • a gate stack can be formed in the released recess.
  • the gate dielectric layer 1019 and the gate conductor layer 1021 may be deposited sequentially, and the deposited gate conductor layer 1021 may be etched back so that the top surface of the part outside the recess is not higher than and preferably lower than The top surface of the channel layer 1009.
  • the gate conductor layer can be planarized, such as CMP.
  • the gate dielectric layer 1019 may include a high-K gate dielectric such as HfO 2 with a thickness of about 1 nm-5 nm; the gate conductor layer 1021 may include a work function adjusting metal and a gate conductive metal.
  • an oxide interface layer of, for example, about 0.5 nm to 2 nm may also be formed.
  • the end of the gate stack can be embedded in the recess so as to overlap the entire height of the channel layer 1009.
  • the bottom surface of the gate stack defined by the top surface of the isolation layer 1017 is between the top surface and the bottom surface of the channel layer 1009, the overlap between the gate stack and the first conductive layer 1005 can be reduced.
  • the top surface of the gate stack outside the recess is lower than the bottom surface of the channel layer 1009, the overlap between the gate stack and the second conductive layer 1013 can be reduced.
  • the gate conductor layer 1021 may have stress or strain to enhance device performance.
  • the gate conductor layer may have tensile stress (such as TiN or W) to generate compressive stress in the channel
  • tensile stress such as TiN or W
  • the gate conductor layer may have compressive stress to generate tensile stress in the channel. Since the upper end of the active region is movable, this structure can generate much greater stress than planar MOSFETs or FinFETs, and therefore the degree of performance improvement through stress can be much higher.
  • a photoresist 1023 may be formed on the gate conductor layer 1021.
  • the photoresist 1023 is patterned by photolithography to cover a part of the gate stack exposed outside the recess (in this example, the left half of the figure), and expose another part of the gate stack exposed outside the recess (in the In the example, the right half of the figure).
  • the photoresist 1023 can be used as a mask to selectively etch the gate conductor layer 1021, such as RIE. In this way, except for the portion of the gate conductor layer 1021 remaining in the recess, the portion blocked by the photoresist 1019 is retained. This part can be used as a landing pad to the contact portion of the gate conductor layer 1021 (the contact portion 1025-3 described below). According to another embodiment, the gate dielectric layer 1019 may be further selectively etched such as RIE (not shown in the figure). After that, the photoresist 1023 may be removed.
  • an interlayer dielectric layer 1023 may be formed.
  • an oxide may be deposited and planarized, such as CMP, to form the interlayer dielectric layer 1023.
  • a contact portion 1025-1 to the first conductive layer 1005, a contact portion 1023-2 to a contact portion 1025-2 of the second conductive layer 1013, and a contact portion to the gate conductor layer 1021 may be formed 1025-3.
  • These contacts can be formed by etching holes in the interlayer dielectric layer 1023 and the isolation layer 1017, and filling them with conductive materials such as metal (for example, tungsten).
  • a diffusion barrier layer such as TiN can be formed first.
  • the gate conductor layer 1021 extends beyond the outer periphery of the active region, its contact portion 1025-3 can be easily formed.
  • the lower portion of the first conductive layer 1005 extends beyond the active area and there is no gate conductor layer 1021 over at least a part of it, its contact portion 1025-1 can be easily formed.
  • the semiconductor device includes a first conductive layer 1005, a first source/drain layer 1007, a channel layer 1009, and a second source/drain layer 1011 stacked in a vertical direction. And a second conductive layer 1013.
  • One source/drain region is formed in the first conductive layer 1005 and the first source/drain layer 1007, and another source/drain region is formed in the second conductive layer 1013 and the second source/drain layer 1011.
  • the channel layer 1009 is recessed laterally, the gate stack (1019/1021) is formed around the outer circumference of the channel layer 1009, and the end is embedded in the recess.
  • FIG. 8(b) shows the operation described above in connection with FIGS. 2(a) to 8(a) (omitting the first source/drain layer 1007 and the second source/drain layer 1007 and the second source/drain layer) in the situation shown in FIG. 1(b).
  • Layer 1011) the resulting semiconductor device.
  • the semiconductor device shown in FIG. 8(b) is basically the same as the device shown in FIG. 8(a), except that the first conductive layer 1005 and the second conductive layer 1003 can be formed with the channel layer 1009 in the case of a metallic layer. Schottky devices.
  • Figure 8(c) shows the leakage suppression by the operation described above in conjunction with Figures 2(a) to 8(a) (the leakage suppression layer 1003' of the insulating material replaces the semiconductor material in the situation shown in Figure 1(c)). Layer 1003) the resulting semiconductor device.
  • the semiconductor device shown in FIG. 8(b) is basically the same as the device shown in FIG. 8(a) except for the leakage suppression layer.
  • the first source/drain layer 1007 and the second source/drain layer 1011 and the channel layer 1009 comprise the same material, and therefore are relatively concave in the process of making the channel layer 1009 relatively concave.
  • the present disclosure is not limited to this.
  • 9 to 12 show schematic diagrams of a process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • the first source/drain layer 1007 and the second source/drain layer 1011 include a material with etch selectivity with respect to the channel layer 1009, such as the first source/drain layer.
  • the layer 1007 and the second source/drain layer 1011 may include Si, and the channel layer 1009 may include SiGe, but the present disclosure is not limited thereto.
  • the first source/drain layer 1007 and the second source/drain layer 1011 may be substantially unaffected, as shown in FIG. 9.
  • the sacrificial gate 1015 ′ can be formed according to the process described above in conjunction with FIG. 4, as shown in FIG. 10.
  • the sacrificial gate 1015 ′ surrounds the outer circumference of the channel layer 1009 and is located between the first source/drain layer 1007 and the second source/drain layer 1011.
  • selective etching can be used to make The ends of the first source/drain layer 1007 and the second source/drain layer 1011 are relatively recessed, and a dielectric material 1027 is filled in the resulting space.
  • the dielectric material 1027 is between the sacrificial gate 1015' (which will be replaced by a gate stack later) and the conductive layers 1005, 1013, and surrounds the source/drain layers 1007, 1011.
  • the ends of the first source/drain layer 1007 and the second source/drain layer 1011 may still protrude outward with respect to the outer peripheral sidewall of the channel layer 1009 after being relatively recessed.
  • a replacement gate process may be performed to form a gate stack.
  • a dielectric material 1027 is inserted between the formed gate stack and the conductive layers 1005, 1013, which helps reduce capacitance and improve insulation reliability.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (for example, other forms of transistors, etc.), it is possible to form an integrated circuit (IC), and thereby construct an electronic device. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device.
  • the electronic device may also include components such as a display screen matched with an integrated circuit and a wireless transceiver matched with an integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and so on.
  • a method for manufacturing a system on chip is also provided.
  • the method may include the above-mentioned method of manufacturing a semiconductor device.
  • a variety of devices can be integrated on a chip, at least some of which are manufactured according to the method of the present disclosure.

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Abstract

公开了一种带导电层的竖直型半导体器件及其制造方法及包括该器件的电子设备。根据实施例，半导体器件可以包括：衬底；依次设置在衬底上的第一金属性层、沟道层和第二金属性层；以及绕沟道层的至少部分外周形成的栅堆叠，其中，第一金属性层和第二金属性层以及沟道层是单晶结构。

Description

带导电层的竖直型半导体器件及其制造方法及电子设备
相关申请的引用
本申请要求于2020年6月12日递交的题为“带导电层的竖直型半导体器件及其制造方法及电子设备”的中国专利申请202010539695.6的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及带有导电层特别是金属性层的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件所占的面积不易进一步缩小或制造成本不易进一步降低。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小或制造成本更易降低。
在竖直型器件中，希望沟道采用单晶材料，因为相对于多晶材料，可以降低沟道电阻并因此可以堆叠多个竖直型器件从而实现高集成密度。但是，对于单晶的沟道材料，一方面难以控制栅长，另一方面难以在源/漏区提供低电阻。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有导电层特别是金属性层以在源/漏区提供低电阻的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一方面，提供了一种半导体器件，包括：衬底；依次设置在衬底上的第一金属性层、沟道层和第二金属性层；以及绕沟道层的至少部分外周形成的栅堆叠，其中，第一金属性层和第二金属性层以及沟道层是单晶结构。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；依次设置 在衬底上的第一导电层、第一源/漏层、沟道层、第二源/漏层和第二导电层；以及绕沟道层的至少部分外周形成的栅堆叠，其中，第一导电层和第二导电层、第一源/漏层和第二源/漏层以及沟道层是单晶结构。导电层可以包括掺杂半导体材料。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成第一金属性层、沟道层和第二金属性层；将第一金属性层、沟道层和第二金属性层构图为预定形状；以及绕沟道层的至少部分外周形成栅堆叠。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成第一导电层、第一源/漏层、沟道层、第二源/漏层和第二导电层；将第一导电层、第一源/漏层、沟道层、第二源/漏层和第二导电层构图为预定形状；以及绕沟道层的至少部分外周形成栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括由上述半导体器件形成的集成电路。
根据本公开的实施例，栅堆叠绕沟道层的至少部分外周形成且沟道可以形成于沟道层中，从而栅长实质上由沟道层的厚度确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。另外，在沟道层两侧设置了导电层特别是金属性层，其可以是源/漏区或源/漏区的一部分，从而降低源/漏电阻。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1(a)至8(c)示出了根据本公开实施例的制造半导体器件的流程的示意图；以及
图9至12示出了根据本公开另一实施例的制造半导体器件的流程的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的竖直型半导体器件可以包括在衬底上依次叠置的第一导电层、沟道层和第二导电层。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和开态电流增强层(带隙比相邻层大或小的半导体层)。第一导电层和第二导电层本身中可以分别形成器件的源/漏区(可以分别称为“第一源/漏区”和“第二源/漏区”)。或者，第一源/漏层可以介于第一导电层与沟道层之间，且第二源/漏层可以介于第二导电层与沟道层之间。第一源/漏区和第二源/漏区也可以形成在第一源/漏层和第二源/漏层中。另外，在沟道层中可以形成器件的沟道区。
第一导电层和第二导电层可以是高导电性的材料层，如金属性层或掺杂半导体层。在存在第一源/漏层和第二源/漏层的情况下，第一导电层和第二导电层可以分别与第一源/漏层和第二源/漏层形成欧姆接触，以降低电阻。在不存在第一源/漏层和第二源/漏层的情况下，第一导电层和第二导电层特别是金属性层可以与沟道层形成肖特基结，并因此可以形成肖特基器件。
第一导电层、第一源/漏层、沟道层、第二源/漏层和第二导电层中各层可以是单晶材料，从而可以具有高载流子迁移率和低漏电流，并因此可以改善器件性能。这些层可以通过生长如外延生长来形成。由于外延生长，至少一部分 相邻层之间可以具有清晰的晶体界面，并且至少一些界面的至少一部分乃至全部可以是共格界面。
栅堆叠可以绕沟道层的至少部分外周形成，并可以控制沟道区的通/断。根据实施例，栅堆叠特别是其靠近沟道层的端部可以自对准于沟道层。例如，沟道层的外周侧壁可以相对向内凹入。这样，所形成的栅堆叠的端部可以嵌于沟道层的相对凹入中，减少与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于刻蚀定时来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。
这种半导体器件例如可以如下制造。
可以在衬底上依次形成第一导电层、沟道层和第二导电层。或者，还可以在第一导电层与沟道层之间形成第一源/漏层，且可以在沟道层与第二导电层之间形成第二源/漏层。如上所述，可以在衬底上通过外延生长来形成各层，且保持各层为单晶体系。在生长时，可以控制所生长的各层特别是沟道层的厚度。
对于叠置的第一导电层、沟道层和第二导电层(以及可选地，第一源/漏层和第二源/漏层)，可以在其中限定有源区。例如，可以将它们依次选择性刻蚀为所需的形状。通常，有源区可以呈柱状(例如，圆柱状)。为了便于在后继工艺中连接第一导电层中形成的源/漏区，对第一导电层的刻蚀可以只针对第一导电层的上部，从而第一导电层的下部可以延伸超出其上部的外周。然后，可以绕沟道层的外周形成栅堆叠。
另外，可以使沟道层的外周(以及可选地，第一源/漏层和第二源/漏层的外周)相对于第一、第二导电层的外周向内凹入，以便限定容纳栅堆叠的空间。例如，这可以通过选择性刻蚀来实现。这种情况下，栅堆叠可以嵌入该凹入中。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀 或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1(a)至8(c)示出了根据本公开实施例的制造半导体器件的流程的示意图。
如图1(a)所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001中，可以通过例如离子注入或扩散掺杂，形成阱区。例如，如果要形成p型器件，则可以形成n型阱区；而如果要形成n型器件，则可以形成p型阱区。不同导电类型的阱区可以通过相应导电类型的杂质(p型杂质如B或BF2等，n型杂质如P或As等)来形成。可以进行退火，以激活注入的杂质。阱区中的掺杂浓度可以为例如约1E17-1E19cm -3。
在衬底1001上，可以形成用于设置有源区的材料层(这些材料层均可以形成为单晶结构，以确保特别是有源区中的沟道层能够具有单晶结构以降低沟道电阻)。在一个示例中，为抑制泄漏，在形成用于有源区的材料层之前，可以先形成泄漏抑制层。
例如，泄漏抑制层可以包括半导体材料如Si，如图1(a)中的1003所示。半导体材料的泄漏抑制层1003可以通过例如外延生长形成，并可以通过离子注入或在外延生长时原位掺杂而被掺杂为与阱区相反的导电类型。于是，泄漏抑制层1003与阱区可以形成pn结。一般而言，相比于随后将要形成的肖特基结泄漏，pn结泄漏相对较小。
备选地，泄漏抑制层可以包括绝缘材料，如图1(c)中的1003′所示。绝缘材料的泄漏抑制层1003′可以通过生长例如化学气相淀积(CVD)形成。为减少晶体缺陷，泄漏抑制层1003′的晶格常数与衬底1001的晶格常数相差可以在约+/-2％以内。例如，泄漏抑制层1003′可以包括SrTiO 3、(LaY) 2O 3、LaAlO 3或LaLuO 3，但本公开不限于此。
在泄漏抑制层1003或1003′上，可以依次形成第一导电层1005、第一源/漏层1007、沟道层1009、第二源/漏层1011和第二导电层1013。
第一导电层1005和第二导电层1013可以具有高导电性。例如，第一导电 层1005和第二导电层1013可以包括金属性材料如NiSi 2或CoSi 2，并可以通过生长如CVD形成。或者，第一导电层1005和第二导电层1013也可以包括半导体材料，可以通过例如外延生长形成，并可以被掺杂(例如，在生长时原位掺杂)从而具有高导电性，例如掺杂GaAs或掺杂GaAs：Si。第一导电层1005和第二导电层1013可以包括相同的材料，当然也可以包括不同的材料。为减少晶体缺陷，第一导电层1005和第二导电层1013的晶格常数与衬底1001的晶格常数相差可以在约+/-2％以内。第一导电层1005和第二导电层1013可以形成源/漏区或源/漏区的一部分(例如，用作源/漏区与互连相接触的接触部)，厚度例如为约5nm-50nm。
第一源/漏层1007、沟道层1009和第二源/漏层1011可以是通过例如外延生长而形成的半导体材料层。第一源/漏层1007和第二源/漏层1011可以用于形成源/漏区(的一部分)，因此可以被掺杂(例如，在生长时原位掺杂)为与需要形成的器件的类型相对应的导电类型，例如对于p型器件掺杂为p型，对于n型器件掺杂为n型，掺杂浓度为约1E19-1E21cm-3，厚度可以为例如约2nm-5nm。在此，第一源/漏层1007和第二源/漏层1011相对于第一导电层1005和第二导电层1013较薄，从而随后形成的源/漏区的大部分具有高导电性，以降低电阻。第一源/漏层1007和第二源/漏层1011可以包括相同的材料，但是本公开不限于此。另外，沟底层1009可以未有意掺杂，或轻掺杂(例如，在生长时原位掺杂)以调节器件的阈值电压，厚度可以为例如约10nm-200nm。
第一源/漏层1007、沟道层1009和第二源/漏层1011可以包括各种合适的半导体材料，例如Si、SiGe、Ge、III-V族化合物半导体如GaAs等。为减少晶体缺陷，第一源/漏层1007、沟道层1009和第二源/漏层1011各自的晶格常数与衬底1001的晶格常数相差可以在约+/-2％以内。在一个示例中，第一源/漏层1007、沟道层1009和第二源/漏层1011可以包括相同的材料如Si。在其他示例中，第一源/漏层1007、沟道层1009和第二源/漏层1011中相邻的层之间可以具有刻蚀选择性，例如第一源/漏层1007和第二源/漏层1011可以包括Si，沟道层1009可以包括SiGe。
在图1(a)和1(c)所示的示例中，在沟道层1009的上下两侧，分别设置了高掺杂半导体层(1007、1011)和导电层(1005、1013)，以便形成源/漏区。 高掺杂半导体层(1007、1011)与导电层(1005、1013)之间可以形成欧姆接触，以降低电阻。但是，本公开不限于此。例如，如图1(b)所示，可以省略高掺杂半导体层，而在沟道层1009的上下两侧直接设置导电层1005和1013。在导电层1005和1013包括金属性层的情况下，它们与沟道层1009可以形成肖特基结，并因此可以与沟道层1009一起构成肖特基器件。
衬底1001上形成的这些层分别从下层生长，以保持单晶体系。相邻的层之间可以具有晶体界面和/或掺杂浓度界面。另外，至少一些相邻的层之间的至少部分界面可以是共格界面。
尽管图1(a)、1(b)和1(c)分别示出了不同的情形，但是它们可以不同的方式组合。例如，图1(b)中的泄漏抑制层1003可以形成为如图1(c)中1003′所示的绝缘材料，或者图1(c)中也可以省略源/漏层1007和1011。在以下的描述中，主要以图1(a)所示的情况为例进行描述。但是，这些描述同样可以适用于例如图1(b)和1(c)所示等其他情形。
接下来，可以限定器件的有源区。例如，这可以如下进行。具体地，如图2(a)和2(b)(图2(a)是截面图，图2(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以形成光刻胶(未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状(在该示例中，大致圆形)，并以构图后的光刻胶为掩模，依次对第二导电层1013、第二源/漏层1011、沟道层1009、第一源/漏层1007和第一导电层1005进行选择性刻蚀如反应离子刻蚀(RIE)。在此，刻蚀可以进行到第一导电层1005中，但并未进行到第一导电层1005的底面处。这是为了便于随后形成的接触部容易地着落到第一导电层1005上。于是，刻蚀后第二导电层1013、第二源/漏层1011、沟道层1009、第一源/漏层1007和第一导电层1005的上部形成柱状(在本示例中，圆柱状)，它们限定了有源区。RIE例如可以按大致垂直于衬底表面的方向进行，从而该柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
在此，大致圆形(直径例如为约10nm-100nm)的有源区将导致形成纳米线器件。但是，本公开不限于此。例如，有源区可以被构图为矩形(长例如为约10nm-10μm以提供足够的器件电流，宽例如为约10nm-100nm以实现短沟道效应的良好控制)，从而可以形成纳米片器件。当然，有源区的形状不 限于此。
为了形成自对准的栅堆叠，可以使沟道层1009的外周侧壁相对凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。例如，如图3所示，可以相对于第一导电层1005和第二导电层1013，例如通过采用TMAH溶液的湿法刻蚀，选择性刻蚀沟道层1009。为精确地控制刻蚀深度，对沟道层1009的刻蚀可以通过原子层刻蚀(ALE)来进行。围绕沟道层1009的外周，刻蚀深度可以大致相同。也即，刻蚀后沟道层1009可以保持与第二导电层1013大致中心对准，且形状保持基本相同(但缩小了)。在该示例中，第一源/漏层1007和第二源/漏层1011也包括Si，因此也可以被刻蚀，且刻蚀后的形状可以与沟道层1009大致相同且大致中心对准。
在沟道层1009(以及第一源/漏层1007和第二源/漏层1011)相对于第一导电层1005和第二导电层1013形成的凹入中，随后将形成栅堆叠。为避免后继处理对于沟道层1009造成影响或者在该凹入中留下不必要的材料从而影响后继栅堆叠的形成，可以在该凹入中填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过淀积氮化物，然后对淀积的氮化物进行回蚀如RIE。可以沿竖直方向进行RIE，从而氮化物可仅留在凹入内，形成牺牲栅1015，如图4所示。这种情况下，牺牲栅1015可以基本上填满上述凹入。
可以在有源区周围形成隔离层，以实现电隔离。例如，如图5所示，可以在图4所示的结构上淀积氧化物，并对其回蚀，以形成隔离层1017。在回蚀之前，可以对淀积的氧化物进行平坦化处理如化学机械抛光(CMP)或溅射。在此，隔离层1017的顶面可以在沟道层1009的顶面与底面之间。
然后，可以进行替代栅工艺。
例如，如图6所示，可以通过选择性刻蚀，去除牺牲栅1015，以释放该凹入中的空间。可以在释放的凹入中形成栅堆叠。具体地，可以依次淀积栅介质层1019和栅导体层1021，并对所淀积的栅导体层1021进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1009的顶面。在回蚀之前，可以对栅导体层进行平坦化处理如CMP。例如，栅介质层1019可以包括高K栅介质如HfO 2，厚度为约1nm-5nm；栅导体层1021可以包括功函数调节金 属和栅导电金属。在形成栅介质层1019之前，还可以形成例如约0.5nm-2nm的氧化物界面层。
这样，栅堆叠的端部可以嵌入到凹入中，从而与沟道层1009的整个高度相交迭。另外，由于隔离层1017的顶面所限定的栅堆叠的底面在沟道层1009的顶面与底面之间，因此，可以减小栅堆叠与第一导电层1005之间的交迭。另外，由于栅堆叠在凹入之外的部分的顶面低于沟道层1009的底面，因此，可以减小栅堆叠与第二导电层1013之间的交迭。
根据实施例，栅导体层1021中可以带有应力或应变，以增强器件性能。例如，对于p型器件，栅导体层可以具有拉应力(例如TiN或W)以便在沟道中产生压应力，而对于n型器件，栅导体层可以具有压应力以便在沟道中产生拉应力。由于有源区的上端可移动，因此这种结构能够产生比平面MOSFET或FinFET大得多的应力，并因此通过应力提升性能的程度可以高得多。
接下来，可以对栅堆叠的形状进行调整，以便于后继互连制作。例如，如图7所示，可以在栅导体层1021上形成光刻胶1023。光刻胶1023例如通过光刻构图为覆盖栅堆叠露于凹入之外的一部分(在该示例中，图中左半部)，且露出栅堆叠露于凹入之外的另一部分(在该示例中，图中右半边)。
然后，如图8(a)所示，可以光刻胶1023为掩模，对栅导体层1021进行选择性刻蚀如RIE。这样，栅导体层1021除了留于凹入之内的部分之外，被光刻胶1019遮挡的部分得以保留。该部分可以用作到栅导体层1021的接触部(下述的接触部1025-3)的着落焊盘。根据另一实施例，也可以进一步对栅介质层1019进行选择性刻蚀如RIE(图中未示出)。之后，可以去除光刻胶1023。
然后，可以形成层间电介质层1023。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1023。在层间电介质层1023中，可以形成到第一导电层1005的接触部1025-1、到第二导电层1013的接触部1025-2的接触部1023-2以及到栅导体层1021的接触部1025-3。这些接触部可以通过在层间电介质层1023以及隔离层1017中刻蚀孔洞，并在其中填充导电材料如金属(例如，钨)来形成。在淀积金属之前，可以先形成扩散阻挡层例如TiN。
由于栅导体层1021延伸超出有源区外周，从而可以容易地形成它的接触部1025-3。另外，由于第一导电层1005的下部延伸超出有源区之外且至少在 其一部分上方并不存在栅导体层1021，从而可以容易地形成它的接触部1025-1。
如图8(a)所示，根据该实施例的半导体器件包括沿竖直方向叠置的第一导电层1005、第一源/漏层1007、沟道层1009、第二源/漏层1011和第二导电层1013。在第一导电层1005和第一源/漏层1007中形成了一个源/漏区，在第二导电层1013和第二源/漏层1011中形成了另一源/漏区。沟道层1009横向凹入，栅堆叠(1019/1021)绕沟道层1009的外周形成，且端部嵌于该凹入中。
图8(b)示出了在图1(b)所示的情形下通过以上结合图2(a)至8(a)描述的操作(省略第一源/漏层1007和第二源/漏层1011)得到的半导体器件。图8(b)所示的半导体器件与图8(a)所示的器件基本上相同，除了第一导电层1005、第二导电层1003在金属性层的情况下与沟道层1009可以形成肖特基器件。
图8(c)示出了在图1(c)所示的情形下通过以上结合图2(a)至8(a)描述的操作(绝缘材料的泄漏抑制层1003′代替半导体材料的泄漏抑制层1003)得到的半导体器件。图8(b)所示的半导体器件与图8(a)所示的器件基本上相同，除了泄漏抑制层不同。
在以上实施例中，第一源/漏层1007和第二源/漏层1011与沟道层1009包括相同的材料，并因此在使沟道层1009相对凹入的工艺中也相对凹入了。但是，本公开不限于此。
图9至12示出了根据本公开另一实施例的制造半导体器件的流程的示意图。
如图9所示，根据以上结合图1(a)、2(a)和2(b)的说明，以相同的方式在衬底1001上形成各材料层并构图有源区。与上述实施例的区别在于，在该实施例中，第一源/漏层1007和第二源/漏层1011包括相对于沟道层1009具备刻蚀选择性的材料，例如第一源/漏层1007和第二源/漏层1011可以包括Si，而沟道层1009可以包括SiGe，但是本公开不限于此。
类似地，可以通过选择性刻蚀，使沟道层1009相对凹入。在此，由于刻蚀选择性，第一源/漏层1007和第二源/漏层1011可以基本不受影响，如图9所示。可以按照以上结合图4描述的处理，形成牺牲栅1015′，如图10所示。在此，牺牲栅1015′围绕沟道层1009的外周，且位于第一源/漏层1007和第二源/漏层1011之间。
为了进一步降低随后形成的栅堆叠与源/漏之间的交迭(降低寄生电容)并改进栅与源/漏之间的绝缘可靠性，如图11所示，可以通过选择性刻蚀，使第一源/漏层1007和第二源/漏层1011的端部相对凹入，并在由此导致的空间中填充电介质材料1027。电介质材料1027介于牺牲栅1015′(随后将被替换为栅堆叠)与导电层1005、1013之间，且围绕源/漏层1007、1011。在此，第一源/漏层1007和第二源/漏层1011的端部在相对凹入之后仍然可以相对于沟道层1009的外周侧壁向外伸出。
之后，如以上参考图5至8(c)所述，可以进行替代栅工艺，以形成栅堆叠。如图12所示，形成的栅堆叠与导电层1005、1013之间插入了电介质材料1027，有助于降低电容并改进绝缘可靠性。
该实施例的其他方面可以与上述实施例中相同。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (32)

  1. 一种半导体器件，包括：
    衬底；
    依次设置在所述衬底上的第一金属性层、沟道层和第二金属性层；以及
    绕所述沟道层的至少部分外周形成的栅堆叠，
    其中，所述第一金属性层和所述第二金属性层以及所述沟道层是单晶结构。
  2. 根据权利要求1所述的半导体器件，其中，
    所述第一金属性层与所述沟道层之间的界面至少部分是共格界面；和/或
    所述第二金属性层与所述沟道层之间的界面至少部分是共格界面。
  3. 根据权利要求1所述的半导体器件，其中，
    所述第一金属性层与所述沟道层之间的界面是共格界面；和/或
    所述第二金属性层与所述沟道层之间的界面是共格界面。
  4. 根据权利要求1至3中任一项所述的半导体器件，其中，
    所述第一金属性层与所述沟道层形成肖特基结，
    所述第二金属性层与所述沟道层形成肖特基结。
  5. 根据权利要求1所述的半导体器件，还包括：
    设于所述第一金属性层与所述沟道层之间的第一源/漏层；以及
    设于所述第二金属性层与所述沟道层之间的第二源/漏层，
    其中，所述第一源/漏层和所述第二源/漏层是单晶结构。
  6. 根据权利要求5所述的半导体器件，其中，
    所述第一金属性层与所述第一源/漏层之间的界面至少部分是共格界面；和/或
    所述第二金属性层与所述第二源/漏层之间的界面至少部分是共格界面。
  7. 根据权利要求5所述的半导体器件，其中，
    所述第一金属性层与所述第一源/漏层之间的界面是共格界面；和/或
    所述第二金属性层与所述第二源/漏层之间的界面是共格界面。
  8. 根据权利要求5至7中任一项所述的半导体器件，其中，
    所述第一金属性层与所述第一源/漏层形成欧姆接触，
    所述第二金属性层与所述第二源/漏层形成欧姆接触。
  9. 根据权利要求1至8中任一项所述的半导体器件，其中，所述第一金属性层和所述第二金属性层各自的晶格常数与所述衬底的晶格常数相差在+/-2％以内。
  10. 根据权利要求1至9中任一项所述的半导体器件，其中，所述第一金属性层和所述第二金属性层各自包括NiSi 2或CoSi 2。
  11. 一种半导体器件，包括：
    衬底；
    依次设置在所述衬底上的第一导电层、第一源/漏层、沟道层、第二源/漏层和第二导电层；以及
    绕所述沟道层的至少部分外周形成的栅堆叠，
    其中，所述第一导电层和所述第二导电层、所述第一源/漏层和所述第二源/漏层以及所述沟道层是单晶结构。
  12. 根据权利要求11所述的半导体器件，其中，所述第一导电层和所述第二导电层各自的晶格常数与所述衬底的晶格常数相差在+/-2％以内。
  13. 根据权利要求11或12所述的半导体器件，其中，所述第一导电层和所述第二导电层各自包括掺杂GaAs或掺杂GaAs：Si。
  14. 根据权利要求1至13中任一项所述的半导体器件，还包括：
    设于所述第一金属性层或所述第一导电层与所述衬底之间的泄漏抑制层。
  15. 根据权利要求14所述的半导体器件，其中，所述衬底中包括阱区，所述泄漏抑制层与所述阱区形成pn结。
  16. 根据权利要求14所述的半导体器件，其中，所述泄漏抑制层包括单晶结构的绝缘层。
  17. 根据权利要求16所述的半导体器件，其中，所述绝缘层的晶格常数与所述衬底的晶格常数相差在+/-2％以内。
  18. 根据权利要求16所述的半导体器件，其中，所述绝缘层包括SrTiO 3、(LaY) 2O 3、LaAlO 3或LaLuO 3。
  19. 根据权利要求5或11所述的半导体器件，还包括：
    分别设于所述栅堆叠与所述第一金属性层或所述第一导电层之间、所述栅 堆叠与所述第二金属性层或所述第二导电层之间，且分别围绕所述第一源/漏层、所述第二源/漏层的电介质层。
  20. 根据权利要求1至19中任一项所述的半导体器件，其中，所述栅堆叠靠近所述沟道层的端部与所述沟道层自对准。
  21. 一种制造半导体器件的方法，包括：
    在衬底上依次形成第一金属性层、沟道层和第二金属性层；
    将所述第一金属性层、所述沟道层和所述第二金属性层构图为预定形状；以及
    绕所述沟道层的至少部分外周形成栅堆叠。
  22. 根据权利要求21所述的方法，还包括：
    在所述第一金属性层与所述沟道层之间形成第一源/漏层；以及
    在所述第二金属性层与所述沟道层之间形成第二源/漏层。
  23. 根据权利要求21或22所述的方法，其中，所述第一金属性层和所述第二金属性层各自包括NiSi 2或CoSi 2。
  24. 一种制造半导体器件的方法，包括：
    在衬底上依次形成第一导电层、第一源/漏层、沟道层、第二源/漏层和第二导电层；
    将所述第一导电层、所述第一源/漏层、所述沟道层、所述第二源/漏层和所述第二导电层构图为预定形状；以及
    绕所述沟道层的至少部分外周形成栅堆叠。
  25. 根据权利要求24所述的方法，其中，所述第一导电层和所述第二导电层各自包括掺杂GaAs或掺杂GaAs：Si。
  26. 根据权利要求21至25中任一项所述的方法，还包括：
    在所述衬底与所述第一金属性层或所述第一导电层之间形成泄漏抑制层。
  27. 根据权利要求21至26中任一项所述的方法，其中，形成各层的方法包括外延生长单晶结构的各层。
  28. 根据权利要求26所述的方法，还包括：
    在衬底中形成阱区，
    其中，所述泄漏抑制层与所述阱区形成pn结。
  29. 根据权利要求26所述的方法，其中，所述泄漏抑制层包括单晶结构的绝缘层。
  30. 根据权利要求29所述的方法，其中，所述绝缘层包括SrTiO 3、(LaY) 2O 3、LaAlO 3或LaLuO 3。
  31. 一种电子设备，包括由如权利要求1至18中任一项所述的半导体器件形成的集成电路。
  32. 根据权利要求31所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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