CN107887441A - 半导体器件及其制造方法及包括该器件的电子设备 - Google Patents

半导体器件及其制造方法及包括该器件的电子设备 Download PDF

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CN107887441A
CN107887441A CN201710530250.XA CN201710530250A CN107887441A CN 107887441 A CN107887441 A CN 107887441A CN 201710530250 A CN201710530250 A CN 201710530250A CN 107887441 A CN107887441 A CN 107887441A
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layer
source drain
channel layer
semiconductor devices
source
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CN107887441B (zh
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朱慧珑
王桂磊
亨利·H·阿达姆松
张严波
朱正勇
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to PCT/CN2017/095178 priority Critical patent/WO2018059109A1/zh
Priority to US16/337,882 priority patent/US20200027950A1/en
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Abstract

公开了一种半导体器件及其制造方法及包括该器件的电子设备。根据实施例，半导体器件可以包括：衬底；依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层，其中，沟道层包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料；以及绕沟道层的外周形成的栅堆叠。

Description

半导体器件及其制造方法及包括该器件的电子设备
技术领域
本公开涉及半导体领域，具体地，涉及具有增强开态电流和/或减小关态电流的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有增强开态电流和/或减小关态电流的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层，其中，沟道层包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料；以及绕沟道层的外周形成的栅堆叠。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上外延生长第一源/漏层；在第一源/漏层上外延生长与Si材料相比具有增大开态电流和/或减小关态电流的沟道层；在沟道层上外延生长第二源/漏层；在第一源/漏层、沟道层和第二源/漏层中限定该半导体器件的有源区；以及绕沟道层的外周形成栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括由上述半导体器件形成的集成电路。
根据本公开的实施例，沟道层可以包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料。例如，对于p型器件，沟道层可以包括有利于增大开态电流和/或减小关态电流的半导体材料如IV族或III-V族半导材料如Ge、SiGe、SiGeSn、GeSn、InSb、InGaSb；对于n型器件，沟道层可以包括可以包括有利于增大开态电流和/或减小关态电流的半导体材料如IV族或III-V族化合物半导材料SiGe、Ge、GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、GaN、InSb、InGaSb。
另外，栅堆叠绕沟道层的外周形成且沟道形成于沟道层中，从而栅长由沟道层的厚度确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。沟道层的外周相对于第一、第二源/漏层的外周可以向内凹入，从而栅堆叠可以嵌入该凹入中，减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。另外，沟道层可以是单晶半导体材料，可以具有高的开态电流和/或小的关态电流，从而改善了器件性能。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1～10(b)示出了根据本公开实施例的制造半导体器件的流程的示意图；以及
图11示出了根据本公开另一实施例的半导体器件的示意截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的竖直型半导体器件可以包括在衬底上依次叠置的第一源/漏层、沟道层和第二源/漏层。在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。沟道层可以包括与Si材料相比增大开态电流和/或减小关态电流的半导体材料。例如，对于n型器件，沟道层可采用有利于改进电子迁移率的半导体材料，例如III-V族化合物半导体如GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN；对于p型器件，沟道层可采用有利于改进空穴迁移率的半导体材料，例如IV族或III-V族半导体材料如Ge、SiGe、SiGeSn、InSb、InGaSb或GeSn。
根据本公开的实施例，这种半导体器件可以是常规场效应晶体管(FET)。在FET的情况下，第一源/漏层和第二源/漏层(或者说，沟道层两侧的源/漏区)可以具有相同导电类型(例如，n型或p型)的掺杂。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。或者，这种半导体器件可以是隧穿FET。在隧穿FET的情况下，第一源/漏层和第二源/漏层(或者说，沟道层两侧的源/漏区)可以具有不同导电类型(例如，分别为n型和p型)的掺杂。这种情况下，带电粒子如电子可以从源区隧穿通过沟道区而进入漏区，从而使源区和漏区之间形成导通路径。尽管常规FET和隧穿FET中的导通机制并不相同，但是它们均表现出可通过栅来控制源/漏区之间导通与否的电学性能。因此，对于常规FET和隧穿FET，统一以术语“源/漏层(源/漏区)”和“沟道层(沟道区)”来描述，尽管在隧穿FET中并不存在通常意义上的“沟道”。
栅堆叠可以绕沟道层的外周形成。于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于耗时刻蚀来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。沟道层的外周可以相对于第一、第二源/漏层的外周向内凹入。这样，所形成的栅堆叠可以嵌于沟道层相对于第一、第二源/漏层的凹入中，减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
沟道层可以由单晶半导体材料构成，以改善器件性能。当然，第一、第二源/漏层也可以由单晶半导体材料构成。这种情况下，沟道层的单晶半导体材料与源/漏层的单晶半导体材料可以是共晶体。沟道层单晶半导体材料的电子或空穴迁移率可以大于第一、第二源/漏层的电子或空穴迁移率。另外，第一、第二源/漏层的禁带宽度可以大于沟道层单晶半导体材料的禁带宽度。
根据本公开的实施例，沟道层单晶半导体材料与第一、第二源/漏层可以具有相同的晶体结构。在这种情况下，第一、第二源/漏层在没有应变的情况下的晶格常数可以大于沟道层单晶半导体材料在没有应变的情况下的晶格常数。于是，沟道层单晶半导体材料的载流子迁移率可以大于其在没有应变的情况下的载流子迁移率，或沟道层单晶半导体材料的较轻载流子的有效质量可以小于其在没有应变的情况下的较轻载流子的有效质量，或沟道层单晶半导体材料的较轻载流子的浓度可以大于其在没有应变的情况下的较轻载流子的浓度。备选地，第一、第二源/漏层在没有应变的情况下的晶格常数可以小于沟道层单晶半导体材料在没有应变的情况下的晶格常数。于是，沟道层单晶半导体材料的电子迁移率大于其在没有应变的情况下的电子迁移率，或沟道层单晶半导体材料的电子的有效质量小于其在没有应变的情况下的电子的有效质量。
根据本公开的实施例，还可以在第一源/漏层与沟道层之间和/或在沟道层与第二源/漏层之间(在隧穿FET的情况下，特别是在构成隧穿结的两层之间)设置泄漏限制层或开态电流增强层。泄漏限制层的带隙可以大于其上方与之邻接的层和其下方与之邻接的层中至少之一的带隙。开态电流增强层的带隙可以小于其上方与之邻接的层和其下方与之邻接的层中至少之一的带隙。由于这种带隙的差异，可以抑制泄漏或增强开态电流。
根据本公开的实施例，对于源/漏区的掺杂可以部分地进入与源/漏区邻接的沟道层靠近第一源/漏层和第二源/漏层的端部或泄漏限制层、开态电流增强层(如果存在的话)中。由此，在沟道层靠近第一源/漏层和第二源/漏层的端部或泄漏限制层中形成掺杂分布，这有助于降低器件导通时源/漏区与沟道区之间的电阻，从而提升器件性能。
根据本公开的实施例，第一、第二源/漏层可以包括与沟道层不同的半导体材料(但可以属于相同的材料体系，例如，对于n型器件，源/漏层与沟道层可以包括不同的III-V族化合物半导体材料或IV族半导体材料；对于p型器件，源/漏层与沟道层可以包括不同的IV族半导体材料或III-V族化合物半导体材料)。这样，有利于对沟道层进行处理例如选择性刻蚀和/或开关电流的优化，以使之相对于第一、第二源/漏层凹入。另外，第一源/漏层和第二源/漏层可以包括相同的半导体材料。
各半导体层可以是衬底上的外延层。例如，第一源/漏层可以是在衬底上外延生长的半导体层，沟道层可以是在第一源/漏层上外延生长的半导体层，第二源/漏层可以是在沟道层上外延生长的半导体层。
这种半导体器件例如可以如下制造。具体地，可以在衬底上外延生长第一源/漏层。接着，可以在第一源/漏层上外延生长沟道层，在生长沟道层时可以利用与Si材料相比增大开态电流和/或减小关态电流的非硅半导体材料。并可以在沟道层上外延生长第二源/漏层。在外延生长时，可以控制所生长的沟道层的厚度。由于分别外延生长，至少一对相邻层之间可以具有清晰的晶体界面。另外，可以对各层分别进行掺杂，于是至少一对相邻层之间可以具有掺杂浓度界面。
在第一源/漏层与沟道层之间和/或在沟道层与第二源/漏层之间，还可以外延生长泄漏限制层和/或开态电流增强层，以抑制泄漏和/或增强开态电流。
对于叠置的第一源/漏层、沟道层和第二源/漏层(以及泄漏限制层或开态电流增强层，如果存在的话)，可以在其中限定有源区。例如，可以将它们依次选择性刻蚀为所需的形状。通常，有源区可以呈柱状(例如，圆柱状)。为了便于在后继工艺中连接第一源/漏层中形成的源/漏区，对第一源/漏层的刻蚀可以只针对第一源/漏层的上部，从而第一源/漏层的下部可以延伸超出其上部的外周。然后，可以绕沟道层的外周形成栅堆叠。
另外，可以使沟道层的外周相对于第一、第二源/漏层的外周向内凹入，以便限定容纳栅堆叠的空间。例如，这可以通过选择性刻蚀来实现。这种情况下，栅堆叠可以嵌入该凹入中。
在第一、第二源/漏层中可以形成源/漏区。例如，这可以通过对第一、第二源/漏层掺杂来实现。例如，可以进行离子注入、等离子体掺杂，或者在生长第一、第二源/漏层时原位掺杂。对于第一、第二源/漏层的掺杂可以进入与它们邻接的层中。
本公开可以各种形式呈现，以下将描述其中一些示例。
图1～10(b)示出了根据本公开实施例的制造半导体器件的流程图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、III-V族化合物半导体衬底或IV族半导体衬底(例如SiGe、Ge、SiGeSn、GeSn、GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN)等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在该示例中，对于将要在衬底1001上形成的器件，通过半导体材料选择(例如，非硅材料)来改善其性能。为了改善之后生长的其他半导体材料层的质量，可以在衬底1001上，例如通过外延生长，形成缓冲层1003。例如，缓冲层1003可以包括Si1-bGeb(例如，b在约0.1至1之间)，厚度为例如约200nm至几个微米。缓冲层1003的至少顶部可以是弛豫的，从而随后可以在此之上生长高质量的其他半导体材料层。
在缓冲层的顶部，可以形成阱区1003w。如果要形成p型器件，则阱区1003w可以是n型阱；如果要形成n型器件，则阱区1003w可以是p型阱。阱区1003w例如可以通过向缓冲层1003中注入相应导电类型(p型或n型)掺杂剂来形成，掺杂浓度可以为约1E17-2E18cm-3。本领域存在多种方式来设置这种阱区，在此不再赘述。
在缓冲层1003上，可以通过例如外延生长，依次形成第一源/漏层1005、第一泄漏限制层1007、沟道层1009、第二泄漏限制层1011和第二源/漏层1013。这些都是半导体材料层。
沟道层1009可以包括能够增大开态电流和/或减小关态电流的半导体材料，例如，对于p型器件，可以是能够改进载流子迁移率的材料。在此，所谓“改进”，一般是相对于常规的Si材料而言的(在没有应变或应力的情况下)。例如，沟道层1009可以包括IV族半导体材料，如Ge或Si1-yGey(例如，y在约0.1至1之间)。相对于Si材料而言，Ge系材料可以增强电子或者空穴的迁移率，因此对于n型器件和p型器件均适用。沟道层1009的厚度可以确定栅长，例如为约10-100nm。在外延生长沟道层1009时，可以对其进行原位掺杂，以调节器件的阈值电压(Vt)。例如，对于n型器件，可以对沟道层1009进行p型掺杂(例如，B或In)；对于p型器件，可以对沟道层1009进行n型掺杂(例如，P或As)，掺杂浓度可以为约1E17-2E18cm-3。当然，沟道层1009也可以并未有意掺杂。
第一源/漏层1005和第二源/漏层1013可以包括不同于沟道层的半导体材料。在此，所谓“不同”，不仅可以是指构成组分不同，而且可以是指构成组分相同但组分含量不同。这种不同主要是为了在以下处理中提供刻蚀选择性。例如，第一源/漏层1005可以包括Si1-xGex(例如，x在0至1之间，但是x不同于y；x与y之间的差别越大，所提供的刻蚀选择性越明显)，第二源/漏层1013可以包括Si1-zGez(例如，z在0至1之间，但是z不同于y；z与y之间的差别越大，所提供的刻蚀选择性越明显)。第一源/漏层1005和第二源/漏层1013的材料可以大致相同，即x可以近似等于或等于z。第一源/漏层1005和第二源/漏层1013的厚度可以为约20-50nm。在外延生长第一源/漏层1005和第二源/漏层1013时，可以对它们进行原位掺杂。例如，对于n型器件，可以对第一源/漏层1005和第二源/漏层1013进行n型掺杂(例如，As或P)；对于p型器件，可以对第一源/漏层1005和第二源/漏层1013进行p型掺杂(例如，B或BF2)，掺杂浓度可以为约1E17-1E20cm-3。
泄漏限制层1007和1011可以包括不同于沟道层和源/漏层的半导体材料。同样地，这种不同主要是为了在以下处理中提供刻蚀选择性。例如，泄漏限制层1007可以包括Si1- LR1GeLR1(例如，LR1在0至1之间，但是LR1不同于x、y、z；LR1与x、y、z之间的差别越大，所提供的刻蚀选择性越明显)，泄漏限制层1011可以包括Si1-LR2GeLR2(例如，LR2在0至1之间，但是LR2不同于x、y、z；LR2与x、y、z之间的差别越大，所提供的刻蚀选择性越明显)。泄漏限制层1007和1011的材料可以大致相同，即LR1可以近似等于或等于LR2。泄漏限制层1007和1011的厚度可以为约1-10nm。
在此，提供泄漏限制层1007和1011以抑制泄漏。为此，泄漏限制层1007和1011的带隙可以大于其上方与之邻接的层以及其下方与之邻接的层中至少之一的带隙。例如，对于泄漏限制层1007，其带隙可以大于第一源/漏层1005和沟道层1009中至少一方的带隙，为此LR1可以大于x，大于y，或者大于x和y二者。同样地，对于泄漏限制层1011，其带隙可以大于沟道层1009和第二源/漏层1013中至少一方的带隙，为此LR2可以大于y，大于z，或者大于y和z二者。
另外，在生长泄漏限制层1007和1011时，可以对其进行原位掺杂。例如，对于n型器件，可以对泄漏限制层1007和1011进行n型掺杂(例如，As或P)；对于p型器件，可以对泄漏限制层1007和1011进行p型掺杂(例如，B或BF2)，掺杂浓度可以为约1E18-1E21cm-3。
当然，也可以省略泄漏限制层1007和1011。这种情况下，第一源/漏层、沟道层和第二源/漏层可以依次叠置且彼此邻接。
接下来，可以限定器件的有源区。例如，这可以如下进行。具体地，如图2(a)和2(b)(图2(a)是截面图，图2(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图1所示的第一源/漏层1005、第一泄漏限制层1007、沟道层1009、第二泄漏限制层1011和第二源/漏层1013的叠层上形成光刻胶(未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状(在该示例中，大致圆形，也可其它形状，如长方形)，并以构图后的光刻胶为掩模，依次对第二源/漏层1013、第二泄漏限制层1011、沟道层1009、第一泄漏限制层1007和第一源/漏层1005进行选择性刻蚀如反应离子刻蚀(RIE)。刻蚀可以进行到第一源/漏层1005中，但并未进行到第一源/漏层1005的底面处。于是，刻蚀后各半导体层呈柱状或墙状(在本示例中，圆柱状)。RIE例如可以按大致垂直于衬底表面的方向进行，从而该柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
然后，如图3所示，可以使沟道层1009的外周相对于第一源/漏层1005和第二源/漏层1013(以及第一泄漏限制层1007和第二泄漏限制层1011)的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。例如，这可以通过相对于第一源/漏层1005和第二源/漏层1013(以及第一泄漏限制层1007和第二泄漏限制层1011)，进一步选择性刻蚀沟道层1009来实现。如上所述，由于y与x、z(以及LR1、LR2、b)之间的差别，可以实现这种选择性刻蚀。选择性刻蚀可以使用原子层刻蚀(Atomic Layer Etch，ALE)或者数字化刻蚀(DigitalEtch)的方法进行精确可控的刻蚀。
这样，就限定了该半导体器件的有源区，即刻蚀后的第一源/漏层1005、沟道层1009和第二源/漏层1013(以及第一泄漏限制层1007和第二泄漏限制层1011)。在该示例中，有源区大致呈柱状。在有源区中，第一源/漏层1005的外周和第二源/漏层1013的外周实质上对准，而沟道层1009的外周相对凹入。
当然，有源区的形状不限于此，而是可以根据设计布局形成其他形状。例如，在俯视图中，有源区可以呈椭圆形、方形、矩形等。
在沟道层1009相对于第一源/漏层1005和第二源/漏层1013的外周而形成的凹入中，随后将形成栅堆叠。为避免后继处理对于沟道层1009造成影响或者在该凹入中留下不必要的材料从而影响后继栅堆叠的形成，可以在该凹入中填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过在图3所示的结构上淀积氮化物，然后对淀积的氮化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮化物可仅留在凹入内，形成牺牲栅1015，如图4所示。这种情况下，牺牲栅1015可以基本上填满上述凹入。
可以按照类似的工艺，通过选择性刻蚀泄漏限制层1007和1011使其相对凹入，选择性刻蚀可以使用ALE的方法进行精确可控的刻蚀，并在凹入中填充介质侧墙1017，如图5所示。介质侧墙1017可以包括低k介质如氧化物、氮化物或氮氧化物。在此，介质侧墙1017可以包括不同于牺牲栅1015的材料，例如氮氧化物，以便随后不会随牺牲栅一同去除。
如果需要，特别是在以上并未对泄漏限制层1007和1011进行(原位)掺杂的情况下，可以进行退火处理，以将源/漏层1005、1013中的掺杂剂驱入到泄漏限制层1007和1011中，以便减少源/漏区与沟道之间的电阻，从而提升器件性能。这种退火处理也可以激活源/漏层1005、1013中的掺杂剂。
另外，还可以在源/漏层的表面进行硅化处理，以降低接触电阻。例如，可以在图5所示的结构上淀积一层金属如Co、Ti或NiPt等，然后在约200-600℃的温度下进行退火，使得金属与SiGe发生反应从而生成硅化物(例如，在NiPt的情况下得到SiNiPt)层。之后，可以去除未反应的剩余金属。
可以在有源区周围形成隔离层，以实现电隔离。例如，如图6所示，可以在图5所示的结构上淀积氧化物，并对其回蚀，以形成隔离层1019。在回蚀之前，可以对淀积的氧化物进行平坦化处理如化学机械抛光(CMP)或溅射。在此，隔离层1019的顶面可以靠近沟道层1009与第一泄漏限制层1007之间的界面。
在形成隔离层时，可以保留牺牲栅1015，以避免隔离层的材料进入要容纳栅堆叠的上述凹入中。之后，可以去除牺牲栅1015，以释放该凹入中的空间。例如，可以相对于隔离层1019(氧化物)、介质侧墙1017(氮氧化物)以及第二源/漏层1013(Si1-zGez)和沟道层1009(Si1-yGey)，选择性刻蚀牺牲栅1015(氮化物)。
然后，如图7所示，可以在凹入中形成栅堆叠。具体地，可以在图6所示的结构(去除牺牲栅1015)上依次淀积栅介质层1021和栅导体层1023，并对所淀积的栅导体层1023(以及可选地栅介质层1021)进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1009的顶面。例如，栅介质层1021可以包括高K栅介质如HfO2；栅导体层1023可以包括金属栅导体。另外，在栅介质层1021和栅导体层1023之间，还可以形成功函数调节层。在形成栅介质层1021之前，还可以形成例如氧化物的界面层。
这样，栅堆叠可以嵌入到凹入中，从而与沟道层1009的整个高度相交迭。
另外，隔离层1019的顶面可以不低于沟道层1009与第一泄漏限制层1007之间的界面，优选地在沟道层1009的顶面与底面之间，以减少或避免栅堆叠与源/漏之间的可能交迭，从而减小栅与源/漏之间的寄生电容。
接下来，可以对栅堆叠的形状进行调整，以便于后继互连制作。例如，如图8(a)和8(b)(图8(a)是截面图，图8(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图7所示的结构上形成光刻胶1025。该光刻胶1025例如通过光刻构图为覆盖栅堆叠露于凹入之外的一部分(在该示例中，图中左半部)，且露出栅堆叠露于凹入之外的另一部分(在该示例中，图中右半边)。
然后，如图9(a)和9(b)(图9(a)是截面图，图9(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以光刻胶1025为掩模，对栅导体层1023进行选择性刻蚀如RIE。这样，栅导体层1023除了留于凹入之内的部分之外，被光刻胶1025遮挡的部分得以保留。如图所示，栅导体层1023从凹入中呈条状延伸超出有源区外周，并可以具有增大面积的端部(例如，用作接触垫)。随后，可以通过该部分来实现到栅堆叠的电连接。
根据另一实施例，也可以进一步对栅介质层1021进行选择性刻蚀如RIE(图中未示出)。之后，可以去除光刻胶1021。
然后，可以如图10(a)和10(b)(图10(a)是截面图，图10(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，在图9(a)和9(b)所示的结构上形成层间电介质层1027。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1027。在层间电介质层1027中，可以形成到第一源/漏层1005的接触部1029-1、到第二源/漏层1013的接触部1029-2以及到栅导体层1023的接触部1029-3。这些接触部可以通过在层间电介质层1027以及隔离层1019中刻蚀孔洞，并在其中填充导电材料如金属来形成。
根据另一实施例，在沉积层间电介质层1027之前，可以去除介质侧墙1017，形成气体侧墙。例如，在沉积层间电介质层1027之前，可以依次去除栅介质层1021、隔离层1019和介质侧墙1017，然后沉积层间电介质层1027，在泄漏限制层1007和1011的两边可留下未填充的间隙，形成气隙侧墙。
由于栅导体层1023延伸超出有源区外周，从而可以容易地形成它的接触部1029-3。另外，由于第一源/漏层1005的下部延伸超出上方的有源层之外且至少在其一部分上方并不存在栅导体层，从而可以容易地形成它的接触部1029-1。
如图10(a)和10(b)所示，根据该实施例的半导体器件包括沿竖直方向叠置的第一源/漏层1005、沟道层1009和第二源/漏层1013。在第一源/漏层1005和第二源/漏层1013中形成了源/漏区。沟道层1009横向凹入，栅堆叠(1021/1023)绕沟道层1009的外周形成，且嵌于该凹入中。沟道层1009可以包括能够增大开态电流和/或减小关态电流的材料。另外，在第一源/漏层1005与沟道层1009之间以及沟道层1009与第二源/漏层1013之间形成有泄漏限制层1007、1011。
这里需要指出的是，沟道层相对于源/漏层的凹入在最终器件中可能并不存在。例如，由于上述的硅化处理，源/漏层可能变细了。
在以上实施例中，沟道层使用了IV族Ge系材料，这对于p型器件是特别有利的。例如，可以形成GeSn/Ge/GeSn、Ge/SiGe/Ge、SiGeSn/SiGeSn/SiGeSn(源漏层中Ge、Sn的组分可以大于沟道层中Ge、Sn的组分)、GeSn/SiGeSn/GeSn等堆叠。这种情况下，沟道层中可以具有增强的应变。
根据本公开的另一实施例，沟道层可以使用III-V族化合物半导体材料，同样可以增大开态电流和/或减小关态电流。III-V族化合物半导体材料的沟道层特别适用于n型器件。沟道层III-V族化合物半导体材料可以包括GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、GaN、InSb、InGaSb等之一或它们的组合。沟道层半导体材料也可以包括SiGe、Ge等。
第一源/漏层1005和第二源/漏层1013也可以包括III-V族化合物半导体材料，例如GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、GaN、InSb、InGaSb等。源/漏层中III族元素和V族元素的配比与沟道层中III族元素和V族元素的配比可以不同。备选地，第一源/漏层1005和第二源/漏层1013源/漏层也可以包括IV族半导体材料，例如SiGe、Ge、SiGeSn、GeSn、InSb、InGaSb等。
例如，沟道层1009可以包括InGaAs，厚度为约20-100nm。第一源/漏层1005和第二源/漏层1013可以包括不同于沟道层的半导体材料，例如不同的III-V族化合物半导体材料如InP，厚度为约20-40nm。它们可以如上所述进行掺杂。
同样地，也可以形成泄漏限制层1007和1011。泄漏限制层1007可以包括IV族半导体材料如上述Si1-LR1GeLR1(例如，LR1在0至1之间)或者III-V族化合物半导体材料，泄漏限制层1011可以包括IV族半导体材料如上述Si1-LR2GeLR2(例如，LR2在0至1之间)或者III-V族化合物半导体材料。可以选择LR1、LR2的数值或者III-V族化合物半导体材料的组分和/或组分含量，以使泄漏限制层1007和1011的带隙大于其上方与之邻接的层以及其下方与之邻接的层中至少之一的带隙。例如，泄漏限制层1007可以包括SiGe、Ge、SiGeSn、GeSn、GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、GaN、InSb、InGaSb之一或它们的组合。
为了与这样的半导体叠层相适应，缓冲层1003包括Si1-bGeb(例如，b在约0.5至1之间)。
在以上实施例中，对第一源/漏层1005和第二源/漏层1013进行相同导电类型的掺杂(例如，p型掺杂或n型掺杂)，从而可以形成常规FET(pFET或nFET)。根据本公开的另一实施例，可以对第一源/漏层1005和第二源/漏层1013进行不同导电类型的掺杂(例如，其中一个n型掺杂，其中另一个p型掺杂)，从而形成隧穿FET。沟道层1009可以未有意掺杂(即，为本征层)或者可以轻掺杂。这种掺杂可以在生长这些半导体层时通过原位掺杂得到。
在隧穿FET的情况下，可以不设置两个泄漏限制层，而是仅在隧穿结处设置泄漏限制层。图11示出了这种情况下得到的器件。如图11所示，在沟道层1009与第二源/漏层1013之间设置泄漏限制层1011，而省略了泄漏限制层1007。当然，如果在第一源/漏层与沟道层1009之间发生隧穿，则可以在第一源/漏层与沟道层1009之间设置泄漏限制层1007，而省略泄漏限制层1011。
在以上实施例中，使用了带隙比下层或上层大的泄漏限制层。根据本公开的另一实施例，特别是在隧穿FET的情况下，代替泄漏限制层，可以使用开态电流增强层。在这种情况下，开态电流增强层的带隙可以大于其上方与之邻接的层以及其下方与之邻接的层中至少之一的带隙。为此LR1可以小于x，小于y，或者小于x和y二者；LR2可以小于y，小于z，或者小于y和z二者。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (34)

1.一种半导体器件，包括：
衬底；
依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层，其中，沟道层包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料；以及
绕沟道层的外周形成的栅堆叠。
2.根据权利要求1所述的半导体器件，其中，
对于p型器件，沟道层包括IV族材料体系或III-V族化合物半导材料；
对于n型器件，沟道层包括IV族材料体系或III-V族化合物半导材料。
3.根据权利要求1或2所述的半导体器件，其中，
对于p型器件，第一源/漏层和第二源/漏层包括SiGe、Ge、SiGeSn、InSb、InGaSb或GeSn，沟道层包括SiGe、Ge、SiGeSn、InSb、InGaSb或GeSn；
对于n型器件，第一源/漏层和第二源/漏层包括SiGe、Ge、SiGeSn、GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa或GaN，沟道层包括SiGe、Ge、GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN，源/漏材料和沟道材料的掺杂以及III-V元素化合物元素配比不同。
4.根据权利要求1所述的半导体器件，其中，第一源/漏层和第二源/漏层具有相同导电类型的掺杂，从而所述半导体器件构成竖直型场效应晶体管。
5.根据权利要求1所述的半导体器件，其中，第一源/漏层和第二源/漏层具有不同导电类型的掺杂，从而所述半导体器件构成竖直型隧穿场效应晶体管。
6.根据权利要求4或5所述的半导体器件，还包括：设于第一源/漏层与沟道层之间以及沟道层与第二源/漏层之间的泄漏限制层和/或开态电流增强层。
7.根据权利要求5所述的半导体器件，其中，第一源/漏层和第二源/漏层之一与沟道层构成隧穿结，该半导体器件还包括设于该源/漏层与沟道层之间的泄漏限制层和/或开态电流增强层。
8.根据权利要求6或7所述的半导体器件，其中，
泄漏限制层的带隙大于其上方与之邻接的层和其下方与之邻接的层中至少之一的带隙，
开态电流增强层的带隙小于其上方与之邻接的层和其下方与之邻接的层中至少之一的带隙。
9.根据权利要求6或7所述的半导体器件，还包括：设于泄漏限制层或开态电流增强层两端的介质侧墙。
10.根据权利要求9所述的半导体器件，其中，介质侧墙包括低k介质或气体。
11.根据权利要求10所述的半导体器件，其中，低k介质包括氧化物、氮化物或氮氧化物。
12.根据权利要求6或7所述的半导体器件，其中，泄漏限制层或开态电流增强层包括SiGe、Ge、SiGeSn、GeSn、GaAs、InGaAs、Inp、AlGaAs、InAlAs、InAs、InGa、InAlGa、GaN、InSb、InGaSb之一或它们的组合。
13.根据权利要求1所述的半导体器件，其中，沟道层包括沟道层单晶半导体材料。
14.根据权利要求13所述的半导体器件，其中，沟道层单晶半导体材料与第一、第二源/漏层具有相同的晶体结构。
15.根据权利要求1所述的半导体器件，其中，第一源/漏层是在衬底上外延生长的半导体层，沟道层是在第一源/漏层上外延生长的半导体层，第二源/漏层是在沟道层上外延生长的半导体层。
16.根据权利要求1所述的半导体器件，其中，沟道层的外周相对于第一、第二源/漏层的外周向内凹入，栅堆叠嵌于沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，自对准于沟道层。
17.根据权利要求6或7所述的半导体器件，其中，在第一源漏层、沟道层、第二源/漏层和泄漏限制层或开态电流增强层中的至少一对相邻层之间，具有晶体界面。
18.根据权利要求1所述的半导体器件，其中，在第一源漏层、沟道层和第二源/漏层的至少一对相邻层之间，具有晶体界面。
19.一种制造半导体器件的方法，包括：
在衬底上外延生长第一源/漏层；
在第一源/漏层上外延生长与Si材料相比具有增大开态电流和/或减小关态电流的沟道层；
在沟道层上外延生长第二源/漏层；
在第一源/漏层、沟道层和第二源/漏层中限定该半导体器件的有源区；以及
绕沟道层的外周形成栅堆叠。
20.根据权利要求19所述的方法，还包括：
在第一源/漏层与沟道层之间和/或在沟道层与第二源/漏层之间外延生长泄漏限制层和/或开态电流增强层。
21.根据权利要求19或20所述的方法，其中，限定有源区还包括：
使沟道层的外周相对于第一、第二源/漏层的外周向内凹入。
22.根据权利要求21所述的方法，其中，限定有源区包括：
依次对第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀；以及
进一步选择性刻蚀沟道层，使得沟道层相对于第一、第二源/漏层的外周凹入。
23.根据权利要求22所述的方法，其中，限定的有源区呈柱状，且刻蚀后的第一源/漏层的上部呈柱状而下部延伸超出柱状上部的外周。
24.根据权利要求20所述的方法，还包括：
对泄漏限制层或开态电流增强层进行选择性刻蚀，以使其相对凹入；以及
在泄漏限制层或开态电流增强层的相对凹入中，形成介质侧墙。
25.根据权利要求22或24所述的方法，其中，所述选择性刻蚀为原子层刻蚀或数字化刻蚀。
26.根据权利要求24所述的方法，其中所述形成介质侧墙包括形成低k介质侧墙和/或气体侧墙。
27.根据权利要求21所述的方法，还包括：
对第一源/漏层和第二源/漏层进行掺杂，以在第一源/漏层和第二源/漏层中形成源/漏区。
28.根据权利要求27所述的方法，其中，对第一源/漏层和第二源/漏层进行掺杂包括：对第一源/漏层和第二源/漏层进行相同导电类型的掺杂或不同导电类型的掺杂。
29.根据权利要求27或28所述的方法，其中，进行掺杂包括：
在生长同时进行原位掺杂。
30.根据权利要求21所述的方法，还包括：
在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅；
在衬底上有源区的周围形成隔离层，其中隔离层的顶面靠近沟道层与其下方与之邻接的层之间的界面。
31.根据权利要求30所述的方法，其中，形成栅堆叠包括：
在隔离层上依次形成栅介质层和栅导体层；以及
回蚀栅导体层，使得栅导体层在所述凹入之外的部分的顶面低于沟道层的顶面。
32.一种电子设备，包括由如权利要求1至18中任一项所述的半导体器件形成的集成电路。
33.根据权利要求32所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
34.根据权利要求32所述的电子设备，该电子设备包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或移动电源。
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