CN107887443B - 半导体器件及其制造方法及包括该器件的电子设备 - Google Patents

半导体器件及其制造方法及包括该器件的电子设备 Download PDF

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CN107887443B
CN107887443B CN201710531762.8A CN201710531762A CN107887443B CN 107887443 B CN107887443 B CN 107887443B CN 201710531762 A CN201710531762 A CN 201710531762A CN 107887443 B CN107887443 B CN 107887443B
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source
layer
drain
channel layer
semiconductor device
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CN107887443A (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Abstract

公开了一种半导体器件及其制造方法及包括该器件的电子设备。根据实施例，半导体器件可以包括：衬底；依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层，其中，第一源漏层与沟道层之间和/或沟道层与第二源/漏层之间具有晶体晶面和/或掺杂浓度界面；以及绕沟道层的外周形成的栅堆叠。

Description

半导体器件及其制造方法及包括该器件的电子设备
技术领域
本公开涉及半导体领域，具体地，涉及竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，缩小水平型器件所占的面积，一般要求源极、漏极和栅极所占的面积缩小，使器件性能变差(例如，功耗和电阻增加)，故水平型器件的面积不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件所占的面积更容易缩小。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有改进性能的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层，其中，第一源漏层与沟道层之间和/或沟道层与第二源/漏层之间具有晶体晶面和/或掺杂浓度界面；以及绕沟道层的外周形成的栅堆叠。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上设置第一源/漏层、沟道层和第二源/漏层的叠层，其中，第一源漏层与沟道层之间和/或沟道层与第二源/漏层之间具有晶体晶面和/或掺杂浓度界面；在第一源/漏层、沟道层和第二源/漏层中限定该半导体器件的有源区；以及绕沟道层的外周形成栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括由上述半导体器件形成的集成电路。
根据本公开的实施例，栅堆叠绕沟道层的外周形成且沟道形成于沟道层中，从而栅长由沟道层的厚度确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。沟道层的外周相对于第一、第二源/漏层的外周可以向内凹入，从而栅堆叠可以嵌入该凹入中，减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。另外，沟道层可以是单晶半导体材料，可以具有高载流子迁移率和低泄漏电流，从而改善了器件性能。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至11示出了根据本公开实施例的制造半导体器件的流程的示意图；
图12至21示出了根据本公开另一实施例的制造半导体器件的流程的示意图；
图22(a)至27示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图；
图28示出了根据本公开另一实施例的半导体器件的截面图；
图29和30示出了根据本公开实施例的源/漏层细化处理的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的竖直型半导体器件可以包括在衬底上依次叠置的第一源/漏层、沟道层和第二源/漏层。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和/或开态电流增强层(带隙比相邻层大或小的半导体层)。在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。根据本公开的实施例，这种半导体器件可以是常规场效应晶体管(FET)。在FET的情况下，第一源/漏层和第二源/漏层(或者说，沟道层两侧的源/漏区)可以具有相同导电类型(例如，n型或p型)的掺杂。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。或者，这种半导体器件可以是隧穿FET。在隧穿FET的情况下，第一源/漏层和第二源/漏层(或者说，沟道层两侧的源/漏区)可以具有不同导电类型(例如，分别为n型和p型)的掺杂。这种情况下，带电粒子如电子可以从源区隧穿通过沟道区而进入漏区，从而使源区和漏区之间形成导通路径。尽管常规FET和隧穿FET中的导通机制并不相同，但是它们均表现出可通过栅来控制源/漏区之间导通与否的电学性能。因此，对于常规FET和随穿FET，统一以术语“源/漏层(源/漏区)”和“沟道层(沟道区)”来描述，尽管在隧穿FET中并不存在通常意义上的“沟道”。
栅堆叠可以绕沟道层的外周形成。于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于耗时刻蚀来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。沟道层的外周可以相对于第一、第二源/漏层的外周向内凹入。这样，所形成的栅堆叠可以嵌于沟道层相对于第一、第二源/漏层的凹入中。优选地，栅堆叠在第一源/漏层、沟道层和第二源/漏层的叠置方向(竖直方向，例如大致垂直于衬底表面)上的范围处于所述凹入在该方向上的范围之内。于是，可以减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
沟道层可以由单晶半导体材料构成，以改善器件性能。当然，第一、第二源/漏层也可以由单晶半导体材料构成。这种情况下，沟道层的单晶半导体材料与源/漏层的单晶半导体材料可以是共晶体。沟道层单晶半导体材料的电子或空穴迁移率可以大于第一、第二源/漏层的电子或空穴迁移率。另外，第一、第二源/漏层的禁带宽度可以大于沟道层单晶半导体材料的禁带宽度。
根据本公开的实施例，沟道层单晶半导体材料与第一、第二源/漏层可以具有相同的晶体结构。在这种情况下，第一、第二源/漏层在没有应变的情况下的晶格常数可以大于沟道层单晶半导体材料在没有应变的情况下的晶格常数。于是，沟道层单晶半导体材料的载流子迁移率可以大于其在没有应变的情况下的载流子迁移率，或沟道层单晶半导体材料的载流子的有效质量可以小于其在没有应变的情况下的载流子的有效质量，或沟道层单晶半导体材料的较轻载流子的浓度可以大于其在没有应变的情况下的较轻载流子的浓度。备选地，第一、第二源/漏层在没有应变的情况下的晶格常数可以小于沟道层单晶半导体材料在没有应变的情况下的晶格常数。于是，当沟道层单晶半导体材料的<110>方向与源漏之间的电流密度矢量平行时，沟道层单晶半导体材料的电子迁移率大于其在没有应变的情况下的电子迁移率，或沟道层单晶半导体材料的电子的有效质量小于其在没有应变的情况下的电子的有效质量。
根据本公开的实施例，对于源/漏区的掺杂可以部分地进入沟道层靠近第一源/漏层和第二源/漏层的端部。由此，在沟道层靠近第一源/漏层和第二源/漏层的端部形成掺杂分布，这有助于降低器件导通时源/漏区与沟道区之间的电阻，从而提升器件性能。
根据本公开的实施例，沟道层可以包括与第一、第二源/漏层不同的半导体材料。这样，有利于对沟道层进行处理例如选择性刻蚀，以使之相对于第一、第二源/漏层凹入。另外，第一源/漏层和第二源/漏层可以包括相同的半导体材料。
例如，第一源/漏层可以是半导体衬底自身。这种情况下，沟道层可以是在衬底上外延生长的半导体层，第二源/漏层可以是在沟道层上外延生长的半导体层。备选地，第一源/漏层可以是在衬底上外延生长的半导体层。这种情况下，沟道层可以是在第一源/漏层上外延生长的半导体层，第二源/漏层可以是在沟道层上外延生长的半导体层。
根据本公开的实施例，还可以在第一源/漏层和第二源/漏层的表面上设置应力衬层。对于n型器件，应力衬层可以带压应力，以在沟道层中产生拉应力；对于p型器件，应力衬层可以带拉应力，以在沟道层中产生压应力。因此，可以进一步改善器件性能。
这种半导体器件例如可以如下制造。具体地，可以在衬底上设置第一源/漏层、沟道层和第二源/漏层的叠层。如上所述，可以通过衬底自身或者通过在衬底上外延生长来设置第一源/漏层。接着，可以在第一源/漏层上外延生长沟道层，并可以在沟道层上外延生长第二源/漏层。在外延生长时，可以控制所生长的沟道层的厚度。由于分别外延生长，至少一些相邻层之间可以具有清晰的晶体界面。另外，各层可以分别不同地掺杂，因此至少一些相邻层之间可以具有掺杂浓度界面。
对于叠置的第一源/漏层、沟道层和第二源/漏层，可以在其中限定有源区。例如，可以将它们依次选择性刻蚀为所需的形状。通常，有源区可以呈柱状(例如，圆柱状)。为了便于在后继工艺中连接第一源/漏层中形成的源/漏区，对第一源/漏层的刻蚀可以只针对第一源/漏层的上部，从而第一源/漏层的下部可以延伸超出其上部的外周。然后，可以绕沟道层的外周形成栅堆叠。
另外，可以使沟道层的外周相对于第一、第二源/漏层的外周向内凹入，以便限定容纳栅堆叠的空间。例如，这可以通过选择性刻蚀来实现。这种情况下，栅堆叠可以嵌入该凹入中。
在第一、第二源/漏层中可以形成源/漏区。例如，这可以通过对第一、第二源/漏层掺杂来实现。例如，可以进行离子注入、等离子体掺杂，或者在生长第一、第二源/漏层时原位掺杂。根据一有利实施例，可以在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅，然后在第一、第二源/漏层的表面上形成掺杂剂源层，并通过例如退火使掺杂剂源层中的掺杂剂经第一、第二源/漏层进入有源区中。牺牲栅可以阻止掺杂剂源层中的掺杂剂直接进入沟道层中。但是，可以有部分掺杂剂经由第一、第二源/漏层而进入沟道层靠近第一源/漏层和第二源/漏层的端部。
本公开可以各种形式呈现，以下将描述其中一些示例。
图1至11示出了根据本公开实施例的制造半导体器件的流程图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001上，可以通过例如外延生长，依次形成沟道层1003和另一半导体层1005。例如，沟道层1003可以包括不同于衬底1001、半导体层1005的半导体材料如SiGe(Ge的原子百分比可以为约10-40％)，厚度为约10-100nm；半导体层1005可以包括与衬底1001相同的半导体材料如Si，厚度为约20-50nm。当然，本公开不限于此。例如，沟道层1003可以包括与衬底1001或半导体层1005相同的构成组分，但是组分含量不同的半导体材料(例如，都是SiGe，但是其中Ge的原子百分比不同)，只要沟道层1003相对于之上的衬底1001以及之上的半导体层1005具备刻蚀选择性。
接下来，可以限定器件的有源区。例如，这可以如下进行。具体地，如图2(a)和2(b)(图2(a)是截面图，图2(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图1所示的衬底1001、沟道层1003和半导体层1005的叠层上形成光刻胶(未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状(在该示例中，大致圆形，也可采用其它形状，例如长方形)，并以构图后的光刻胶为掩模，依次对半导体层1005、沟道层1003和衬底1001进行选择性刻蚀如反应离子刻蚀(RIE)。刻蚀进行到衬底1001中，但并未进行到衬底1001的底面处。于是，刻蚀后半导体层1005、沟道层1003以及衬底1001的上部形成柱状(在本示例中，圆柱状)。RIE例如可以按大致垂直于衬底表面的方向进行，从而该柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
然后，如图3所示，可以使沟道层1003的外周相对于衬底1001和半导体层1005的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。例如，这可以通过相对于衬底1001和半导体层1005，进一步选择性刻蚀沟道层1003来实现。例如，可以使用原子层刻蚀(Atomic Layer Etch)或数字化刻蚀(Digital Etch)来进行选择性刻蚀。例如，通过例如热处理，使衬底1001、沟道层1003和半导体层1005的表面氧化，且然后去除它们各自的表面氧化层。在沟道层1003是SiGe且衬底1001和半导体层1005为Si的情况下，SiGe的氧化速率高于Si的氧化速率，且SiGe上的氧化物更易于去除。可以重复氧化-去除氧化物的步骤，以实现所需的凹入。相比于选择性刻蚀，这种方式可以更好地控制凹入的程度。
这样，就限定了该半导体器件的有源区(刻蚀后的衬底1001尤其是其上部、沟道层1003和半导体层1005)。在该示例中，有源区大致呈柱状。在有源区中，衬底1001的上部和半导体层1005的外周实质上对准，而沟道层1003的外周相对凹入。该凹入的上下侧壁分别由沟道层1003与半导体层1005以及沟道层与衬底1001之间的界面限定。
当然，有源区的形状不限于此，而是可以根据没计布局形成其他形状。例如，在俯视图中，有源区可以呈椭圆形、方形、矩形等。
在沟道层1003相对于衬底1001的上部和半导体层1005的外周而形成的凹入中，随后将形成栅堆叠。为避免后继处理对于沟道层1003造成影响或者在该凹入中留下不必要的材料从而影响后继栅堆叠的形成，可以在该凹入中填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过在图3所示的结构上淀积氮化物，然后对淀积的氮化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮化物可仅留在凹入内，形成牺牲栅1007，如图4所示。这种情况下，牺牲栅1007可以基本上填满上述凹入。
接下来，可以在衬底1001和半导体层1005中形成源/漏区。这可以通过对衬底1001和半导体层1005进行掺杂来形成。例如，这可以如下进行。
具体地，如图5所示，可以在图4所示的结构上形成掺杂剂源层1009。例如，掺杂剂源层1009可以包括氧化物如氧化硅，其中含有掺杂剂。对于n型器件，可以包含n型掺杂剂；对于p型器件，可以包含p型掺杂剂。在此，掺杂剂源层1009可以是一薄膜，从而可以通过例如化学气相淀积(CVD)或原子层淀积(ALD)等大致共形地淀积在图4所示结构的表面上。
接着，如图6所示，可以通过例如退火，使掺杂剂源层1009中包含的掺杂剂进入有源区中，从而在其中形成掺杂区，如图中的阴影部分所示。更具体地，可以在衬底1001中形成源/漏区之一1011-1，且在半导体层1005中形成另一源/漏区1011-2。之后，可以去除掺杂剂源层1009。
另外，尽管有牺牲栅1007存在，但是掺杂剂也可以经由衬底1001和半导体层1005而进入沟道层1003中，从而在沟道层1003的上下两端处形成一定的掺杂分布，如图中的椭圆虚线圈所示。这种掺杂分布可以降低器件导通时源漏区之间的电阻，从而提升器件性能。
在以上示例中，通过从掺杂剂源层向有源区中驱入(drive in)掺杂剂来形成源/漏区，但是本公开不限于此。例如，可以通过离子注入、等离子体掺杂(例如，沿着图4中结构的表面进行共形掺杂)等方式，来形成源/漏区。或者，在以上结合图1描述的处理中，可以在衬底1001中形成阱区，然后在之上生长沟道层1003，接着在沟道层1003上生长半导体层1005上对其进行原位掺杂。在生长沟道层1003时，也可以对其进行原位掺杂，以便调节器件的阈值电压(Vt)。
在该示例中，掺杂剂源层1009包括沿衬底1001的水平表面延伸的部分，从而衬底1001中形成的掺杂区延伸超出柱状有源区的外周。这样，在后继工艺中可以容易地通过该掺杂区电连接到源/漏区1011-1。
另外，为了降低接触电阻，还可以对源/漏层进行硅化处理。例如，可以在图6所示的结构上淀积一层NiPt(例如，Pt含量为约2-10％，厚度为约2-10nm)，并在约200-400℃的温度下退火，使NiPt与Si发生反应，从而生成SiNiPt。之后，可以去除未反应的剩余NiPt。
可以在有源区周围形成隔离层，以实现电隔离。例如，如图7所示，可以在图6所示的结构上淀积氧化物，并对其回蚀，以形成隔离层1013。在回蚀之前，可以对淀积的氧化物进行平坦化处理如化学机械抛光(CMP)或溅射。在此，隔离层1013的顶面可以靠近沟道层1003与衬底1001之间的界面。
在形成隔离层时，可以保留牺牲栅1007，以避免隔离层的材料进入要容纳栅堆叠的上述凹入中。之后，可以去除牺牲栅1007，以释放该凹入中的空间。例如，可以相对于隔离层1013(氧化物)以及半导体层1005(Si)和沟道层1003(SiGe)，选择性刻蚀牺牲栅1007(氮化物)。
然后，如图8所示，可以在凹入中形成栅堆叠。具体地，可以在图7所示的结构(去除牺牲栅1007)上依次淀积栅介质层1015和栅导体层1017，并对所淀积的栅导体层1017(以及可选地栅介质层1015)进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1003的顶面。例如，栅介质层1015可以包括高K栅介质如HfO2；栅导体层1017可以包括金属栅导体。另外，在栅介质层1015和栅导体层1017之间，还可以形成功函数调节层。在形成栅介质层1015之前，还可以形成例如氧化物的界面层。
这样，栅堆叠可以嵌入到凹入中，从而与沟道层1003的整个高度相交迭。
另外，取决于隔离层1013的顶面位置，栅堆叠可能与下方的源/漏区1011-1存在一定的交迭(例如，在隔离层1013的顶面低于沟道层1003与衬底1001之间的界面的情况下)，这会增加栅与源/漏之间的寄生电容。因此，优选地，隔离层1013的顶面不低于沟道层1003与衬底1001之间的界面。
接下来，可以对栅堆叠的形状进行调整，以便于后继互连制作。例如，如图9所示，可以在图8所示的结构上形成光刻胶1019。该光刻胶1019例如通过光刻构图为覆盖栅堆叠露于凹入之外的一部分(在该示例中，图中左半部，该部分可以呈从有源区的外周向外沿一定方向延伸的条状)，且露出栅堆叠露于凹入之外的另一部分(在该示例中，图中右半边)。
然后，如图10所示，可以光刻胶1019为掩模，对栅导体层1017进行选择性刻蚀如RIE。这样，栅导体层1017除了留于凹入之内的部分之外，被光刻胶1019遮挡的部分得以保留。随后，可以通过该部分来实现到栅堆叠的电连接。
根据另一实施例，也可以进一步对栅介质层1015进行选择性刻蚀如RIE(图中未示出)。之后，可以去除光刻胶1019。
然后，可以如图11所示，在图10所示的结构上形成层间电介质层1021。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1021。在层间电介质层1021中，可以形成到源/漏区1011-1的接触部1023-1、到源/漏区1011-2的接触部1023-2以及到栅导体层1017的接触部1023-3。这些接触部可以通过在层间电介质层1021以及隔离层1013中刻蚀孔洞，并在其中填充导电材料如金属来形成。
由于栅导体层1017延伸超出有源区外周，从而可以容易地形成它的接触部1023-3。另外，由于衬底1001中的掺杂区延伸超出有源区之外且至少在其一部分上方并不存在栅导体层，从而可以容易地形成它的接触部1023-1。
如图11所示，根据该实施例的半导体器件包括沿竖直方向叠置的衬底1001、沟道层1003和半导体层1005。在衬底1001中形成了源/漏区1011-1，在半导体层1005中形成了源/漏区1011-2。沟道层1003横向凹入，栅堆叠(1015/1017)绕沟道层1003的外周形成，且嵌于该凹入中。
图12至21示出了根据本公开另一实施例的制造半导体器件的流程图。以下，将主要描述本实施例与上述实施例的不同之处。
如图12所示，提供衬底2001。关于衬底，可以参见以上结合图1的描述。在此，同样以体Si衬底为例进行描述。
在衬底2001上，可以通过例如外延生长，依次形成第一源/漏层2031、沟道层2003和第二源/漏层2005。例如，对于p型器件，第一源/漏层2031可以包括SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm；沟道层2003可以包括Si，厚度为约10-100nm；第二源/漏层2005可以包括SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm。SiGe在没有应变的情况下的晶格常数大于Si在没有应变的情况下的晶格常数。第一源/漏层2031、沟道层2003和第二源/漏层2005的材料选择不限于此，可以包括能够提供适当刻蚀选择性的其他半导体材料。例如，对于n型器件，第一源/漏层2031和第二源/漏层2005可以包括Si：C(C的原子百分比可以为约0.1-5％)，厚度为约20-50nm；沟道层2003可以包括Si，厚度为约10-100nm。Si：C在没有应变的情况下的晶格常数小于Si在没有应变的情况下的晶格常数。
根据另一实施例，第一、第二源/漏层可以包括Si1-xGex，沟道层可以包括Si1-yGey，其中x、y在0至1之间，x＜y且y＞0.05(特别是对于n型器件)。或者，第一、第二源/漏层可以包括Si1-xGex，沟道层可以包括Si1-yGey，其中x、y在0至1之间，x＞y且x＞0.05(特别是对于p型器件)。或者，第一、第二源/漏层可以包括Si：C，沟道层可以包括Si1-yGey，其中y≥0(特别是对于n型器件)。
在外延生长第一源/漏层2031和第二源/漏层2005时，可以对它们进行原位掺杂。例如，对于n型器件，可以对第一源/漏层2031和第二源/漏层2005进行n型掺杂；对于p型器件，可以对第一源/漏层2031和第二源/漏层2005进行p型掺杂。另外，还可以对沟道层2003进行原位掺杂，以调节器件的阈值电压(Vt)。例如，对于n型器件，可以对沟道层2003进行p型掺杂；对于p型器件，可以对沟道层2003进行n型掺杂。另外，对于无结器件，可以对第一源/漏层2031、沟道层2003和第二源/漏层2005进行相同类型的掺杂。特别是在源/漏层为Si：C且沟道层为Si的情况下，这种原位掺杂有助于在后继工艺中对它们进行选择性刻蚀。例如，Si：C的第一源/漏层2031和第二源/漏层2005中的掺杂浓度(例如，n型掺杂剂)可以为约1E19-1E21cm-3，而Si的沟道层2003中的掺杂浓度(例如，p型掺杂剂)可以为约1E17-1E19cm-3。
对于各层的掺杂不限于原位掺杂。例如，可以在生长之后通过离子注入或者气相推入等方式来进行掺杂。
接下来，可以限定器件的有源区。如图13所示，可以依次对第二源/漏层2005、沟道层2003和第一源/漏层2031进行选择性刻蚀如RIE。对此，可以参见以上结合图2(a)和2(b)的描述。对于p型器件，在RIE之后，由于SiGe在没有应变的情况下的晶格常数大于Si在没有应变的情况下的晶格常数，在Si中产生应变，此应变会使Si的空穴迁移率大于其在没有应变的情况下的空穴迁移率，或Si的轻空穴的有效质量小于其在没有应变的情况下的轻空穴的有效质量，或Si的轻空穴的浓度大于其在没有应变的情况下的轻空穴的浓度，进而使p型器件的开态电流增加并因此增强了p型器件的性能。备选地，对于n型器件，在RIE之后，由于Si：C在没有应变的情况下的晶格常数小于Si在没有应变的情况下的晶格常数，在Si中产生应变，此应变会使Si的电子迁移率大于其在没有应变的情况下的电子迁移率，或Si的电子的有效质量小于其在没有应变的情况下的电子的有效质量，进而使n型器件的开态电流增加并以此增强了n型器件的性能。
另外，如果选用SiGe作为沟道层材料而用Si作为源/漏层材料，此选择既可以增加p型器件的开态电流，又可以减小p型器件的关态电流，从而增强了p型器件的性能。原因在于Si的禁带宽度大于SiGe的禁带宽度，而SiGe中空穴迁移率大于Si的空穴迁移率。
在该示例中，刻蚀可以进行到第一源/漏层2031，但并未进行到第一源/漏层2031的底面处。但是，本公开不限于此，对第一源/漏层2031的刻蚀电可以进行至第一源/漏层2031的底面。
然后，如图14所示，可以使沟道层2003的外周相对于第一源/漏层2031和第二源/漏层2005的外周凹入。如上所述，这可以通过选择性刻蚀(例如可以使用TMAH溶液进行湿法刻蚀)或者数字刻蚀等处理来实现。对此，可以参见以上结合图3的描述。该凹入的上下侧壁分别由沟道层2003与第二源/漏层2005以及沟道层与第一源/漏层2031之间的界面限定。同样地，可以在沟道层2003相对于第一源/漏层2031和第二源/漏层2005的凹入处，形成牺牲栅2007，如图15所示。
接下来，可以在第一源/漏层2031和第二源/漏层2005中形成源/漏区。这可以按照上述工艺来进行。例如，如图16所示，可以在图15所示的结构上形成掺杂剂源层2009。接着，如图17所示，可以通过例如退火，使掺杂剂源层2009中包含的掺杂剂进入有源区中，从而在其中形成掺杂区，如图中的阴影部分所示。更具体地，可以在第一源/漏层2031中形成源/漏区之一2011-1，且在第二源/漏层2005中形成另一源/漏区2011-2。之后，可以去除掺杂剂源层2009。对此，可以参见以上结合图4至6的描述。
同样地，掺杂剂也可以经由第一源/漏层2031和第二源/漏层2005而进入沟道层2003中，从而在沟道层2003的上下两端处形成一定的掺杂分布，如图中的椭圆虚线圈所示。
当然，由于第一源/漏层2031和第二源/漏层2005如上所述在生长时已被掺杂，故而可以省略形成掺杂剂源层并从掺杂剂源层向源/漏层中驱入掺杂剂的该步骤。即便如此，也可以进行退火处理，以使第一源/漏层2031和第二源/漏层2005中的掺杂剂进入沟道层2003中，从而在沟道层2003的上下两端处形成一定的掺杂分布。
可以在有源区周围形成隔离层，以实现电隔离。例如，如图18所示，可以在图17所示的结构上形成隔离层2013。在此，隔离层2013的顶面可以位于沟道层2003的顶面与底面之间，这有助于形成自对准的栅堆叠。之后，可以去除牺牲栅2007，以释放该凹入中的空间。关于隔离层的详细描述，可以参见以上结合图7的描述。
然后，如图19所示，可以在凹入中形成栅堆叠。具体地，栅堆叠包括栅介质层2015和栅导体层2017。对此，可以参见以上结合图8的描述。由于隔离层2013的顶面设置，栅堆叠仅与沟道层2003在竖直方向上的侧面相交迭，而与第一、第二源/漏层各自在竖直方向上的侧面不交迭。即，栅堆叠自对准于沟道层2003。
接下来，如图20所示，可以对栅堆叠的形状进行调整，以便于后继互连制作。然后，可以如图21所示，在图20所示的结构上形成层间电介质层2021并在层间电介质层2021中形成到源/漏区2011-1的接触部2023-1、到源/漏区2011-2的接触部2023-2以及到栅导体层2017的接触部2023-3。对此，可以参见以上结合图9至11的描述。
图22(a)至27示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图。以下，将主要描述本实施例与上述实施例的不同之处。
在如以上结合图9和10所述对栅导体层1017进行构图之后，可以进一步处理，以露出衬底1001和半导体层1005的表面(半导体层1005的表面事实上已经露出在外)，特别是即将要在之上形成接触部的上表面。为此，如图22(a)和22(b)(图22(a)是截面图，图22(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以对栅介质层1015和隔离层1013进行选择性刻蚀如RIE。RIE可以沿大致垂直于衬底表面的方向进行。于是，除了留于栅堆叠和沟道层下方的部分之外，衬底1001的上表面被露出。
然后，可以在图22(a)和22(b)所示的结构上形成一应力衬层1201，如图23所示。例如，可以通过大致共形地淀积一层氮化物层，来形成应力衬层1201。应力衬层1201的厚度可以为约10-50nm。对于n型器件，应力衬层1201可以带压应力，以在沟道层中产生拉应力；而对于p型器件，应力衬层1201可以带拉应力，以在沟道层中产生压应力。
如图23所示，应力衬层1201可以覆盖半导体层1005以及衬底1001的上表面，于是可以保护有源区，而且可以在随后的接触孔刻蚀时充当刻蚀停止层。
之后，可以如以上结合图11所述，形成层间电介质层1021，如图24所示。然后，在层间电介质层1021中，可以形成各种接触部。
具体地，如图25所示，可以在层间电介质层1021上形成光刻胶1203，并通过光刻将光刻胶1203构图为露出要形成接触孔的部分。之后，以构图后的光刻胶1203为掩模，对层间电介质层1021进行选择性刻蚀如RIE。在此，RIE可以停止于应力衬层1201。
参见图11，由于到源/漏区1011-1的接触部1023-1、到源/漏区1011-2的接触部1023-2以及到栅导体层1017的接触部1023-3具有不同的高度，因此对于接触孔的刻蚀是困难的。而在该实施例中，由于应力衬层1201的存在，可以相对容易地控制接触孔刻蚀的停止。
然后，如图26所示，可以进一步对应力衬层1201进行刻蚀如RIE。在此，RIE可以停止于半导体材料的衬底1001和半导体层1005上。由于应力衬层1201可以具有基本上均匀的厚度，因而对应力衬层1201的刻蚀可以相对容易地控制。
之后，如图27所示，可以通过向接触孔中填充导电材料如金属(例如，W)等，来形成各接触部。在填充金属之前，可以在接触孔的内壁上形成阻挡层如TiN。
图28示出了根据本公开另一实施例的半导体器件的截面图。
图28所示的半导体器件与图21所示的半导体器件基本上相同，除了还包括应力衬层2201之外。关于应力衬层2201，可以参见以上关于应力衬层1201的描述。
根据本公开的另一实施例，所形成的接触部例如上述1023-1、1023-2、1023-3或2023-1、2023-2、2023-3中的至少之一可以是带应力或应变的，例如由带应力或应变金属形成。例如，到沟道层上方的源/漏层即第二源漏层的接触部1023-2或2023-2对于n型器件可以带拉应力，而对于p型器件可以带压应力。到沟道层下方的源/漏层即第一源/漏层的接触部1023-1或2023-1对于n型器件可以带压应力，而对于p型器件可以带拉应力。到栅导体的接触部1023-3或2023-3对于n型器件可以带压应力，而对于p型器件可以带拉应力。
在此需要指出的是，尽管在以上实施例中使沟道层相对于源/漏层凹入以便能形成自对准的牺牲栅或栅堆叠，但是这种凹入在最终的器件结构中可能并不存在。例如，由于如上所述的硅化处理，源/漏层的外周表面向内缩回。或者，为了降低源/漏与栅之间的电容，还可以对源/漏层进行细化处理，并部分地用低k介质替代。例如，如图29所示，可以在图17所示的结构中，选择性刻蚀源/漏层，使其变细(甚至可以细于沟道层)。之后，如图30所示，可以通过侧墙(spacer)形成工艺，利用低k介质来形成低k介质侧墙2007′。之后，在去除牺牲栅2007之后，仍然存在“凹入”，但这是沟道层2003相对于低k介质侧墙2007′(而并非是相对于源/漏层)的凹入。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (37)

1.一种半导体器件，包括：
衬底；
依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层，其中，第一源/漏层与沟道层之间和/或沟道层与第二源/漏层之间具有晶体晶面和/或掺杂浓度界面；以及
绕沟道层的外周形成的栅堆叠，其中栅堆叠包括栅导体层和栅介质层，
其中，栅堆叠自对准于沟道层。
2.根据权利要求1所述的半导体器件，其中，沟道层的外周相对于第一、第二源/漏层的外周凹入，且栅堆叠嵌于沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，其中栅堆叠靠近沟道层一侧的端部具有与沟道层的底面共面的底面以及与沟道层的顶面共面的顶面，栅介质层包括设于栅导体层与沟道层之间的部分以及分别沿着第一源/漏层的顶面和第二源/漏层的底面延伸的部分。
3.根据权利要求1或2所述的半导体器件，其中，沟道层包括沟道层单晶半导体材料。
4.根据权利要求3所述的半导体器件，其中，沟道层单晶半导体材料与第一、第二源/漏层具有相同的晶体结构。
5.根据权利要求4所述的半导体器件，其中，第一、第二源/漏层在没有应变的情况下的晶格常数大于沟道层单晶半导体材料在没有应变的情况下的晶格常数。
6.根据权利要求5所述的半导体器件，其中，沟道层单晶半导体材料的载流子迁移率大于其在没有应变的情况下的载流子迁移率，或沟道层单晶半导体材料的载流子的有效质量小于其在没有应变的情况下的载流子的有效质量，或沟道层单晶半导体材料的较轻载流子的浓度大于其在没有应变的情况下的较轻载流子的浓度。
7.根据权利要求4所述的半导体器件，其中，第一、第二源/漏层在没有应变的情况下的晶格常数小于沟道层单晶半导体材料在没有应变的情况下的晶格常数。
8.根据权利要求7所述的半导体器件，其中，当沟道层单晶半导体材料的<110>方向与源/漏之间的电流密度矢量平行时，沟道层单晶半导体材料的电子迁移率大于其在没有应变的情况下的电子迁移率，或沟道层单晶半导体材料的电子的有效质量小于其在没有应变的情况下的电子的有效质量。
9.根据权利要求3所述的半导体器件，其中，沟道层单晶半导体材料的电子或空穴迁移率大于第一、第二源/漏层的电子或空穴迁移率。
10.根据权利要求3所述的半导体器件，其中，第一、第二源/漏层的禁带宽度大于沟道层单晶半导体材料的禁带宽度。
11.根据权利要求1所述的半导体器件，其中，沟道层靠近第一源/漏层和第二源/漏层的端部具有掺杂分布。
12.根据权利要求1所述的半导体器件，还包括：
在衬底上形成的隔离层，其中隔离层的顶面靠近沟道层与第一源/漏层之间的界面或者处于沟道层的顶面与底面之间。
13.根据权利要求1所述的半导体器件，其中，第一源/漏层和第二源/漏层包括相同的半导体材料。
14.根据权利要求1所述的半导体器件，其中，第二源/漏层的外周与第一源/漏层的至少上部的外周实质上对准。
15. 根据权利要求1所述的半导体器件，其中，
第一源/漏层是衬底的一部分，沟道层是在衬底上外延生长的半导体层，第二源/漏层是在沟道层上外延生长的半导体层；或者
第一源/漏层是在衬底上外延生长的半导体层，沟道层是在第一源/漏层上外延生长的半导体层，第二源/漏层是在沟道层上外延生长的半导体层。
16.根据权利要求1所述的半导体器件，其中，沟道层包括与第一、第二源/漏层不同的半导体材料。
17. 根据权利要求1所述的半导体器件，其中，
第一、第二源/漏层包括Si1-xGex，沟道层包括Si1-yGey, 其中x < y和y > 0.05；或者
第一、第二源/漏层包括Si1-xGex，沟道层包括Si1-yGey, 其中x > y和x > 0.05；或者
第一、第二源/漏层包括Si:C，沟道层包括Si1-yGey, 其中y ≥ 0。
18.根据权利要求1所述的半导体器件，其中，所述第一源/漏层、沟道层和第二源/漏层被掺杂。
19.根据权利要求1所述的半导体器件，还包括在第一源/漏层和第二源/漏层的表面上设置的应力衬层。
20.根据权利要求19所述的半导体器件，其中，对于n型器件，应力衬层带压应力，以在沟道层中产生拉应力；对于p型器件，应力衬层带拉应力，以在沟道层中产生压应力。
21.根据权利要求2所述的半导体器件，其中，栅堆叠在第一源/漏层、沟道层和第二源/漏层的叠置方向上的范围处于所述凹入在该方向上的范围之内。
22.根据权利要求1所述的半导体器件，还包括：
位于第一源/漏层上方到第一源/漏层的第一接触部、位于第二源/漏层上方到第二源/漏层的第二接触部以及位于栅堆叠上方到栅堆叠的第三接触部，
其中，第一接触部、第二接触部和第三接触部中至少之一带应力。
23.根据权利要求22所述的半导体器件，其中，
第一接触部对于n型器件带压应力，而对于p型器件带拉应力；
第二接触部对于n型器件带拉应力，而对于p型器件带压应力；
第三接触部对于n型器件带压应力，而对于p型器件带拉应力。
24.一种制造半导体器件的方法，包括：
在衬底上设置第一源/漏层、沟道层和第二源/漏层的叠层，其中，第一源/漏层与沟道层之间和/或沟道层与第二源/漏层之间具有晶体晶面和/或掺杂浓度界面；
依次对第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀；
进一步相对于第一、第二源/漏层而选择性刻蚀沟道层，使得沟道层相对于第一、第二源/漏层的外周凹入，从而在第一源/漏层、沟道层和第二源/漏层中限定该半导体器件的有源区；
在衬底上有源区的周围形成隔离层，其中隔离层的顶面靠近沟道层与第一源/漏层之间的界面或者处于沟道层的顶面与底面之间；
在隔离层上依次形成栅介质层和栅导体层；以及
回蚀栅导体层，使得栅导体层在所述凹入之外的部分的顶面低于沟道层的顶面，从而绕沟道层的外周形成栅堆叠，栅堆叠嵌于沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，从而栅堆叠自对准于沟道层。
25. 根据权利要求24所述的方法，其中，设置第一源/漏层包括：
通过衬底来提供该第一源/漏层；或者
在衬底上外延生长该第一源/漏层。
26.根据权利要求24所述的方法，其中，选择性刻蚀是原子层刻蚀或数字化刻蚀。
27.根据权利要求24所述的方法，其中，限定的有源区呈柱状，且刻蚀后的第一源/漏层的上部呈柱状而下部延伸超出柱状上部的外周。
28.根据权利要求24所述的方法，还包括：
对第一源/漏层和第二源/漏层进行掺杂，以在第一源/漏层和第二源/漏层中形成源/漏区。
29.根据权利要求28所述的方法，其中，进行掺杂包括：
在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅；
在第一源/漏层和第二源/漏层的表面上形成掺杂剂源层；以及
使掺杂剂源层中的掺杂剂经第一、第二源/漏层进入有源区中。
30.根据权利要求29所述的方法，其中，掺杂剂不仅进入第一、第二源/漏层中，还进入沟道层靠近第一源/漏层和第二源/漏层的端部。
31.根据权利要求24所述的方法，还包括：在第一源/漏层和第二源/漏层的表面上形成应力衬层。
32.根据权利要求31所述的方法，其中，
形成栅堆叠包括：将栅堆叠构图为包括环绕沟道层延伸的部分以及沿远离沟道层的方向延伸的部分，
形成应力衬层包括：
露出第二源/漏层的上表面以及第一源/漏层除了被栅堆叠和沟道层所覆盖的部分之外的上表面部分；
在第一源/漏层和第二源/漏层以及栅堆叠的露出上表面上形成应力衬层。
33.根据权利要求32所述的方法，其中，应力衬层还充当接触孔刻蚀时的刻蚀停止层。
34.根据权利要求24所述的方法，还包括：
在第一源/漏层上方形成到第一源/漏层的第一接触部，在第二源/漏层上方形成到第二源/漏层的第二接触部，在栅堆叠上方形成到栅堆叠的第三接触部，
其中，第一接触部、第二接触部和第三接触部中至少之一带应力。
35.一种电子设备，包括由如权利要求1至23中任一项所述的半导体器件形成的集成电路。
36.根据权利要求35所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
37.根据权利要求35所述的电子设备，该电子设备包括智能电话、计算机、平板电脑、可穿戴设备或移动电源。
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