CN107887386A - 集成电路单元及其制造方法及包括该单元的电子设备 - Google Patents

集成电路单元及其制造方法及包括该单元的电子设备 Download PDF

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CN107887386A
CN107887386A CN201710530950.9A CN201710530950A CN107887386A CN 107887386 A CN107887386 A CN 107887386A CN 201710530950 A CN201710530950 A CN 201710530950A CN 107887386 A CN107887386 A CN 107887386A
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source drain
channel layer
periphery
layer
integrated circuit
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CN107887386B (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

公开了一种集成电路单元及其制造方法及包括该集成电路单元的电子设备。根据实施例，集成电路单元可以包括：彼此叠置在衬底上的第一器件和第二器件，其中第一器件和第二器件各自均包括依次叠置的第一源/漏层、沟道层和第二源/漏层以及绕沟道层外周形成的栅堆叠，其中，第一器件的沟道层和第二器件的沟道层至少之一包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料。

Description

集成电路单元及其制造方法及包括该单元的电子设备
技术领域
本公开涉及半导体领域，具体地，涉及基于竖直型器件的集成电路单元及其制造方法以及包括这种集成电路单元的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件所占的面积不易进一步缩小或制造成本不易进一步降低。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小或制造成本更易降低。纳米线(nanowire)竖直型环绕栅场效应晶体管(V-GAAFET，Vertical Gate-all-around Field Effect Transistor)是未来高性能器件的候选之一。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种基于堆叠竖直型器件且具有改进特性的集成电路单元及其制造方法以及包括这种集成电路单元的电子设备。
根据本公开的一个方面，提供了一种集成电路单元，包括：彼此叠置在衬底上的第一器件和第二器件，其中第一器件和第二器件各自均包括依次叠置的第一源/漏层、沟道层和第二源/漏层以及绕沟道层外周形成的栅堆叠，其中，第一器件的沟道层和第二器件的沟道层至少之一包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料。
根据本公开的另一方面，提供了一种制造集成电路单元的方法，包括：在衬底上设置第一器件的第一源/漏层、沟道层和第二源/漏层以及第二器件的第一源/漏层、沟道层和第二源/漏层的叠层，其中第一器件的沟道层与第二器件的沟道层至少之一包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料；分别选择性刻蚀第二器件的沟道层和第一器件的沟道层，使得第二器件的沟道层的外周相对于第二器件的第一源/漏层和第二源/漏层的外周向内凹入，第一器件的沟道层的外周相对于第一器件的第一源/漏层和第二源/漏层的外周向内凹入；以及分别绕第二器件的沟道层和第一器件的沟道层的外周形成第二器件的栅堆叠和第一器件的栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括上述集成电路单元。
根据本公开的实施例，衬底上叠置的器件中至少之一可以包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料，于是可以优化性能。例如，对于n型器件，可以利用有利于增强电子迁移率的材料如SiGe、Ge或III-V族材料如GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN之一或它们的组合等；对于p型器件，可以利用有利于增强空穴迁移率的材料如SiGe、Ge、SiGeSn、InSb、InGaSb或GeSn等。
根据本公开的实施例，沟道层可以实现为纳米线的形式，源/漏层可以分设于纳米线的上下两侧，且栅堆叠可以环绕沟道层的外周形成，从而形成纳米线竖直型环绕栅场效应晶体管(V-GAAFET)结构。可以竖直堆叠多个(不同导电类型的)纳米线V-GAAFET，以提升集成度。沟道形成于沟道层中，从而栅长由沟道层的厚度确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1(a)是示出了根据本公开实施例的集成电路单元的简化结构图；
图1(b)是示出了根据本公开实施例的集成电路单元用作反相器时的电路图；
图2至19示出了根据本公开实施例的制造集成电路单元的流程的示意图；以及
图20示出了根据本公开另一实施例的集成电路单元的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
图1(a)是示出了根据本公开实施例的集成电路单元的简化结构图。
如图1(a)所述，根据该实施例的集成电路单元100基于在竖直方向上叠置的竖直型器件。在本例中，以叠置不同导电类型的器件如pFET和nFET为例进行描述，但是本公开不限于此。例如，可以叠置相同导电类型的器件。在图1(a)的示例中，nFET叠置在pFET上。但是，本公开不限于此，例如pFET可以叠置在nFET上。在此，各竖直型器件可以包括(在衬底上)依次叠置的第一源/漏层、沟道层和第二源/漏层。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和开态电流增强层(带隙比相邻层大或小的半导体层)。具体地，pFET可以包括p型器件第一源/漏层103、p型器件沟道层105-1、105-2以及p型器件第二源/漏层107，nFET可以包括n型器件第一源/漏层109、n型器件沟道层111以及n型器件第二源/漏层113。在以下描述中，除非另外明确指出，否则在同时使用“沟道层”和“第一/第二源/漏层”的情况下，是指同一器件的沟道层和第一/第二源漏层。
在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。栅堆叠可以绕沟道层的外周形成。具体地，pFET的栅堆叠(包括栅介质层125和栅导体层127)可以环绕p型器件沟道层105-1、105-2，nFET的栅堆叠(包括栅介质层125和栅导体层131)可以环绕n型器件沟道层111。在此，沟道层可以形成为纳米线的形式，从而得到纳米线竖直型环绕栅场效应晶体管(V-GAAFET)器件。另外，在该示例中，nFET和pFET包括相同的栅介质层125，但是本公开不限于此，例如它们可以具有不同的栅介质层。
于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于平坦化(如CMP)和/或时控刻蚀来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。
各层可以分别生长，从而至少一对相邻的半导体层之间可以具有清晰的晶体界面)。另外，各层可以分别进行掺杂，从而至少一对相邻的半导体层之间可以具有掺杂浓度界面。另外，可以相对自由地选择各层的材料，例如针对nFET和pFET采用不同的材料或者选择新型材料如SiGe、Ge或III-V族材料等，以便改善器件性能。在此，叠置的器件中至少之一可以包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料。特别是，不同导电类型的器件可以具有不同的沟道层材料，于是可以针对不同导电类型器件分别优化性能。例如，对于nFET，沟道层可采用有利于改进电子迁移率的半导体材料，例如SiGe、Ge或III-V族材料如GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN之一或它们的组合；对于pFET，沟道层可采用有利于改进空穴迁移率的半导体材料，例如SiGe、Ge、SiGeSn、InSb、InGaSb或GeSn。
沟道层的外周可以相对于第一、第二源/漏层的外周向内凹入。这样，所形成的栅堆叠可以嵌于沟道层相对于第一、第二源/漏层的凹入中，减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
沟道层可以由单晶半导体材料构成，以改善器件性能。当然，第一、第二源/漏层也可以由单晶半导体材料构成。这种情况下，沟道层的单晶半导体材料与源/漏层的单晶半导体材料可以具有相同的晶体结构。
根据本公开的实施例，第一、第二源/漏层可以包括与沟道层不同的半导体材料(但可以属于相同的材料体系，例如，对于n型器件，源/漏层与沟道层可以包括不同的IV族半导体材料和不同的III-V族化合物半导体材料，例如SiGe、Ge或III-V族材料如GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN；对于p型器件，源/漏层与沟道层也可以包括不同的IV族半导体材料和不同III-V族化合物半导体材料，例如SiGe、SiGeSn、InSb、InGaSb或GeSn。这样，有利于对沟道层进行处理例如选择性刻蚀，以使之相对于第一、第二源/漏层凹入。另外，第一源/漏层和第二源/漏层可以包括相同的半导体材料。
为了节省占用面积，上方的器件(在本例中，nFET)可以完全叠置于下方的器件(在本例中，pFET)的上方。也即，在俯视图中，上方的器件(特别是其有源区)的外廓不超出下方的器件(特别是其有源区)的外廓。
在本例中，考虑到nFET和pFET驱动能力的差异(电子的迁移率通常是空穴的迁移率的两倍)，为提供对称的电路设计，在此可以提供两个pFET器件(图1(a)中所示的pFET1和pFET2)和一个nFET器件。两个pFET器件pFET1和pFET2通过共用相同的第一源/漏层103和第二源/漏层107而彼此并接，且它们共用相同的栅堆叠125/127。因此，两个pFET器件pFET1和pFET2相当于单个pFET器件操作(因此，在以下描述中，将pFET1和pFET2一体示出为pFET)，但驱动能力为单个pFET的两倍(从而与单个nFET器件的驱动能力基本相同)。
由于需要提供两个pFET器件，故而p型器件沟道层包括彼此分离的两个部分105-1、105-2(这两个部分可以具有基本上相同的尺寸)，从而提供两个沟道。这两个部分或者说沟道可以并联连接。在这种情况下，pFET有源区的面积大于nFET有源区的面积。故而在本例中，将pFET设置于下方，而nFET叠置于pFET上。这可以使得接触部不会占用额外的面积，如以下进一步详细所述。
nFET的沟道层111可以与pFET的沟道层的两个部分105-1、105-2之一(在图1(a)所示的示例中，右侧的105-2)在竖直方向上基本对准。pFET的沟道层的另一部分(在图1(a)所示的示例中，左侧的105-1)相对于nFET的沟道层111在横向上偏移。
在本例中，pFET的第二源/漏层107和nFET的第一源/漏层109彼此交迭(在该示例中，彼此物理接触)，并可以电连接在一起。因此，pFET和nFET串接在一起。为了更好的电连接，nFET的第一源/漏层109可以在pFET的第二源/漏层107的基本上整个上表面上延伸。例如，nFET的第一源/漏层109的外周可以与pFET的第二源/漏层107的外周基本上重合(在俯视图中基本上重合)。
为了易于制造到nFET的第一源/漏层109(以及pFET的第二源/漏层107)的接触部137-OUT，nFET的第一源/漏层109(以及pFET的第二源/漏层107)可以相对于其上方的器件功能层(有源区中各材料层、栅堆叠等)特别是nFET的第二源/漏层113伸出。因为nFET的第二源/漏层113位于nFET的沟道层111上方(在nFET的沟道层111与pFET的沟道层105-2基本上对准的情况下，也因此位于pFET的沟道层105-2上方)，而第一源/漏层109(以及pFET的第二源/漏层107)需要延伸到pFET的沟道层105-1上方，所以nFET的第一源/漏层109(以及pFET的第二源/漏层107)可以相对于nFET的第二源/漏层113在向着pFET的沟道层105-1的方向上伸出(图1(a)中向着左侧伸出)。这样，不需要额外的面积来设置这样的伸出。于是，接触部137-OUT可以处于nFET的第一源/漏层109(以及pFET的第二源/漏层107)上方，而不占用额外的面积。
类似地，为了易于制造到pFET的第一源/漏层103的接触部137-Vdd，pFET的第一源/漏层103可以相对于其上方的器件功能层特别是pFET的第二源/漏层107(以及nFET的第一源/漏层109)伸出(图1(a)中向着左侧伸出)。于是，接触部137-Vdd可以处于pFET的第一源/漏层103上方，而不占用额外的面积。
同样地，为了易于制造到栅堆叠的接触部137-IN，nFET的栅堆叠125/131可以相对于其上方的器件功能层特别是nFET的第二源/漏层113伸出(图1(a)中向着右侧伸出)，类似地pFET的栅堆叠125/131可以相对于其上方的器件功能层特别是nFET的第二源/漏层113、nFET的第一源/漏层109以及pFET的第二源/漏层107伸出。为了避免与接触部137-OUT之间的相互影响，栅堆叠可以向着与nFET的第一源/漏层109以及pFET的第二源/漏层107相对于nFET的第二源/漏层113伸出的方向不同例如相反的方向伸出(图1(a)中向着右侧伸出)。于是，接触部137-IN可以位于栅堆叠上方，而不占用额外的面积。在该示例中，nFET的栅堆叠和pFET的栅堆叠电连接在一起，从而共用相同的接触部137-IN。
另外，在该集成电路单元中，由于nFET的第二源/漏层113位于有源区的最上方，所以可以在nFET的第二源/漏层113上方设置到nFET的第二源/漏层113的接触部137-GND，而不占用额外面积。
因此，在该集成电路单元100中，所有接触部137-Vdd、137-GND、137-IN和137-OUT可以与集成电路单元100中的V-GAAFET共享面积，而不占用额外面积。相比于按常规工艺制造的互补金属氧化物半导体(CMOS)或水平型环绕栅场效应晶体管(H-GAAFET)，面积可以减小约30-40％。
图1(b)示出了图1(a)所示的集成电路单元用作反相器时的电路图。
如上所述，nFET和pFET串接在一起，且它们的栅极电连接在一起，可以通过接触部137-IN接收输入信号IN。pFET的源/漏极之一可以通过接触部137-Vdd接收供电电压，而nFET的源/漏极之一可以通过接触部137-GND接地。pFET和nFET彼此连接在一起的源/漏极可以通过接触部137-OUT输出输出信号OUT。该输出信号OUT是输入信号IN的反相信号。于是，在这种连接方式下，该集成电路单元构成反相器。
当然，这种nFET和pFET相串接的集成电路单元不限于用作反相器，也可以用作其他功能部件或者功能部件的组成部分。
这种半导体器件例如可以如下制造。具体地，可以在衬底上设置p型器件第一源/漏层、p型器件沟道层和p型器件第二源/漏层以及n型器件第一源/漏层、n型器件沟道层和n型器件第二源/漏层的叠层(得到nFET叠置在pFET上的结构)。当然，n型器件的各层可以设置在下侧，而p型器件的各层可以设置在上侧(得到pFET叠置在nFET上的结构，这种情况下，可以将以下描述中的p型和n型互换)。如上所述，可以通过外延生长，来依次形成各层。在外延生长时，可以控制所生长的各层特别是沟道层的厚度。另外，在外延生长时，可以对源/漏层进行原位掺杂。可选地，可以对沟道层进行原位掺杂。
对于所设置的叠层，可以在其中限定有源区。在限定有源区时，可以将叠层中的至少部分层选择性刻蚀为所需的形状。例如，可以选择性刻蚀n型器件沟道层和p型器件沟道层，使得n型器件沟道层的外周相对于n型器件第一源/漏层和n型器件第二源/漏层的外周向内凹入，p型器件沟道层的外周相对于p型器件第一源/漏层和p型器件第二源/漏层的外周向内凹入。如上所述，可以将p型器件沟道层分离为彼此间隔开的第一部分和第二部分。这些凹入可以限定容纳栅堆叠的空间。然后，可以分别绕n型器件沟道层和p型器件沟道层的外周形成n型器件栅堆叠和p型器件栅堆叠。
如上所述，为了便于接触部的制造，可以选择性刻蚀n型器件第二源/漏层，使得处于叠层最上方的n型器件第二源/漏层相对于其他源/漏层具有缩减的面积(即，其他源/漏层相对于n型器件第二源/漏层伸出)，从而不妨碍到其他源/漏层的接触部的形成。n型器件沟道层可以被选择性刻蚀为相对于被选择性刻蚀后的n型器件第二源/漏层凹入。
类似地，如上所述，为了便于接触部的制造，可以选择性刻蚀n型器件第一源/漏层和p型器件第二源/漏层，使得它们相对于被选择性刻蚀后的n型器件第二源/漏层伸出，但相对于p型器件第一源/漏层具有缩减的面积。这样，一方面可以方便地制造到n型器件第一源/漏层和p型器件第二源/漏层的接触部，另一方面可以不妨碍到p型器件第一源/漏层的接触部的制造。选择性刻蚀可以包括原子层刻蚀(Atomic Layer etch)或数字化刻蚀(Digital Etch)。
另外，为了形成如上所述伸出且因此便于接触部制造的栅堆叠，可以使用替代栅技术。例如，可以在各沟道层的相应凹入中分别形成牺牲栅。之后，可以利用n型器件栅堆叠和p型器件栅堆叠分别替换牺牲栅。替代栅工艺可以结合在对有源区的限定过程中，以保留合适的栅位置。
根据本公开的实施例，由于n型器件和p型器件各自的有源区材料的不同(例如，分别为III-V族化合物半导体材料和IV族半导体材料)，从而可以对n型器件和p型器件的有源区分别进行处理。
在该示例中，由于n器件叠置在p型器件之上，从而先对上方的n型器件进行处理。在对n型器件进行处理时，可以遮蔽p型器件的有源区。例如，可以选择性刻蚀n型器件沟道层从而使其相对于n型器件第二源/漏层凹入，然后可以在该凹入中形成第一牺牲栅，以保留针对n型器件的栅位置。然后，可以进一步选择性刻蚀n型器件第一源/漏层和n型器件第二源/漏层，使它们的面积缩减，从而第一牺牲栅具有相对于n类型器件第二源/漏层的伸出部分。
接着，可以对p型器件进行处理，此时可以遮蔽n型器件的有源区。例如，可以选择性刻蚀p型器件沟道层从而使其相对于p型器件第二源/漏层凹入，然后可以在该凹入中形成第二牺牲栅，以保留针对p型器件的栅位置。然后，可以可以进一步选择性刻蚀p型器件第二源/漏层，使其面积缩减，从而第二牺牲栅具有相对于p型器件第二源/漏层(以及n型器件第一源/漏层)的伸出部分。选择性刻蚀可以包括原子层刻蚀(Atomic Layer etch)或数字化刻蚀(Digital Etch)。
于是，牺牲栅相对于各自上方的有源层伸出。由于最后形成的n型器件栅堆叠和p型器件栅堆叠占据了牺牲栅所在的位置，从而也相对于各自上方的有源层伸出，并因此可以容易地制造到它们的接触部。
本公开可以各种形式呈现，以下将描述其中一些示例。
图2至19示出了根据本公开实施例的制造集成电路单元的流程的示意图。
如图2所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在该示例中，对于将要在衬底1001上形成的器件，通过半导体材料选择(例如，非硅材料)来改善其性能。为了改善之后生长的其他半导体材料层的质量，可以在衬底1001上，例如通过外延生长，形成缓冲层1101。在如下所述在衬底1001上先制造p型器件然后在p型器件上叠置n型器件的情况下，特别是针对p型器件使用IV族半导体材料的情况下，缓冲层1101可以包括Ge，厚度为例如约200nm至几个微米。
在缓冲层1101上，可以形成p型层1103和n型层1105。例如，这可以通过在缓冲层1101上外延生长Ge，并在生长同时进行原位掺杂(分别掺杂p型杂质如B或BF2以及n型杂质如P或As)来形成。由于缓冲层1101的存在，p型层1103和n型层1105可以是弛豫的。
如果在衬底1001上先制造p型器件然后在p型器件上叠置n型器件，则可以在衬底1001中，形成p型层1103在下而n型层1105在上的结构。p型层1103中杂质的浓度可以为约1E17-1E20cm-3，n型层1105中杂质的浓度可以为约1E17-2E18cm-3。
如果在衬底1001上先制造n型器件然后在n型器件上叠置p型器件，则可以在衬底1001中，形成p型层1103在上而n型层1105在下的结构。这种情况下，p型层1103中杂质的浓度可以为约1E17-2E18cm-3，n型层1105中杂质的浓度可以为约1E17-1E20cm-3。
这种p型层1103和n型层1105可以在后继提供电隔离。
在以下示例中，以先制造p型器件然后在p型器件上叠置n型器件为例进行描述。
在n型层1105上，可以通过例如外延生长，依次形成用于p型器件的有源材料层即p型器件第一源/漏层1003、p型器件沟道层1005和p型器件第二源/漏层1007以及用于n型器件的有源材料层即n型器件第一源/漏层1009、n型器件沟道层1011和n型器件第二源/漏层1013。在此，对于p型器件沟道层，可以选择有利于增强空穴迁移率(例如，相对于硅材料)的半导体材料如SiGe(Ge的原子百分比可以为约25-75％)、Ge、InSb、InGaSb或GeSn；对于n型器件沟道层，可以选择有利于增强电子迁移率(例如，相对于硅材料)的半导体材料如SiGe、Ge或III-V族化合物半导体材料，例如SiGe、Ge或III-V族材料GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN。
p型器件源/漏层可以包括相同的半导体材料，但可以不同于沟道层的半导体材料，例如不同的IV族半导体材料和不同III-V族化合物半导体材料，例如SiGe(Ge的原子百分比可以为约25-75％)、SiGeSn、InSb、InGaSb或GeSn。n型器件源/漏层可以包括相同的半导体材料，但可以不同于沟道层的半导体材料，例如SiGe、Ge或III-V族材料GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN。在一个示例中，n型器件源/漏层可以包括InP，沟道层可以包括InGaAs。在此，材料的选择使得沟道层与源/漏层之间可以具有刻蚀选择性，即，可以刻蚀一方而同时基本不影响另一方。
根据本公开的实施例，。可以将IV族半导体材料如SiGe或Ge材料制备的器件先制备在Si基衬底上，然后再将III-V族化合物半导体材料制备的器件制备在SiGe或Ge基的器件上。因为在无应变的情况下，Ge的晶格常数与Si的晶格常数失配比III-V族化合物的晶格常数与Si的晶格常数失配要小(因为在无应变的情况下，Si的晶格常数＜SiGe或Ge的晶格常数＜III-V族化合物的晶格常数)，故在Si基上生长SiGe或Ge更容易减少缺陷和提高器件性能和产品成品率。
各沟道层和源/漏层可以具有合适的厚度，例如约20-40nm。在此，p型器件沟道层1005与n型器件沟道层1011可以具有基本上相同的厚度，以便提供为n型器件和p型器件提供基本上相同的栅长。
各源/漏层可以被掺杂为合适的导电类型。例如，p型器件源/漏层可以被掺杂为p型，掺杂浓度为约1E18-1E20cm-3；n型器件源/漏层可以被掺杂为n型，掺杂浓度为约1E18-1E20cm-3。这种掺杂例如可以通过在外延生长时利用p型杂质如B或BF2或者n型杂质如As或P进行原位掺杂来实现。
另外，可以按需对沟道层进行掺杂或者不掺杂。对于p型器件沟道层1005，可以n型轻掺杂，例如掺杂浓度为约1E17-2E18cm-3；对于n型器件沟道层1011，可以p型轻掺杂，例如掺杂浓度为约1E17-2E18cm-3。
p型掺杂的p型器件第一源/漏层1003与下方的n型层1105和p型层1103构成pnp结构，以提供电隔离。
接下来，可以对有源材料层进行构图，以限定器件的有源区。如上所述，考虑到n型器件和p型器件驱动能力的差异，p型器件和n型器件的有源区面积不同。可以分别针对p型器件和n型器件进行有源区限定。
例如，如图3(a)和3(b)(图3(a)是俯视图，图3(b)是沿图3(a)中AA′线的截面图)所示，可以在图2所示的结构上形成介质层1015。该介质层1015可以在后继工艺中提供对有源材料层的保护，充当(刻蚀/平坦化处理)停止层、掩模层等。例如，介质层1015可以包括氮化物(例如，氮化硅)，厚度为约50-150nm。在介质层1015上，可以形成用于对p型器件的有源材料层进行构图的掩模如光刻胶1017。通过光刻(曝光和显影)将光刻胶1017构图，使得构图后的光刻胶1017具有第一主体部分1017-1和第二主体部分1017-2。这些主体部分随后可以用来限定沟道层的位置，因此可以具有与所希望形成的沟道层的形状相对应的形状。例如，在纳米线形式的沟道层的情况下，主体部分可以为圆形(随后可以得到截面大致为圆形的沟道层)。当然，本公开不限于此，而是可以形成其他形状例如多边形。另外，第一主体部分1017-1和第二主体部分1017-2可以具有基本上相同的大小(例如，基本上相同的半径)。
在第一主体部分1017-1和第二主体部分1017-2之间，可以具有连接部分1017-c。连接部分1017-c从第一主体部分1017-1延伸到第二主体部分1017-2。连接部分1017-c的纵轴可以与第一主体部分1017-1和第二主体部分1017-2的中心连线重合。连接部分1017-c的存在可以保证p型器件第二源/漏层1007在后继构图中不会分成分离的部分，而保持一体延伸。
另外，还存在从第二主体部分1017-2的外周向外延伸的延伸部分1017-p。延伸部分1017-p随后可以用来限定栅堆叠的伸出。延伸部分1017-p的纵轴可以与连接部分1017-c的纵轴相重合，但是本公开不限于此。在此，连接部分1017-c的线宽W1大于延伸部分1017-p的线宽W2。但是，连接部分1017-c的线宽W1优选地小于主体部分1017-1、1017-2的线宽(直径)，从而沟道层主要由主体部分1017-1、1017-2来限定，而不是由连接部分1017-c来限定。具体地，对于形状由该掩模限定的材料层而言，当从该材料层的外周对其进行各向同性刻蚀时，随着时间流逝，首先是与延伸部分1017-p(尺度最小)相对应的部分被去除，然后是与连接部分1017-c(尺度中等)相对应的部分被去除，最终可以得到与主体部分(尺度最大)相对应的两个分离部分。
于是，光刻胶1017可以呈葫芦状。
该葫芦状的光刻胶1017可以用来限定p型器件的有源区。例如，如图4(a)和4(b)(图4(a)是俯视图，图4(b)是沿图4(a)中AA′线的截面图)所示，可以将光刻胶1017的形状转移到下方的材料层特别是p型器件的有源材料层中。例如，可以通过利用光刻胶1017为掩模，以大致垂直于衬底表面的方向进行反应离子刻蚀(RIE)，依次对介质层1015、n型器件第二源/漏层1013、n型器件沟道层1011、n型器件第一源/漏层1009、p型器件第二源/漏层1007和p型器件沟道层1005进行构图。刻蚀可以停止于p型器件第一源/漏层1003。这些被构图的层均呈与光刻胶1017相同的葫芦状，于是相应地具有第一主体部分和第二主体部分、第一主体部分与第二主体部分之间的连接部分以及从第二主体部分的外周向外延伸的延伸部分。在此，不需要对有源材料层中最下层的p型器件第一源/漏层1003进行构图，因为其形状不会影响上方器件的形成。
接下来，可以限定n型器件的有源区。为此，如图5(a)和5(b)(图5(a)是俯视图，图5(b)是沿图5(a)中AA′线的截面图)所示，可以在衬底上形成保护层1019，以保护p型器件的有源材料层。例如，保护层1019可以包括氧化物。例如，可以去除光刻胶1017，并在衬底上淀积氧化物，对淀积的氧化物进行平坦化处理如化学机械抛光(CMP)，CMP可以停止于介质层1015，且随后对氧化物进行回蚀来形成保护层1019。在此，回蚀后保护层1019的顶面可以位于n型器件沟道层1011的底面附近。这样，p型器件的有源材料层1005、1007的侧面可以被遮挡，以免于受后继刻蚀的影响。另外，在该示例中，n型器件第一源/漏层1009的侧面也被遮挡(可能有少部分露出，例如由于保护层1019的顶面略低于n型器件沟道层1011的底面)。于是，在后继工艺在，n型器件第一源/漏层1009的外廓可以与p型器件第二源/漏层1007的外廓基本上对准(在俯视图中基本上重合)。
之后，可以在介质层1015上形成遮蔽层如光刻胶1017′。光刻胶1017′可以构图为覆盖介质层1015(当前已被构图为与光刻胶1017相同的葫芦状)的第二主体部分以及延伸部分(以及可选地，至少一部分连接部分，在图5(a)和5(b)所示的示例中，例如大致一半连接部分)。
介质层1015光刻胶1017′覆盖的部分可以用来限定n型器件的有源区。例如，如图6(a)和6(b)(图6(a)是俯视图，图6(b)是沿图6(a)中AA′线的截面图)所示，可以将介质层1015被光刻胶1017′覆盖部分的形状转移到下方的材料层特别是n型器件的有源材料层中。例如，可以通过利用光刻胶1017′为掩模，以大致垂直于衬底表面的方向进行RIE，依次对介质层1015、n型器件第二源/漏层1013和n型器件沟道层1011进行构图。如上所述，为了使得n型器件第一源/漏层1009与p型器件第二源/漏层1007一致、均匀地接触，在此可以将n型器件第一源/漏层1009与p型器件第二源/漏层1007相同地构图。而且，n型器件第一源/漏层1009是n型器件有源材料层中的最下层，也不会影响上方n型器件的形成。因此，刻蚀可以停止于n型器件第一源/漏层1009。这些被构图的层均呈与介质层1015被光刻胶1017′所覆盖的部分相同的形状，于是相应地具有主体部分(对应于光刻胶1017的第二部分)以及从主体部分两侧伸出的突出部分(对应于光刻胶1017的延伸部分以及部分连接部分)。
之后，可以去除光刻胶1017′，以露出各有源材料层，以便进一步对沟道层进行构图，以限定栅堆叠的空间。例如，如图7(a)和7(b)(图7(a)是俯视图，图7(b)是沿图7(a)中AA′线的截面图)所示，可以使n型器件沟道层1011的外周相对于n型器件源/漏层的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。例如，这可以通过相对于InP材料的源/漏层1009、1013，进一步选择性刻蚀InGaAs材料的沟道层1011来实现。
在此，可以采用各向同性刻蚀，例如可以采用H2O2和EDTA溶液。对于n型器件沟道层1011，其呈与光刻胶1017′相同的形状(主体为岛状，两侧有突出)，刻蚀从该形状的外周基本上相等地向内侧进行。由于如上所述，岛状主体的线宽大于两侧突出的线宽，从而随着刻蚀的进行，两侧的突出将被刻蚀掉，且刻蚀大部分沿着岛状主体的外周(在该示例中，圆形)向内进行。由于各向同性刻蚀，故而刻蚀线仍然呈与岛状主体的外周大致相同的形状(在两侧稍有突出，这种突出随着刻蚀进行会越来越不明显)。最终，留下的沟道层1011可以大致以岛状主体的中心为中心，且外周形状与岛状主体的外周形状基本上相同(但尺寸缩减)。在本示例中圆形的情形下，最终的n型器件沟道层1011基本上是与岛状主体大致同心的圆形，如图7(a)中“N”所示的虚线圈所示。
所形成的沟道层N可以呈(圆)柱状，其直径为约5-50nm，或者为沟道层厚度的三分之二左右。于是，沟道层N可以形成纳米线的形式。为了很好地控制纳米线N的直径，可以使用原子层刻蚀(ALE)技术。
在此，在对n型器件沟道层1011进一步选择性刻蚀之前，可以对保护层1019进行进一步回蚀，以使其顶面下降到n型器件第一源/漏层1009的底面附近。当然，对于保护层1019的这种回蚀，也可以在如以上结合体5(a)和5(b)所述形成保护层1019时完成。
在沟道层相对于源/漏层的外周而形成的凹入中，可以填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过在图7(a)和7(b)所示的结构上淀积氮氧化物，然后对淀积的氮氧化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮氧化物可仅留在凹入内，形成牺牲栅1019，如图8所示。这种情况下，牺牲栅1019可以基本上填满上述凹入。
然后，如图9(a)和9(b)(图9(a)是俯视图，图9(b)是沿图9(a)中AA′线的截面图)所示，可以选择性刻蚀源/漏层1009、1013，以使它们的边缘向内缩进，从而牺牲栅1019相对于上方的有源材料层伸出。
在此，类似地，可以采用各向同性刻蚀。对于n型器件第一源/漏层1009，其呈与光刻胶1017相同的形状(上述葫芦状)，刻蚀从该形状的外周基本上相等地向内侧进行。由于如上所述连接部分的线宽W1＞延伸部分的线宽W2，因此随着刻蚀的进行，延伸部分将先被刻蚀掉。在此，控制刻蚀的时间，使得刻蚀进行至延伸部分被刻蚀掉而连接部分未被刻断(并保持一定的宽度)。另外，岛状(在该示例中，圆形)的第一主体部分和第二主体部分外周分别内缩。于是，刻蚀后n型器件第一源/漏层1009可以呈哑铃状。另外，n型器件第一源/漏层1009的上表面的一部分由于外露而受到刻蚀，从而可能有一定的降低。
对于n型器件第二源/漏层1013，其呈与光刻胶1017′相同的形状(主体为岛状，两侧有突出)，刻蚀从该形状的外周基本上相等地向内侧进行。类似地，刻蚀后n型器件第二源/漏层1013可能呈岛状(在与连接部分相对应的位置处，可能有一定突出)。
这样，就限定了n型器件的有源区(并保持了其栅堆叠的位置)。然后，可以进一步限定p型器件的有源区。
为此，可以遮蔽n型器件的有源区，并露出p型器件的有源区。例如，如图10所示，可以在图9所示的结构上淀积氧化物1107，并对其进行平坦化如CMP。然后，可以利用光刻胶1109，对淀积的氧化物1107进行选择性刻蚀如RIE。光刻胶1109可以构图为覆盖n型器件的有源区，但露出p型器件的至少部分有源区。于是，氧化物1107可以遮蔽n型器件的有源区，并露出露出p型器件的至少部分有源区。之后，可以去除光刻胶1109。
然后，如图11所示，可以使p型器件沟道层1005的外周相对于p型器件源/漏层的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。例如，这可以通过相对于SiGe材料的源/漏层1003、1007，进一步选择性刻蚀Ge材料的沟道层1005来实现。
在此，可以采用各向同性刻蚀。对于p型器件沟道层1005中，其呈与光刻胶1017相同的形状(葫芦状)。由于如上所述，岛状的第一主体部分和第二主体部分的线宽大于连接部分和延伸部分的线宽，从而随着刻蚀的进行，连接部分和延伸部分将被刻蚀掉，且刻蚀大部分沿着第一主体部分和第二主体部分的外周(在该示例中，圆形)向内进行。最终，留下的沟道层1005可以分别大致以第一主体部分和第二主体部分的中心为中心，且外周形状与第一主体部分和第二主体部分的外周形状基本上相同(但尺寸缩减)。在本示例中圆形的情形下，最终的p型器件沟道层1005被分离为两部分P1和P2，基本上是分别与第一主体部分和第二主体部分大致同心的圆形。
所形成的沟道层P1和P2可以呈(圆)柱状，其直径为约5-50nm，或者为沟道层厚度的三分之二左右。于是，沟道层P1和P2可以形成纳米线的形式。为了很好地控制纳米线P1和P2的直径，可以使用原子层刻蚀(ALE)技术。
另外，由于光刻胶1017′与光刻胶1017在位置上基本重叠，故而N和P2可以在竖直方向上基本上对准。
类似地，可以在沟道层相对于源/漏层的外周而形成的凹入中形成牺牲栅以占据栅堆叠的空间。例如，这可以通过在图10所示的结构上淀积氮氧化物，然后对淀积的氮氧化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮氧化物可仅留在凹入内，形成牺牲栅1019′，如图12所示。这种情况下，牺牲栅1019′可以基本上填满上述凹入。
然后，如图13所示，可以选择性刻蚀源/漏层1007，以使其边缘向内缩进，从而牺牲栅1019′相对于上方的有源材料层伸出。
在此，类似地，可以采用各向同性刻蚀。对于p型器件第二源/漏层1007，其呈与光刻胶1017相同的形状(上述葫芦状)，刻蚀从该形状的外周基本上相等地向内侧进行。由于如上所述连接部分的线宽W1＞延伸部分的线宽W2，因此随着刻蚀的进行，延伸部分将先被刻蚀掉。在此，控制刻蚀的时间，使得刻蚀进行至延伸部分被刻蚀掉而连接部分未被刻断(并保持一定的宽度)。另外，岛状(在该示例中，圆形)的第一主体部分和第二主体部分外周分别内缩。于是，刻蚀后p型器件第二源/漏层1007可以呈哑铃状。由于p型器件第二源/漏层1007和n型器件第一源/漏层1009在刻蚀之前具有由相同掩模1017限定的相同形状(葫芦状)，因此它们最终可以呈现基本上相同的形状(均是从葫芦状的外周开始各向同性刻蚀一段时间后得到的形状，具体地，上述哑铃状)。如果它们的刻蚀程度基本上相同，则p型器件第二源/漏层1007和n型器件第一源/漏层1009可以彼此对准叠置，它们的外周可以彼此重合(在俯视图中重合)。
另外，p型器件第一源/漏层1003的上表面的一部分由于外露而受到刻蚀，从而可能有一定的降低。
这样，就限定了p型器件的有源区(并保持了其栅堆叠的位置)。
在此，为了进一步改善性能，可以进行热退火工艺，以使源/漏层中的杂质进入沟道层(例如，p型器件第一源/漏层1003中的p型杂质可以进入p型器件沟道层P1和P2的下端，p型器件第二源/漏层1007中的p型杂质可以进入p型器件沟道层P1和P2的上端；n型器件第一源/漏层1009中的n型杂质可以进入n型器件沟道层N的下端，n型器件第二源/漏层1013中的n型杂质可以进入n型器件沟道层N的上端)中，从而在沟道层的上下两端处形成一定的掺杂分布。这种掺杂分布可以降低器件导通时源漏区之间的电阻，从而提升器件性能。
另外，还可以在源/漏层的表面进行硅化处理，以降低接触电阻。例如，可以在图13所示的结构(可以去除遮蔽层1107)上淀积一层NiPt(Pt的含量为约1-10％)，然后在约200-600℃的温度下进行退火，使得NiPt与SiGe发生反应从而生成硅化物(在此，SiNiPt)层。之后，可以去除未反应的剩余NiPt。
由于源/漏层1003、1007、1009、1013外周表面的一部分转化成硅化物，因此它们的外周可以向内缩进，从而沟道层的外周相对于相应源/漏层的外周不一定凹入，而是可以凸出。但是由于牺牲栅已经保持了栅的位置，所以尽管沟道层的外周可能相对于相应源/漏层的外周凸出，但不会影响栅堆叠的形成。
接下来，可以进行将牺牲栅替换为真正栅堆叠的替代栅工艺。
为此，可以先将各层之间当前存在的间隙填满。例如，如图14所示，可以在衬底上淀积一层氧化物1023，并对氧化物进行回蚀(例如，通过沿垂直于衬底表面的方向进行RIE)，从而将氧化物填入各间隙中。在回蚀之前，可以对淀积的氧化物进行平坦化处理如CMP。
如图14所示，尽管填充了氧化物1023，但是由于牺牲栅1019和1019′的伸出结构，其侧壁仍然暴露于外，从而便于对其进行替换操作。
如图15所示，可以通过选择性刻蚀，去除牺牲栅1019和1019′，然后可以在由于牺牲栅1019和1019′的去除而留下的空间中形成栅堆叠。具体地，可以依次淀积栅介质层1025和栅导体层1027，然后可以通过选择性刻蚀(例如，通过沿垂直于衬底表面的方向进行RIE)，去除栅介质层1025和栅导体层1027位于由于牺牲栅1019和1019′的去除而留下的空间之外的部分。在此，栅介质层1025可以包括高K栅介质如HfO2，栅导体层1027可以包括金属栅导体。在栅介质层1025和栅导体层1027之间还可以设置功函数调节层。
另外，可以针对n型器件和p型器件设置不同的栅堆叠。为此，如图16所示，可以形成介质层1029来保护针对p型器件形成的栅堆叠125/127。例如，可以在图15所示的结构上淀积氧化物，可以对淀积的氧化物进行平坦化处理如CMP，之后进行回蚀(例如，通过沿垂直于衬底表面的方向进行RIE)，来形成介质层1029。在该示例中，由于介质层1029与氧化物1023相同材质，故而在图16中将它们统一示出为1029。介质层1029以露出n型器件沟道层N外周形成的栅堆叠但并不露出p型器件沟道层P1和P2外周形成的栅堆叠为宜，例如，回蚀后的介质层1029的上表面可以留于n型器件第一源/漏层1009的上表面和下表面之间。
之后，如图17所示，可以通过选择性刻蚀，去除栅导体层1027(以及功函数调节层，如果存在的话)，并形成针对n型器件的(功函数调节层和)栅导体层1031。在该示例中，并未替换栅介质层1025，当然也可以对其进行替换。
这样，栅堆叠可以嵌入到凹入中，从而与各沟道层的整个高度相交迭。
然后，可以形成电接触部。
例如，如图18所示，可以通过选择性刻蚀(例如，通过沿垂直于衬底表面的方向进行RIE)，至少部分地去除介质层1029，然后在所得到的结构上淀积衬层1033。衬层1033可以包括氮化物，并可以作为刻蚀停止层和器件保护层。然后，可以形成层间电介质层1035。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1035。然后，如图19所示，在层间电介质层1035中，可以形成到n型器件第二源/漏层1013的接触部1037-GND、到n型器件第一源/漏层1009(以及p型器件第二源/漏层1007)的接触部1037-OUT、到p型器件第一源/漏层1003的接触部1037-Vdd以及到栅导体层1021和1031的接触部1037-IN。这些接触部可以通过在层间电介质层1035以及相关材料层中刻蚀孔洞，并在其中填充导电材料如金属来形成。
如上所述，各接触部均位于器件的占用面积上方，从而不占用额外面积。
在刻蚀接触孔时，由于各接触孔的深度不同，难以控制刻蚀停止。由于衬层1033的存在，在对层间电介质层1035进行刻蚀时，可以衬层1033为刻蚀停止层，从而可以相对容易地控制刻蚀深度。
图20示出了根据本公开另一实施例的集成电路单元的截面图。如图20所示，根据本实施例的集成电路单元与上述实施例中的集成电路单元一样，除了还包括到衬底的接触部1037-SUB之外。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成一个多个这样的集成电路单元以及其他器件(例如，FET等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述集成电路单元的电子设备。电子设备还可以包括与集成电路单元配合的显示屏幕以及与集成电路单元配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造集成电路单元的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (34)

1.一种集成电路单元，包括：
彼此叠置在衬底上的第一器件和第二器件，其中第一器件和第二器件各自均包括依次叠置的第一源/漏层、沟道层和第二源/漏层以及绕沟道层外周形成的栅堆叠，
其中，第一器件的沟道层和第二器件的沟道层至少之一包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料。
2.根据权利要求1所述的集成电路单元，其中，第一器件和第二器件具有不同导电类型。
3.根据权利要求1所述的集成电路单元，其中，
第一器件的第一源/漏层和第二源/漏层包括与第一器件的沟道层不同的半导体材料；和/或
第二器件的第一源/漏层和第二源/漏层包括与第二器件的沟道层不同的半导体材料。
4.根据权利要求1所述的集成电路单元，其中，第一器件的沟道层和第二器件的沟道层包括彼此不同的半导体材料。
5.根据权利要求1所述的集成电路单元，其中，
第一器件和第二器件具有不同导电类型，且第二器件叠置于第一器件上；
在无应变的情况下，衬底材料的晶格常数小于第一器件的沟道层的半导体材料的晶格常数；
在无应变的情况下，第一器件的沟道层的半导体材料的晶格常数小于第二器件的沟道层的半导体材料的晶格常数。
6.根据权利要求1所述的集成电路单元，其中，
第一器件具有两个沟道层而第二器件具有单个沟道层，且第一器件的两个沟道层并联连接。
7.根据权利要求6所述的集成电路单元，其中，第一器件的两个沟道层实质上共面。
8.根据权利要求1至7中任一项所述的集成电路单元，其中，第一器件的沟道层和第二器件的沟道层均包括单晶半导体材料。
9.根据权利要求8所述的集成电路单元，其中，第一器件的第一源/漏层和第二源/漏层以及第二器件的第一源/漏层和第二源/漏层均包括单晶半导体材料。
10.根据权利要求9所述的集成电路单元，其中，沟道层的单晶半导体材料与源/漏层的单晶半导体材料具有相同的晶体结构。
11.根据权利要求1所述的集成电路单元，其中，
第一器件是p型器件，其沟道层包括SiGe、Ge、SiGeSn、InSb、InGaSb或GeSn；
第二器件是n型器件，其沟道层包括SiGe、Ge或III-V族化合物半导体。
12.根据权利要求11所述的集成电路单元，其中，III-V族化合物半导体包括GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN之一或它们的组合。
13.根据权利要求11或12所述的集成电路单元，其中，
第一器件的第一源/漏层和第二源/漏层包括SiGe SiGeSn、InSb、InGaSb或GeSn，沟道层包括SiGe、Ge、SiGeSn、InSb、InGaSb或GeSn；
第二器件的第一源/漏层和第二源/漏层包括GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN，沟道层包括SiGe、Ge、GaAs、InGaAs、InP、AlGaAs、InAlAs、InAs、InGa、InAlGa、InSb、InGaSb或GaN。
14.根据权利要求1所述的集成电路单元，其中，第二器件叠置在第一器件上，且第一器件的第二源/漏层与第二器件的第一源/漏层物理接触。
15.根据权利要求14所述的集成电路单元，其中，第二器件的第一源/漏层的外周与第一器件的第二源/漏层的外周基本上重合。
16.根据权利要求14或15所述的集成电路单元，其中，第一器件的沟道层包括彼此分离的第一部分和第二部分，第一器件的第一源/漏层和第二源/漏层分别一体延伸且与沟道层的第一部分和第二部分二者交迭。
17.根据权利要求16所述的集成电路单元，其中，第二器件的沟道层与第一器件的沟道层的第一部分和第二部分之一在竖直方向上基本上对准。
18.根据权利要求17所述的集成电路单元，其中，
第一器件的第二源/漏层、第二器件的第一源/漏层相对于第二器件的第二源/漏层向着第一器件的沟道层的第一部分和第二部分中另一个的上方伸出，
第一器件的栅堆叠和第二器件的栅堆叠相对于第二器件的第二源/漏层向着与第一器件的第二源/漏层、第二器件的第一源/漏层的伸出方向相反的方向伸出。
19.根据权利要求16所述的集成电路单元，其中，
第二器件的第一源/漏层、第一器件的第二源/漏层各自包括位于第一器件的沟道层的第一部分上方的第一主体部分、位于第一器件的沟道层的第二部分上方的第二主体部分以及第一主体部分和第二主体部分之间的连接部分，
其中，第二器件的第一源/漏层、第一器件的第二源/漏层各自的第一主体部分的外周相对于第一器件的沟道层的第一部分的外周基本上平行地延伸，第二器件的第一源/漏层、第一器件的第二源/漏层各自的第二主体部分的外周相对于第一器件的沟道层的第二部分的外周基本上平行地延伸。
20.根据权利要求1所述的集成电路单元，其中，
第一器件的沟道层的外周相对于第一器件的第一源/漏层和第二源/漏层的外周向内凹入，第一器件的栅堆叠嵌入于该凹入中，自对准于沟道层；
第二器件的沟道层的外周相对于第二器件的第一源/漏层和第二源/漏层的外周向内凹入，第二器件的栅堆叠嵌入于该凹入中，自对准于沟道层。
21.根据前述权利要求中任一项所述的集成电路单元，其中，在各源/漏层和沟道层中至少一对相邻的层之间，存在晶体界面。
22.一种制造集成电路单元的方法，包括：
在衬底上设置第一器件的第一源/漏层、沟道层和第二源/漏层以及第二器件的第一源/漏层、沟道层和第二源/漏层的叠层，其中第一器件的沟道层和第二器件的沟道层至少之一包括与Si材料相比具有增大开态电流和/或减小关态电流的半导体材料；
分别选择性刻蚀第二器件的沟道层和第一器件的沟道层，使得第二器件的沟道层的外周相对于第二器件的第一源/漏层和第二源/漏层的外周向内凹入，第一器件的沟道层的外周相对于第一器件的第一源/漏层和第二源/漏层的外周向内凹入；以及
分别绕第二器件的沟道层和第一器件的沟道层的外周形成第二器件的栅堆叠和第一器件的栅堆叠。
23.根据权利要求22所述的方法，其中，通过外延生长，来设置所述叠层。
24.根据权利要求22所述的方法，其中，在选择性刻蚀第一器件的沟道层时，将该沟道层分离为彼此间隔开的第一部分和第二部分。
25.根据权利要求24所述的方法，其中，选择性刻蚀第二器件的沟道层包括：
选择性刻蚀第二器件的第二源/漏层，使得第二器件的第二源/漏层相对于其他源/漏层具有缩减的面积；以及
选择性刻蚀第二器件的沟道层，使得第二器件的沟道层相对于被选择性刻蚀后的第二器件的第二源/漏层凹入。
26.根据权利要求25所述的方法，其中，形成第二器件的栅堆叠和第一器件的栅堆叠包括：
在第二器件的沟道层相对于第二器件的第二源/漏层的凹入中形成第一牺牲栅；
选择性刻蚀第二器件的第一源/漏层和第二源/漏层，使它们的面积缩减，从而第一牺牲栅具有相对于第二器件的第二源/漏层的伸出部分；
在第一器件的沟道层相对于第一器件的第二源/漏层的凹入中形成第二牺牲栅；
选择性刻蚀第一器件的第二源/漏层，从而第二牺牲栅具有相对于第二器件的第一源/漏层和第一器件的第二源/漏层的伸出部分；以及
利用第二器件的栅堆叠和第一器件的栅堆叠分别替换第一牺牲栅和第二牺牲栅。
27.根据权利要求22至26中任一项所述的方法，其中，所述选择性刻蚀包括原子层刻蚀或者数字化刻蚀。
28.根据权利要求26所述的方法，其中，被选择性刻蚀后的第二器件的第一源/漏层和第一器件的第二源/漏层具有基本上重合的外周。
29.根据权利要求26所述的方法，其中，被选择性刻蚀后的第二器件的第一源/漏层和第一器件的第二源/漏层相对于被选择性刻蚀后的第二器件的第二源/漏层伸出，但相对于第一器件的第一源/漏层具有缩减的面积。
30.根据权利要求22所述的方法，其中，选择性刻蚀第二器件的沟道层和第一器件的沟道层包括：
在所述叠层上设置掩模，掩模包括第一主体部分和第二主体部分以及第一主体部分和第二主体部件之间的连接部分，并且还包括从第一主体部分的外周向外延伸的延伸部分，其中延伸部分的线宽小于连接部分的线宽；
利用所述掩模，依次选择性刻蚀第二器件的第二源/漏层、沟道层和第一源/漏层以及第一器件的第二源/漏层和沟道层；
在所述叠层上设置遮蔽层，所述遮蔽层遮蔽所述叠层与第一掩模的第一主体部分以及与延伸部分相对应的部分；
在存在遮蔽层的情况下，依次选择性刻蚀第二器件的第二源/漏层和沟道层；
去除遮蔽层；
选择性刻蚀第二器件的沟道层，使得第二器件的沟道层的外周相对于掩模的第一主体部分的外周凹入；
选择性刻蚀第一器件的沟道层，使得第一器件的沟道层分为分别相对于掩模的第一主体部分和第二主体部分的外周凹入且彼此分离的第一部分和第二部分。
31.根据权利要求30所述的方法，其中，
在选择性刻蚀第二器件的沟道层之后且在选择性刻蚀第一器件的沟道层之前，该方法还包括：绕第二器件的沟道层的外周形成第一牺牲栅；以及进一步选择性刻蚀第二器件的第一源/漏层和第二源/漏层，使得第二器件的第二源/漏层的外周相对于掩模的第一主体部分的外周凹入，而不存在与延伸部分相对应的部分，第二器件的第一源/漏层包括外周分别相对于掩模的第一主体部分和第二主体部分的外周凹入的第一部分和第二部分以及第一部分和第二部分之间的连接部分；
在选择性刻蚀第二器件的沟道层之后，该方法还包括：绕第一器件的沟道层的外周形成第二牺牲栅；以及进一步选择性刻蚀第一器件的第二源/漏层，使得第一器件的第二源/漏层包括外周分别相对于掩模的第一主体部分和第二主体部分的外周凹入的第一部分和第二部分以及第一部分和第二部分之间的连接部分，
形成栅堆叠包括：分别利用第二器件的栅堆叠和第一器件的栅堆叠分别替换第一牺牲栅和第二牺牲栅。
32.一种电子设备，包括由如权利要求1至21中任一项所述的集成电路单元。
33.根据权利要求32所述的电子设备，还包括：与所述集成电路单元配合的显示器以及与所述集成电路单元配合的无线收发器。
34.根据权利要求32所述的电子设备，该电子设备包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或移动电源。
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