CN107887384A - 半导体器件及其制造方法及包括该器件的电子设备 - Google Patents

半导体器件及其制造方法及包括该器件的电子设备 Download PDF

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CN107887384A
CN107887384A CN201710530685.4A CN201710530685A CN107887384A CN 107887384 A CN107887384 A CN 107887384A CN 201710530685 A CN201710530685 A CN 201710530685A CN 107887384 A CN107887384 A CN 107887384A
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source drain
channel layer
layer
grid
source
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CN107887384B (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202011005535.XA priority Critical patent/CN112018111B/zh
Priority to US15/720,913 priority patent/US10833193B2/en
Publication of CN107887384A publication Critical patent/CN107887384A/zh
Priority to US17/033,284 priority patent/US11695074B2/en
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Priority to US18/317,722 priority patent/US20230369489A1/en
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Abstract

公开了一种半导体器件及其制造方法及包括该器件的电子设备。根据实施例，半导体器件可以包括：衬底；在衬底上形成的第一器件和第二器件，第一器件和第二器件分别包括：依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层；以及绕沟道层的外周形成的栅堆叠；其中，第一器件的沟道层与第二器件的沟道层基本共面。

Description

半导体器件及其制造方法及包括该器件的电子设备
技术领域
本公开涉及半导体领域，具体地，涉及竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，缩小水平型器件所占的面积，一般要求源极、漏极和栅极所占的面积缩小，使器件性能变差(例如，功耗和电阻增加)，故水平型器件的面积不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件所占的面积更容易缩小。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有改进特性的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；在衬底上形成的第一器件和第二器件，第一器件和第二器件分别包括：依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层；以及绕沟道层的外周形成的栅堆叠，其中，第一器件的沟道层与第二器件的沟道层基本共面。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上外延生长第一源/漏层；在第一源/漏层上形成在第一器件区域和第二器件区域中基本共面的沟道层；在沟道层上外延生长第二源/漏层；从堆叠的第一源/漏层、沟道层和第二源/漏层分别在第一器件区域和第二器件区域限定出第一器件的有源区和第二器件的有源区；以及分别绕第一器件和第二器件各自有源区中的沟道层的外周形成相应器件的栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括由上述半导体器件形成的集成电路。
根据本公开的实施例，在竖直型器件中，栅堆叠绕沟道层的外周形成且沟道形成于沟道层中，从而栅长由沟道层的厚度确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。衬底上不同区域中形成的竖直型器件可以具有不同的沟道长度。沟道层的外周相对于第一、第二源/漏层的外周可以向内凹入，从而栅堆叠可以嵌入该凹入中，减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。另外，沟道层可以是单晶半导体材料，可以具有高载流子迁移率和低泄漏电流，从而改善了器件性能。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至19示出了根据本公开实施例的制造半导体器件的流程的示意图；
图20和21分别示出了根据本公开实施例的CMOS配置的半导体器件的端子连接方式；
图22至25示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图；
图26示出了根据本公开另一实施例的半导体器件的截面图；
图27和28示出了根据本公开实施例的源/漏层细化处理；
图29和30示出了根据本公开实施例对沟道层进行减薄处理的示意图；
图31和32示出了根据本公开实施例对沟道层进行减薄处理的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的半导体器件基于竖直型器件。竖直型器件可以包括在衬底上依次叠置的第一源/漏层、沟道层和第二源/漏层。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和开态电流增强层(带隙比相邻层大或小的半导体层)。在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。
栅堆叠可以绕沟道层的外周形成。于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于耗时刻蚀来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。
衬底上不同器件区域中的器件各自的沟道层可以实质上共面，例如它们可以在大致平行于衬底表面的平面上延伸。在一个示例中，各器件区域处的沟道层的上表面和/或下表面可以基本上共面。因此，各器件区域处的沟道层可以具有不同的厚度，相应地可以具有不同的沟道长度。
沟道层的外周可以相对于第一、第二源/漏层的外周向内凹入。这样，所形成的栅堆叠可以嵌于沟道层相对于第一、第二源/漏层的凹入中。优选地，栅堆叠在第一源/漏层、沟道层和第二源/漏层的叠置方向(竖直方向，例如大致垂直于衬底表面)上的范围处于所述凹入在该方向上的范围之内。于是，可以减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
在第一器件和第二器件为不同导电类型器件的情况下(例如，第一器件为n型器件，第二器件为p型器件)，栅堆叠特别是其中的栅导体层可能需要对第一器件和第二器件分别不同地形成(例如，以不同功函数的栅导体材料来分别形成n型器件和p型器件的栅导体层)。例如，第一器件和第二器件可以分别包括具有适合功函数且嵌入于相应凹入内的相应栅导体材料。
另外，为了便于制造到栅导体层的电接触，还可以包括将栅导体层引出的栅极接触垫。这种栅极接触垫可以与栅堆叠(具体地，栅导体层)电接触，并沿着远离沟道层的方向延伸(例如，延伸超出有源区外周)。有利地，为了便于制造，可以利用第一器件和第二器件之一(例如，第一器件)的栅导体层来形成这种栅极接触垫，即便对于另一器件(例如，第二器件)。例如，一种器件(例如，第一器件)的栅导体层可以从相应凹入向外延伸从而充当栅极接触垫，另外其栅导体层的另一部分可以延伸至另一种器件(例如，第二器件)的栅导体层，从而充当栅极接触垫。
沟道层可以由单晶半导体材料构成，以改善器件性能。当然，第一、第二源/漏层也可以由单晶半导体材料构成。这种情况下，沟道层的单晶半导体材料与源/漏层的单晶半导体材料可以是共晶体。沟道层单晶半导体材料的电子或空穴迁移率可以大于第一、第二源/漏层的电子或空穴迁移率。另外，第一、第二源/漏层的禁带宽度可以大于沟道层单晶半导体材料的禁带宽度。
根据本公开的实施例，沟道层单晶半导体材料与第一、第二源/漏层可以具有相同的晶体结构。在这种情况下，第一、第二源/漏层在没有应变的情况下的晶格常数可以大于沟道层单晶半导体材料在没有应变的情况下的晶格常数。于是，沟道层单晶半导体材料的载流子迁移率可以大于其在没有应变的情况下的载流子迁移率，或沟道层单晶半导体材料的轻载流子的有效质量可以小于其在没有应变的情况下的轻载流子的有效质量，或沟道层单晶半导体材料的轻载流子的浓度可以大于其在没有应变的情况下的轻载流子的浓度。备选地，第一、第二源/漏层在没有应变的情况下的晶格常数可以小于沟道层单晶半导体材料在没有应变的情况下的晶格常数。于是，沟道层单晶半导体材料的电子迁移率大于其在没有应变的情况下的电子迁移率，或沟道层单晶半导体材料的电子的有效质量小于其在没有应变的情况下的电子的有效质量。
根据本公开的实施例，对于源/漏区的掺杂可以部分地进入沟道层靠近第一源/漏层和第二源/漏层的端部。由此，在沟道层靠近第一源/漏层和第二源/漏层的端部形成掺杂分布，这有助于降低器件导通时源/漏区与沟道区之间的电阻，从而提升器件性能。
根据本公开的实施例，沟道层可以包括与第一、第二源/漏层不同的半导体材料。这样，有利于对沟道层进行处理例如选择性刻蚀，以使之相对于第一、第二源/漏层凹入。另外，第一源/漏层和第二源/漏层可以包括相同的半导体材料。
有源区中的各层可以通过外延生长形成，从而可以精确地控制其厚度。例如，第一源/漏层可以是在衬底上外延生长的半导体层，沟道层可以是在第一源/漏层上外延生长的半导体层，第二源/漏层可以是在沟道层上外延生长的半导体层。
根据本公开的实施例，还可以在第一器件和/或第二器件各自的第一源/漏层和第二源/漏层的表面上设置应力衬层。对于n型器件，应力衬层可以带压应力，以在沟道层中产生拉应力；对于p型器件，应力衬层可以带拉应力，以在沟道层中产生压应力。因此，可以进一步改善器件性能。
根据本公开的实施例，第一器件和第二器件可以是不同导电类型的器件，并因此可以形成互补金属氧化物半导体(CMOS)配置。
这种半导体器件例如可以如下制造。具体地，可以在衬底上外延生长第一源/漏层，在第一源/漏层上形成在第一器件区域和第二器件区域中基本共面的沟道层，并在沟道层上外延生长第二源/漏层。在外延生长时，可以控制所生长的沟道层的厚度。由于分别外延生长，至少一些相邻层之间可以具有清晰的晶体界面。另外，可以对各层分别进行掺杂，于是至少一些相邻层之间可以具有掺杂浓度界面。
对于沟道层，可以对通过一定的处理，使得其在第一器件区域和第二器件区域可以具有不同的厚度。例如，可以在生长沟道层之后对其在某器件区域中的部分进行减薄处理(例如，刻蚀)，或者在某器件区域中进一步生长；或者，可以在生长第一源/漏层之后对其在某器件区域中的部分进行减薄处理(例如，刻蚀)，然后再生长沟道层。
对于叠置的第一源/漏层、沟道层和第二源/漏层，可以分别在第一器件区域和第二器件区域中限定第一器件和第二器件的有源区。例如，可以将它们依次选择性刻蚀为所需的形状。第一器件和第二器件各自的有源区可以由相同的第一源/漏层、沟道层和第二源/漏层来得到。通常，有源区可以呈柱状(例如，圆柱状)。为了便于在后继工艺中连接第一源/漏层中形成的源/漏区，对第一源/漏层的刻蚀可以只针对第一源/漏层的上部，从而第一源/漏层的下部可以延伸超出其上部的外周。然后，可以绕沟道层的外周形成栅堆叠。
另外，可以使沟道层的外周相对于第一、第二源/漏层的外周向内凹入，以便限定容纳栅堆叠的空间。例如，这可以通过选择性刻蚀来实现。这种情况下，栅堆叠可以嵌入该凹入中。
在第一、第二源/漏层中可以形成源/漏区。例如，这可以通过对第一、第二源/漏层掺杂来实现。例如，可以进行离子注入、等离子体掺杂等。根据一有利实施例，可以在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅，然后在第一、第二源/漏层的表面上形成掺杂剂源层，并通过例如退火使掺杂剂源层中的掺杂剂经第一、第二源/漏层进入有源区中。牺牲栅可以阻止掺杂剂源层中的掺杂剂直接进入沟道层中。但是，可以有部分掺杂剂经由第一、第二源/漏层而进入沟道层靠近第一源/漏层和第二源/漏层的端部。如果第一器件和第二器件具有不同的导电类型，则可以分别进行掺杂。
可以分别在第一器件和第二器件各自的沟道层的凹入中形成针对相应器件的栅堆叠。如果第一器件和第二器件具有不同导电类型且分别形成不同的栅堆叠，则它们的栅堆叠可以分别先后形成。在后一次形成栅堆叠时，可以利用其中的栅导体层来形成第一器件和第二器件各自的栅极接触垫。这可以通过对栅导体层进行构图来形成。
本公开可以各种形式呈现，以下将描述其中一些示例。
图1至19示出了根据本公开实施例的制造半导体器件的流程的示意图。在以下，以分别形成n型器件和p型器件为例进行描述，以便更详尽地展现形成不同导电类型器件的情况。应当理解，当然也可以形成相同导电类型的器件。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供p型硅晶片作为衬底1001。在衬底1001中，例如可以通过离子注入，形成n型阱区1001w。p型器件可以形成在n型阱区1001w上(因此将其称作p型器件区域)；而n型器件可以形成在p型Si衬底1001的其他区域上(因此将其称作n型器件区域)。
在衬底1001上，可以通过例如外延生长，依次形成第一源/漏层1031、沟道层1003和第二源/漏层1005。例如，第一源/漏层1031可以包括SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm；沟道层1003可以包括Si，厚度为约10-100nm；第二源/漏层1005可以包括SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm。SiGe在没有应变的情况下的晶格常数大于Si在没有应变的情况下的晶格常数。第一源/漏层1031、沟道层1003和第二源/漏层1005的材料选择不限于此，可以包括能够提供适当刻蚀选择性的其他半导体材料。例如，沟道层1003可以包括与第一源/漏层1031、第二源/漏层1005相同的构成组分，但是组分含量不同的半导体材料(例如，都是SiGe，但是其中Ge的原子百分比不同)，只要沟道层1031相对于之上的第一源/漏层1031以及之上的第二源/漏层1005具备刻蚀选择性。另外，第一源/漏层1031和第二源/漏层1005可以包括Si：C(C的原子百分比可以为约0.1-5％)，沟道层1003可以包括Si。Si:C在没有应变的情况下的晶格常数小于Si在没有应变的情况下的晶格常数。
接下来，可以限定器件的有源区。例如，这可以如下进行。具体地，如图2(a)和2(b)(图2(a)是截面图，图2(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图1所示的第一源/漏层1031、沟道层1003和第二源/漏层1005的叠层上形成光刻胶(未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状(在该示例中，大致圆形)，并以构图后的光刻胶为掩模，依次对第二源/漏层1005、沟道层1003和第一源/漏层1031进行选择性刻蚀如反应离子刻蚀(RIE)。刻蚀进行到第一源/漏层1031中，但并未进行到第一源/漏层1031的底面处，以便于后继制造接触部。于是，刻蚀后第二源/漏层1005、沟道层1003以及第一源/漏层1031的上部形成柱状(在本示例中，圆柱状)。RIE例如可以按大致垂直于衬底表面的方向进行，从而该柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
在该示例中，分别在p型器件区域和n型器件区域构图针对p型器件和n型器件的有源区。在此，为描述方便起见，将针对p型器件的第一源/漏层、沟道层和第二源/漏层分别标示为1031p、1003p和1005p，将针对n型器件的第一源/漏层、沟道层和第二源/漏层分别标示为1031n、1003n和1005n。在该阶段，第一源/漏层1031在p型器件和n型器件区域之间尚连续，图2(a)中以虚线示意性示出了p型器件区域和n型器件区域之间的边界。
在以下的描述中，当对p型器件区域和n型器件区域统一进行描述时，使用1031、1003和1005的附图标记；而当需要对p型器件区域和n型器件区域分别进行描述时，则分别使用1031p、1003p和1005p以及1031n、1003n和1005n的附图标记。
在该示例(SiGe-Si-SiGe叠层)中，在RIE之后，由于SiGe在没有应变的情况下的晶格常数大于Si在没有应变的情况下的晶格常数，在Si中产生应变，此应变会使Si的空穴迁移率大于其在没有应变的情况下的空穴迁移率，或Si的轻空穴的有效质量小于其在没有应变的情况下的轻空穴的有效质量，或Si的轻空穴的浓度大于其在没有应变的情况下的轻空穴的浓度，进而使p型器件的开态电流增加并因此增强了p型器件的性能。
备选地，在Si:C-Si-Si:C叠层的情况下，在RIE之后，由于Si:C在没有应变的情况下的晶格常数小于Si在没有应变的情况下的晶格常数，在Si中产生应变，此应变会使Si的电子迁移率大于其在没有应变的情况下的电子迁移率，或Si的电子的有效质量小于其在没有应变的情况下的电子的有效质量，进而使n型器件的开态电流增加并以此增强了n型器件的性能。
另外，如果选用SiGe作为沟道层材料而用Si作为源/漏层材料，此选择既可以增加p型器件的开态电流，又可以减小p型器件的关态电流，从而增强了p型器件的性能。原因在于Si的禁带宽度大于SiGe的禁带宽度，而SiGe中空穴迁移率大于Si的空穴迁移率。
然后，如图3所示，可以使沟道层1003的外周相对于第一源/漏层1031和第二源/漏层1005的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。该凹入的上下侧壁分别由沟道层1003与第二源/漏层1005以及沟道层与第一源/漏层1031之间的界面限定。例如，这可以通过相对于第一源/漏层1031和第二源/漏层1005，进一步选择性刻蚀(例如，各向同性刻蚀，例如可以使用TMAH溶液进行湿法刻蚀)沟道层1003来实现。例如，可以使用原子层刻蚀(ALE)或者数字化刻蚀来进行选择性刻蚀。例如，通过例如热处理，使第一源/漏层1031、沟道层1003和第二源/漏层1005的表面氧化，且然后去除它们各自的表面氧化层。在沟道层1003是SiGe且第一源/漏层1031和第二源/漏层1005为Si的情况下，SiGe的氧化速率高于Si的氧化速率，且SiGe上的氧化物更易于去除。可以重复氧化-去除氧化物的步骤，以实现所需的凹入。相比于选择性刻蚀，这种方式可以更好地控制凹入的程度。
这样，就限定了有源区(刻蚀后的第一源/漏层1031、沟道层1003和第二源/漏层1005)。在该示例中，有源区大致呈柱状。在有源区中，第一源/漏层1031的上部和第二源/漏层1005的外周实质上对准，而沟道层1003的外周相对凹入。该凹入的上下侧壁分别由沟道层1003与半第二源/漏层1005以及沟道层1003与第一源/漏层1031之间的界面限定。
当然，有源区的形状不限于此，而是可以根据设计布局形成其他形状。例如，在俯视图中，有源区可以呈椭圆形、方形、矩形等。
在沟道层1003相对于第一源/漏层1031的上部和第二源/漏层1005的外周而形成的凹入中，随后将形成栅堆叠。为避免后继处理对于沟道层1003造成影响或者在该凹入中留下不必要的材料从而影响后继栅堆叠的形成，可以在该凹入中填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过在图3所示的结构上淀积氮化物，然后对淀积的氮化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮化物可仅留在凹入内，形成牺牲栅1007，如图4所示。这种情况下，牺牲栅1007可以基本上填满上述凹入。
另外，还可以制作浅沟槽隔离(STI)。例如，可以通过在需要隔离之处刻蚀沟槽，然后在沟槽中填充氧化物，来形成STI 1051，如图5所示。本领域技术人员知道多种STI工艺，在此不再赘述。STI 1051可以分别设置在p型器件的有源区周围以及n型器件的有源区周围。
接下来，可以在第一源/漏层1031和第二源/漏层1005中形成源/漏区。这可以通过对第一源/漏层1031和第二源/漏层1005进行掺杂来形成。例如，这可以如下进行。
具体地，如图6所示，可以在图5所示的结构上形成p型掺杂剂源层1009p。例如，p型掺杂剂源层1009p可以包括氧化物如氧化硅，其中含有p型掺杂剂如B。在此，掺杂剂源层1009可以是一薄膜，例如厚度为约2-10nm，从而可以通过例如化学气相淀积(CVD)或原子层淀积(ALD)等大致共形地淀积在图5所示结构的表面上。
另外，为了避免与随后形成的n型掺杂剂源层之间的交叉污染，可以在p型掺杂剂源层1009p上形成扩散阻挡层1053。例如，扩散阻挡层1053可以包括氮化物、氮氧化物、氧化物等，厚度为约0.5-5nm。
然后，如图7所示，可以对p型掺杂剂源层1009p(以及扩散阻挡层1053)进行构图(例如，通过光刻)，使其留于需要进行p型掺杂的区域。在该示例中，p型掺杂剂源层1009p可以留于p型器件区域(因为其源/漏层需要p型掺杂)以及n型器件区域中将形成体接触的区域(如果有的话，因为对于n型器件可以形成p型的体接触区)。
接着，如图8所示，可以在图7所示的结构上形成n型掺杂剂源层1009n。例如，n型掺杂剂源层1009n可以包括氧化物，其中含有n型掺杂剂如As或P，厚度为约2-10nm。n型掺杂剂源层1009n可以按p型掺杂剂源层1009p相同的方式形成。n型掺杂剂源层1009n可以覆盖需要n型掺杂的区域，例如n型器件区域(因为其源/漏层需要n型掺杂)以及p型器件区域中将形成体接触的区域(如果有的话，因为对于p型器件可以形成n型的体接触区)。
可选地，还可以在n型掺杂剂源层1009n形成另一扩散阻挡层，以抑制向外扩散或交叉污染。
接着，如图9所示，可以通过例如在约800-1100℃下进行退火，使掺杂剂源层1009p和1009n中包含的掺杂剂进入有源区中，从而在其中形成掺杂区，如图中的阴影部分所示。更具体地，在p型器件区域中，可以在第一源/漏层1031p中形成p型器件的源/漏区之一1011p-1，且在第二源/漏层1005p中形成p型器件的另一源/漏区1011p-2。类似地，在n型器件区域中，可以在第一源/漏层1031n中形成n型器件的源/漏区之一1011n-1，且在第二源/漏层1005n中形成n型器件的另一源/漏区1011n-2。之后，可以去除掺杂剂源层1009p和1009n以及扩散阻挡层1053。
另外，尽管有牺牲栅1007存在，但是掺杂剂也可以经由第一源/漏层1031和第二源/漏层1005而进入沟道层1003中，从而在沟道层1003的上下两端处形成一定的掺杂分布(例如形成延伸区)，如图中的椭圆虚线圈所示。这种掺杂分布可以降低器件导通时源漏区之间的电阻，从而提升器件性能。
在以上示例中，通过从掺杂剂源层向有源区中驱入(drive in)掺杂剂来形成源/漏区，但是本公开不限于此。例如，可以通过离子注入、等离子体掺杂(例如，沿着图5中结构的表面进行共形掺杂)等方式，来形成源/漏区。当然，可以对需要p型掺杂的区域和需要n型掺杂的区域分别进行。在对一个区域进行处理时，可以利用例如光刻胶遮挡另一区域。这种分区域处理在CMOS工艺中是常见的。另外，如果形成相同导电类型的器件，则还可以在生长源/漏层时进行原位掺杂。
在以上示例中，先形成p型掺杂剂源层1009p，然后再形成n型掺杂剂源层1009n。但是本公开不限于此，它们的顺序可以交换。
另外，为了降低源/漏与栅之间的电容，还可以对源/漏层进行细化处理，并部分地用低k介质替代。例如，如图27所示，可以在图9所示的结构(去除掺杂剂源层和扩散阻挡层)中，选择性刻蚀源/漏层，使其变细(甚至可以细于沟道层)。之后，如图28所示，可以通过侧墙(spacer)形成工艺，利用低k介质来形成低k介质侧墙1007′。
另外，为了降低接触电阻，还可以对源/漏层进行硅化处理。例如，可以在图9所示的结构(去除掺杂剂源层和扩散阻挡层或在上述源/漏极进行细化处理之后且在形成低k介质侧墙1007′之前)上淀积一层NiPt(例如，Pt含量为约2-10％，厚度为约2-10nm)，并在约200-400℃的温度下退火，使NiPt与Si发生反应，从而生成SiNiPt。之后，可以去除未反应的剩余NiPt。
接下来，可以形成栅堆叠。为了减少栅堆叠与源/漏层之间的交迭，可以在有源区周围形成介质层，以遮挡下层的源/漏层1031。例如，如图10所示，可以在图9所示的结构上(或者，在进行源/漏层细化处理的情况下，在图28所示的结构上)淀积氧化物，并对其回蚀，以形成介质层1013。在回蚀之前，可以对淀积的氧化物进行平坦化处理如化学机械抛光(CMP)或溅射。在此，介质层1013的顶面可以位于沟道层1003的顶面与底面之间，这有助于形成自对准的栅堆叠，这将在以下进一步详细描述。
在形成介质层时，可以保留牺牲栅1007，以避免介质层的材料进入要容纳栅堆叠的上述凹入中。之后，可以去除牺牲栅1007，以释放该凹入中的空间。例如，可以相对于介质层1013(氧化物)以及第二源/漏层1005(SiGe)和沟道层1003(Si)，选择性刻蚀牺牲栅1007(氮化物)。
然后，如图11所示，可以在凹入中形成栅堆叠。在此，可以针对p型器件和n型器件，分别形成不同的栅堆叠。以下，以先形成p型器件的栅堆叠为例进行描述。但是，本公开不限于此，例如也可以先形成n型器件的栅堆叠。
具体地，可以在图10所示的结构(去除牺牲栅1007)上依次淀积栅介质层1015和针对p型器件的栅导体层1017p，并对所淀积的栅导体层1017p(以及可选地栅介质层1015)进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1003的顶面。例如，栅介质层1015可以包括高K栅介质如HfO2；栅导体层1017p可以包括金属栅导体。另外，在栅介质层1015和栅导体层1017p之间，还可以形成功函数调节层。在形成栅介质层1015之前，还可以形成例如氧化物的界面层。
由于介质层1013的顶面设置，栅堆叠仅与沟道层1003在竖直方向上的侧面相交迭，而与第一、第二源/漏层各自在竖直方向上的侧面不交迭。即，栅堆叠自对准于沟道层1003。这样，栅堆叠可以嵌入到凹入中，从而与沟道层1003的整个高度相交迭。
然后，如图12所示，可以对栅导体层1017p进行选择性刻蚀如RIE。刻蚀可以有源区特别是顶端的第二源/漏层为掩模。例如，可以以大致垂直于衬底表面的方向进行RIE，于是栅导体层1019p可仅留在凹入内。刻蚀可以停止于栅介质层1015。然后，如图13所示，可以利用例如光刻胶1055遮蔽p型器件区域中的栅导体层1017p(当前处于凹入内)，并露出n型器件区域中的栅导体层1017p。之后，可以通过选择性刻蚀如湿法腐蚀，去除n型器件区域中的栅导体层1017p。于是，形成了针对p型器件的栅堆叠(1015/1017p)，该栅堆叠嵌入在p型器件的沟道层1003p的凹入中。
接下来，可以形成针对n型器件的栅堆叠。n型器件的栅堆叠也可以类似地形成。例如，如图14所示，可以形成针对n型器件的栅导体层1017n。例如，可以在图13所示的结构(去除光刻胶1055)上淀积栅导体层1017n，并对所淀积的栅导体层1017n进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1003的顶面。例如，栅导体层1017n可以包括金属栅导体。另外，在栅介质层1015和栅导体层1017n之间，还可以形成功函数调节层。在该示例中，n型器件和p型器件可以共用相同的栅介质层1015；当然，本公开不限于此，例如也可以去除栅介质层1015，并针对n型器件另外形成栅介质层。由于n型器件沟道层1003n和p型器件沟道层1003p是同时经过薄膜生长和选择性刻蚀而形成的，n型器件沟道层1003n的上表面与p型器件沟道层1003p的上表面基本共面，n型器件沟道层1003n的下表面与p型器件沟道层1003p的下表面基本共面。
可以看到，栅导体层1017n不仅形成于n型器件区域中，还形成于p型器件区域中，且与栅导体层1017p相接触。之后，可以利用栅导体层1017n制作栅极接触垫，以便随后制作到栅极的接触部。
当然，形成栅堆叠的方式不限于此。例如，在形成针对p型器件的栅堆叠之后，可以利用光刻胶遮蔽p型器件区域，并通过选择性刻蚀如RIE，去除栅导体层1017p在n型器件区域的部分。然后，可以在n型器件区域中形成针对n型器件的栅堆叠(例如，在保留光刻胶遮蔽p型器件区域的情况下)。
接下来，可以对栅导体层1017n进行构图，形成栅极接触垫，以便于后继互连制作。例如，如图15(a)和15(b)(图15(a)是截面图，图15(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图14所示的结构上形成光刻胶1019。该光刻胶1019例如通过光刻构图为覆盖栅导体层1017n露于凹入之外的一部分，且露出栅导体层1017n露于凹入之外的其他部分。在该示例中，如图15(b)所示，光刻胶1019在p型器件区域和n型器件区域可以分别呈从相应有源区的外周向外沿一定方向延伸的条状。为便于构图，p型器件区域和n型器件区域上的光刻胶条彼此实质上对准。
然后，如图16所示，可以光刻胶1019为掩模，对栅导体层1017n进行选择性刻蚀如RIE。这样，栅导体层1017n除了留于凹入之内的部分之外，被光刻胶1019遮挡的部分得以保留，并用作栅极接触垫。随后，可以通过这种栅极接触垫来实现到栅堆叠的电连接。
根据另一实施例，可以进一步处理，以露出第一源/漏层1031和第二源/漏层1005的表面(第二源/漏层1005的表面事实上已经露出在外)，特别是即将要在之上形成接触部的上表面。为此，可以进一步对栅介质层1015和隔离层1013进行选择性刻蚀如RIE。RIE可以沿大致垂直于衬底表面的方向进行。于是，除了留于栅堆叠下方的部分之外，第一源/漏层1031的上表面被露出。之后，可以去除光刻胶1019。
然后，可以分别在p型器件和n型器件的有源区(特别是源/漏层)表面上形成应力衬层。例如，如图17所示，可以在图16所示的结构上形成针对p型器件的应力衬层1101。例如，可以通过大致共形地淀积一层氮化物层，来形成应力衬层1101。应力衬层1101的厚度可以为约10-50nm，可以带拉应力，以在沟道层中产生压应力。另外，在应力衬层1101上可以形成例如淀积刻蚀停止层1103，例如氧化物。然后，可以形成覆盖p型器件区域的光刻胶1057，并以光刻胶1057为掩模，对刻蚀停止层1103以及应力衬层1101进行选择性刻蚀如RIE，使其留于p型器件区域中。之后，可以去除光刻胶1057。
另外，可以按相似的方式，在n型器件区域上形成应力衬层1105。例如，如图18所示，可以在图17所示的结构上形成针对n型器件的应力衬层1105。例如，可以通过大致共形地淀积一层氮化物层，来形成应力衬层1105。应力衬层1105的厚度可以为约10-50nm，可以带压应力，以在沟道层中产生拉应力。然后，可以形成覆盖n型器件区域的光刻胶1059，并以光刻胶1059为掩模，对应力衬层1105进行选择性刻蚀如RIE，使其留于n型器件区域中。RIE可以停止于刻蚀停止层1103。之后，可以去除光刻胶1059。
这样，就在p型器件区域和n型器件区域分别形成了相应的应力衬层，它们的形成顺序可以交换。如图所示，应力衬层可以覆盖源/漏层的上表面，于是可以保护有源区，而且可以在随后的接触孔刻蚀时充当刻蚀停止层。
然后，可以如图19所示，在图18所示的结构上形成层间电介质层1021。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1021。在图19中，将氧化物的刻蚀停止层1103与层间电介质层一体示出。在层间电介质层1021中，对于p型器件区域，可以形成到源/漏区1011p-1的接触部1023p-1、到源/漏区1011p-2的接触部1023p-2以及到栅导体层1017的接触部1023p-3，并可以形成到阱区1001w的接触部1023n-w。类似地，对于n型器件区域，可以形成到源/漏区1011n-1的接触部1023n-1、到源/漏区1011n-2的接触部1023n-2以及到栅导体层1017的接触部1023n-3，并可以形成到p型衬底1001的接触部1023p-w。这些接触部可以通过在层间电介质层1021以及应力衬层中刻蚀孔洞，并在其中填充导电材料如金属(例如，钨)来形成。在填充金属之前，可以在接触孔的内壁上形成阻挡层如TiN。
在刻蚀接触孔时，对于层间电介质层1021的刻蚀，可以停止于应力衬层，然后可以对基本上均匀厚度的应力衬层进行刻蚀。由于到源/漏区的接触部以及到栅导体层的接触部具有不同的高度，因此对于接触孔的刻蚀是困难的。而在该实施例中，由于应力施加层的存在，可以相对容易地控制接触孔刻蚀的停止。
由于栅极接触垫的存在，从而可以容易地形成到栅极的接触部。另外，由于第一源/漏层中的掺杂区延伸超出有源区之外且至少在其一部分上方并不存在栅极接触垫，从而可以容易地形成它的接触部。
如图19所示，根据该实施例的半导体器件可以包括均为竖直器件形式的p型器件和n型器件。p型器件和n型器件各自均包括沿竖直方向叠置的第一源/漏层1031、沟道层1003和第二源/漏层1005。在第一源/漏层1031和第二源/漏层1005中形成了源/漏区。沟道层1003横向凹入，栅堆叠绕沟道层1003的外周形成，且嵌于该凹入中。各器件还包括从栅导体向外延伸的栅极接触垫。
图20和21分别示出了根据该实施例的CMOS配置的半导体器件的端子连接方式。
如图20所示，p型器件的第一源/漏层1031p和n型阱可以连接到供电电压Vdd，栅极可以连接到输入信号IN，并可以从第二源/漏层1005p引出输出信号OUT。类似地，n型器件的第一源/漏层1031n和p型衬底可以连接到地电压GND(在此，假定Vdd大于GND)，栅极可以连接到输入信号IN，并可以从第二源/漏层1005n引出输出信号OUT。在这种连接方式下，在p型器件区域和n器件区域中，第一源/漏层与阱区(或p型衬底)之间并没有结泄漏。但是，可能存在阱之间(n型阱区与p型衬底之间)的结泄漏。
备选地，如图21所示，可以将图20中所示的第一源/漏层和第二源/漏层的连接互换。在这种连接方式下，尽管可能存在第一源/漏层与阱区(或p型衬底)之间的结泄漏，但是在某些情况下可以节省面积，因为n型器件和p型器件可以共享接触部。以下将对此进一步描述。
图22至25示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图。
在如以上结合图9所述形成源/漏区并去除掺杂剂源层以及扩散阻挡层之后，如图22所示，可以在p型器件与n型器件区域之间形成导电桥1107。例如，可以图在9所示的结构(去除掺杂剂源层和扩散阻挡层)上，淀积一层导电材料如金属。然后，形成光刻胶1061，该光刻胶1061被构图为覆盖在p型器件与n型器件区域之间延伸的一部分导电材料。之后，可以光刻胶1061为掩模，对导电材料进行选择性刻蚀如RIE，得到导电桥1107。该导电桥1107跨越STI，将p型器件的第一源/漏层1031p和n型器件的第一源/漏层1031n电连接在一起。
备选地，可以按形成导电桥1107的方式，形成一层Si。然后，在进行硅化处理的情况下，Si层可以转变为导电的硅化物，并构成导电桥1107。
接下来，可以按照上述实施例中相同的方式进行处理。
如图23(a)和23(b)(图23(a)是截面图，图23(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以形成p型器件和n型器件各自的栅堆叠，然后形成光刻胶1019′对栅导体层进行构图，以形成栅极接触垫。与上述实施例的不同之处在于，在该示例中，光刻胶1019′在p型器件区域和n型器件区域之间连续延伸。于是，如图24(a)和24(b)(图24(a)是截面图，图24(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，栅导体层1017n从n型器件延伸到p型器件。另外，在图24(b)中，以虚线框示意性示出了导电桥1017。
图25示出了形成接触部之后的器件结构。如图25所示，在该示例中，p型器件和n型器件可以共享栅极接触部1023-3以及源/漏接触部1023-1。其他连接方式可以与前述实施例中相同。可以看到，接触部的数目从8减到了6，于是可以减少接触部面积。
图26示出了根据本公开另一实施例的半导体器件的截面图。
图26中示出了金属化叠层中的若干层，如第一金属层M1和第二金属层M2以及它们之间的过孔。p型器件和n型器件可以共享栅极接触部1023-3，并可以接收输入信号。但是，在该示例中，并未形成导电桥。p型器件和n型器件各自的源/漏接触部1023p、1023n可以在第二金属层M2中互连在一起，并构成输出。在图26所示的连接方式下，如上所述，在源/漏层与阱区之间可以没有结泄漏，从而可以降低功耗。
根据本公开的实施例，还可以在不同器件区域处形成不同的沟道层厚度(从而提供不同的栅长)。
例如，如图29所示，在如以上结合图1所述在衬底1001上生长第一源/漏层1031和沟道层1003之后，可以对沟道层1003进行减薄处理。第一源/漏层1031和沟道层1003可以大致均匀地生长(从而具有基本均匀的厚度，因此它们各自的上下表面可以大致平行于衬底表面延伸)。在第一器件区域处，可以通过选择性刻蚀，使沟道层1003的厚度减小，此时第二器件区域可以被遮蔽(例如，通过光刻胶)。于是，尽管沟道层1003在衬底1001上仍然沿着平行于衬底表面的平面一体延伸，但是其厚度发生变化(由于其顶面凹入)。
然后，如图30所示，可以在沟道层1003上进一步生长第二源/漏层1005。随着第二源/漏层1005的生长，各器件区域之间的厚度差异可以逐渐减小，甚至最终消失(体现为第二源/漏层1005的顶面实质上平坦，且大致平行于衬底表面；但是，如果第二源/漏层1005较薄，则仍然可能存在厚度波动，这不影响后继工艺的进行)。
根据另一实施例，如图31所示，在如以上结合图1所述在衬底1001上生长第一源/漏层1031之后，可以对第一源/漏层1031进行减薄处理。第一源/漏层1031可以大致均匀地生长(从而具有基本均匀的厚度，因此其上下表面可以大致平行于衬底表面延伸)。在第一器件区域处，可以通过选择性刻蚀，使第一源/漏层1031的厚度减小，此时第二器件区域可以被遮蔽(例如，通过光刻胶)。
然后，如图32所示，可以在第一源/漏层1031上进一步生长沟道层1003。随着第二源/漏层沟道层1003的生长，各器件区域之间的厚度差异可以逐渐减小，甚至最终消失(体现为沟道层1003的顶面实质上平坦，且大致平行于衬底表面；但是，如果沟道层1003较薄，则仍然可能存在厚度波动，这不影响后继工艺的进行)。之后，可以在沟道层1003上进一步生长第二源/漏层1005。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (40)

1.一种半导体器件，包括：
衬底；
在衬底上形成的第一器件和第二器件，第一器件和第二器件分别包括：
依次叠置在衬底上的第一源/漏层、沟道层和第二源/漏层；以及
绕沟道层的外周形成的栅堆叠，
其中，第一器件的沟道层与第二器件的沟道层基本共面。
2.根据权利要求1所述的半导体器件，其中，
第一器件的沟道层的上表面与第二器件的沟道层的上表面基本共面；和/或
第一器件的沟道层的下表面与第二器件的沟道层的下表面基本共面。
3.根据权利要求1所述的半导体器件，其中，第一器件的沟道层的厚度与第二器件的沟道层的厚度不同，或者第一器件的沟道长度与第二器件的沟道长度不同。
4.根据权利要求1所述的半导体器件，还包括：从栅堆叠中的栅导体层沿着远离沟道层的方向延伸的栅极接触垫，其中，第一器件和第二器件中至少之一的栅导体层和相应的栅极接触垫包括不同的材料。
5.根据权利要求4所述的半导体器件，其中，第一器件和第二器件的栅极接触垫包括相同的材料。
6.根据权利要求4所述的半导体器件，其中，第一器件和第二器件中另一个的栅导体层和相应的栅极接触垫包括相同的材料，且成一体延伸。
7.根据权利要求4至6中任一项所述的半导体器件，其中，第一器件和第二器件的栅极接触垫彼此电连接。
8.根据权利要求7所述的半导体器件，其中，第一器件和第二器件的栅极接触垫彼此直接物理连接。
9.根据权利要求1所述的半导体器件，其中，第一器件和第二器件各自的沟道层包括与第一、第二源/漏层不同的半导体材料。
10.根据权利要求1所述的半导体器件，其中，沟道层包括沟道层单晶半导体材料。
11.根据权利要求1所述的半导体器件，其中，沟道层靠近第一源/漏层和第二源/漏层的端部具有掺杂分布。
12.根据权利要求1所述的半导体器件，还包括：
在衬底上形成的隔离层，其中隔离层的顶面处于沟道层的顶面与底面之间。
13.根据权利要求1所述的半导体器件，其中，第一源/漏层是在衬底上外延生长的半导体层，沟道层是在第一源/漏层上外延生长的半导体层，第二源/漏层是在沟道层上外延生长的半导体层，源/漏层与沟道层之间具有晶体界面和/或掺杂浓度界面。
14.根据权利要求1所述的半导体器件，其中，沟道层的外周相对于第一、第二源/漏层的外周向内凹入，栅堆叠嵌于沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中。
15.根据权利要求1所述的半导体器件，其中，沟道层的外周相对于第一、第二源/漏层的外周向外凸出。
16.根据权利要求1所述的半导体器件，还包括在第一器件的第一源/漏层和第二源/漏层的表面上设置的第一应力衬层以及在第二器件的第一源/漏层和第二源/漏层的表面上设置的第二应力衬层中至少之一。
17.根据权利要求16中所述的半导体器件，其中，
第一器件是n型器件，且第一应力衬层带压应力；
第二器件是p型器件，且第二应力衬层带拉应力。
18.根据权利要求7所述的半导体器件，其中，
第一器件是n型器件且第二器件是p型器件，二者形成CMOS配置，
所述半导体器件还包括：连接第一器件的第一源/漏层与p型器件的第一源/漏层的导电桥。
19.一种制造半导体器件的方法，包括：
在衬底上外延生长第一源/漏层；
在第一源/漏层上形成在第一器件区域和第二器件区域中基本共面的沟道层；
在沟道层上外延生长第二源/漏层；
从堆叠的第一源/漏层、沟道层和第二源/漏层分别在第一器件区域和第二器件区域限定出第一器件的有源区和第二器件的有源区；以及
分别绕第一器件和第二器件各自有源区中的沟道层的外周形成相应器件的栅堆叠。
20.根据权利要求19所述的方法，其中，形成基本共面的沟道层包括外延生长。
21.根据权利要求19所述的方法，其中，形成基本共面的沟道层包括：
在第一源/漏层上均匀地生长沟道层；以及
在第一器件区域和第二器件区域之一中减薄所生长的沟道层。
22.根据权利要求19所述的方法，其中，形成基本共面的沟道层包括：
在第一源/漏层上均匀地生长沟道层；以及
在第一器件区域和第二器件区域之一中进一步生长沟道层。
23.根据权利要求19所述的方法，其中，生长第一源/漏层包括：
在衬底上均匀地生长第一源/漏层；以及
在第一器件区域和第二器件区域之一中减薄所生长的第一源/漏层。
24.根据权利要求19所述的方法，还包括：
形成第一器件和第二器件各自的栅极接触垫，栅极接触垫分别从相应栅堆叠中的栅导体层沿着远离沟道层的方向延伸，且第一器件和第二器件中至少之一的栅导体层和相应的栅极接触垫包括不同的材料。
25.根据权利要求24所述的方法，其中，利用第一器件和第二器件之一的栅导体层来形成栅极接触垫。
26.根据权利要求24所述的方法，其中，
限定有源区包括：在第一器件和第二器件各自的有源区中，使沟道层的外周相对于第一、第二源/漏层的外周凹入，
形成栅堆叠包括：分别在第一器件和第二器件各自有源区中的沟道层的凹入中形成针对相应器件的栅堆叠。
27.根据权利要求26所述的方法，其中，限定有源区包括：
依次对第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀；以及
进一步选择性刻蚀沟道层，使得沟道层相对于第一、第二源/漏层的外周凹入。
28.根据权利要求27所述的方法，其中，所述选择性刻蚀包括原子层刻蚀。
29.根据权利要求26所述的方法，还包括：
分别对第一器件和第二器件各自的第一源/漏层和第二源/漏层进行掺杂，以在第一源/漏层和第二源/漏层中形成源/漏区。
30.根据权利要求29所述的方法，其中，进行掺杂包括：
在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅；
在第一源/漏层和第二源/漏层的表面上形成掺杂剂源层；以及
使掺杂剂源层中的掺杂剂经第一、第二源/漏层进入有源区中，
其中，对于第一器件和第二器件分别形成具有相应导电类型掺杂剂的掺杂剂层。
31.根据权利要求30所述的方法，其中，掺杂剂不仅进入第一、第二源/漏层中，还进入沟道层靠近第一源/漏层和第二源/漏层的端部。
32.根据权利要求26所述的方法，还包括：
在衬底上有源区的周围形成隔离层，其中隔离层的顶面处于沟道层的顶面与底面之间。
33.根据权利要求32所述的方法，其中，
形成第一器件和第二器件之一的栅堆叠包括：
在隔离层上依次形成栅介质层和第一栅导体层；以及
选择性刻蚀第一栅导体层，使得第一栅导体层在所述凹入之外的部分被去除，
形成第一器件和第二器件中另一个的栅堆叠包括：
在隔离层上依次形成栅介质层和第二栅导体层；以及
回蚀第二栅导体层，使得第二栅导体层在所述凹入之外的部分的顶面低于沟道层的顶面，
其中，形成栅极接触垫包括：对第二栅导体层处于凹入之外的部分进行构图。
34.根据权利要求33所述的方法，其中，将第二栅导体层构图为一直延伸到物理接触第一栅导体层。
35.根据权利要求19所述的方法，还包括：分别在第一器件和第二器件各自的第一源/漏层和第二源/漏层的表面上形成第一应力衬层和第二应力衬层。
36.根据权利要求35所述方法，其中，应力衬层还充当接触孔刻蚀时的刻蚀停止层。
37.根据权利要求30所述的方法，还包括：
对第一源/漏层和和第二源/漏层进行细化处理，使得沟道层相对于第一源/漏层和第二源/漏层不凹入。
38.一种电子设备，包括由如权利要求1至18中任一项所述的半导体器件形成的集成电路。
39.根据权利要求38所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
40.根据权利要求38所述的电子设备，该电子设备包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或移动电源。
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