WO2020082406A1 - 半导体器件及其制造方法及包括该器件的电子设备 - Google Patents

半导体器件及其制造方法及包括该器件的电子设备 Download PDF

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Publication number
WO2020082406A1
WO2020082406A1 PCT/CN2018/113052 CN2018113052W WO2020082406A1 WO 2020082406 A1 WO2020082406 A1 WO 2020082406A1 CN 2018113052 W CN2018113052 W CN 2018113052W WO 2020082406 A1 WO2020082406 A1 WO 2020082406A1
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layer
channel layer
source
drain
semiconductor
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PCT/CN2018/113052
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English (en)
French (fr)
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朱慧珑
张永奎
尹晓艮
李晨
刘永波
贾昆鹏
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中国科学院微电子研究所
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Priority to US17/250,770 priority Critical patent/US20210193533A1/en
Publication of WO2020082406A1 publication Critical patent/WO2020082406A1/zh
Priority to US18/477,004 priority patent/US20240021483A1/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to vertical semiconductor devices and methods of manufacturing the same, and electronic equipment including such semiconductor devices.
  • a horizontal type device such as a metal oxide semiconductor field effect transistor (MOSFET)
  • MOSFET metal oxide semiconductor field effect transistor
  • the source, gate, and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, reducing the area occupied by horizontal devices generally requires that the areas occupied by the source, drain, and gate are reduced, which degrades device performance (eg, increased power consumption and resistance). The area is not easy to shrink further.
  • the source, gate, and drain are arranged in a direction substantially perpendicular to the surface of the substrate. Therefore, compared with the horizontal type device, the area occupied by the vertical type device is easier to shrink.
  • an object of the present disclosure is at least partially to provide a vertical type semiconductor device capable of providing improved characteristics, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.
  • a semiconductor device including: a substrate; a first device and a second device formed on the substrate, each of the first device and the second device includes: from below on the substrate A first source / drain layer, a channel layer, and a second source / drain layer stacked in this order, and a gate stack formed around at least a portion of the outer periphery of the channel layer; the channel layer of each of the first device and the second device At least part of the side walls extend along different crystal planes or families of planes.
  • a method of manufacturing a semiconductor device including: providing a stack of a first source / drain layer, a channel layer, and a second source / drain layer on a substrate from bottom to top;
  • the stacked first source / drain layer, channel layer, and second source / drain layer respectively define an active region of the first device and an active region of the second device, and make the respective grooves of the first device and the second device At least part of the sidewalls of the channel layer extend along different crystal planes or families of planes; and a gate stack of the corresponding device is formed around at least part of the periphery of the channel layer in the respective active regions of the first device and the second device.
  • an electronic device including an integrated circuit formed at least in part by the above-described semiconductor device.
  • a semiconductor device includes a vertical type device, which can greatly reduce the area and save space compared to a horizontal type device.
  • the gate stack is formed around at least part of the outer periphery of the channel layer and the channel is formed in the channel layer, so that the gate length can be determined by the thickness of the channel layer, and better control of the gate length can be achieved.
  • at least a part of the sidewalls of the channel layer of different devices may be arranged to extend along different crystal planes or crystal plane families. Since the carriers can have different mobilities in different crystal planes or plane family directions, the carrier mobility in the channel layer of different devices can be adjusted, thereby adjusting the conduction effect of different devices to optimize The overall performance of semiconductor devices.
  • 1 to 18 are schematic diagrams showing the flow of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • 19 to 20 are schematic diagrams showing some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • a layer / element when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / between element.
  • the layer / element may be "below” the other layer / element.
  • the semiconductor device may include a plurality of vertical type devices formed on the substrate.
  • Each vertical device may include a first source / drain layer, a channel layer, and a second source / drain layer sequentially stacked on the substrate.
  • the layers may be adjacent to each other.
  • there may be other semiconductor layers in the middle such as a leakage suppression layer and / or an on-state current enhancement layer (semiconductor layer with a larger or smaller band gap than the adjacent layer).
  • the source / drain regions of the device may be formed in the first source / drain layer and the second source / drain layer, and the channel region of the device may be formed in the channel layer.
  • a conductive channel can be formed through the channel region between the source / drain regions that are located at both ends of the channel region.
  • the stacking configuration of the active regions of different vertical devices may be the same or different.
  • the sidewalls of the channel layer of different devices may extend along different crystal planes or families of crystal planes. Since the carriers can have different mobilities in different crystal planes or plane family directions, the carrier mobility in the channel layer of different devices can be adjusted, thereby adjusting the conduction effect of different devices to optimize The overall performance of semiconductor devices.
  • the channel layer is a single crystal semiconductor material or one of Si, SiGe, or Ge crystals
  • at least part of the sidewalls of the channel layer of the n-type device may be along the (100) crystal plane or ⁇ 100 ⁇ crystal plane Family extension, because the crystal plane or crystal plane family is conducive to electron mobility; and at least part of the sidewall layer of the channel layer of the p-type device can extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family, because the crystal The face or crystal face family favors the mobility of holes.
  • CMOS complementary metal oxide semiconductor
  • not all sidewalls of the channel layer may be optimized (ie, they are extended along a desired crystal plane or family of crystal planes), but only a part of the sidewalls may be optimized.
  • the channel layer can be chamfered.
  • the rounded portion of the side wall may not extend along the desired crystal plane or plane family.
  • the side wall of the channel layer with a larger area can be optimized, and the influence of the side wall with a smaller area can be ignored, for example, in the case of a nanometer wafer.
  • the crystal plane of the sidewall is not a single crystal plane family.
  • the first source / drain layer of the device may point in the direction of its second source / drain layer in the [100] crystal direction or in the ⁇ 100> crystal direction group, which is parallel to the ⁇ 100 ⁇ crystal plane
  • the family and ⁇ 110 ⁇ crystal plane family that is, the ⁇ 100 ⁇ crystal plane family and ⁇ 110 ⁇ crystal plane family may be substantially perpendicular to the substrate, such that the channel layer extending along the ⁇ 100 ⁇ crystal plane family or ⁇ 110 ⁇ crystal plane family
  • the sidewall may be substantially perpendicular to the substrate.
  • the channel layer may be chamfered so that the corner formed by the adjacent sidewalls of the channel layer may be relatively gentle rounded.
  • the channel layer may be composed of a single crystal semiconductor material to improve device performance, such as reducing channel resistance.
  • the single crystal semiconductor materials of the channel layers of different devices may have the same crystal orientation, and / or may have the same crystal structure. In this way, the channel layer of these devices can be manufactured with the same substrate, which is convenient to manufacture and has fewer defects.
  • the first and second source / drain layers may also be composed of single crystal semiconductor materials.
  • the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source / drain layer may be eutectic.
  • the electron or hole mobility of the single crystal semiconductor material of the channel layer may be greater than the electron or hole mobility of the first and second source / drain layers.
  • the forbidden band width of the first and second source / drain layers may be greater than the forbidden band width of the single crystal semiconductor material of the channel layer.
  • the gate stack may be formed around at least part of the periphery of the channel layer. Therefore, the gate length can be determined by the thickness of the channel layer itself, rather than depending on the etching time as in the conventional technique.
  • the channel layer can be formed by epitaxial growth, for example, so that its thickness can be well controlled. Therefore, the gate length can be well controlled.
  • the channel layers of different devices on the substrate can be substantially coplanar, for example they can extend in a plane that is substantially parallel to the surface of the substrate.
  • the upper surface and / or the lower surface of the channel layer of each device may be substantially coplanar. Therefore, the channel layer of each device may have a different thickness, and accordingly may have a different channel length.
  • the gate stack can be self-aligned to the channel layer.
  • the gate stack and the channel layer may be substantially coplanar.
  • the upper surface of the channel layer and at least a portion of the upper surface of the gate stack may be substantially coplanar, and / or the lower surface of the channel layer and at least a portion of the lower surface of the gate stack may be substantially coplanar.
  • the outer periphery of the channel layer may be recessed inward relative to the outer periphery of the first and second source / drain layers. In this way, the formed gate stack can be embedded in the recess of the channel layer relative to the first and second source / drain layers.
  • the range of the gate stack in the stacking direction of the first source / drain layer, the channel layer, and the second source / drain layer lies in the direction in which the recess is in this direction Within range.
  • the gate stack, especially the gate conductor layer therein may need to be
  • the device and the second device are formed differently (for example, the gate conductor layers of the n-type device and the p-type device are respectively formed with gate conductor materials of different work functions).
  • the first device and the second device may respectively include respective gate conductor materials having suitable work functions and self-aligned to respective channel layers.
  • a gate contact pad leading out of the gate conductor layer may also be included.
  • Such gate contact pads may be in electrical contact with the gate stack (specifically, the gate conductor layer) and extend in a direction away from the channel layer (eg, beyond the periphery of the active region).
  • a gate contact pad may be formed using the gate conductor layer of one of the first device and the second device (eg, the first device), even for another device (eg, the second device) .
  • the gate conductor layer of a device may extend outward from the corresponding recess to serve as a gate contact pad, and another part of the gate conductor layer may extend to another device (for example, the first device). Two devices), thus serving as a gate contact pad.
  • Each layer in the active region can be formed by epitaxial growth, so that its thickness can be accurately controlled.
  • the first source / drain layer may be a semiconductor layer epitaxially grown on the substrate
  • the channel layer may be a semiconductor layer epitaxially grown on the first source / drain layer
  • the second source / drain layer may be a channel An epitaxially grown semiconductor layer on the layer.
  • Such a semiconductor device can be manufactured as follows, for example. Specifically, a stack of the first source / drain layer, the channel layer, and the second source / drain layer may be provided on the substrate from bottom to top.
  • the first source / drain layer may be provided by the substrate itself or by epitaxial growth on the substrate.
  • a channel layer may be epitaxially grown on the first source / drain layer, and a second source / drain layer may be epitaxially grown on the channel layer.
  • the thickness of the grown channel layer can be controlled. Due to the respective epitaxial growth, at least a pair of adjacent layers may have a clear crystal interface.
  • each layer may be doped differently, so that at least a pair of adjacent layers may have a doping concentration interface.
  • certain processing may be performed so that it may have different thicknesses in the first device region and the second device region.
  • the channel layer may be thinned (eg, etched) after growing the channel layer, or the channel layer may be further grown (ie, thickened) in a device region; or, the After growing the first source / drain layer, a thinning process (eg, etching) is performed on a portion of the device region, and then the channel layer is regrown.
  • the active region of the first device and the active of the second device may be defined in the first device region and the second device region, respectively Area. For example, they can be selectively etched into desired shapes in sequence. The respective active regions of the first device and the second device can be obtained from the same first source / drain layer, channel layer and second source / drain layer.
  • the sidewall of the channel layer may be formed along a certain crystal plane or family of crystal planes.
  • the same mask is usually used when defining the active region, so the sidewalls of the first source / drain layer and the second source / drain layer can also extend along the same crystal plane or family of crystal planes. Therefore, the active region may have a square column shape.
  • the first device and the second device especially when they have different conductivity types, at least part of the sidewalls of their respective channel layers may extend along different crystal planes or crystal plane families.
  • the etching of the first source / drain layer may only target the upper part of the first source / drain layer, so that the first source / drain layer The lower part can extend beyond the periphery of its upper part. Then, a gate stack of the corresponding device is formed around at least part of the periphery of the channel layer in the respective active regions of the first device and the second device, respectively.
  • the outer periphery of the channel layer may be recessed inward with respect to the outer periphery of the first and second source / drain layers, so as to define a space for accommodating the gate stack.
  • this can be achieved by selective etching.
  • the gate stack can be embedded in the recess.
  • the recess of the channel layer can be achieved by isotropic etching.
  • the sharp corners formed between the adjacent sidewalls of the channel layer can be treated as relatively gentle rounded corners.
  • Source / drain regions may be formed in the first and second source / drain layers. For example, this can be achieved by doping the first and second source / drain layers. For example, ion implantation, plasma doping, etc. can be performed.
  • a sacrificial gate may be formed in the recess formed by the outer periphery of the channel layer relative to the outer periphery of the first and second source / drain layers, and then on the surfaces of the first and second source / drain layers A dopant source layer is formed, and the dopant in the dopant source layer enters the active region through the first and second source / drain layers by, for example, annealing.
  • the sacrificial gate can prevent the dopant in the dopant source layer from directly entering the channel layer. However, some dopants may enter the channel layer near the ends of the first source / drain layer and the second source / drain layer via the first and second source / drain layers. If the first device and the second device have different conductivity types, they can be doped separately.
  • Gate stacks for respective devices may be formed in the recesses of the channel layers of the first device and the second device, respectively. If the first device and the second device have different conductivity types and respectively form different gate stacks, their gate stacks may be formed one after another. When the gate stack is formed at a later time, the gate conductor layers therein can be used to form the gate contact pads of the first device and the second device. This can be formed by patterning the gate conductor layer.
  • FIGS. 1 to 18 show schematic diagrams of the flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • the description will be made by taking n-type devices and p-type devices separately as an example, in order to show the formation of devices of different conductivity types in more detail. It should be understood that, of course, devices of the same conductivity type can also be formed.
  • a substrate 1001 is provided.
  • the substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is taken as an example for description.
  • a p-type silicon wafer is provided as the substrate 1001.
  • an n-type well region 1001w can be formed by ion implantation, for example.
  • the p-type device can be formed on the n-type well region 1001w (hence it is called a p-type device region); and the n-type device can be formed on another region of the p-type Si substrate 1001 (hence it is called an n-type device region).
  • the substrate 1001 may be (100) single crystal silicon, single crystal silicon germanium, or single crystal germanium wafer. At this time, there are both ⁇ 100 ⁇ crystal planes and ⁇ 110 ⁇ crystal planes among the crystal planes perpendicular to the (100) crystal plane, which is advantageous for the manufacture of the following devices.
  • a first source / drain layer 1031, a channel layer 1003, and a second source / drain layer 1005 may be sequentially formed by, for example, epitaxial growth.
  • the first source / drain layer 1031 may include SiGe (the atomic percentage of Ge may be about 10-40%) with a thickness of about 20-50 nm;
  • the channel layer 1003 may include Si with a thickness of about 10-100 nm;
  • the second The source / drain layer 1005 may include SiGe (the atomic percentage of Ge may be about 10-40%), and the thickness is about 20-50 nm.
  • the material selection of the first source / drain layer 1031, the channel layer 1003, and the second source / drain layer 1005 is not limited thereto, and may include other semiconductor materials that can provide appropriate etching selectivity.
  • the channel layer 1003 may include Si: C, Ge, or a group III-V compound semiconductor material.
  • the channel layer 1003 may include the same constituent components as the first source / drain layer 1031 and the second source / drain layer 1005, but semiconductor materials with different component contents (for example, all are SiGe, but the atoms of Ge (The percentages are different) as long as the channel layer 1031 has an etch selectivity with respect to the first source / drain layer 1031 above and the second source / drain layer 1005 above.
  • FIGS. 2 (a) and 2 (b) are cross-sectional views
  • FIG. 2 (b) is a top view, where the line AA ′ shows the location of the cross-section
  • a photoresist (not shown) is formed on the second source / drain layer 1005 shown in FIG. 1, and the photoresist is patterned into a desired shape by photolithography (exposure and development).
  • the photoresist may be patterned according to the crystal plane or crystal plane family direction.
  • the channel sidewall is expected to extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family, so the corresponding photoresist can be patterned so that the sidewall is parallel to the substrate 1001 ( 110)
  • a substantially rectangular pattern of crystal planes or ⁇ 110 ⁇ crystal plane families because the channel layer is epitaxially grown on the substrate 1001, and is also parallel to the (110) crystal plane or ⁇ 110 ⁇ crystal plane family of the channel layer).
  • the channel sidewalls are expected to extend along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family, so the corresponding photoresist can be patterned so that the sidewalls are parallel to the substrate 1001 (100) crystal plane or ⁇ 100 ⁇ crystal plane family (because the channel layer is epitaxially grown on the substrate 1001, it is also parallel to the (100) crystal plane or ⁇ 100 ⁇ crystal plane family of the channel layer) substantially rectangular pattern .
  • the second source / drain layer 1005, the channel layer 1003, and the first source / drain layer 1031 are sequentially subjected to selective etching such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • the etching proceeds into the first source / drain layer 1031, but does not proceed to the bottom surface of the first source / drain layer 1031, so as to facilitate subsequent manufacturing of the contact.
  • the upper portions of the second source / drain layer 1005, the channel layer 1003, and the first source / drain layer 1031 are formed in a rectangular column shape.
  • RIE can be performed, for example, in a direction substantially perpendicular to the surface of the substrate, so that the two square columns are also substantially perpendicular to the surface of the substrate. After that, the photoresist can be removed.
  • the active regions for p-type devices and n-type devices are patterned in the p-type device region and the n-type device region, respectively.
  • the first source / drain layer, channel layer, and second source / drain layer for p-type devices are denoted as 1031p, 1003p, and 1005p, respectively, and the first source / drain layer for n-type devices
  • the drain layer, the channel layer, and the second source / drain layer are marked as 1031n, 1003n, and 1005n, respectively.
  • the first source / drain layer 1031 is still continuous between the p-type device and the n-type device region, and the dotted line between the p-type device region and the n-type device region is schematically shown in FIG. 2 (a). boundary.
  • reference numerals 1031, 1003, and 1005 are used; and when the p-type device area and the n-type device area need to be described separately , Then use the reference signs of 1031p, 1003p and 1005p and 1031n, 1003n and 1005n respectively.
  • the crystal plane or ⁇ 110 ⁇ crystal plane family extends, and at least part of the sidewalls of the second source / drain layer 1005n, channel layer 1003n, and first source / drain layer 1031n of the n-type device region are along (100)
  • the crystal plane or ⁇ 100 ⁇ crystal plane family extends.
  • FIGS. 3 (a) and 3 (b) are a front cross-sectional view
  • FIG. 3 (b) is a top cross-sectional view
  • line 11 ′ shows the cut-away position of the top cross-section
  • AA ′ The line shows the cross-sectional position of the cross section of the front view
  • the outer periphery of the channel layer 1003 can be recessed relative to the outer periphery of the first source / drain layer 1031 and the second source / drain layer 1005 (in this example, along (Recessed in the lateral direction parallel to the substrate surface).
  • the concave upper and lower side walls are respectively defined by the interface between the channel layer 1003 and the second source / drain layer 1005 and between the channel layer 1003 and the first source / drain layer 1031.
  • this can be achieved by further isotropically selectively etching the channel layer 1003 with respect to the first source / drain layer 1031 and the second source / drain layer 1005 (for example, wet etching using a TMAH solution) .
  • atomic layer etching (ALE) or digital etching can be used to perform selective etching in order to more precisely control the amount of etching.
  • each device the active regions of each device (the first source / drain layer 1031 after etching, the channel layer 1003, and the second source / drain layer 1005) are respectively defined.
  • the active area of each device is roughly square column-shaped.
  • the upper portion of the first source / drain layer 1031p and the outer circumference of the second source / drain layer 1005p are substantially aligned, and the outer circumference of the channel layer 1003p is relatively concave. As shown in FIG.
  • the channel layer 1003p since isotropic etching is used, the channel layer 1003p remains substantially conformal before and after etching, so that it is in the shape of a square column with a smaller lateral dimension, and at least part of its sidewalls still remain along (110) Crystal plane or ⁇ 110 ⁇ crystal plane family extension.
  • the upper portion of the first source / drain layer 1031n and the outer periphery of the second source / drain layer 1005n are substantially aligned, and the outer periphery of the channel layer 1003n is relatively concave. As shown in FIG.
  • the channel layer 1003n remains substantially conformal before and after the etching, so that it has a square column shape with a smaller lateral dimension, and at least part of its side walls still maintain the edge (100) Crystal plane or ⁇ 100 ⁇ crystal plane family extension.
  • the upper and lower side walls of each recess are respectively defined by the interface between the channel layer 1003 and the semi-second source / drain layer 1005 and between the channel layer 1003 and the first source / drain layer 1031.
  • the sidewalls of the channel layer 1003p extend along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family, so that sharp corners are formed between adjacent sidewalls thereof.
  • the sidewalls of the channel layer 1003n extend along the (100) crystal plane or ⁇ 100 ⁇ crystal plane family, so that sharp corners are formed between adjacent sidewalls thereof.
  • sharp corners may be damaged in subsequent processes, resulting in process instability, device reliability degradation, and device performance fluctuations.
  • sharp corners can be chamfered to make them smooth.
  • sharp corners can be treated as rounded corners by oxidation (and subsequent removal of the oxide layer), see FIG. 4 (b).
  • a gate stack will be formed subsequently.
  • a material layer may be filled in the recess to occupy the space of the gate stack (thus, This material layer may be referred to as a "sacrificial gate"). For example, this can be done by depositing nitride on the structure shown in FIGS. 3 (a) and 3 (b), and then etching back the deposited nitride such as RIE.
  • FIGS. 4 (a) and 4 (b) FIGS. 4 (a) and 4 (b)
  • FIGS. 4 (a) and 4 (b) FIGS. 4 (a) and 4 (b)
  • FIGS. 4 (a) and 4 (b) FIGS. 4 (a) and 4 (b)
  • FIGS. 4 (a) and 4 (b) FIGS. 4 (a) and 4 (b)
  • FIGS. 4 (a) and 4 (b) FIGS. 4 (a) is a front sectional view
  • 4 (b) is a cross-sectional view from above, where line 11 'shows the intercepting position of the cross-section in plan view, and line AA' shows the intercepting position of the cross-section in front view).
  • the sacrificial gate 1007 may substantially fill the above-mentioned recess.
  • shallow trench isolation can also be fabricated.
  • the STI 1051 can be formed by etching the trench where isolation is needed and then filling the trench with oxide, as shown in FIG. 5.
  • oxide as shown in FIG. 5.
  • STI 1051 can be disposed around the active area of the p-type device and around the active area of the n-type device, respectively.
  • source / drain regions may be formed in the first source / drain layer 1031 and the second source / drain layer 1005. This can be formed by doping the first source / drain layer 1031 and the second source / drain layer 1005. For example, this can be done as follows.
  • a p-type dopant source layer 1009p may be formed on the structure shown in FIG.
  • the p-type dopant source layer 1009p may include an oxide such as silicon oxide, which contains a p-type dopant such as B.
  • the dopant source layer 1009p may be a thin film, for example, with a thickness of about 2-10 nm, so that it can be deposited approximately conformally in the pattern by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). 5 on the surface of the structure shown.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a diffusion barrier layer 1053 may be further formed on the p-type dopant source layer 1009p, as shown in FIG. 6 (b) Show.
  • the diffusion barrier layer 1053 may include nitride, oxynitride, oxide, etc., with a thickness of about 0.5-5 nm.
  • the p-type dopant source layer 1009p (and the diffusion barrier layer 1053) may be patterned (for example, by photolithography) to be left in the area where p-type doping is required.
  • the p-type dopant source layer 1009p can be left in the p-type device region (because its source / drain layer requires p-type doping) and the n-type device region where body contact will be formed (if any) , Because p-type body contact regions can be formed for n-type devices).
  • an n-type dopant source layer 1009n can be formed on the structure shown in FIG. 7.
  • the n-type dopant source layer 1009n may include an oxide containing an n-type dopant such as As or P and having a thickness of about 2-10 nm.
  • the n-type dopant source layer 1009n may be formed in the same manner as the p-type dopant source layer 1009p.
  • the n-type dopant source layer 1009n can cover areas that require n-type doping, such as n-type device areas (because its source / drain layers require n-type doping) and p-type device areas that will form body contacts (if Yes, because n-type body contact regions can be formed for p-type devices).
  • another diffusion barrier layer may be formed on the n-type dopant source layer 1009n to suppress out-diffusion or cross-contamination.
  • the dopant contained in the dopant source layers 1009p and 1009n may enter the active region by annealing at, for example, about 800-1100 ° C., thereby forming a doped region therein, As shown in the shaded part of the figure. More specifically, in the p-type device region, one of the source / drain regions 1011p-1 of the p-type device may be formed in the first source / drain layer 1031p, and the p-type device may be formed in the second source / drain layer 1005p Another source / drain region 1011p-2.
  • one of the source / drain regions 1011n-1 of the n-type device can be formed in the first source / drain layer 1031n, and the n-type device can be formed in the second source / drain layer 1005n Another source / drain region 1011n-2. Thereafter, the dopant source layers 1009p and 1009n and the diffusion barrier layer 1053 can be removed.
  • the dopant can also enter the channel layer 1003 via the first source / drain layer 1031 and the second source / drain layer 1005, so that a certain amount is formed at the upper and lower ends of the channel layer 1003
  • the doping distribution (for example, forming an extension region) is shown in the dashed ellipse in the figure. This doping profile can reduce the resistance between the source / drain region and the channel when the device is turned on, thereby improving device performance.
  • the source / drain regions are formed by driving the dopant into the active region from the dopant source layer, but the present disclosure is not limited thereto.
  • the source / drain regions can be formed by ion implantation, plasma doping (eg, conformal doping along the surface of the structure in FIG. 5), and the like.
  • the region requiring p-type doping and the region requiring n-type doping can be performed separately.
  • photoresist can be used to block another area. This sub-regional processing is common in CMOS processes.
  • in-situ doping can also be performed when growing the source / drain layers.
  • the p-type dopant source layer 1009p is formed first, and then the n-type dopant source layer 1009n is formed.
  • the present disclosure is not limited to this, and their order may be exchanged.
  • the source / drain layer may also be silicidated.
  • a layer of NiPt (for example, Pt content of about 2-10% and a thickness of about 2-10 nm) may be deposited on the structure shown in FIG. 9 (removing the dopant source layer and the diffusion barrier layer) Annealing at a temperature of about 200-400 ° C causes NiPt to react with Si to produce SiNiPt. After that, unreacted remaining NiPt can be removed to form silicide 1501 on the surface of the source / drain layer, as shown in FIG. 10. In this example, silicide 1501 is also formed on the horizontal surface of the lower portion (unetched portion) of the first source / drain layer 1031.
  • a gate stack can be formed.
  • a dielectric layer may be formed around the active region to shield the underlying source / drain layer 1031.
  • an oxide can be deposited on the structure shown in FIG. 10 and etched back to form a dielectric layer 1013, which serves as the first isolation Floor.
  • the deposited oxide can be planarized, such as chemical mechanical polishing (CMP) or sputtering.
  • CMP chemical mechanical polishing
  • the top surface of the dielectric layer 1013 may be located between the top surface and the bottom surface of the channel layer 1003, which helps to form a self-aligned gate stack, which will be described in further detail below.
  • the sacrificial gate 1007 may be retained to prevent the material of the first isolation layer from entering the above-mentioned channel layer 1003 to accommodate the gate stack relative to the first source / drain layer 1031 and the second source / drain layer 1005 In the recess. Thereafter, the sacrificial gate 1007 may be removed to release the recessed space of the channel layer 1003 relative to the first source / drain layer 1031 and the second source / drain layer 1005.
  • the sacrificial gate 1007 can be selectively etched relative to the dielectric layer 1013 (oxide) and the first source / drain layer 1031, the second source / drain layer 1005 (SiGe), and the channel layer 1003 (Si) ).
  • a gate stack can be formed in the recess.
  • different gate stacks can be formed for p-type devices and n-type devices, respectively.
  • description will be made by taking the gate stack of the p-type device first as an example.
  • the present disclosure is not limited to this, for example, the gate stack of the n-type device may also be formed first.
  • a gate dielectric layer 1015 and a gate conductor layer 1017p for a p-type device can be sequentially deposited on the structure shown in FIG. 11 (b) (with the sacrificial gate 1007 removed), and the deposited
  • the gate conductor layer 1017p (and optionally the gate dielectric layer 1015) is etched back so that the top surface of the portion outside the recess is not higher than and preferably lower than the top surface of the channel layer 1003.
  • the gate dielectric layer 1015 may include a high-K gate dielectric such as HfO 2 ; the gate conductor layer 1017p may include a metal gate conductor.
  • a function adjustment layer can also be formed between the gate dielectric layer 1015 and the gate conductor layer 1017p.
  • an interface layer such as oxide may also be formed.
  • the gate stack Due to the top surface of the dielectric layer 1013, the gate stack only overlaps the side surface of the channel layer 1003 in the vertical direction, and does not overlap the side surfaces of the first and second source / drain layers in the vertical direction. That is, the gate stack is self-aligned with the channel layer 1003. In this way, the gate stack can be embedded in the recess so as to overlap the entire height of the channel layer 1003.
  • the gate conductor layer 1017p may be selectively etched such as RIE.
  • the etching can use the active region, especially the second source / drain layer at the top, as a mask.
  • RIE can be performed in a direction substantially perpendicular to the surface of the substrate, so that the gate conductor layer 1017p can be left only in the recess.
  • the etching may stop at the gate dielectric layer 1015.
  • the gate conductor layer 1017p in the p-type device region (currently in the recess) can be masked with, for example, photoresist 1055, and the gate conductor layer 1017p in the n-type device region is exposed.
  • the gate conductor layer 1017p in the n-type device region can be removed by selective etching such as wet etching.
  • a gate stack (1015 / 1017p) for the p-type device is formed, which is embedded in the recess of the channel layer 1003p of the p-type device.
  • a gate stack for n-type devices can be formed.
  • the gate stack of the n-type device can also be formed similarly.
  • a gate conductor layer 1017n for n-type devices may be formed.
  • the gate conductor layer 1017n can be deposited on the structure shown in FIG. 14 (with the photoresist 1055 removed), and the deposited gate conductor layer 1017n can be etched back on top of the portion outside the recess
  • the surface is not higher than and preferably lower than the top surface of the channel layer 1003.
  • the gate conductor layer 1017n may include a metal gate conductor.
  • a function adjustment layer can also be formed between the gate dielectric layer 1015 and the gate conductor layer 1017n.
  • the n-type device and the p-type device may share the same gate dielectric layer 1015; of course, the present disclosure is not limited thereto, for example, the gate dielectric layer 1015 may also be removed, and a gate dielectric layer is additionally formed for the n-type device.
  • the n-type device channel layer 1003n and the p-type device channel layer 1003p are formed by thin film growth and selective etching at the same time, the upper surface of the n-type device channel layer 1003n and the p-type device channel layer 1003p The surfaces are substantially coplanar, and the lower surface of the n-type device channel layer 1003n and the lower surface of the p-type device channel layer 1003p are substantially coplanar.
  • the gate conductor layer 1017n is formed not only in the n-type device region but also in the p-type device region, and is in contact with the gate conductor layer 1017p.
  • the gate contact pad 1017n may be used to fabricate a gate contact pad so as to subsequently fabricate a contact portion of the gate.
  • the manner of forming the gate stack is not limited to this.
  • the p-type device region can be masked with photoresist, and the portion of the gate conductor layer 1017p in the n-type device region is removed by selective etching such as RIE.
  • a gate stack for the n-type device may be formed in the n-type device region (for example, in the case where the photoresist remains to shield the p-type device region).
  • the gate conductor layer 1017n may be patterned to form gate contact pads for subsequent interconnection fabrication.
  • FIGS. 16 (a) and 16 (b) FIGS. 16 (a) and 16 (b)
  • FIGS. 16 (a) and 16 (b) FIGS. 16 (a) is a cross-sectional view
  • FIG. 16 (b) is a top view, where the line AA ′ shows the location of the cross-section
  • a photoresist 1019 is formed on the structure shown in 15.
  • the photoresist 1019 is patterned, for example, by photolithography to cover a portion of the gate conductor layer 1017n exposed to the recess, and to expose the other portion of the gate conductor layer 1017n exposed to the recess.
  • FIG. 16 (a) is a cross-sectional view
  • FIG. 16 (b) is a top view, where the line AA ′ shows the location of the cross-section
  • a photoresist 1019 is formed on the structure shown in 15.
  • the photoresist 1019 in the p-type device region and the n-type device region may respectively take the form of stripes extending in a certain direction from the outer periphery of the corresponding active region.
  • the photoresist stripes on the p-type device region and the n-type device region are substantially aligned with each other.
  • FIGS. 17 (a) and 17 (b) are cross-sectional views, and FIG. 17 (b) is a top view, where the line AA ′ shows the cross-sectional cut position
  • photolithography can be performed.
  • the glue 1019 is used as a mask to selectively etch the gate conductor layer 1017n such as RIE.
  • the gate conductor layer 1017n except for the portion left in the recess, the portion blocked by the photoresist 1019 is retained and used as a gate contact pad. Subsequently, electrical connection to the gate stack can be achieved through such gate contact pads.
  • the sidewall of the channel layer of the p-type device extends at least partially along the (110) crystal plane or ⁇ 110 ⁇ crystal plane family, and the channel layer of the n-type device The sidewalls extend at least partially along the (100) crystal plane or the ⁇ 100 ⁇ crystal plane family, and the gate contact pads 1017n may be oriented outward from the outer periphery of the corresponding active region in a certain direction in the p-type device region and the n-type device region, respectively Extended strips.
  • an interlayer dielectric layer 1057 may be formed on the structure shown in FIGS. 17 (a) and 17 (b).
  • an oxide may be deposited and planarized such as CMP to form the interlayer dielectric layer 1057.
  • electrical contacts 1023p-1 to 1023p-4 to the n-type well region and the source / drain regions of the p-type device and the gate conductor layer can be formed to the p-type substrate and n-type The source / drain regions of the device and the electrical contacts 1023n-1 to 1023n-4 of the gate conductor layer.
  • These contacts may be formed by etching holes in the interlayer dielectric layer 1057 and filling conductive materials such as metals (e.g., tungsten) therein. Before filling the metal, a barrier layer such as TiN may be formed on the inner wall of the contact hole.
  • conductive materials such as metals (e.g., tungsten) therein.
  • a barrier layer such as TiN may be formed on the inner wall of the contact hole.
  • the semiconductor device may include a p-type device and an n-type device both in the form of vertical devices.
  • the p-type device and the n-type device each include a first source / drain layer 1031, a channel layer 1003, and a second source / drain layer 1005 stacked in the vertical direction.
  • Source / drain regions are formed in the first source / drain layer 1031 and the second source / drain layer 1005.
  • the channel layer 1003 is laterally recessed, the gate stack is formed around the outer periphery of the channel layer 1003, and embedded in the recess, the sidewalls of the channel layers 1003p and 1003n of the p-type device and the n-type device extend along different crystal planes.
  • Each device also includes a gate contact pad extending outward from the gate conductor.
  • 19 to 20 are schematic diagrams showing some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • the source / drain layer can also be refined. For example, as shown in FIG. 19, in the structure shown in FIG. 9 (removing the dopant source layer and the diffusion barrier layer), the source / drain layer can be selectively etched to reduce the lateral size (even smaller than the channel) Floor).
  • the source / drain layer after the refinement treatment may be silicided to form silicide on the surface of the source / drain layer. The process of the silicide treatment has been described above in conjunction with FIG. 10, in This will not be repeated here. After that, as shown in FIG.
  • a shielding layer 1007 ' may be formed on the sidewalls of the second source / drain layer 1005 and the first source / drain layer 1031 recessed relative to the sacrificial gate 1007,
  • the side walls of 'and the side walls of the sacrificial gate 1007 are substantially coplanar.
  • a low-k dielectric sidewall spacer 1007 ' can be formed by using a low-k dielectric through a spacer forming process.
  • the gate stack is formed in the recess formed by the channel layer 1003 relative to the sidewall spacer 1007 '.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic equipment. For example, by integrating a plurality of such semiconductor devices and other devices (for example, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and an electronic device can be constructed therefrom. Therefore, the present disclosure also provides an electronic apparatus including the above semiconductor device.
  • the electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), artificial intelligence, wearable devices, mobile power supplies, and the like.
  • a method of manufacturing a system on chip is also provided.
  • the method may include the above-described method of manufacturing a semiconductor device.
  • various devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

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Abstract

公开了一种半导体器件及其制造方法及包括该器件的电子设备。半导体器件包括：衬底；在衬底上形成的第一器件和第二器件，第一器件和第二器件各自均包括：在衬底上从下至上依次叠置的第一源/漏层、沟道层和第二源/漏层，以及绕沟道层的至少部分外周形成的栅堆叠；第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸。

Description

半导体器件及其制造方法及包括该器件的电子设备
相关申请的引用
本申请要求于2018年10月26日递交的题为“半导体器件及其制造方法及包括该器件的电子设备”的中国专利申请201811265735.1的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，缩小水平型器件所占的面积，一般要求源极、漏极和栅极所占的面积缩小，使器件性能变差(例如，功耗和电阻增加)，故水平型器件的面积不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件所占的面积更容易缩小。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种能够提供改进特性的竖直型半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；在衬底上形成的第一器件和第二器件，第一器件和第二器件各自均包括：在衬底上从下至上依次叠置的第一源/漏层、沟道层和第二源/漏层，以及绕沟道层的至少部分外周形成的栅堆叠；第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上从下至上设置第一源/漏层、沟道层和第二源/漏层的叠层；从堆叠的第一 源/漏层、沟道层和第二源/漏层分别限定出第一器件的有源区和第二器件的有源区，且使第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸；以及分别绕第一器件和第二器件各自有源区中的沟道层的至少部分外周形成相应器件的栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括至少部分地由上述半导体器件形成的集成电路。
根据本公开的实施例，半导体器件包括竖直型器件，相比于水平型器件能够大幅度地缩小面积，节省空间。栅堆叠绕沟道层的至少部分外周形成且沟道形成于沟道层中，从而栅长可以由沟道层的厚度确定，可以实现对栅长的较好控制。另外，可以将不同器件的沟道层的至少一部分侧壁设置为沿不同晶体晶面或晶面族延伸。由于载流子在不同晶体晶面或晶面族方向上可以具有不同的迁移率，于是可以调节不同器件的沟道层中的载流子迁移率，进而调节不同器件的导通效果，以优化半导体器件的整体性能。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至18示出了根据本公开实施例的制造半导体器件的流程的示意图；
图19至20示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系 仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开实施例的半导体器件可以包括在衬底上形成的多个竖直型器件。各竖直型器件可以包括在衬底上依次叠置的第一源/漏层、沟道层和第二源/漏层。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和/或开态电流增强层(带隙比相邻层大或小的半导体层)。在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。不同竖直器件的有源区叠层配置可以相同，也可以不同。
根据本公开的实施例，不同器件特别是不同导电类型的器件的沟道层的至少一部分侧壁可以沿不同的晶体晶面或晶面族延伸。由于载流子在不同晶体晶面或晶面族方向上可以具有不同的迁移率，于是可以调节不同器件的沟道层中的载流子迁移率，进而调节不同器件的导通效果，以优化半导体器件的整体性能。例如，在沟道层为单晶半导体材料或者为Si、SiGe或Ge晶体之一的情况下，n型器件的沟道层侧壁中至少部分可以沿(100)晶面或{100}晶面族延伸，因为该晶面或晶面族有利于电子的迁移率；而p型器件的沟道层侧壁中至少部分可以沿(110)晶面或{110}晶面族延伸，因为该晶面或晶面族有利于空穴的迁移率。另外，在器件为不同导电类型时，可以形成互补金属氧化物半导体(CMOS)配置。
根据本公开的实施例，可以并非对沟道层的所有侧壁进行优化(即，使它们均沿期望的晶体晶面或晶面族延伸)，而是只对部分侧壁进行优化。例如，为提升器件可靠性和降低工艺波动，可以对沟道层进行倒角处理。此时，侧壁的圆角部分可能并非沿着期望的晶体晶面或晶面族延伸。又如，可以对沟道层的侧壁中面积较大的侧壁进行优化，而忽略面积较小的侧壁的影响，例如在纳 米片的情况下。此种情况下，侧壁的晶面不是单一晶面族。
根据本公开的实施例，器件的第一源/漏层可以沿[100]晶向或沿<100>晶向族指向其第二源/漏层的方向，该指向平行于{100}晶面族和{110}晶面族，即{100}晶面族和{110}晶面族可以大致垂直于衬底，使得沿{100}晶面族或{110}晶面族延伸的沟道层侧壁可以大致垂直于衬底。
在沟道层的侧壁沿晶体晶面或晶面族延伸时，沟道层的相邻侧壁之间可能形成尖角。这种尖角并不稳定，可能降低器件的可靠性和造成器件性能的波动。为此，可以对沟道层进行倒角处理，使得沟道层的相邻侧壁所形成的角可以为相对和缓的圆角。
沟道层可以由单晶半导体材料构成，以改善器件性能，例如降低沟道电阻。不同器件的沟道层的单晶半导体材料可以具有相同的晶向，和/或可以具有相同的晶体结构。这样，这些器件的沟道层可以用同样的基体制造，制造方便且缺陷较少。
当然，第一、第二源/漏层也可以由单晶半导体材料构成。这种情况下，沟道层的单晶半导体材料与源/漏层的单晶半导体材料可以是共晶体。沟道层单晶半导体材料的电子或空穴迁移率可以大于第一、第二源/漏层的电子或空穴迁移率。另外，第一、第二源/漏层的禁带宽度可以大于沟道层单晶半导体材料的禁带宽度。
栅堆叠可以绕沟道层的至少部分外周形成。于是，栅长可以由沟道层自身的厚度来确定，而不是如常规技术中那样依赖于刻蚀时间来确定。沟道层例如可以通过外延生长来形成，从而其厚度可以很好地控制。因此，可以很好地控制栅长。
衬底上不同器件的沟道层可以实质上共面，例如它们可以在大致平行于衬底表面的平面上延伸。在一个示例中，各器件的沟道层的上表面和/或下表面可以基本上共面。因此，各器件的沟道层可以具有不同的厚度，相应地可以具有不同的沟道长度。
栅堆叠可以自对准于沟道层。例如，栅堆叠和沟道层可以基本大致共面。在一个示例中，沟道层的上表面和栅堆叠的至少部分上表面可以基本共面，和/或沟道层的下表面和栅堆叠的至少部分下表面可以基本共面。例如，沟道层 的外周可以相对于第一、第二源/漏层的外周向内凹入。这样，所形成的栅堆叠可以嵌于沟道层相对于第一、第二源/漏层的凹入中。栅堆叠在第一源/漏层、沟道层和第二源/漏层的叠置方向(竖直方向，例如大致垂直于衬底表面)上的范围处于所述凹入在该方向上的范围之内。于是，可以减少或甚至避免与源/漏区的交迭，有助于降低栅与源/漏之间的寄生电容。
在第一器件和第二器件为不同导电类型器件的情况下(例如，第一器件为n型器件，第二器件为p型器件)，栅堆叠特别是其中的栅导体层可能需要对第一器件和第二器件分别不同地形成(例如，以不同功函数的栅导体材料来分别形成n型器件和p型器件的栅导体层)。例如，第一器件和第二器件可以分别包括具有适合功函数且自对准于相应沟道层的相应栅导体材料。
另外，为了便于制造到栅导体层的电接触，还可以包括将栅导体层引出的栅极接触垫。这种栅极接触垫可以与栅堆叠(具体地，栅导体层)电接触，并沿着远离沟道层的方向延伸(例如，延伸超出有源区外周)。有利地，为了便于制造，可以利用第一器件和第二器件之一(例如，第一器件)的栅导体层来形成这种栅极接触垫，即便对于另一器件(例如，第二器件)。例如，一种器件(例如，第一器件)的栅导体层可以从相应凹入向外延伸从而充当栅极接触垫，另外其栅导体层的另一部分可以延伸至另一种器件(例如，第二器件)的栅导体层，从而充当栅极接触垫。
有源区中的各层可以通过外延生长形成，从而可以精确地控制其厚度。例如，第一源/漏层可以是在衬底上外延生长的半导体层，沟道层可以是在第一源/漏层上外延生长的半导体层，第二源/漏层可以是在沟道层上外延生长的半导体层。
这种半导体器件例如可以如下制造。具体地，可以在衬底上从下至上设置第一源/漏层、沟道层和第二源/漏层的叠层。例如可以通过衬底自身或者通过在衬底上外延生长来设置第一源/漏层。接着，可以在第一源/漏层上外延生长沟道层，并可以在沟道层上外延生长第二源/漏层。在外延生长时，可以控制所生长的沟道层的厚度。由于分别外延生长，至少一对相邻层之间可以具有清晰的晶体界面。另外，可以分别对各层进行不同掺杂，于是至少一对相邻层之间可以具有掺杂浓度界面。对于沟道层，可以进行一定的处理，使得其在第一 器件区域和第二器件区域可以具有不同的厚度。例如，可以在生长沟道层之后对其在某器件区域中的部分进行减薄处理(例如，刻蚀)，或者在某器件区域进一步生长沟道层(即，加厚)；或者，可以在生长第一源/漏层之后对其在某器件区域中的部分进行减薄处理(例如，刻蚀)，然后再生长沟道层。
对于堆叠的第一源/漏层、沟道层和第二源/漏层，可以分别在第一器件区域和第二器件区域中限定出第一器件的有源区和第二器件的有源区。例如，可以将它们依次选择性刻蚀为所需的形状。第一器件和第二器件各自的有源区可以由相同的第一源/漏层、沟道层和第二源/漏层来得到。
根据本公开的实施例，可以沿一定的晶体晶面或晶面族来形成沟道层的侧壁。当然，在限定有源区时通常利用相同的掩模，于是第一源/漏层和第二源/漏层的侧壁也可以沿相同的晶体晶面或晶面族延伸。于是，有源区可以呈方柱状。另外，对于第一器件和第二器件，特别是在它们具有不同导电类型时，它们各自的沟道层的侧壁中至少部分可以沿不同的晶体晶面或晶面族延伸。
为了便于在后继工艺中连接第一源/漏层中形成的源/漏区，对第一源/漏层的刻蚀可以只针对第一源/漏层的上部，从而第一源/漏层的下部可以延伸超出其上部的外周。然后，分别绕第一器件和第二器件各自有源区中的沟道层的至少部分外周形成相应器件的栅堆叠。
另外，可以使沟道层的外周相对于第一、第二源/漏层的外周向内凹入，以便限定容纳栅堆叠的空间。例如，这可以通过选择性刻蚀来实现。这种情况下，栅堆叠可以嵌入该凹入中。为了保持沟道层的侧壁仍然沿相应晶体晶面或晶面族延伸，沟道层的凹入可以通过各向同性刻蚀来实现。
为了提高器件的可靠性，可以将沟道层的相邻侧壁之间形成的尖角处理为相对和缓的圆角。
在第一、第二源/漏层中可以形成源/漏区。例如，这可以通过对第一、第二源/漏层掺杂来实现。例如，可以进行离子注入、等离子体掺杂等。根据一有利实施例，可以在沟道层的外周相对于第一、第二源/漏层的外周形成的凹入中，形成牺牲栅，然后在第一、第二源/漏层的表面上形成掺杂剂源层，并通过例如退火使掺杂剂源层中的掺杂剂经第一、第二源/漏层进入有源区中。牺牲栅可以阻止掺杂剂源层中的掺杂剂直接进入沟道层中。但是，可以有部分 掺杂剂经由第一、第二源/漏层而进入沟道层靠近第一源/漏层和第二源/漏层的端部。如果第一器件和第二器件具有不同的导电类型，则可以分别进行掺杂。
可以分别在第一器件和第二器件各自的沟道层的凹入中形成针对相应器件的栅堆叠。如果第一器件和第二器件具有不同导电类型且分别形成不同的栅堆叠，则它们的栅堆叠可以分别先后形成。在后一次形成栅堆叠时，可以利用其中的栅导体层来形成第一器件和第二器件各自的栅极接触垫。这可以通过对栅导体层进行构图来形成。
本公开可以各种形式呈现，以下将描述其中一些示例。
图1至18示出了根据本公开实施例的制造半导体器件的流程的示意图。在以下，以分别形成n型器件和p型器件为例进行描述，以便更详尽地展现形成不同导电类型器件的情况。应当理解，当然也可以形成相同导电类型的器件。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供p型硅晶片作为衬底1001。在衬底1001中，例如可以通过离子注入，形成n型阱区1001w。p型器件可以形成在n型阱区1001w上(因此将其称作p型器件区域)；而n型器件可以形成在p型Si衬底1001的其他区域上(因此将其称作n型器件区域)。根据本公开的实施例，衬底1001可以是(100)单晶硅、单晶锗硅或单晶锗晶圆。此时，与(100)晶面垂直的晶面中既有{100}晶面族的晶面又有{110}晶面族的晶面，有利于下述器件的制造。
在衬底1001上，可以通过例如外延生长，依次形成第一源/漏层1031、沟道层1003和第二源/漏层1005。例如，第一源/漏层1031可以包括SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm；沟道层1003可以包括Si，厚度为约10-100nm；第二源/漏层1005可以包括SiGe(Ge的原子百分比可以为约10-40％)，厚度为约20-50nm。第一源/漏层1031、沟道层1003和第二源/漏层1005的材料选择不限于此，可以包括能够提供适当刻蚀选择性的其他半导体材料。例如，沟道层1003可以包括Si：C、Ge或III-V族化合物半导体材料。另外，沟道层1003可以包括与第一源/漏层1031、第二源/漏层1005 相同的构成组分，但是组分含量不同的半导体材料(例如，都是SiGe，但是其中Ge的原子百分比不同)，只要沟道层1031相对于之上的第一源/漏层1031以及之上的第二源/漏层1005具备刻蚀选择性。
接下来，可以限定器件的有源区。例如，这可以如下进行。具体地，如图2(a)和2(b)(图2(a)是截面图，图2(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图1所示的第二源/漏层1005上形成光刻胶(未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状。在此，可以根据晶体晶面或晶面族方向来对光刻胶进行构图。例如，对于左侧的p型器件，期望其沟道侧壁沿着(110)晶面或{110}晶面族延伸，故而可以将相应光刻胶构图为侧壁平行于衬底1001的(110)晶面或{110}晶面族(由于沟道层外延生长在衬底1001上，故而也平行于沟道层的(110)晶面或{110}晶面族)的大致矩形图案。类似地，对于右侧的n型器件，期望其沟道侧壁沿着(100)晶面或{100}晶面族延伸，故而可以将相应光刻胶构图为侧壁平行于衬底1001的(100)晶面或{100}晶面族(由于沟道层外延生长在衬底1001上，故而也平行于沟道层的(100)晶面或{100}晶面族)的大致矩形图案。然后，以构图后的光刻胶为掩模，依次对第二源/漏层1005、沟道层1003和第一源/漏层1031进行选择性刻蚀如反应离子刻蚀(RIE)。刻蚀进行到第一源/漏层1031中，但并未进行到第一源/漏层1031的底面处，以便于后继制造接触部。于是，刻蚀后第二源/漏层1005、沟道层1003以及第一源/漏层1031的上部形成方柱状。RIE例如可以按大致垂直于衬底表面的方向进行，从而两个方柱状也大致垂直于衬底表面。之后，可以去除光刻胶。
在该示例中，分别在p型器件区域和n型器件区域构图针对p型器件和n型器件的有源区。在此，为描述方便起见，将针对p型器件的第一源/漏层、沟道层和第二源/漏层分别标示为1031p、1003p和1005p，将针对n型器件的第一源/漏层、沟道层和第二源/漏层分别标示为1031n、1003n和1005n。在该阶段，第一源/漏层1031在p型器件和n型器件区域之间尚连续，图2(a)中以虚线示意性示出了p型器件区域和n型器件区域之间的边界。在以下的描述中，当对p型器件区域和n型器件区域统一进行描述时，使用1031、1003和1005的附图标记；而当需要对p型器件区域和n型器件区域分别进行描述时，则分 别使用1031p、1003p和1005p以及1031n、1003n和1005n的附图标记。
如图图2(a)和2(b)所示，刻蚀后p型器件区域的第二源/漏层1005p、沟道层1003p和第一源/漏层1031p的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，而n型器件区域的第二源/漏层1005n、沟道层1003n和第一源/漏层1031n的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
然后，如图3(a)和3(b)(图3(a)是正视截面图，图3(b)是俯视截面图，其中的11′线示出了俯视截面的截取位置，AA′线示出了正视截面的截取位置)所示，可以使沟道层1003的外周相对于第一源/漏层1031和第二源/漏层1005的外周凹入(在该示例中，沿大致平行于衬底表面的横向方向凹入)。该凹入的上下侧壁分别由沟道层1003与第二源/漏层1005以及沟道层1003与第一源/漏层1031之间的界面限定。例如，这可以通过相对于第一源/漏层1031和第二源/漏层1005，进一步各向同性地选择性刻蚀(例如可以使用TMAH溶液进行湿法刻蚀)沟道层1003来实现。例如，可以使用原子层刻蚀(ALE)或数字化刻蚀，来进行选择性刻蚀，以便更精确地控制刻蚀的量。
这样，就分别限定了各器件的有源区(刻蚀后的第一源/漏层1031、沟道层1003和第二源/漏层1005)。在该示例中，各器件的有源区均大致呈方柱状。在p型器件的有源区中，第一源/漏层1031p的上部和第二源/漏层1005p的外周实质上对准，而沟道层1003p的外周相对凹入。如图3(b)所示，由于采用各向同性刻蚀，沟道层1003p在刻蚀前后基本保持共形，从而呈横向尺寸较小的方柱状，且其侧壁中至少部分依然保持沿(110)晶面或{110}晶面族延伸。在n型器件的有源区中，第一源/漏层1031n的上部和第二源/漏层1005n的外周实质上对准，而沟道层1003n的外周相对凹入。如图3(b)所示，由于采用各向同性刻蚀，沟道层1003n在刻蚀前后基本保持共形，从而呈横向尺寸较小的方柱状，且其侧壁中至少部分依然保持沿(100)晶面或{100}晶面族延伸。各凹入的上下侧壁均分别由沟道层1003与半第二源/漏层1005以及沟道层1003与第一源/漏层1031之间的界面限定。
如图3(b)所示，沟道层1003p的侧壁沿(110)晶面或{110}晶面族延伸，从而其相邻侧壁之间形成尖角。同样地，沟道层1003n的侧壁沿(100)晶面或{100}晶面族延伸，从而其相邻侧壁之间形成尖角。这种尖角在随后的工艺 中可能损坏，导致工艺的不稳地性、器件可靠性的下降和器件性能的波动。为此，可以对这种尖角进行倒角处理，以使其圆滑。例如，可以通过氧化(且随后去除氧化层)，来将这种尖角处理为圆角，参见图4(b)。
在沟道层1003相对于第一源/漏层1031的上部和第二源/漏层1005的外周而形成的凹入中，随后将形成栅堆叠。为避免后继处理对于沟道层1003造成影响或者在该凹入中留下不必要的材料从而影响后继栅堆叠的形成，可以在该凹入中填充一材料层以占据栅堆叠的空间(因此，该材料层可以称作“牺牲栅”)。例如，这可以通过在图3(a)和3(b)所示的结构上淀积氮化物，然后对淀积的氮化物进行回蚀如RIE。可以以大致垂直于衬底表面的方向进行RIE，氮化物可仅留在凹入内，形成牺牲栅1007，如图4(a)和4(b)(图4(a)是正视截面图，图4(b)是俯视截面图，其中的11′线示出了俯视截面的截取位置，AA′线示出了正视截面的截取位置)所示。这种情况下，牺牲栅1007可以基本上填满上述凹入。
另外，还可以制作浅沟槽隔离(STI)。例如，可以通过在需要隔离之处刻蚀沟槽，然后在沟槽中填充氧化物，来形成STI 1051，如图5所示。本领域技术人员知道多种STI工艺，在此不再赘述。STI 1051可以分别设置在p型器件的有源区周围以及n型器件的有源区周围。
接下来，可以在第一源/漏层1031和第二源/漏层1005中形成源/漏区。这可以通过对第一源/漏层1031和第二源/漏层1005进行掺杂来形成。例如，这可以如下进行。
具体地，如图6(a)所示，可以在图5所示的结构上形成p型掺杂剂源层1009p。例如，p型掺杂剂源层1009p可以包括氧化物如氧化硅，其中含有p型掺杂剂如B。在此，掺杂剂源层1009p可以是一薄膜，例如厚度为约2-10nm，从而可以通过例如化学气相淀积(CVD)或原子层淀积(ALD)等大致共形地淀积在图5所示结构的表面上。
另外，可选地，为了避免与随后形成的n型掺杂剂源层之间的交叉污染，可以进一步在p型掺杂剂源层1009p上形成扩散阻挡层1053，如图6(b)所示。例如，扩散阻挡层1053可以包括氮化物、氮氧化物、氧化物等，厚度为约0.5-5nm。
然后，如图7所示，可以对p型掺杂剂源层1009p(以及扩散阻挡层1053)进行构图(例如，通过光刻)，使其留于需要进行p型掺杂的区域。在该示例中，p型掺杂剂源层1009p可以留于p型器件区域(因为其源/漏层需要p型掺杂)以及n型器件区域中将形成体接触的区域(如果有的话，因为对于n型器件可以形成p型的体接触区)。
接着，如图8所示，可以在图7所示的结构上形成n型掺杂剂源层1009n。例如，n型掺杂剂源层1009n可以包括氧化物，其中含有n型掺杂剂如As或P，厚度为约2-10nm。n型掺杂剂源层1009n可以按p型掺杂剂源层1009p相同的方式形成。n型掺杂剂源层1009n可以覆盖需要n型掺杂的区域，例如n型器件区域(因为其源/漏层需要n型掺杂)以及p型器件区域中将形成体接触的区域(如果有的话，因为对于p型器件可以形成n型的体接触区)。
可选地，还可以在n型掺杂剂源层1009n形成另一扩散阻挡层(图中未示出)，以抑制向外扩散或交叉污染。
接着，如图9所示，可以通过例如在约800-1100℃下进行退火，使掺杂剂源层1009p和1009n中包含的掺杂剂进入有源区中，从而在其中形成掺杂区，如图中的阴影部分所示。更具体地，在p型器件区域中，可以在第一源/漏层1031p中形成p型器件的源/漏区之一1011p-1，且在第二源/漏层1005p中形成p型器件的另一源/漏区1011p-2。类似地，在n型器件区域中，可以在第一源/漏层1031n中形成n型器件的源/漏区之一1011n-1，且在第二源/漏层1005n中形成n型器件的另一源/漏区1011n-2。之后，可以去除掺杂剂源层1009p和1009n以及扩散阻挡层1053。
尽管有牺牲栅1007存在，但是掺杂剂也可以经由第一源/漏层1031和第二源/漏层1005而进入沟道层1003中，从而在沟道层1003的上下两端处形成一定的掺杂分布(例如形成延伸区)，如图中的椭圆虚线图所示。这种掺杂分布可以降低器件导通时源/漏区与沟道之间的电阻，从而提升器件性能。
在以上示例中，通过从掺杂剂源层向有源区中驱入(drive in)掺杂剂来形成源/漏区，但是本公开不限于此。例如，可以通过离子注入、等离子体掺杂(例如，沿着图5中结构的表面进行共形掺杂)等方式，来形成源/漏区。当然，可以对需要p型掺杂的区域和需要n型掺杂的区域分别进行。在对一个区 域进行处理时，可以利用例如光刻胶遮挡另一区域。这种分区域处理在CMOS工艺中是常见的。另外，如果形成相同导电类型的器件，则还可以在生长源/漏层时进行原位掺杂。
在以上示例中，先形成p型掺杂剂源层1009p，然后再形成n型掺杂剂源层1009n。但是本公开不限于此，它们的顺序可以交换。
进一步地，为了降低接触电阻，还可以对源/漏层进行硅化处理。例如，可以在图9所示的结构(去除掺杂剂源层和扩散阻挡层)上淀积一层NiPt(例如，Pt含量为约2-10％，厚度为约2-10nm)，并在约200-400℃的温度下退火，使NiPt与Si发生反应，从而生成SiNiPt。之后，可以去除未反应的剩余NiPt，在源/漏层的表面形成硅化物1501，如图10所示。在该示例中，硅化物1501还形成在第一源/漏层1031的下部(未被刻蚀的部分)的水平表面上。
接下来，可以形成栅堆叠。为了减少栅堆叠与源/漏层之间的交迭，可以在有源区周围形成电介质层，以遮挡下层的源/漏层1031。例如，如图11(a)和11(b)所示，可以在图10所示的结构上淀积氧化物，并对其回蚀，以形成电介质层1013，该电介质层1013作为第一隔离层。在回蚀之前，可以对淀积的氧化物进行平坦化处理如化学机械抛光(CMP)或溅射。在此，电介质层1013的顶面可以位于沟道层1003的顶面与底面之间，这有助于形成自对准的栅堆叠，这将在以下进一步详细描述。
在形成第一隔离层时，可以保留牺牲栅1007，以避免第一隔离层的材料进入要容纳栅堆叠的上述沟道层1003相对于第一源/漏层1031、第二源/漏层1005的凹入中。之后，可以去除牺牲栅1007，以释放沟道层1003相对于第一源/漏层1031、第二源/漏层1005的凹入中的空间。例如，可以相对于电介质层1013(氧化物)以及第一源/漏层1031、第二源/漏层1005(SiGe)和沟道层1003(Si)，选择性刻蚀牺牲栅1007(氮化物)。
然后，可以在凹入中形成栅堆叠。在此，可以针对p型器件和n型器件，分别形成不同的栅堆叠。以下，以先形成p型器件的栅堆叠为例进行描述。但是，本公开不限于此，例如也可以先形成n型器件的栅堆叠。
具体地，如图12所示，可以在图11(b)所示的结构(去除牺牲栅1007)上依次淀积栅介质层1015和针对p型器件的栅导体层1017p，并对所淀积的 栅导体层1017p(以及可选地栅介质层1015)进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1003的顶面。例如，栅介质层1015可以包括高K栅介质如HfO 2；栅导体层1017p可以包括金属栅导体。另外，在栅介质层1015和栅导体层1017p之间，还可以形成功函数调节层。在形成栅介质层1015之前，还可以形成例如氧化物的界面层。
由于电介质层1013的顶面设置，栅堆叠仅与沟道层1003在竖直方向上的侧面相交迭，而与第一、第二源/漏层各自在竖直方向上的侧面不交迭。即，栅堆叠自对准于沟道层1003。这样，栅堆叠可以嵌入到凹入中，从而与沟道层1003的整个高度相交迭。
然后，如图13所示，可以对栅导体层1017p进行选择性刻蚀如RIE。刻蚀可以有源区特别是顶端的第二源/漏层为掩模。例如，可以以大致垂直于衬底表面的方向进行RIE，于是栅导体层1017p可仅留在凹入内。刻蚀可以停止于栅介质层1015。然后，如图14所示，可以利用例如光刻胶1055遮蔽p型器件区域中的栅导体层1017p(当前处于凹入内)，并露出n型器件区域中的栅导体层1017p。之后，可以通过选择性刻蚀如湿法腐蚀，去除n型器件区域中的栅导体层1017p。于是，形成了针对p型器件的栅堆叠(1015/1017p)，该栅堆叠嵌入在p型器件的沟道层1003p的凹入中。
接下来，可以形成针对n型器件的栅堆叠。n型器件的栅堆叠也可以类似地形成。例如，如图15所示，可以形成针对n型器件的栅导体层1017n。例如，可以在图14所示的结构(去除光刻胶1055)上淀积栅导体层1017n，并对所淀积的栅导体层1017n进行回蚀，使其在凹入之外的部分的顶面不高于且优选低于沟道层1003的顶面。例如，栅导体层1017n可以包括金属栅导体。另外，在栅介质层1015和栅导体层1017n之间，还可以形成功函数调节层。在该示例中，n型器件和p型器件可以共用相同的栅介质层1015；当然，本公开不限于此，例如也可以去除栅介质层1015，并针对n型器件另外形成栅介质层。由于n型器件沟道层1003n和p型器件沟道层1003p是同时经过薄膜生长和选择性刻蚀而形成的，n型器件沟道层1003n的上表面与p型器件沟道层1003p的上表面基本共面，n型器件沟道层1003n的下表面与p型器件沟道层1003p的下表面基本共面。
可以看到，栅导体层1017n不仅形成于n型器件区域中，还形成于p型器件区域中，且与栅导体层1017p相接触。之后，可以利用栅导体层1017n制作栅极接触垫，以便随后制作到栅极的接触部。
当然，形成栅堆叠的方式不限于此。例如，在形成针对p型器件的栅堆叠之后，可以利用光刻胶遮蔽p型器件区域，并通过选择性刻蚀如RIE，去除栅导体层1017p在n型器件区域的部分。然后，可以在n型器件区域中形成针对n型器件的栅堆叠(例如，在保留光刻胶遮蔽p型器件区域的情况下)。
接下来，可以对栅导体层1017n进行构图，形成栅极接触垫，以便于后继互连制作。例如，如图16(a)和16(b)(图16(a)是截面图，图16(b)是俯视图，其中的AA′线示出了截面的截取位置)所示，可以在图15所示的结构上形成光刻胶1019。该光刻胶1019例如通过光刻构图为覆盖栅导体层1017n露于凹入之外的一部分，且露出栅导体层1017n露于凹入之外的其他部分。在该示例中，如图16(b)所示，光刻胶1019在p型器件区域和n型器件区域可以分别呈从相应有源区的外周向外沿一定方向延伸的条状。为便于构图，p型器件区域和n型器件区域上的光刻胶条彼此实质上对准。
然后，如图17(a)和17(b)(图17(a)为截面图，图17(b)为俯视图，其中的AA′线示出了截面的截取位置)所示，可以光刻胶1019为掩模，对栅导体层1017n进行选择性刻蚀如RIE。这样，栅导体层1017n除了留于凹入之内的部分之外，被光刻胶1019遮挡的部分得以保留，并用作栅极接触垫。随后，可以通过这种栅极接触垫来实现到栅堆叠的电连接。
在该示例中，如图17(b)所示，p型器件的沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，n型器件的沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，栅极接触垫1017n在p型器件区域和n型器件区域可以分别呈从相应有源区的外周向外沿一定方向延伸的条状。
然后，可以如图18所示，在图17(a)和17(b)所示的结构上形成层间电介质层1057。例如，可以淀积氧化物并对其进行平坦化如CMP来形成层间电介质层1057。在层间电介质层1057中，可以形成到n型阱区以及p型器件的源/漏区和栅导体层的电接触部1023p-1至1023p-4，可以形成到p型衬底以及n型器件的源/漏区和栅导体层的电接触部1023n-1至1023n-4。这些接触部可以 通过在层间电介质层1057中刻蚀孔洞，，并在其中填充导电材料如金属(例如，钨)来形成。在填充金属之前，可以在接触孔的内壁上形成阻挡层如TiN。
根据该实施例的半导体器件可以包括均为竖直器件形式的p型器件和n型器件。p型器件和n型器件各自均包括沿竖直方向叠置的第一源/漏层1031、沟道层1003和第二源/漏层1005。在第一源/漏层1031和第二源/漏层1005中形成了源/漏区。沟道层1003横向凹入，栅堆叠绕沟道层1003的外周形成，且嵌于该凹入中，p型器件和n型器件的沟道层1003p和1003n的侧壁沿不同晶面延伸。各器件还包括从栅导体向外延伸的栅极接触垫。
图19至20示出了根据本公开另一实施例的制造半导体器件的流程中部分阶段的示意图。
为了通过减小源/漏与栅之间的正对面积从而降低源/漏与栅之间的重叠电容，还可以对源/漏层进行细化处理。例如，如图19所示，可以在图9所示的结构(去除掺杂剂源层和扩散阻挡层)中，选择性刻蚀源/漏层，使其横向尺寸减少(甚至可以小于沟道层)。可选地，为了降低接触电阻，可以对细化处理后的源/漏层进行硅化处理，在源/漏层的表面处形成硅化物，硅化处理的过程在上文中结合图10已说明，在此不再赘述。之后，如图20所示，可以在第二源/漏层1005、第一源/漏层1031的侧壁中相对于牺牲栅1007凹入的侧壁上形成遮蔽层1007’，该遮蔽层1007’的侧壁与牺牲栅1007的侧壁实质上共面。例如可以通过侧墙(spacer)形成工艺，利用低k介质来形成低k介质侧墙1007′。在后续过程中，栅叠层形成于沟道层1003相对于侧墙1007’所形成的凹入中。
接下来，在沟道层1003相对于遮蔽层1007’的凹入中形成栅堆叠、形成栅极接触垫、以及形成两个器件各自的电接触部的工艺可以按上文结合图10至18描述的工艺进行，在此不再赘述。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算 机、平板电脑(PC)、人工智能、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (33)

  1. 一种半导体器件，包括：
    衬底；
    在衬底上形成的第一器件和第二器件，第一器件和第二器件各自均包括：在衬底上从下至上依次叠置的第一源/漏层、沟道层和第二源/漏层，以及绕沟道层的至少部分外周形成的栅堆叠；
    第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸。
  2. 根据权利要求1所述的半导体器件，其中，
    第一器件沟道层是半导体的单晶材料和/或第二器件沟道层是半导体的单晶材料。
  3. 根据权利要求2所述的半导体器件，其中，
    第一器件为n型器件，其沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族，而第二器件为n型器件，其沟道层的侧壁至少部分沿(100)晶面或{100}晶面族延伸。
  4. 根据权利要求1所述的半导体器件，其中，
    第一器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，而第二器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
  5. 根据权利要求4所述的半导体器件，其中，所述第一器件的第一源/漏 层指向第二源/漏层的方向沿[100]晶向或沿<100>晶向族，和/或所述第二器件的第一源/漏层指向第二源/漏层的方向沿[100]晶向或沿<100>晶向族。
  6. 根据权利要求1所述的半导体器件，其中，
    第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶向与第二器件的沟道层的晶向相同。
  7. 根据权利要求1所述的半导体器件，其中，
    第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶体结构与第二器件的沟道层的晶体结构相同。
  8. 根据权利要求1所述的半导体器件，其中：
    第一器件的沟道层的相邻侧壁所形成的角为圆角；并且/或者
    第二器件的沟道层的相邻侧壁所形成的角为圆角。
  9. 根据权利要求1所述的半导体器件，其中，沟道层的外周相对于第一、第二源/漏层的外周向内凹入。
  10. 根据权利要求1所述的半导体器件，其中，第一器件的沟道层的上表面与第二器件的沟道层的上表面基本共面和/或第一器件的沟道层的下表面与第二器件的沟道层的下表面基本共面。
  11. 根据权利要求1所述的半导体器件，第一器件和第二器件各自还包括：从栅堆叠中的栅导体层沿着远离沟道层的方向横向延伸的栅极接触垫，其中，第一器件和第二器件中至少之一的栅导体层和相应的栅极接触垫包括不同的材料。
  12. 根据权利要求11所述的半导体器件，其中，第一器件和第二器件的栅极接触垫包括相同的材料。
  13. 根据权利要求12所述的半导体器件，其中，第一器件和第二器件中任一个的栅导体层和相应的栅极接触垫包括相同的材料，且成一体延伸。
  14. 根据权利要求1所述的半导体器件，其中，第一器件的沟道层的上表面与第一器件的栅堆叠的至少部分的上表面基本共面且第一器件的沟道层的下表面与第一器件的栅堆叠的至少部分的下表面基本共面，和/或第二器件的沟道层的上表面与第二器件的栅堆叠的至少部分的上表面基本共面且第二器 件的沟道层的下表面与第二器件的栅堆叠的至少部分的下表面基本共面。
  15. 一种制造半导体器件的方法，包括：
    在衬底上从下至上设置第一源/漏层、沟道层和第二源/漏层的叠层；
    从堆叠的第一源/漏层、沟道层和第二源/漏层分别限定出第一器件的有源区和第二器件的有源区，且使第一器件和第二器件各自的沟道层的侧壁中至少部分沿不同的晶体晶面或晶面族延伸；以及
    分别绕第一器件和第二器件各自有源区中的沟道层的至少部分外周形成相应器件的栅堆叠。
  16. 根据权利要求15所述的方法，其中，
    第一器件的沟道层是半导体的单晶材料和/或第二器件的沟道层是半导体的单晶材料。
  17. 根据权利要求16所述的方法，其中，
    第一器件为n型器件，其沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，而第二器件为n型器件，其沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
  18. 根据权利要求15所述的方法，其中，
    第一器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸，而第二器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸；或者
    第一器件为p型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(110)晶面或{110}晶面族延伸，而第二器件为n型器件，其沟道层的半导体材料为Si、SiGe或Ge晶体之一并且沟道层的侧壁中至少部分沿(100)晶面或{100}晶面族延伸。
  19. 根据权利要求18所述的方法，其中，所述第一器件的第一源/漏层指向第二源/漏层的方向是沿[100]晶向或沿<100>晶向族，和/或所述第二器件的 第一源/漏层指向第二源/漏层的方向是沿[100]晶向或沿<100>晶向族。
  20. 根据权利要求15所述的方法，其中，
    第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶向与第二器件的沟道层的晶向相同。
  21. 根据权利要求15所述的方法，其中，
    第一器件的沟道层是半导体的单晶材料且第二器件的沟道层是半导体的单晶材料，且第一器件的沟道层的晶体结构与第二器件的沟道层的晶体结构相同。
  22. 根据权利要求15所述的方法，其中：
    限定第一器件的有源区包括：
    依次对第一器件的第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀以形成侧壁沿第一晶体晶面或晶面族延伸的图案，并通过各向同性刻蚀使得沟道层的外周相对于第一、第二源/漏层的外周凹入；
    在第一器件的沟道层相对于第一、第二源/漏层的凹入中形成第一器件的牺牲栅；
    限定第二器件的有源区包括：
    依次对第二器件的第二源/漏层、沟道层和第一源/漏层进行选择性刻蚀以形成侧壁沿第二晶体晶面或晶面族延伸的图案，并通过各向同性刻蚀使得沟道层的外周相对于第一、第二源/漏层的外周凹入；
    在第二器件的沟道层相对于第一、第二源/漏层的凹入中形成第二器件的牺牲栅。
  23. 据权利要求22所述的方法，其中：
    限定第一器件的有源区还包括：在对第一器件的沟道层进行各向同性刻蚀后，将第一器件的沟道层的相邻侧壁形成的尖角处理为圆角；并且/或者
    限定第二器件的有源区还包括：在对第二器件的沟道层进行各向同性刻蚀后，将第二器件沟道层的相邻侧壁形成的尖角处理为圆角。
  24. 根据权利要求22所述的方法，其中，在限定第一器件和第二器件的有源区之后，该方法还包括：
    在第一器件的第一源/漏层和第二源/漏层的表面上形成掺杂剂源层；以及
    使掺杂剂源层中的掺杂剂进入第一器件的第一、第二源/漏层中。
  25. 根据权利要求24所述的方法，其中，在限定第一器件和第二器件的有源区之后，该方法还包括：
    在第二器件的第一源/漏层和第二源/漏层的表面上形成另一掺杂剂源层；以及
    使另一掺杂剂源层中的掺杂剂进入第二器件的第一、第二源/漏层中。
  26. 根据权利要求22所述的方法，其中，在形成牺牲栅之后，该方法还包括：
    在第一器件的第一、第二源/漏层的表面上形成硅化物；和/或
    在第二器件的第一、第二源/漏层的表面上形成硅化物。
  27. 根据权利要求22所述的方法，其中，形成第一器件和第二器件的栅堆叠包括：
    在衬底上第一器件和第二器件的有源区的周围形成第一隔离层，其中第一隔离层的顶面处于沟道层的顶面与底面之间；
    去除第一器件和第二器件的牺牲栅，以释放沟道层相对于第一、第二源/漏层的凹入中的空间；
    在第一隔离层上依次形成第一器件的栅介质层和栅导体层；
    回蚀栅导体层，去除栅导体层在所述凹入之外的部分；
    去除第二器件的沟道层相对于第一、第二源/漏层的凹入中的栅导体层；
    在第二器件的所述凹入中形成第二器件的栅导体层；以及
    回蚀第二器件的栅导体层，使栅导体层在所述凹入之外的部分的顶面低于沟道层的顶面。
  28. 根据权利要求27所述的方法，还包括：
    形成第一器件和第二器件各自的栅极接触垫，栅极接触垫分别从相应栅堆叠中的栅导体层沿着远离沟道层的方向延伸，且第一器件和第二器件中至少之一的栅导体层和相应的栅极接触垫包括不同的材料。
  29. 根据权利要求28所述的方法，其中，利用第一器件和第二器件中任一个的栅导体层来形成栅极接触垫。
  30. 根据权利要求15所述的方法，其中，在衬底上设置第一源/漏层、沟 道层和第二源/漏层的叠层包括：
    在衬底上外延生长第一半导体层，作为第一源/漏层；
    在第一源/漏层上外延生长第二半导体层，作为沟道层；以及
    在沟道层上外延生长第三半导体层，作为第二源/漏层。
  31. 一种电子设备，包括至少部分地由如权利要求1至14中任一项所述的半导体器件形成的集成电路。
  32. 根据权利要求31所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
  33. 根据权利要求31所述的电子设备，该电子设备包括如下至少一个：智能电话、计算机、平板电脑、可穿戴设备、和/或移动电源。
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