WO2023024299A1 - 具有双栅结构的半导体器件及其制造方法及电子设备 - Google Patents

具有双栅结构的半导体器件及其制造方法及电子设备 Download PDF

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WO2023024299A1
WO2023024299A1 PCT/CN2021/133509 CN2021133509W WO2023024299A1 WO 2023024299 A1 WO2023024299 A1 WO 2023024299A1 CN 2021133509 W CN2021133509 W CN 2021133509W WO 2023024299 A1 WO2023024299 A1 WO 2023024299A1
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layer
gate stack
gate
semiconductor device
material layer
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PCT/CN2021/133509
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Publication of WO2023024299A1 publication Critical patent/WO2023024299A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device having a double gate structure, a manufacturing method thereof, and an electronic device including the semiconductor device.
  • Fin Field Effect Transistor Fin Field Effect Transistor
  • MBCFET Multi-Bridge Channel Field Effect Transistor
  • GIDL gate induced drain leakage
  • an object of the present disclosure is at least partially to provide a semiconductor device with a double gate structure, a method for manufacturing the same, and an electronic device including the semiconductor device.
  • a semiconductor device comprising: a vertical channel portion on a substrate; source/drain portions at the upper and lower ends of the channel portion with respect to the substrate; A first gate stack on a first side in a first direction lateral to the substrate and a second gate stack on a second side of the channel portion opposite to the first side in the first direction.
  • the distance between at least one of the upper edge and the lower edge in the vertical direction of the end of the first gate stack close to the channel portion and the corresponding source/drain portion may be smaller than that of the end of the second gate stack close to the channel portion.
  • the distance between at least one of the upper edge and the lower edge corresponding to the at least one edge in the vertical direction and the corresponding source/drain part may be smaller than that of the end of the second gate stack close to the channel portion.
  • a method of manufacturing a semiconductor device including: disposing a stack of a first material layer, a second material layer, and a third material layer on a substrate, the stack having The bottom is a first side and a second side opposite to each other in the first direction of the lateral direction; on the first side and the second side, the sidewalls of the second material layer are opposite to the sidewalls of the first material layer and the third material layer Concave in the first direction, thereby defining a first concave portion; on the first side and the second side, further etch the first material layer, the second material layer and the third material layer, so that the first concave portion is vertically
  • the size in the direction is increased; a channel layer is formed in the first concave portion; a first gate stack is formed in the first concave portion formed with the channel layer; A strip-shaped opening extending in a second direction, the second direction intersecting the first direction, thereby dividing the stack into two parts on the first side and the second
  • an electronic device including the above-mentioned semiconductor device.
  • a first gate stack and a second gate stack may be respectively formed on opposite sides of the channel portion. At least one side in the vertical direction, respective edges of the first gate stack and the second gate stack may be offset relative to each other to suppress GIDL.
  • FIGS. 5(a), 6(a), and 21(a) are top views, wherein, Figure 5(a) shows the position of AA' line and CC' line, and Figure 6(a) shows the position of BB' line; Figure 1 to 4, 5(b), 6(b), 7 to 9, 10(a), 10(b), 11 to 14, 15(a), 16, 17(a), 18(a), 20(a), 21(b) are cross sections along line AA' Fig. 6 (c) is the sectional view along BB ' line; Fig. 5 (c), 6 (d) is the sectional view along CC ' line; Fig. 15 (b), 17 (b), 18 (b) , 19, 20(b) are cross-sectional views taken along the DD' line in the corresponding cross-sectional view, wherein the position of the DD' line is shown in Figure 15(b);
  • 22(a) and 22(b) respectively show the energy band diagram of the n-type device according to the comparative example and the energy band diagram of the n-type device according to the embodiment of the present invention
  • FIG. 23(a) to 24(b) schematically show some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure, wherein, Fig. 23(a), 23(b), 24(a) and 24(b) are cross-sectional views along the line AA';
  • FIGS. 25 to 26 schematically show some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure, wherein FIGS. 25 and 26 are cross-sectional views along line AA';
  • 27( a ) and 27( b ) show energy band diagrams of n-type devices according to other embodiments of the present disclosure, respectively.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • a vertical type semiconductor device having an active region disposed vertically (eg, in a direction substantially perpendicular to a surface of the substrate) on a substrate.
  • the channel portion may be a vertical nanosheet or nanowire, such as a curved nanosheet or nanowire with a C-shaped cross-section (e.g., a cross-section perpendicular to the substrate surface), so this device may be called a C-channel field effect transistor ( C-Channel FET, namely CCFET).
  • C-Channel FET namely CCFET
  • nanosheets or nanowires may be formed by epitaxial growth and thus may be a unitary monolithic sheet and may have a substantially uniform thickness.
  • the channel portion may have strain or stress in the vertical direction. Due to this strain, the lattice constant of the material of the channel portion is different from that of the material without strain.
  • the semiconductor device may further include source/drain portions respectively disposed at upper and lower ends of the channel portion.
  • the source/drain may have some doping.
  • the source/drain portion may have p-type doping; for an n-type device, the source/drain portion may have n-type doping.
  • the channel part may have certain doping to adjust the threshold voltage of the device.
  • the semiconductor device may be a junctionless device, wherein the channel portion and the source/drain portion may have doping of the same conductivity type.
  • the semiconductor device may be a tunneling type device, wherein the source/drain portions at both ends of the channel portion may have opposite doping types to each other.
  • Source/drain portions may be disposed in corresponding semiconductor layers.
  • the source/drain portions may be doped regions in the corresponding semiconductor layers.
  • the source/drain portions may be part or all of the corresponding semiconductor layers.
  • Source/drain portions may be formed by diffusion doping as described below. In this case, the doping concentration interface may be substantially along a vertical direction relative to the substrate.
  • the channel portion may include a single crystal semiconductor material.
  • the source/drain portions or the semiconductor layer in which they are formed may also comprise a single crystal semiconductor material.
  • they can all be formed by epitaxial growth.
  • the semiconductor device may further include a first gate stack and a second gate stack disposed on opposite sides of the channel portion in a lateral direction, respectively. Edges of at least one side in the vertical direction of the first gate stack and the second gate stack may be offset relative to each other. For example, the distance between at least one of the upper and lower edges in the vertical direction of the end of the first gate stack close to the channel part and the corresponding source/drain part is smaller than that of the end of the second gate stack close to the channel part The distance between at least one edge corresponding to the above-mentioned at least one edge among the upper edge and the lower edge in the vertical direction and the corresponding source/drain portion. This helps suppress GIDL.
  • Such a semiconductor device can be manufactured, for example, as follows.
  • a stack of a first material layer, a second material layer and a third material layer may be provided on a substrate.
  • the first material layer may define the position of the lower source/drain
  • the second material layer may define the position of the gate stack
  • the third material layer may define the position of the upper source/drain.
  • the first material layer may be provided through a substrate such as an upper portion of the substrate, and a second material layer and a third material layer may be sequentially formed on the first material layer by, for example, epitaxial growth.
  • the first material layer, the second material layer and the third material layer may be sequentially formed on the substrate by eg epitaxial growth.
  • the stack may include first and second sides opposing each other in a first direction and third and fourth sides opposing each other in a second direction intersecting (eg, perpendicular to) the first direction.
  • the stack may have a quadrangular shape such as a rectangle or a square in top view.
  • the first concave portion may have a curved surface concave toward an inner side of the stack.
  • a channel portion may be formed on a surface of the first concave portion.
  • the first active layer may be formed by performing epitaxial growth on the exposed surface of the stack, and a portion of the first active layer on the surface of the first concave portion may be used as a channel portion (also referred to as a “channel portion”). channel layer").
  • One device may be formed based on the first active layer on the sidewalls of the first side and the second side of the stack, respectively. Thus, based on a single stack, two devices opposite each other can be formed.
  • a first gate stack may be formed in the first recess where the channel layer is formed.
  • the first concave portion may be formed such that a dimension of the first concave portion in a vertical direction may be different from (eg, greater than) a thickness of the second material layer in a vertical direction after the first active layer is formed. In this way, a first gate stack and a second gate stack with different gate lengths can be fabricated.
  • Source/drain parts may be formed in the first material layer and the third material layer.
  • the source/drain may be formed by doping the first material layer and the third material layer. This doping can be achieved by a solid-phase dopant source layer.
  • the first position holding layer may be formed in the first concave part where the channel layer is formed so as not to affect the channel layer.
  • Openings can be formed in the stack to separate the active regions of the two devices.
  • the opening may extend along the second direction, so that the stack is divided into two parts on the first side and the second side respectively, and the two parts respectively have their own channel layers.
  • the second material layer can be replaced by a second gate stack.
  • first concave portion on the first side and the second side it is also possible to similarly form the second concave portion on the third side and the fourth side and form the second position holding layer therein. This helps to improve the topography and dimensional control of the channel layer.
  • the thickness and gate length of the nanosheets or nanowires used as the channel part are mainly determined by epitaxial growth, rather than by etching or photolithography, so it is possible to have a good channel size/thickness and grid length control.
  • the disclosure can be presented in various forms, some examples of which are described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etch selectivity.
  • the desired etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching It may be selective, and the layer of material may be etch-selective relative to other layers exposed to the same etch formulation.
  • FIG. 1 to 21(b) schematically illustrate some stages in the flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided (the upper part of which may constitute the above-mentioned first material layer).
  • the substrate 1001 may be various types of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is used as an example for description.
  • a silicon wafer is provided as a substrate 1001 .
  • a well region may be formed. If a p-type device is to be formed, the well region can be an n-type well; if an n-type device is to be formed, the well region can be a p-type well.
  • the well region can be formed, for example, by implanting a dopant of a corresponding conductivity type (p-type dopant such as B or In, or n-type dopant such as As or P) into the substrate 1001 followed by thermal annealing.
  • p-type dopant such as B or In, or n-type dopant such as As or P
  • a second material layer 1003 and a third material layer 1005 may be formed by, for example, epitaxial growth.
  • the second material layer 1003 can be used to define the position of the gate stack, and has a thickness of about 20nm-50nm, for example.
  • the third material layer 1005 can be used to define the position of the upper source/drain part, and its thickness is, for example, about 20nm-200nm.
  • Adjacent layers among the substrate 1001 and the above layers formed thereon may have etch selectivity relative to each other.
  • the substrate 1001 is a silicon wafer
  • the second material layer 1003 may include SiGe (for example, Ge atomic percentage is about 10%-30%)
  • the third material layer 1005 may include Si.
  • the transverse directions x, z and the vertical direction y are schematically shown in FIG. 1 .
  • the x and z directions may be parallel to the top surface of the substrate 1001 and may be perpendicular to each other; the y direction may be substantially perpendicular to the top surface of the substrate 1001 . Since the top is not constrained, the stress in the y direction in the second material layer 1003 can be released.
  • the x direction may be the aforementioned first direction
  • the z direction may be the aforementioned second direction.
  • a spacer pattern transfer technique is used in the following compositions.
  • a mandrel may be formed.
  • a layer 1011 for a mandrel pattern may be formed on the third material layer 1005 by, for example, deposition.
  • the layer 1011 for the mandrel pattern may include amorphous silicon or polycrystalline silicon with a thickness of about 50nm-150nm.
  • the etching stop layer 1009 may be formed first by, for example, deposition.
  • the etch stop layer 1009 may include oxide (eg, silicon oxide) with a thickness of about 1 nm-10 nm.
  • a hard mask layer 1013 may be formed by, for example, deposition.
  • the hard mask layer 1013 may include nitride (eg, silicon nitride) with a thickness of about 30nm-100nm.
  • the layer 1011 for the core pattern may be patterned into the core pattern.
  • a photoresist 1007 may be formed on the hard mask layer 1013 and patterned into strips extending along the z direction by photolithography.
  • the photoresist 1007 can be used as an etching mask, and the hard mask layer 1013 and the layer 1011 for the pattern of the core mold are selectively etched sequentially by, for example, reactive ion etching (RIE), and the pattern of the photoresist is transferred to hard mask layer 1013 and layer 1011 for mandrel patterning.
  • RIE reactive ion etching
  • RIE can be performed in a substantially vertical direction and can be stopped at etch stop layer 1009 .
  • the photoresist 1007 may be removed.
  • partition walls 1017 may be formed on the sidewalls on opposite sides of the core pattern 1011 in the x direction.
  • a layer of nitride with a thickness of about 10nm-100nm can be deposited in a substantially conformal manner, and then anisotropic etching such as RIE can be performed on the deposited nitride layer along the vertical direction (which can be along the substantially vertical direction. direction, and may stop at etch stop layer 1009) to remove its lateral extension and leave its vertical extension, thereby obtaining partition wall 1017.
  • Partition walls 1017 can then be used to define the location of the device's active regions.
  • the mandrel pattern formed as described above and the side walls 1017 formed on its side walls extend in the z direction. Their extent in the z-direction, and thus the extent of the active region of the device in the z-direction, can be defined.
  • a photoresist 1015 can be formed on the structure shown in Figure 4 and patterned by photolithography to occupy a certain area in the z direction, for example along the x direction Extended strips.
  • the photoresist 1015 can be used as an etching mask, and the underlying layers are sequentially etched selectively by, for example, RIE. Etching may be performed into the substrate 1001 , especially into the well region therein, thereby forming grooves in the substrate 1001 . Isolation, such as shallow trench isolation (STI), may subsequently be formed in the formed recess. Afterwards, the photoresist 1015 may be removed.
  • STI shallow trench isolation
  • the sidewalls of the second material layer 1003 in the z direction are currently exposed to the outside.
  • the sidewalls in the z direction can shield the sidewalls of the second material layer 1003 in the z direction.
  • the second material layer 1003 may be selectively etched so that its sidewalls in the z direction are relatively concave to form a concave portion.
  • atomic layer etching ALE
  • the amount of etching may be about 5nm-20nm.
  • the sidewalls of the second material layer 1003 may exhibit different shapes after etching. FIG.
  • the sidewall of the second material layer 1003 is in a C-shape concave inward.
  • the present disclosure is not limited thereto.
  • the sidewall of the second material layer 1003 may be nearly vertical after etching.
  • the etch can be isotropic, especially when larger etch volumes are required.
  • a dielectric material may be filled. This filling can be done by deposition followed by etch back. For example, a dielectric material such as oxide sufficient to fill the recess can be deposited on the substrate, and then the deposited dielectric material is etched back such as RIE.
  • the dielectric material can be left in the recess to form the first position holding layer 1019 .
  • the deposited dielectric material may be planarized such as chemical mechanical polishing (CMP) (CMP may stop at the hard mask layer 1013).
  • a certain thickness of dielectric material may be left on the substrate 1001 during etching back, so as to form the protective layer 1021 .
  • the protection layer 1021 may be located in a groove of the substrate 1001 , and its top surface is lower than the top surface of the substrate 1001 .
  • the exposed portion of the etch stop layer 1009 also an oxide in this example
  • the protective layer 1021 can protect the surface of the substrate 1001 in the following processes. For example, in this example, the range of the active region in the z direction is limited first. Subsequently, the extent of the active region in the x-direction will be defined. The protective layer 1021 can also avoid affecting the surface of the substrate that is currently exposed in the groove (see FIG. 5( c )) when defining the extent in the x-direction. In addition, in the case of forming different types of well regions in the substrate 1001 , the protection layer 1021 can protect the pn junction between the different types of well regions from being damaged by etching.
  • the upper part (first material layer) of the third material layer 1005, the second material layer 1003 and the substrate 1001 (the first material layer) can be patterned into a ridge structure (in fact , the range of the ridge structure in the z direction has been limited by the above-mentioned processing).
  • the hard mask layer 1013 and the partition wall 1017 can be used as an etching mask, and each layer is sequentially selectively etched by, for example, RIE to transfer the pattern to the underlying layer.
  • the upper portion of the substrate 1001, the second material layer 1003 and the third material layer 1005 may form a ridge structure.
  • the etching may not affect the portions of the substrate 1001 on both sides of the ridge structure in the z direction.
  • the etching can enter into the well region of the substrate 1001 .
  • the extent of etching into substrate 1001 may be substantially the same or similar to the extent of etching into substrate 1001 described above in connection with FIGS. 5( a ) to 5 ( c ).
  • grooves are formed in the substrate 1001 .
  • a protective layer can be formed in these grooves, for example by depositing, planarizing and then etching back an oxide.
  • This protective layer 1023 surrounds the periphery of the ridge structure together with the previous protective layer 1021 . In this way, similar processing conditions can be provided around the ridge structure, that is, grooves are formed in the substrate 1001, and protective layers 1021, 1023 are formed in the grooves.
  • a space for a gate stack may be reserved at both ends of the second material layer in the x direction.
  • the second material layer 1003 may be selectively etched so that its sidewalls in the x-direction are relatively recessed to form a recess (which may define a space for a gate stack).
  • ALE can be used.
  • the amount of etching may be about 10 nm-40 nm.
  • the sidewall of the second material layer 1003 may present a C-shape concave inward.
  • the etch can be isotropic, especially when larger etch volumes are required.
  • the C-shaped sidewall of the second material layer 1003 has a larger curvature at the upper and lower ends, and a smaller curvature at the waist or middle. Of course, the side walls can also be close to vertical.
  • a first active layer may be formed on sidewalls of the ridge structure to subsequently define a channel portion.
  • the ridge structure (specifically, the first material layer, the exposed surfaces of the second material layer and the third material layer) are etched back so that their peripheral sidewalls can be laterally recessed relative to the peripheral sidewalls of the partition walls 1017 .
  • ALE can be used. The etch depth may be, for example, about 10 nm-25 nm.
  • the etchant can be selected such that the etching depths of the first material layer and the third material layer in the vertical direction can be substantially the same.
  • a first active layer 1025 may be formed on the sidewall of the ridge structure by, for example, selective epitaxial growth.
  • the first active layer 1025 may not be formed on the surface of the first position maintaining layer 1019 due to selective epitaxial growth.
  • the first active layer 1025 may then define a channel portion with a thickness of, for example, about 3nm-15nm. Since the channel portion (although it may be C-shaped) mainly extends in the vertical direction, the first active layer 1025 (especially its part on the sidewall of the second material layer) can also be called a (vertical) trench road layer.
  • the thickness of the first active layer 1025 (which is subsequently used as a channel portion) can be determined by an epitaxial growth process, so the thickness of the channel portion can be better controlled.
  • the first active layer 1025 can be doped in-situ during epitaxial growth to adjust the threshold voltage of the device.
  • the portion of the first active layer 1025 on the sidewalls of the first material layer and the third material layer is shown to be relatively thick, so that its sidewall is substantially the same as the sidewall of the partition wall 1017. Flush, this is for illustration purposes only.
  • the grown first active layer 1025 may have a substantially uniform thickness.
  • the sidewalls of the portions of the first active layer 1025 on the sidewalls of the first and third material layers may be recessed relative to the sidewalls of the partition walls 1017, or may even protrude.
  • the above-mentioned etch-back of the ridge structure can respectively etch the upper end and the lower end of the concave portion upward and downward, so that after the first active layer 1025 is grown, the height t1 of the concave portion (corresponding to the first The gate length of the gate stack) may be different from the thickness t2 of the second material layer 1003 (corresponding to the gate length of the subsequently formed second gate stack), especially in this example t1 may be greater than t2.
  • the first gate stack and the second gate stack respectively formed on the left and right sides of the first active layer 1025 subsequently may have different gate lengths.
  • the etch recipe can be selected such that the upper and lower ends of the recess are etched up and down by substantially the same amount.
  • the height-increased concave portion may be self-aligned to the second material layer 1003 , so that the first gate stack and the second gate stack respectively formed on the left and right sides of the first active layer 1025 subsequently may be self-aligned with each other.
  • the first active layer 1025 may include various semiconductor materials, such as elemental semiconductor materials such as Si, Ge, etc., or compound semiconductor materials such as SiGe, InP, GaAs, InGaAs, etc.
  • the material of the first active layer 1025 can be appropriately selected according to the performance requirements of the design for the device.
  • the first active layer 1025 may include Si.
  • the first active layer 1025 on opposite sides of the ridge structure in the x direction may have substantially the same characteristics (for example, material, size, doping characteristics, etc.), and may be mutually symmetrically disposed on opposite sides of the second material layer.
  • the present disclosure is not limited thereto.
  • two devices facing each other can be formed.
  • the first active layer 1025 on opposite sides of the ridge structure may have different characteristics, for example, in at least one of thickness, material and doping characteristics. This can be achieved by masking one device region while growing the first active layer in the other device region.
  • the lattice constant of the material of the first active layer 1025 under no strain may be different from that of the material of the second material layer 1003 under no strain.
  • the first active layer 1025 may have tensile stress (eg , for n-type devices); and when the lattice constant of the material of the second material layer 1003 is less than the lattice constant of the material of the first active layer 1025 without strain, in the first active layer 1025 There may be compressive stress (eg, for p-type devices).
  • the first active layer 1025 includes Si
  • the second material layer 1003 in this example, SiGe
  • the first active layer 1025 may have a value approximately at x direction of tensile stress.
  • different types and/or different levels of stress may also be achieved by using different materials or combinations of materials.
  • an etch stop layer 1025 a and a first active layer 1025 b may be sequentially formed on the sidewall of the ridge structure by eg selective epitaxial growth.
  • the etch stop layer 1025a can define the etch stop position when the second material layer 1003 is etched subsequently (this is because the first active layer 1025b and the second material layer 1003 both comprise SiGe in this example, if no etch
  • the stop layer 1025a, which may affect the first active layer 1025b) when etching the second material layer 1003, has a thickness of, for example, about 1 nm-5 nm.
  • the first active layer 1025b may then define a channel portion, as described above, with a thickness of, for example, about 3nm-15nm.
  • the etch stop layer 1025a may include Si
  • the first active layer 1025b may include SiGe.
  • the atomic percentage of Ge in the first active layer 1025b may be greater than the atomic percentage of Ge in the second material layer 1003 .
  • III-V compound semiconductor materials can be grown to achieve the desired strain or stress.
  • a first gate stack may subsequently be formed.
  • a second position maintaining layer 1027 may be formed in the concave portion.
  • the second position holding layer 1027 may be formed by deposition and then etched back, and may include a material such as SiC having etch selectivity relative to the first position holding layer 1019 .
  • the part of the first active layer 1025 adjacent to the third material layer 1005 is shown as being integrated with the third material layer 1005 .
  • source/drain doping can be performed.
  • a solid-phase dopant source layer 1029 may be formed on the structure shown in FIG. 11 by, for example, deposition.
  • the solid-phase dopant source layer 1029 may be formed in a substantially conformal manner.
  • the solid-phase dopant source layer 1029 may be an oxide containing dopants with a thickness of about 1 nm-5 nm.
  • the dopant contained in the solid-phase dopant source layer 1029 can be used to dope the source/drain (and optionally, the exposed surface of the substrate 1001), so it can have the same type of conductivity.
  • the solid-phase dopant source layer 1029 may contain a p-type dopant such as B or In; for an n-type device, the solid-phase dopant source layer 1029 may contain an n-type dopant such as P or In. As.
  • the dopant concentration of the solid-phase dopant source layer 1029 may be about 0.1%-5%.
  • the protective layers 1021 and 1023 may be selectively etched by, for example, RIE to expose the surface of the substrate 1001 .
  • the exposed surface of the substrate 1001 can also be doped to form respective contact regions for the source/drain portions S/D at the lower ends of the two devices.
  • the dopant in the solid-phase dopant source layer 1029 can be driven into the first material layer and the third material layer to form the source/drain part S/D (and optionally, can be driven into the lining In the exposed surface of the bottom 1001 to form the respective contact regions of the source/drain portions S/D of the lower ends of the two devices), as shown in FIG. 13 . Afterwards, the solid-phase dopant source layer 1029 may be removed.
  • the (doping concentration) interface of the source/drain portion S/D (with the inner portion of the first material layer and the third material layer) may be substantially parallel to the sidewalls of the first material layer and the third material layer, That is, may be in a vertical direction, and may be aligned with each other.
  • the drive-in degree of the dopant in the lateral direction can be controlled, so that the parts of the first material layer and the third material layer close to the second gate stack formed later (as shown by the dotted circle in the figure) can keep low doping ( relative to the source/drain portions) or substantially unintentionally doped (eg, dopants from the solid-phase dopant source layer 1029 may not substantially enter these portions). This helps prevent band-to-band tunneling due to gate voltage, and/or lowers GIDL.
  • the portion of the first active layer 1025 on the sidewall of the first material layer has substantially the same doping as the surrounding portion of the first material layer (forming the source/drain portion S/D at the lower end), so it is appended below The interface between them is not shown in the figure for convenience of illustration.
  • the first material layer is provided by the upper part of the substrate 1001 .
  • the present disclosure is not limited thereto.
  • the first material layer may also be an epitaxial layer on the substrate 1001 .
  • the first material layer and the third material layer may be doped in-situ during epitaxy instead of using a solid-phase dopant source layer for doping.
  • an isolation layer 1031 such as shallow trench isolation (STI) may be formed, as shown in FIG. 14 .
  • the method for forming the isolation layer may be similar to the method for forming the protective layers 1021 and 1023 as described above, and will not be repeated here.
  • the first position holding layer 1019 and the second position holding layer 1027 (on the outside) and the second material layer 1003 (on the inside) surround a part of the first active layer 1025 .
  • the portion of the first active layer 1025 may serve as a channel portion.
  • the channel part may be a C-shaped curved nanosheet (when the nanosheet is narrow, for example, when the dimension in the z direction perpendicular to the paper surface in FIG. 14 is small, it may become a nanowire).
  • the thickness of the channel portion (in the case of nanowires, thickness or diameter) It is basically determined by the selective growth process of the first active layer 1025 . This is a huge advantage over techniques that use only etching methods or photolithography to determine the thickness, because epitaxial growth processes have much better process control than etching or photolithography. Therefore, the control of stress is also better.
  • Gate stacks may be formed on both sides of the channel portion, respectively.
  • the second position holding layer 1027 (in this example, SiC) can be removed by selective etching.
  • the first position maintaining layer 1019 (in this example, an oxide) may remain. Thereby, the space occupied by the second position maintaining layer 1027 may be released, and a part of the first active layer 1025 may be exposed.
  • a first gate stack may be formed.
  • the gate dielectric layer 1037 can be formed substantially conformally by deposition, and the gate conductor layer 1039 can be formed on the gate dielectric layer 1037 . By depositing and then etching back, the gate conductor layer 1039 can substantially occupy the space where the second position holding layer 1027 was located before.
  • Anisotropic etching such as RIE along the vertical direction, may also be performed on the gate dielectric layer 1037 to expose the hard mask layer 1013 for subsequent processing.
  • the gate dielectric layer 1037 may include a high-k gate dielectric such as HfO 2 , with a thickness of, for example, about 2 nm-10 nm.
  • a high-k gate dielectric such as HfO 2
  • an interfacial layer may also be formed, for example, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of about 0.3nm-1.5nm.
  • the gate conductor layer 1039 may include a work function adjusting metal such as TiN, TaN, TiAlC and the like and a gate conductive metal such as W and the like.
  • the first active layer 1025 is held inside by the second material layer 1003, so that stress therein can be suppressed from being released.
  • the inside of the channel portion may be processed.
  • the first active layer 1025 is held by the gate dielectric layer 1037 and the gate conductor layer 1039 on the outside, so that the stress therein can be prevented from being released.
  • an etch stop layer or a protective layer 1033 may be formed on the isolation layer 1031 .
  • the etch stop layer or protective layer 1033 can be formed in a substantially conformal manner, and can include a desired etch selectivity (eg, with respect to the gate stack, isolation layer, first to third material layers, etc., according to subsequent selections). The nature of the etching operation can be understood) materials such as SiC.
  • a dielectric material 1035 such as an oxide, may be formed by deposition.
  • the dielectric material 1035 helps to open the processing channel to the inside.
  • a planarization process such as CMP may be performed to remove the hard mask layer 1013 to expose the core pattern 1011 .
  • the height of the partition wall 1017 may be reduced.
  • the core pattern 1011 may be removed by selective etching such as wet etching using TMAH solution or dry etching using RIE. In this way, a pair of partition walls 1017 (reduced in height and possibly changed in top shape) are left on the ridge structure extending opposite to each other.
  • the etch stop layer 1009 , the third material layer 1005 , the second material layer 1003 and the upper part of the substrate 1001 can be selectively etched sequentially by using the partition walls 1017 and the dielectric material 1035 as etching masks, for example, by RIE. Etching may be performed into the well region of the substrate 1001 . In this way, in the space surrounded by the isolation layer 1031 , the third material layer 1005 , the second material layer 1003 and the upper part of the substrate 1001 form a pair of stacks corresponding to the partition wall 1017 to define an active region.
  • the formation of the stack for defining the active region is not limited to the partition wall pattern transfer technology, and may also be performed by photolithography using photoresist or the like.
  • the substrate 1001 and the third material layer 1005 both Si in this example
  • the substrate 1001 and the third material layer 1005 both Si in this example
  • the second material layer 1003 SiGe in this example
  • the selective etching of the second material layer 1003 can be stopped at the etch stop layer 1025a, and the etch stop layer 1025a can be further removed to expose the first active layer 1025b.
  • the etch stop layer 1025a can also be retained, because the Si etch stop layer 1025a helps to improve the gate-dielectric interface characteristics.
  • a second gate stack may be formed on the inner side.
  • an isolation layer may be formed inside.
  • an isolation layer can be formed on the inner side by depositing (and planarizing) followed by etching back.
  • this isolation layer may comprise an oxide, and is thus shown as 1031 together with the previous isolation layer 1031 and dielectric material 1035 (also etched back together).
  • the top surface of the isolation layer 1031 may be lower than the top surface of the first material layer (ie, the top surface of the substrate 1001 ) or the bottom surface of the second material layer.
  • the gate dielectric layer 1037' can be formed substantially conformally by deposition, and the gate conductor layer 1039' can be formed on the gate dielectric layer 1037'. By depositing and then etching back, the gate conductor layer 1039 ′ can substantially occupy the space where the second material layer 1003 was located before.
  • the gate dielectric layer 1037' may also include a high-k gate dielectric such as HfO 2 , with a thickness of about 2nm-10nm, for example.
  • a high-k gate dielectric such as HfO 2
  • an interfacial layer such as an oxide with a thickness of about 0.3nm-1.5nm, may also be formed.
  • the gate dielectric layer 1037' may have different performance parameters (eg, material, thickness, etc.) from the gate dielectric layer 1037 .
  • the gate conductor layer 1039' may include a work function adjusting metal such as TiN, TaN, TiAlC, etc. and a gate conductive metal such as W.
  • the gate conductor layer 1039' may have different performance parameters (eg, material, equivalent work function, etc.) from the gate conductor layer 1039 .
  • the gate conductor layer 1039 and the gate conductor layer 1039' may include different metal elements from each other.
  • threshold voltages (Vt) caused by the first gate stack (1037/1039) and the second gate stack (1037'/1039') may be different from each other.
  • Vt of the channel portion near the first gate stack may be lower than the Vt of the channel portion near the second gate stack; and for a p-type device, the Vt of the channel portion near the first gate stack
  • the Vt of the portion of the channel may be higher than the Vt of the portion of the channel close to the second gate stack.
  • the equivalent work functions of the first gate stack (1037/1039) and the second gate stack (1037'/1039') may be different from each other.
  • the equivalent work function of the first gate stack may be smaller than the equivalent work function of the second gate stack (for example, the second gate stack includes Ti, and the first gate stack includes Al); while for a p-type device
  • the equivalent work function of the first gate stack may be greater than the equivalent work function of the second gate stack (eg, the second gate stack includes Al and the first gate stack includes Ti).
  • the device includes a vertical channel portion, which may be in a curved shape such as a C-shape.
  • a first gate stack having a first gate length (t1) may be formed; and on the lateral side (for example, the x direction) of the channel portion
  • a second gate stack having a second gate length (t2) may be formed.
  • the first gate length and the second gate length may be different, especially the first gate length may be greater than the second gate length.
  • the distance between the edge of the first gate stack in the vertical direction (such as the y direction) and the source/drain portion can be smaller than the distance between the edge of the second gate stack in the vertical direction (such as the y direction) and the source/drain portion the distance between.
  • the first gate stack and the second gate stack may be self-aligned to each other, eg their respective centers in the vertical direction (eg, y-direction) may be aligned in the lateral direction (eg, x-direction).
  • first gate stack and the second gate stack are electrically isolated from each other. They may be electrically connected to each other through an interconnection structure formed in a back-end process (BEOL).
  • BEOL back-end process
  • the first gate stack and the second gate stack may be electrically connected in the following manner to save area.
  • the outer gate conductor layer 1039 is surrounded by other layers (for example, gate dielectric layers 1037, 1037', protective layer 1033, first position holding layer 1019) .
  • other layers for example, gate dielectric layers 1037, 1037', protective layer 1033, first position holding layer 1019.
  • at least a part of the sidewall of the gate conductor layer 1039 may be exposed.
  • the gate dielectric layer 1037 ′, the protection layer 1033 and the gate dielectric layer 1037 may be selectively etched in sequence by eg RIE.
  • the first position maintaining layer 1019 may be exposed.
  • the first position maintaining layer 1019 can be selectively etched to release part of the space it occupies.
  • conductors may subsequently be formed to electrically connect the first gate stack and the second gate stack.
  • ALE may be used.
  • the remaining first position holding layer 1019 can protect the channel portion (particularly, the end portion in the z direction), and thus can be referred to as a protective layer.
  • selective etching such as RIE may be further performed on the gate dielectric layer 1037' and the gate dielectric layer 1037, so as to expose at least a part of sidewalls of the gate conductor layers 1039, 1039' in the z direction.
  • a conductive layer 1041 may be formed by deposition.
  • a planarization treatment such as CMP can be performed on the conductor layer 1041 , and the CMP can be stopped at the partition walls 1017 .
  • the conductive layer 1041 can be etched back so that its top surface is lower than the bottom surface of the upper source/drain part (or, the top surface of the second material layer or the bottom surface of the third material layer), so as to avoid the conductive layer 1041 from contacting the source/drain part. Short circuit between drains.
  • the conductor layer 1041 may fill a space released due to the selective etching of the first position maintaining layer 1019 .
  • the gate conductor layers 1039 and 1039 ′ may be electrically connected to each other through the conductor layer 1041 .
  • the two devices are electrically connected to each other due to the conductor layer 1041 .
  • the conductor layer 1041 can be disconnected between two devices by, for example, photolithography, and the landing pad of the gate contact can also be patterned at the same time.
  • a photoresist 1043 can be formed and patterned to mask areas where the landing pads of the gate contacts are to be formed, while exposing other areas.
  • the photoresist 1043 can cover the part of the conductive layer 1041 exposed by the partition wall 1017 on the side of the partition wall 1017 in the z direction (the upper side in FIG.
  • the gate conductor layers 1039, 1039' on the inner and outer sides of the gate extend continuously.
  • the photoresist 1043 (and the partition wall 1017 ) can be used as a mask to selectively etch the RIE conductor layer 1041 .
  • the photoresist 1043 may be removed.
  • the gate conductor layers 1039 , 1039 ′ can also be etched by the etchant used to etch the conductor layer 1041 .
  • the gate conductor layers 1039, 1039' and the conductor layer 1041 are basically left and self-aligned under the partition wall 1017, except that the conductor layer 1041 protrudes a part on one side of the partition wall 1017 (upper side in FIG. 20(b)). to be used outside of the landing pad.
  • the conductor layer 1041 is separated between two opposing devices respectively under the opposing partition walls 1017 .
  • first gate stack 1037/1039
  • second gate stack Stacked 1037'/1039'
  • the first gate stack and the second gate stack may be electrically connected to each other through the conductor layer 1041 . Both ends of the channel portion in the z direction are covered with the first position holding layer 1019 (ie, protective layer).
  • the respective landing pads of the two devices are located on the same side of the opposing partition wall 1017 (upper side in FIG. 20( b )).
  • the present disclosure is not limited thereto.
  • the respective landing pads of the two devices may be located in different locations.
  • a dielectric layer 1043 may be formed on the substrate by, for example, deposition followed by planarization. Then, a contact hole may be formed and filled with a conductive material such as metal to form a contact portion 1045 .
  • the contact portion 1045 may include a contact portion penetrating through the partition wall 1017 and the etch stop layer 1009 to connect to the upper source/drain portion, and a contact portion penetrating the dielectric layer 1043 and the isolation layer 1031 to connect to the contact region of the lower end source/drain portion, And the contact portion penetrating the dielectric layer 1043 to connect to the landing pad of the conductor layer 1041 .
  • 22(a) and 22(b) respectively show the energy band diagram of the n-type device according to the comparative example and the energy band diagram of the n-type device according to the embodiment of the present invention.
  • the source region S and the drain region D can be defined by n-type doping in the active region (the source region S and the drain region D are interchangeable, Therefore, they can be collectively referred to as source/drain regions).
  • a channel region CH may be formed between the source region S and the drain region D.
  • a first gate stack FG (which may be referred to as a front gate) may be formed at one side of the channel region CH, and a second gate stack BG (which may be referred to as a back gate) may be formed at the other side.
  • the first gate stack FG and the second gate stack BG may have the same gate length and be substantially aligned on opposite sides of the channel region CH. Due to this arrangement, on the side of the drain region D, the bandgap (shown by the double-headed arrow in the figure) can become smaller, and thus electrons are easy to tunnel, resulting in GIDL.
  • the edge of the first gate stack FG is farther away from the adjacent source/drain region S or D than the corresponding edge of the second gate stack BG The distance from the adjacent source/drain region S or D. Due to this position shift, the bandgap can be enlarged relative to the situation shown in FIG. 22( a ), it is relatively difficult for electrons to tunnel, and thus GIDL can be suppressed.
  • Figures 22(a) and 22(b) illustrate the principle of suppressing GIDL in the embodiments disclosed in the present invention by taking an n-type device as an example. The same is true for p-type devices.
  • the devices have substantially the same or similar configurations on the source region side and the drain region side.
  • the present disclosure is not limited thereto. From the viewpoint of suppressing GIDL, the concept of the present invention can be applied to the drain region side.
  • a substrate 1001 can be provided as described above, and a well region can be formed therein.
  • a first material layer 1002, a second material layer 1003, and a third material layer 1005 can be formed by, for example, epitaxial growth.
  • the first material layer 1002 can be used to define the position of the source/drain at the lower end, and its thickness is, for example, about 20nm-200nm.
  • the first material layer 1002 can be in-situ doped during growth, and the doping concentration can be about 1E19-1E21 cm ⁇ 3 .
  • Adjacent layers among the substrate 1001 and the above layers formed thereon may have etch selectivity relative to each other.
  • the first material layer 1002 may include Si.
  • a substrate 1001 may be provided as described above, and a well region may be formed therein.
  • a second material layer 1003 and a third material layer 1005 can be formed, for example, by epitaxy.
  • the third material layer 1005 can be in-situ doped during growth, and the doping concentration can be about 1E19-1E21 cm ⁇ 3 .
  • a device as shown in Figure 24(a) can be obtained.
  • the parts of the first material layer and the third material layer close to the second gate stack can be low-doped (relative to the source/drain part) or basically not intentionally doped, only the third material layer
  • the portion of the layer close to the second gate stack can be lightly doped or substantially undoped on purpose (as indicated by the dashed circle in the figure), while the portion of the first material layer close to the second gate stack can be heavily doped (and thus can be become part of the source/drain section).
  • the source/drain portion at the upper end may become the drain.
  • a device as shown in Figure 24(b) can be obtained.
  • the portion of the first material layer close to the second gate stack can be low-doped or substantially unintentionally doped (as shown by the dotted circle in the figure), while the portion of the third material layer close to the second gate stack can be heavily doped (and thus can be part of the source/drain).
  • the source/drain portion at the lower end may become the drain.
  • Fig. 27(a) shows the energy band diagram of the n-type device according to this embodiment.
  • the gate stacks FG and BG of FIG. 27(a) may be the same as those shown in FIG. 22(b), except that on the side of the channel portion (specifically, the side of the source S), the source/drain doping ( In the case of an n-type device, the n-type heavily doped) may extend to the edge of the second gate stack BG. It can be seen that on the drain D side, the benefit of increasing the band gap to suppress GIDL can still be maintained; meanwhile, on the source S side, due to the source/drain doping distribution, the external resistance can be reduced and the performance improved.
  • 25 to 26 schematically illustrate some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • the depths to which the concave portion is etched back upward and downward may be substantially the same.
  • the depths to which the concave portion is etched back upward and downward may be different. This can be achieved by selecting materials for the first material layer and the third material layer, selecting an etching recipe, and the like.
  • FIG. 25 only shows the case where the depth of etching back upward is greater than the depth of etching back downward, but it is also possible that the depth of etching back downward is greater than the depth of etching back upward.
  • the first active layer 1025' may be formed by, for example, selective epitaxial growth.
  • the height t1' of the concave portion may be different from the thickness t2 of the second material layer 1003, especially t1' may be greater than t2.
  • the distance of the upper end of the thickness t1 ′ relative to the upper end of the thickness t2 may be greater than the distance of the lower end of the thickness t1 ′ relative to the lower end of the thickness t2 (the distance may even be zero).
  • the distance between the lower end of the thickness t1' and the lower end of the thickness t2 may be greater than the distance between the upper end of the thickness t1' and the upper end of the thickness t2 (the distance may even be zero).
  • the process can be carried out according to the above-mentioned embodiment.
  • the distance between the edge of the first gate stack and the adjacent source/drain portion is smaller than the distance between the edge of the second gate stack and the adjacent source/drain portion.
  • the distance between the source/drain part (the source/drain part can become the drain); and at the other end of the channel part in the vertical direction, the edge of the first gate stack and the edge of the second gate stack can be mutually Relatively close, it can even be aligned in the lateral direction (x-direction).
  • Fig. 27(b) shows the energy band diagram of the n-type device according to this embodiment.
  • the edges of the first gate stack FG and the second gate stack BG on the side of the source S can be slightly offset relative to each other (even can be aligned with each other), while the edges on the side of the drain D
  • the edges may be offset relatively to each other, in particular the edges of the first gate stack FG are closer to the doping profile of the drain D than the edges of the second gate stack BG. It can be seen that on the drain D side, the increased bandgap can still be maintained to suppress the benefit of GIDL.
  • the first gate stack and the second gate stack are electrically connected to each other through the conductor layer 1041 , and can receive the same electrical signal through the contact portion to the conductor layer 1041 .
  • the present disclosure is not limited thereto.
  • the conductor layer 1041 may not be formed to electrically connect them to each other, and the first gate stack and the second gate stack may be respectively applied with different electrical signals.
  • two devices are formed based on a single ridge structure.
  • a single device may be formed based on a single ridge structure.
  • the single ridge structure may be similar to the stacked part below the single partition wall 1017 above, and the treatment of the single ridge structure is similar to the treatment of the stacked part, except that the trench When processing the outside of the track portion, the sidewall of the single ridge structure on the side of the hard mask layer 1013 or the mandrel pattern can be shielded by another material layer.
  • a semiconductor device may be applied to various electronic devices.
  • integrated circuits ICs
  • electronic equipment can be constructed thereby. Therefore, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic equipment may also include components such as a display screen coordinated with the integrated circuit and a wireless transceiver coordinated with the integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, power banks, and the like.
  • SoC system on a chip
  • the method may include the methods described above.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

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Abstract

公开了一种具有双栅结构的半导体器件及其制造方法及包括这种半导体器件的电子设备。根据实施例，半导体器件可以包括：衬底上的竖直沟道部；相对于衬底分别处于沟道部的上下两端的源/漏部；以及在沟道部在相对于衬底为横向的第一方向上第一侧的第一栅堆叠以及在沟道部在第一方向上与第一侧相对的第二侧的第二栅堆叠。第一栅堆叠靠近沟道部的一端在竖直方向上的上边缘和下边缘中的至少一个边缘与相应的源/漏部之间的距离可以小于第二栅堆叠靠近沟道部的一端在竖直方向上的上边缘和下边缘中与上述至少一个边缘相应的至少一个边缘与相应的源/漏部之间的距离。

Description

具有双栅结构的半导体器件及其制造方法及电子设备
相关申请的引用
本申请要求于2021年8月27日递交的题为“具有双栅结构的半导体器件及其制造方法及电子设备”的中国专利申请202111000215.X的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有双栅结构的半导体器件及其制造方法及包括这种半导体器件的电子设备。
背景技术
随着半导体器件的不断小型化，提出了各种结构的器件例如鳍式场效应晶体管(FinFET)、多桥沟道场效应晶体管(MBCFET)等。但是，这些器件在增加集成密度和增强器件性能方面由于器件结构的限制而改进的空间仍然不能满足要求。
另外，由于光刻和刻蚀等工艺波动，竖直纳米片或纳米线器件如金属氧化物半导体场效应晶体管(MOSFET)难以控制纳米片或纳米线的厚度或直径。而且，难以降低栅致漏极泄漏(GIDL)。例如，对于n型MOSFET，为降低源漏之间的漏电流，可以在栅源之间施加负偏置Vgs(＜0)。然而，如果|Vgs|太大，则可以导致GIDL。因此，GIDL成为降低泄漏的限制因素。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有双栅结构的半导体器件及其制造方法及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底上的竖直沟道部；相对于衬底分别处于沟道部的上下两端的源/漏部；以及在沟道部在相对于衬底为横向的第一方向上第一侧的第一栅堆叠以及在沟道部在第一方向上与第一侧相对的第二侧的第二栅堆叠。第一栅堆叠靠近沟道部的一端在竖直 方向上的上边缘和下边缘中的至少一个边缘与相应的源/漏部之间的距离可以小于第二栅堆叠靠近沟道部的一端在竖直方向上的上边缘和下边缘中与上述至少一个边缘相应的至少一个边缘与相应的源/漏部之间的距离。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上设置第一材料层、第二材料层和第三材料层的堆叠，所述堆叠具有在相对于衬底为横向的第一方向上彼此相对的第一侧和第二侧；在第一侧和第二侧，使第二材料层的侧壁相对于第一材料层和第三材料层的侧壁在第一方向上凹入，从而限定第一凹入部；在第一侧和第二侧，进一步刻蚀第一材料层、第二材料层和第三材料层，使第一凹入部在竖直方向上的尺寸增大；在第一凹入部中形成沟道层；在形成有沟道层的第一凹入部中形成第一栅堆叠；在所述堆叠中形成沿相对于衬底为横向的第二方向延伸的条形开口，第二方向与第一方向相交，从而将所述堆叠分为分别处于第一侧和第二侧的两部分；通过开口，去除第二材料层，并在由于第二材料层的去除而释放的空间中形成第二栅堆叠，其中，第一栅堆叠在竖直方向上的尺寸大于第二栅堆叠在竖直方向上的尺寸。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体器件。
根据本公开的实施例，可以在沟道部的相对两侧分别形成第一栅堆叠和第二栅堆叠。在竖直方向上的至少一侧，第一栅堆叠和第二栅堆叠各自的边缘可以相对于彼此存在偏移，以抑制GIDL。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至21(b)示意性示出了根据本公开实施例的制造半导体器件的流程中的一些阶段，其中：图5(a)、6(a)、21(a)是俯视图，其中，图5(a)中示出了AA′线、CC′线的位置，图6(a)中示出了BB′线的位置；图1至4、5(b)、6(b)、7至9、10(a)、10(b)、11至14、15(a)、16、17(a)、18(a)、20(a)、21(b)是沿AA′线的截面图；图6(c)是沿BB′线的截面图；图5(c)、6(d)是沿CC′线的截面图；图15(b)、17(b)、18(b)、19、20(b)是沿相应截面图中的DD′线截取的剖面图，其中，图15(b)中示出了DD′线的位置；
图22(a)和22(b)分别示出了根据比较例的n型器件的能带图与根据本发明实施例的n型器件的能带图；
图23(a)至24(b)示意性示出了根据本公开另一实施例的制造半导体器件的流程中的一些阶段，其中，图23(a)、23(b)、24(a)和24(b)均是沿AA′线的截面图；
图25至26示意性示出了根据本本公开另一实施例的制造半导体器件的流程中的一些阶段，其中，图25和26均是沿AA′线的截面图；
图27(a)和27(b)分别示出了根据本公开其他实施例的n型器件的能带图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种竖直型半导体器件，具有在衬底上竖直(例如，沿大致垂直于衬底表面的方向)设置的有源区。沟道部可以是竖直纳米片或纳米线，例如截面(例如，垂直于衬底表面的截面)呈C形的弯曲纳米片或纳米线，因此这种器件可以称作C沟道场效应晶体管(C-Channel FET，即CCFET)。如下所述，纳米片或纳米线可以通过外延生长形成，因此可以是 一体的单片，且可以具有实质上均匀的厚度。沟道部可以具有竖直方向上的应变或应力。由于这种应变，沟道部的材料的晶格常数与该材料在无应变时的晶格常数不同。
该半导体器件还可以包括分别设置在沟道部上下两端的源/漏部。源/漏部可以具有一定的掺杂。例如，对于p型器件，源/漏部可以具有p型掺杂；对于n型器件，源/漏部可以具有n型掺杂。沟道部可以具有一定的掺杂，以调整器件的阈值电压。或者，该半导体器件可以是无结器件，其中沟道部与源/漏部可以具有相同导电类型的掺杂。或者，该半导体器件可以是隧穿型器件，其中沟道部两端的源/漏部可以具有彼此相反的掺杂类型。
源/漏部可以设置在相应的半导体层中。例如，源/漏部可以是相应半导体层中的掺杂区。源/漏部可以是相应半导体层的一部分或者全部。在源/漏部是相应半导体层的一部分的情况下，源/漏部与相应半导体层中的其余部分之间可以存在掺杂浓度界面。如下所述，源/漏部可以通过扩散掺杂形成。这种情况下，掺杂浓度界面可以大致沿着相对于衬底的竖直方向。
沟道部可以包括单晶半导体材料。当然，源/漏部或者它们所形成于的半导体层也可以包括单晶半导体材料。例如，它们都可以通过外延生长来形成。
该半导体器件还可以包括分别设置在沟道部在横向上的相对两侧的第一栅堆叠和第二栅堆叠。第一栅堆叠与第二栅堆叠在竖直方向上至少一侧的边缘可以相对于彼此具有偏移。例如，第一栅堆叠靠近沟道部的一端在竖直方向上的上边缘和下边缘中的至少一个边缘与相应的源/漏部之间的距离小于第二栅堆叠靠近沟道部的一端在竖直方向上的上边缘和下边缘中与上述至少一个边缘相应的至少一个边缘与相应的源/漏部之间的距离。这有助于抑制GIDL。
这种半导体器件例如可以如下制造。
根据实施例，可以在衬底上设置第一材料层、第二材料层和第三材料层的堆叠。第一材料层可以限定下端源/漏部的位置，第二材料层可以限定栅堆叠的位置，第三材料层可以限定上端源/漏部的位置。可以通过衬底例如衬底的上部来提供第一材料层，并可以通过例如外延生长来在第一材料层上依次形成第二材料层和第三材料层。或者，可以在衬底上通过例如外延生长，依次形成第一材料层、第二材料层和第三材料层。
可以基于该堆叠来制作半导体器件。该堆叠可以包括在第一方向上彼此相对的第一侧和第二侧以及在与第一方向相交(例如，垂直)的第二方向上彼此相对的第三侧和第四侧。例如，该堆叠在俯视图中可以呈四边形如矩形或方形。
可以在该堆叠的第一侧和第二侧使第二材料层的侧壁相对于第一材料层和第三材料层的侧壁在第一方向上凹入，从而限定第一凹入部，以限定用于第一栅堆叠的空间。第一凹入部可以具有向该堆叠的内侧凹入的弯曲表面。在第一凹入部的表面上可以形成沟道部。例如，可以通过在该堆叠的暴露表面上进行外延生长，来形成第一有源层，第一有源层位于第一凹入部的表面上的部分可以用作沟道部(也可以称作“沟道层”)。可以基于该堆叠的第一侧和第二侧的侧壁上的第一有源层，分别形成一个器件。于是，基于单个堆叠，可以形成彼此相对的两个器件。可以在形成了沟道层的第一凹入部中形成第一栅堆叠。
第一凹入部可以形成为使得在形成第一有源层之后，第一凹入部在竖直方向上的尺寸可以不同于(例如，大于)第二材料层在竖直方向上的厚度。这样，可以制作具有不同栅长的第一栅堆叠和第二栅堆叠。
可以在第一材料层和第三材料层中形成源/漏部。例如，可以通过掺杂第一材料层和第三材料层来形成源/漏部。这种掺杂可以通过固相掺杂剂源层来实现。在形成源/漏部时，可以在形成有沟道层的第一凹入部中形成第一位置保持层，以避免影响沟道层。
可以在该堆叠中形成开口，以分离两个器件的有源区。开口可以沿第二方向延伸，从而使该堆叠分为分别处于第一侧和第二侧的两部分，这两部分分别具有各自的沟道层。可以通过该开口，将第二材料层替换为第二栅堆叠。
在第一侧和第二侧形成第一凹入部之前，还可以在第三侧和第四侧类似地形成第二凹入部并在其中形成第二位置保持层。这有助于改善沟道层的形貌和尺寸控制。
根据本公开的实施例，用作沟道部的纳米片或纳米线的厚度以及栅长主要由外延生长确定，而不是通过刻蚀或光刻来确定，因此可以具有良好的沟道尺寸/厚度和栅长控制。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形 成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至21(b)示意性示出了根据本公开实施例的制造半导体器件的流程中的一些阶段。
如图1所示，提供衬底1001(其上部可以构成上述的第一材料层)。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。
在衬底1001中，可以形成阱区。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。阱区例如可以通过向衬底1001中注入相应导电类型掺杂剂(p型掺杂剂如B或In，或n型掺杂剂如As或P)且随后进行热退火来形成。本领域存在多种方式来设置这种阱区，在此不再赘述。
在衬底1001上，可以通过例如外延生长，形成第二材料层1003和第三材料层1005。第二材料层1003可以用来限定栅堆叠的位置，厚度例如为约20nm-50nm。第三材料层1005可以用来限定上端源/漏部的位置，厚度例如为约20nm-200nm。
衬底1001以及之上形成的上述各层中相邻的层相对于彼此可以具有刻蚀选择性。例如，在衬底1001为硅晶片的情况下，第二材料层1003可以包括SiGe(例如，Ge原子百分比为约10％-30％)，第三材料层1005可以包括Si。
图1中示意性示出了横向方向x、z和竖直方向y。x、z方向可以平行于衬底1001的顶面，并且可以彼此垂直；y方向可以基本上垂直于衬底1001的顶面。由于顶部并无约束，故而第二材料层1003中y方向上的应力可以被释放。x方向可以是上述第一方向，z方向可以是上述第二方向。
根据实施例，在以下构图中使用了隔墙(spacer)图形转移技术。为形成 隔墙，可以形成芯模图案(mandrel)。例如，如图2所示，可以在第三材料层1005上，通过例如淀积，形成用于芯模图案的层1011。例如，用于芯模图案的层1011可以包括非晶硅或多晶硅，厚度为约50nm-150nm。另外，为了更好的刻蚀控制，可以通过例如淀积，先形成刻蚀停止层1009。例如，刻蚀停止层1009可以包括氧化物(例如，氧化硅)，厚度为约1nm-10nm。
在用于芯模图案的层1011上，可以通过例如淀积，形成硬掩模层1013。例如，硬掩模层1013可以包括氮化物(例如，氮化硅)，厚度为约30nm-100nm。
可以将用于芯模图案的层1011构图为芯模图案。
例如，如图3所示，可以在硬掩模层1013上形成光刻胶1007，并通过光刻将其构图为沿z方向延伸的条状。可以光刻胶1007作为刻蚀掩模，通过例如反应离子刻蚀(RIE)依次对硬掩模层1013和用于芯模图案的层1011进行选择性刻蚀，将光刻胶的图案转移到硬掩模层1013和用于芯模图案的层1011中。RIE可以沿大致竖直的方向进行，并可以停止于刻蚀停止层1009。之后，可以去除光刻胶1007。
如图4所示，可以在芯模图案1011在x方向上相对两侧的侧壁上，形成隔墙1017。例如，可以以大致共形的方式淀积一层厚度为约10nm-100nm的氮化物，然后沿竖直方向对淀积的氮化物层进行各向异性刻蚀如RIE(可以沿大致竖直的方向进行，并可以停止于刻蚀停止层1009)，以去除其横向延伸部分而留下其竖直延伸部分，从而得到隔墙1017。隔墙1017随后可以用来限定器件有源区的位置。
如上所述形成的芯模图案及其侧壁上形成的侧墙1017在z方向上延伸。可以限定它们在z方向上的范围，并因此限定器件有源区在z方向上的范围。
如图5(a)至5(c)所示，可以在图4所示的结构上形成光刻胶1015，并通过光刻将其构图为在z方向上占据一定范围，例如沿着x方向延伸的条状。可以光刻胶1015作为刻蚀掩模，通过例如RIE依次对下方的层进行选择性刻蚀。刻蚀可以进行到衬底1001特别是其中的阱区中，从而在衬底1001中形成凹槽。形成的凹槽中随后可以形成隔离，例如浅沟槽隔离(STI)。之后，可以去除光刻胶1015。
如图5(c)所示，第二材料层1003在z方向上的侧壁当前暴露于外。
根据本公开的实施例，为避免在对第二材料层1003在x方向上的侧壁进行处理(以如下所述形成凹入部并在所形成的凹入部中形成沟道层)时影响到其在z方向上的侧壁，可以遮蔽第二材料层1003在z方向上的侧壁。
例如，如图6(a)至6(d)所示，可以对第二材料层1003进行选择性刻蚀，以使其在z方向上的侧壁相对凹入，以形成凹入部。为更好地控制刻蚀的量，可以采用原子层刻蚀(ALE)。例如，刻蚀的量可以是约5nm-20nm。取决于刻蚀的特性，例如第二材料层1003相对于衬底1001和第三材料层1005的刻蚀选择性，刻蚀后第二材料层1003的侧壁可以呈现不同的形状。在图6(d)中示出了刻蚀后第二材料层1003的侧壁为向内侧凹入的C形。但是，本公开不限于此。例如，在刻蚀选择性好时，刻蚀后第二材料层1003的侧壁可以接近竖直。在此，刻蚀可以是各向同性的，特别是在需要较大刻蚀量时。在如此形成的凹入部中，可以填充电介质材料。这种填充可以通过淀积然后回蚀的方式来进行。例如，可以在衬底上淀积足以填满凹入部的电介质材料如氧化物，然后对淀积的电介质材料进行回蚀如RIE。这样，电介质材料可以留于凹入部中而形成第一位置保持层1019。在回蚀之前，可以对淀积的电介质材料进行平坦化处理如化学机械抛光(CMP)(CMP可以停止于硬掩模层1013)。
根据本公开的实施例，在回蚀时可以留下一定厚度的电介质材料在衬底1001上，以形成保护层1021。在此，保护层1021可以处于衬底1001的凹槽中，其顶面低于衬底1001的顶面。另外，在回蚀的过程中，刻蚀停止层1009(在该示例中，也是氧化物)暴露于外的部分也可以被刻蚀。
保护层1021可以在以下处理中保护衬底1001的表面。例如，在该示例中，先限定了有源区在z方向上的范围。随后，将限定有源区在x方向上的范围。保护层1021还可以避免在限定x方向上的范围时对衬底目前在凹槽中暴露于外的表面(参见图5(c))造成影响。另外，在衬底1001中形成不同类型的阱区的情况下，保护层1021可以保护不同类型阱区之间的pn结不被刻蚀破坏。
如图7所示，可以利用硬掩模层1013和隔墙1017，将第三材料层1005、第二材料层1003和衬底1001的上部(第一材料层)构图为脊状结构(事实上，该脊状结构在z方向上的范围已通过上述处理而限定)。例如，可以硬掩模层1013和隔墙1017作为刻蚀掩模，通过例如RIE依次对各层进行选择性刻蚀， 将图案转移到下方的层中。于是，衬底1001的上部、第二材料层1003和第三材料层1005可以形成脊状结构。如上所述，由于保护层1021的存在，刻蚀可以不影响衬底1001在脊状结构在z方向上两侧的部分。
在此，刻蚀可以进入衬底1001的阱区中。刻蚀进入衬底1001中的程度可以与以上结合图5(a)至5(c)描述的刻蚀接入衬底1001中的程度基本相同或者相似。同样地，在衬底1001中形成凹槽。并且也可以在这些凹槽中例如通过淀积、平坦化然后回蚀氧化物来形成保护层(参见图8中的1023)。该保护层1023与之前的保护层1021一起围绕脊状结构的外周。这样，在脊状结构周围可以具有相似的处理条件，即，都是衬底1001中形成有凹槽，凹槽中形成有保护层1021、1023。
可以在第二材料层在x方向上的两端留出用于栅堆叠的空间。例如，如图8所示，可以对第二材料层1003进行选择性刻蚀，以使其在x方向上的侧壁相对凹入，以形成凹入部(可以限定用于栅堆叠的空间)。为更好地控制刻蚀的量，可以采用ALE。例如，刻蚀的量可以为约10nm-40nm。如上所述，刻蚀后第二材料层1003的侧壁可以呈现向内侧凹入的C形。在此，刻蚀可以是各向同性的，特别是在需要较大刻蚀量时。通常，第二材料层1003的C形侧壁在上下两端处曲率较大，而在腰部或中部处曲率较小。当然，侧壁也可以接近竖直。
可以在脊状结构的侧壁上形成第一有源层，以便随后限定沟道部。为使后续在沟道部的左右两侧形成栅堆叠时它们在竖直方向上至少一侧的边缘相对于彼此偏移，如图9所示，可以对脊状结构(具体地，第一材料层、第二材料层和第三材料层的外露表面)进行回蚀，于是其外周侧壁可以相对于隔墙1017的外周侧壁横向凹入。为控制刻蚀深度，可以采用ALE。刻蚀深度可以为例如约10nm-25nm。
在此，可以选择刻蚀剂，使其对于第一材料层和第三材料层在竖直方向上的刻蚀深度可以实质上相同。
然后，如图10(a)所示，可以通过例如选择性外延生长，在脊状结构的侧壁上形成第一有源层1025。由于选择性外延生长，第一位置保持层1019的表面上可以没有形成第一有源层1025。第一有源层1025随后可以限定沟道部， 厚度为例如约3nm-15nm。由于沟道部(尽管可以呈C形)主要在竖直方向上延伸，从而第一有源层1025(特别是其在第二材料层侧壁上的部分)也可以称作(竖直)沟道层。根据本公开的实施例，第一有源层1025(随后用作沟道部)的厚度可以通过外延生长工艺决定，因此可以更好地控制沟道部的厚度。第一有源层1025可以在外延生长时原位掺杂，以调节器件的阈值电压。
在图10(a)中，将第一有源层1025在第一材料层和第三材料层的侧壁上的部分示出为相对较厚，从而其侧壁与隔墙1017的侧壁基本齐平，这仅是为了图示方便。所生长的第一有源层1025可以具有基本上均匀的厚度。另外，第一有源层1025在第一材料层和第三材料层的侧壁上的部分的侧壁可以相对于隔墙1017的侧壁凹入，或者甚至可能突出。
在此，上述对脊状结构的回蚀可以将凹入部的上端和下端分别向上和向下刻蚀，使得生长第一有源层1025之后，凹入部的高度t1(对应于随后形成的第一栅堆叠的栅长)可以与第二材料层1003的厚度t2(对应于随后形成的第二栅堆叠的栅长)不同，特别是在该示例中t1可以大于t2。这样，随后分别在第一有源层1025左右两侧形成的第一栅堆叠和第二栅堆叠可以具有不同的栅长。可以选择刻蚀配方，使凹入部的上端和下端被向上和向下刻蚀的量基本相同。因此，高度增大的凹入部可以自对准于第二材料层1003，从而随后分别在第一有源层1025左右两侧形成的第一栅堆叠和第二栅堆叠可以彼此自对准。
第一有源层1025可以包括各种半导体材料，例如元素半导体材料如Si、Ge等，或者化合物半导体材料如SiGe、InP、GaAs、InGaAs等。可以根据设计对器件的性能要求，适当选择第一有源层1025的材料。在该示例中，第一有源层1025可以包括Si。
在图10(a)的示例中，脊状结构在x方向上相对两侧的第一有源层1025可以具有实质上相同的特征(例如，材料、尺寸、掺杂特性等)，且彼此可以对称设置在第二材料层的相对两侧。但是，本公开不限于此。如下所述，通过单个脊状结构，可以形成彼此相对的两个器件。根据设计对这两个器件的性能要求，脊状结构相对两侧的第一有源层1025可以具有不同的特征，例如在厚度、材料和掺杂特性等至少一个方面不同。这可以通过在一个器件区域中生长第一 有源层时遮蔽另一个器件区域来实现。
根据本公开的其他实施例，为在沟道部中产生应力以增强器件性能，第一有源层1025的材料在无应变时的晶格常数可以不同于第二材料层1003的材料在无应变时的晶格常数。例如，在第二材料层1003的材料在无应变时的晶格常数大于第一有源层1025的材料在无应变时的晶格常数时，第一有源层1025中可以具有拉应力(例如，对于n型器件)；而在第二材料层1003的材料在无应变时的晶格常数小于第一有源层1025的材料在无应变时的晶格常数时，第一有源层1025中可以具有压应力(例如，对于p型器件)。
在第一有源层1025包括Si的情况下，由于如上所述第二材料层1003(在该示例中，SiGe)在y方向上是弛豫的，第一有源层1025可以具有大致在x方向上的拉应力。根据本公开的其他实施例，还可以通过不同的材料或材料组合，来实现不同种类和/或不同等级的应力。
在一个示例中，如图10(b)所示，可以通过例如选择性外延生长，在脊状结构的侧壁上依次形成刻蚀停止层1025a和第一有源层1025b。刻蚀停止层1025a可以在随后刻蚀第二材料层1003时限定刻蚀停止位置(这是因为在该示例中第一有源层1025b和第二材料层1003均包括SiGe，如果不设置刻蚀停止层1025a，则在刻蚀第二材料层1003时可能影响第一有源层1025b)，厚度为例如约1nm-5nm。第一有源层1025b如上所述随后可以限定沟道部，厚度为例如约3nm-15nm。在该示例中，刻蚀停止层1025a可以包括Si，第一有源层1025b可以包括SiGe。为实现压应力，第一有源层1025b中Ge的原子百分比可以大于第二材料层1003中Ge的原子百分比。
当然，可以生长其他不同的半导体材料，例如III-V族化合物半导体材料，以实现希望的应变或应力。
以下，为方便起见，仍以图10(a)的情形为例进行描述。
在凹入部中，随后可以形成第一栅堆叠。为防止后继处理在该凹入部中留下不必要的材料或者影响第一有源层1025，如图11所示，可以在该凹入部中形成第二位置保持层1027。同样地，第二位置保持层1027可以通过淀积然后回蚀的方式形成，且可以包括相对于第一位置保持层1019具有刻蚀选择性的材料如SiC。
在图11及后继附图中，为了图示方便起见，将第一有源层1025与第三材料层1005相邻的部分示出为与第三材料层1005一体。
之后，可以进行源/漏掺杂。
如图12所示，可以通过例如淀积，在图11所示的结构上形成固相掺杂剂源层1029。固相掺杂剂源层1029可以大致共形的方式形成。例如，固相掺杂剂源层1029可以是包含掺杂剂的氧化物，厚度为约1nm-5nm。固相掺杂剂源层1029中包含的掺杂剂可以用于掺杂源/漏部(以及可选地，衬底1001的露出表面)，因此可以具有与所需形成的源/漏部相同的导电类型。例如，对于p型器件，固相掺杂剂源层1029可以包含p型掺杂剂如B或In；对于n型器件，固相掺杂剂源层1029可以包含n型掺杂剂如P或As。固相掺杂剂源层1029的掺杂剂的浓度可以为约0.1％-5％。
在该示例中，在形成固相掺杂剂源层1029之前，可以通过例如RIE，选择性刻蚀保护层1021、1023，以露出衬底1001的表面。这样，衬底1001的露出表面也可被掺杂从而形成两个器件下端的源/漏部S/D各自的接触区。
可以通过退火处理，将固相掺杂剂源层1029中的掺杂剂驱入第一材料层和第三材料层中以形成源/漏部S/D(以及可选地，可以驱入衬底1001的露出表面中以形成两个器件下端的源/漏部S/D各自的接触区)，如图13所示。之后，可以去除固相掺杂剂源层1029。
由于第一材料层和第三材料层可以具有相同的材料，且固相掺杂剂源层1029可以大致共形的方式形成在它们的表面上，因此掺杂剂从固相掺杂剂源层1029向第一材料层和第三材料层中的驱入程度可以大致相同。因此，源/漏部S/D(与第一材料层、第三材料层的内侧部分之间)的(掺杂浓度)界面可以大致平行于第一材料层和第三材料层的侧壁，也即，可以在竖直方向上，且可以彼此对准。
另外，可以控制掺杂剂在横向上的驱入程度，使得第一材料层、第三材料层靠近随后形成的第二栅堆叠的部分(如图中虚线圈所示)可以保持低掺杂(相对于源/漏部)或基本上未有意掺杂(例如，来自固相掺杂剂源层1029的掺杂剂可以基本上没有进入到这些部分中)。这有助于防止由于栅电压而导致的带间隧穿，和/或降低GIDL。
第一有源层1025在第一材料层的侧壁上的部分目前与其周围的第一材料层的部分具有基本相同的掺杂(形成下端的源/漏部S/D)，因此在以下附图中为图示方便起见不再示出它们之间的界面。
在该示例中，第一材料层通过衬底1001的上部提供。但是，本公开不限于此。例如，第一材料层也可以是衬底1001上的外延层。在这种情况下，第一材料层和第三材料层可以在外延时原位掺杂，而不是利用固相掺杂剂源层进行掺杂。
在脊状结构周围的凹槽中，可以形成隔离层1031例如浅沟槽隔离(STI)，如图14所示。形成隔离层的方法可以与如上所述形成保护层1021、1023的方法相似，在此不再赘述。
至此，第一位置保持层1019和第二位置保持层1027(在外侧)以及第二材料层1003(在内侧)围绕第一有源层1025的一部分。第一有源层1025的该部分可以用作沟道部。沟道部可以是呈C形的弯曲纳米片(当纳米片较窄时，例如，图14中垂直于纸面的方向即z方向的尺寸较小时，可以变成纳米线)。由于刻蚀第二材料层1003(SiGe)时相对于第一有源层1025(Si)的高刻蚀选择性，因此沟道部的厚度(纳米线的情况下，为粗细，或者是直径)基本上由第一有源层1025的选择性生长工艺来确定。这相对于仅使用刻蚀方法或光刻方法来确定厚度的技术具有巨大优势，因为相比于刻蚀或光刻，外延生长工艺具有好得多的工艺控制。由此，对于应力的控制也较佳。
可以在沟道部的两侧分别形成栅堆叠。
例如，如图15(a)和15(b)所示，可以通过选择性刻蚀，去除第二位置保持层1027(在该示例中，为SiC)。第一位置保持层1019(在该示例中，为氧化物)可以保留。由此，可释放第二位置保持层1027所占据的空间，并暴露第一有源层1025的一部分。在所释放的空间中，可以形成第一栅堆叠。例如，可以通过淀积，以大致共形的方式形成栅介质层1037，并在栅介质层1037上形成栅导体层1039。通过淀积然后回蚀的方式，栅导体层1039可以实质上占据之前第二位置保持层1027所在的空间。还可以对栅介质层1037进行各向异性刻蚀，如沿竖直方向的RIE，以暴露硬掩模层1013，以便于后继处理。
例如，栅介质层1037可以包括高k栅介质如HfO 2，厚度例如为约2nm- 10nm。在形成高k栅介质之前，还可以形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物，厚度为约0.3nm-1.5nm。栅导体层1039可以包括功函数调节金属如TiN、TaN、TiAlC等和栅导电金属如W等。
另外，在去除第二位置保持层1027时，第一有源层1025在内侧被第二材料层1003保持，从而可以抑制其中的应力被释放。
接下来，可以对沟道部的内侧进行处理。如图15(b)所示，在对沟道部的内侧进行处理时，第一有源层1025在外侧被栅介质层1037和栅导体层1039所保持，从而可以抑制其中的应力被释放。
为提供刻蚀停止层以及避免在对内侧处理时影响外侧业已形成的第一栅堆叠，如图16所示，可以在隔离层1031上形成刻蚀停止层或保护层1033。刻蚀停止层或保护层1033可以大致共形的方式形成，并可以包括具有所需刻蚀选择性(例如，相对于栅堆叠、隔离层、第一至第三材料层等，根据后继的选择性刻蚀操作可明了)的材料如SiC。
在刻蚀停止层或保护层1033上，可以通过淀积来形成例如氧化物的电介质材料1035。该电介质材料1035有助于打开通向内侧的处理通道。例如，可以进行平坦化处理如CMP，去除硬掩模层1013以露出芯模图案1011。在平坦化过程中，隔墙1017的高度可以降低。然后，可以通过选择性刻蚀如采用TMAH溶液的湿法刻蚀或采用RIE的干法刻蚀，去除芯模图案1011。这样，在脊状结构上留下了彼此相对延伸的一对隔墙1017(高度降低，顶端形貌也可能有所改变)。
可以利用隔墙1017以及电介质材料1035作为刻蚀掩模，通过例如RIE，依次选择性刻蚀刻蚀停止层1009、第三材料层1005、第二材料层1003以及衬底1001的上部。刻蚀可以进行到衬底1001的阱区中。这样，在隔离层1031围绕的空间内，第三材料层1005、第二材料层1003以及衬底1001的上部形成了与隔墙1017相对应的一对堆叠，用以限定有源区。
当然，形成用于限定有源区的堆叠不限于隔墙图形转移技术，也可以利用光刻胶等通过光刻来进行。
然后，如图17(a)和17(b)所示，可以相对于第一有源层1025、衬底1001和第三材料层1005(在该示例中均为Si)，通过选择性刻蚀，去除第二材料层 1003(在该示例中为SiGe)。于是，暴露了沟道部的内侧。此时，沟道部在外侧被第一栅堆叠保持，从而可以抑制其中的应力被释放。
在图10(b)所示的情形中，对第二材料层1003的选择性刻蚀可以停止于刻蚀停止层1025a，并且还可以进一步去除刻蚀停止层1025a，以露出第一有源层1025b。或者，也可以保留刻蚀停止层1025a，因为Si的刻蚀停止层1025a有助于改善栅-介质界面特性。
类似地，可以在内侧形成第二栅堆叠。
在形成第二栅堆叠之前，可以在内侧形成隔离层。例如，如图17(a)和17(b)所示，可以通过淀积(且平坦化)然后回蚀的方式，在内侧形成隔离层。例如，该隔离层可以包括氧化物，且因此与之前的隔离层1031和电介质材料1035(也被一起回蚀)一起示出为1031。隔离层1031的顶面可以低于第一材料层的顶面(即，衬底1001的顶面)或者第二材料层的底面。可以通过淀积，以大致共形的方式形成栅介质层1037′，并在栅介质层1037′上形成栅导体层1039′。通过淀积然后回蚀的方式，栅导体层1039′可以实质上占据之前第二材料层1003所在的空间。
类似地，栅介质层1037′也可以包括高k栅介质如HfO 2，厚度例如为约2nm-10nm。在形成高k栅介质之前，还可以形成界面层，例如厚度为约0.3nm-1.5nm的氧化物。
为优化器件性能，栅介质层1037′可以与栅介质层1037具有不同的性能参数(例如，材料、厚度等)。
类似地，栅导体层1039′可以包括功函数调节金属如TiN、TaN、TiAlC等和栅导电金属如W等。为优化器件性能，栅导体层1039′可以与栅导体层1039具有不同的性能参数(例如，材料、等效功函数等)。例如，栅导体层1039和栅导体层1039′可以包括彼此不同的金属元素。
根据本公开的实施例，第一栅堆叠(1037/1039)与第二栅堆叠(1037′/1039′)所导致的阈值电压(Vt)可以彼此不同。例如，对于n型器件，沟道部中靠近第一栅堆叠的部分的Vt可以低于沟道中靠近第二栅堆叠的部分的Vt；而对于p型器件，沟道部中靠近第一栅堆叠的部分的Vt可以高于沟道中靠近第二栅堆叠的部分的Vt。
根据本公开的实施例，第一栅堆叠(1037/1039)与第二栅堆叠(1037′/1039′)的等效功函数可以彼此不同。例如，对于n型器件，第一栅堆叠的等效功函数可以小于第二栅堆叠的等效功函数(例如，第二栅堆叠包括Ti，第一栅堆叠包括Al)；而对于p型器件，第一栅堆叠的等效功函数可以大于第二栅堆叠的等效功函数(例如，第二栅堆叠包括Al，第一栅堆叠包括Ti)。
至此，已基本完成了器件的制造。如图17(a)和17(b)所示，该器件包括竖直沟道部，该竖直沟道部可以呈弯曲形状如C形。在该沟道部在横向(例如，x方向)上的一侧，可以形成具有第一栅长(t1)的第一栅堆叠；而在该沟道部在横向(例如，x方向)上的一侧，可以形成具有第二栅长(t2)的第二栅堆叠。如上所述，第一栅长和第二栅长可以不同，特别是第一栅长可以大于第二栅长。于是，第一栅堆叠在竖直方向(如y方向)上的边缘与源/漏部之间的距离可以小于第二栅堆叠在竖直方向(如y方向)上的边缘与源/漏部之间的距离。第一栅堆叠和第二栅堆叠可以彼此自对准，例如它们各自在竖直方向(例如，y方向)上的中心可以在横向(例如，x方向)上对准。
在此，第一栅堆叠和第二栅堆叠彼此电隔离。它们可以通过在后端工艺(BEOL)中形成的互连结构而彼此电连接。
根据本公开的另一实施例，可以通过如下方式将第一栅堆叠和第二栅堆叠电连接，以节省面积。
在图17(a)和17(b)所示的状态下，外侧形成的栅导体层1039被其他层(例如，栅介质层1037、1037′，保护层1033，第一位置保持层1019)包围。为了使得沟道部内外两侧的栅导体层能彼此电连接，可以暴露栅导体层1039(特别是在z方向上)的至少一部分侧壁。
为此，如图18(a)和18(b)所示，可以通过例如RIE，依次对栅介质层1037′、保护层1033和栅介质层1037进行选择性刻蚀。于是，第一位置保持层1019可以被露出。可以对第一位置保持层1019进行选择性刻蚀，以释放一部分其所占据的空间。在所释放的空间中，随后可以形成导体，以便将第一栅堆叠和第二栅堆叠电连接。为控制对第一位置保持层1019的刻蚀量，可以采用ALE。留下的第一位置保持层1019可以保护沟道部(特别是在z方向上的端部)，且因此可以称作保护层。之后，可以进一步对栅介质层1037′和栅介质层1037进 行选择性刻蚀如RIE，以露出栅导体层1039、1039′在z方向上的至少一部分侧壁。
在隔离层1031上，可以通过淀积，形成导体层1041。可以对导体层1041进行平坦化处理如CMP，CMP可以停止于隔墙1017。然后，可以回蚀导体层1041，以使其顶面低于上端源/漏部的底面(或者，第二材料层的顶面或第三材料层的底面)，以避免导体层1041与源/漏部之间的短路。导体层1041可以填充由于第一位置保持层1019的选择性刻蚀而被释放的空间。栅导体层1039和1039′可以通过导体层1041彼此电连接。
当前，两个器件由于导体层1041而彼此电连接。可以根据器件设计，通过例如光刻，将导体层1041在两个器件之间断开，同时也可以构图栅接触部的着落焊盘(landing pad)。
如图19所示，可以形成光刻胶1043，并将其构图为遮蔽要形成栅接触部的着落焊盘的区域，而露出其他区域。在此，光刻胶1043可以覆盖导体层1041在隔墙1017在z方向上的一侧(图19中上侧)被隔墙1017露出的一部分，以便导体层1041可以在这一侧在沟道部内外两侧的栅导体层1039、1039′之间连续延伸。
然后，如图20(a)和20(b)所示，可以光刻胶1043(以及隔墙1017)作为掩模，选择性刻蚀如RIE导体层1041。之后，可以去除光刻胶1043。在此，栅导体层1039、1039′也可以被用来刻蚀导体层1041的刻蚀剂所刻蚀。
于是，栅导体层1039、1039′以及导体层1041基本留于且自对准于隔墙1017下方，除了导体层1041在隔墙1017的一侧(图20(b)中的上侧)突出一部分以用作着落焊盘之外。导体层1041在分别处于相对隔墙1017下方的两个相对器件之间分离。
如图20(b)所示，在沟道部在x方向上的一侧，具有第一栅堆叠(1037/1039)；在沟道部在x方向上相对的另一侧，具有第二栅堆叠(1037′/1039′)。第一栅堆叠和第二栅堆叠可以通过导体层1041彼此电连接。沟道部在z方向上的两端被第一位置保持层1019(即，保护层)覆盖。
在该示例中，两个器件各自的着落焊盘位于相对的隔墙1017同一侧(图20(b)中上侧)。但是，本公开不限于此。例如，两个器件各自的着落焊盘可以 位于不同位置。
随后，可以制作各种接触部、互连结构等。
例如，如图21(a)和21(b)所示，可以通过例如淀积然后平坦化的方式，在衬底上形成电介质层1043。然后，可以形成接触孔，并在接触孔中填充导电材料如金属，形成接触部1045。接触部1045可以包括穿透隔墙1017和刻蚀停止层1009连接到上端源/漏部的接触部，穿透电介质层1043和隔离层1031连接到下端源/漏部的接触区的接触部，以及穿透电介质层1043连接到导体层1041的着落焊盘的接触部。
图22(a)和22(b)分别示出了根据比较例的n型器件的能带图与根据本发明实施例的n型器件的能带图。
如图22(a)所示，在根据比较例的n型器件中，在有源区中可以通过n型掺杂限定源区S和漏区D(源区S和漏区D可互换，因此它们可统称为源/漏区)。沟道区CH可以形成于源区S和漏区D之间。在沟道区CH的一侧可以形成第一栅堆叠FG(可以称作前栅)，且在另一侧可以形成第二栅堆叠BG(可以称作背栅)。通常，第一栅堆叠FG和第二栅堆叠BG可以具有相同的栅长并在沟道区CH的相对两侧实质上对准。由于这种设置，在漏区D一侧，带隙(如图中的双向箭头所示)可以变小，且因此电子易于隧穿，从而导致GIDL。
如图22(b)所示，在根据本公开实施例的n型器件中，第一栅堆叠FG的边缘距相邻的源/漏区S或D的距离大于第二栅堆叠BG的相应边缘距相邻的源/漏区S或D的距离。由于这种位置偏移，可以相对于图22(a)所示的情形增大带隙，电子相对难以隧穿，并因此可以抑制GIDL。
图22(a)和22(b)以n型器件为例说明了本发明公开的实施例抑制GIDL的原理。对于p型器件，同样如此。
在以上实施例中，器件在源区一侧和漏区一侧具有基本相同或类似的配置。但是，本公开不限于此。从抑制GIDL的角度，本发明的构思可以应用于漏区一侧。
图23(a)至24(b)示意性示出了根据本公开另一实施例的制造半导体器件的流程中的一些阶段。以下主要描述该实施例与上述实施例的不同之处。
如图23(a)所示，可以如上所述提供衬底1001，并可以在其中形成阱区。 在衬底1001上，可以通过例如外延生成，形成第一材料层1002、第二材料层1003和第三材料层1005。第一材料层1002可以用来限定下端源/漏部的位置，厚度例如为约20nm-200nm。第一材料层1002在生长时可以被原位掺杂，掺杂浓度可以为约1E19-1E21cm -3。
衬底1001以及之上形成的上述各层中相邻的层相对于彼此可以具有刻蚀选择性。例如，在衬底1001为硅晶片的情况下，第一材料层1002可以包括Si。
关于第二材料层1003和第三材料层1005，可以参见以上实施例中的描述。
或者，如图23(b)所示，可以如上所述提供衬底1001，并可以在其中形成阱区。在衬底1001上，可以通过例如外延生成，形成第二材料层1003和第三材料层1005。与上述实施例中不同，第三材料层1005可以在生长时被原位掺杂，掺杂浓度可以为约1E19-1E21cm -3。
之后，工艺可以按照上述实施例进行。
从图23(a)所示的叠层开始，可以得到如图24(a)所示的器件。与上述实施例中第一材料层、第三材料层各自靠近第二栅堆叠的部分可以为低掺杂(相对于源/漏部)或基本上未有意掺杂的情形不同，仅第三材料层靠近第二栅堆叠的部分可以为低掺杂或基本上未有意掺杂(如图中虚线圈所示)，而第一材料层靠近第二栅堆叠的部分可以重掺杂(并因此可以成为源/漏部的一部分)。在该示例中，上端的源/漏部可以成为漏极。
另外，从图23(b)所示的叠层开始，可以得到如图24(b)所示的器件。类似地，仅第一材料层靠近第二栅堆叠的部分可以为低掺杂或基本上未有意掺杂(如图中虚线圈所示)，而第三材料层靠近第二栅堆叠的部分可以重掺杂(并因此可以成为源/漏部的一部分)。在该示例中，下端的源/漏部可以成为漏极。
图27(a)示出了根据该实施例的n型器件的能带图。图27(a)的栅堆叠FG和BG可以与图22(b)所示的相同，不同之处在于在沟道部一侧(具体地，源极S一侧)，源/漏掺杂(在n型器件的情况下，n型重掺杂)可以延伸到第二栅堆叠BG的边缘处。可以看到，在漏极D一侧，仍然可以保持带隙增大从而抑制GIDL的益处；同时，在源极S一侧，由于源/漏掺杂分布，可以减小外电阻并改进性能。
图25至26示意性示出了根据本公开另一实施例的制造半导体器件的流程中的一些阶段。
在以上实施例中，在结合图9描述的回蚀工艺中，凹入部被向上和向下回蚀的深度可以实质上相同。与此不同，在本实施例中，如图25所示，凹入部被向上和向下回蚀的深度可以不同。这可以通过选择第一材料层和第三材料层的材料、选择刻蚀配方等来实现。图25中仅示出了向上回蚀的深度大于向下回蚀的深度的情形，但是向下回蚀的深度大于向上回蚀的深度也是可能的。
然后，如图26所示，可以通过例如选择性外延生长，形成第一有源层1025′。类似地，生长第一有源层1025之后，凹入部的高度t1′与第二材料层1003的厚度t2可以不同，特别是t1′可以大于t2。在该示例中，厚度t1′的上端相对于厚度t2的上端的距离可以大于厚度t1′的下端相对于厚度t2的下端的距离(该距离甚至可以为零)。当然，根据其他实施例，厚度t1′的下端相对于厚度t2的下端的距离可以大于厚度t1′的上端相对于厚度t2的上端的距离(该距离甚至可以为零)。
之后，工艺可以按照上述实施例进行。在由此得到的器件中，在沟道部在竖直方向上的一端处，第一栅堆叠的边缘与相邻的源/漏部之间的距离小于第二栅堆叠的边缘与相邻的源/漏部之间的距离(该源/漏部可以成为漏极)；而在沟道部在竖直方向上的另一端处，第一栅堆叠的边缘与第二栅堆叠的边缘彼此可以相对较近，甚至可以在横向(x方向)上对准。
图27(b)示出了根据该实施例的n型器件的能带图。在该实施例中，第一栅堆叠FG与第二栅堆叠BG各自在源极S一侧的边缘相对于彼此偏移可以较小(甚至可以彼此对准)，而在漏极D一侧的边缘相对于彼此可以偏移较大，特别是第一栅堆叠FG的边缘相比于第二栅堆叠BG的边缘更靠近漏极D的掺杂分布。可以看到，在漏极D一侧，仍然可以保持带隙增大从而抑制GIDL的益处。
在以上实施例中，第一栅堆叠和第二栅堆叠通过导体层1041彼此电连接，并可以通过到导体层1041的接触部而接收相同的电信号。但是，本公开不限于此。例如，可以不形成导体层1041来将它们彼此电连接，并且第一栅堆叠和第二栅堆叠可以被分别施加不同的电信号。
在以上实施例中，基于单个脊状结构形成两个器件。这有利于简化制造。但是，本公开不限于此。例如，可以基于单个脊状结构形成单个器件。这种情况下，该单个脊状结构可以类似于以上单个隔墙1017下方的叠层部分，且对于该单个脊状结构的处理类似于对该叠层部分的处理，不同之处在于在对沟道部外侧进行处理时，该单个脊状结构在硬掩模层1013或芯模图案这一侧的侧壁可以利用另外的材料层来遮蔽。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，可以基于这样的半导体器件形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (29)

  1. 一种半导体器件，包括：
    衬底上的竖直沟道部；
    相对于所述衬底分别处于所述沟道部的上下两端的源/漏部；以及
    在所述沟道部在相对于衬底为横向的第一方向上第一侧的第一栅堆叠以及在所述沟道部在所述第一方向上与第一侧相对的第二侧的第二栅堆叠，
    其中，所述第一栅堆叠靠近所述沟道部的一端在竖直方向上的上边缘和下边缘中的至少一个边缘与相应的源/漏部之间的距离小于所述第二栅堆叠靠近所述沟道部的一端在竖直方向上的上边缘和下边缘中与所述至少一个边缘相应的至少一个边缘与相应的源/漏部之间的距离。
  2. 根据权利要求1所述的半导体器件，其中，所述第一栅堆叠的栅长大于所述第二栅堆叠的栅长。
  3. 根据权利要求1所述的半导体器件，其中，
    所述半导体器件是n型器件，所述沟道部中邻近所述第一栅堆叠的部分的阈值电压低于所述沟道部中邻近所述第二栅堆叠的部分的阈值电压；或者
    所述半导体器件是p型器件，所述沟道部中邻近所述第一栅堆叠的部分的阈值电压高于所述沟道部中邻近所述第二栅堆叠的部分的阈值电压。
  4. 根据权利要求1所述的半导体器件，其中，
    所述半导体器件是n型器件，所述第一栅堆叠的等效功函数小于所述第二栅堆叠的等效功函数；或者
    所述半导体器件是p型器件，所述第一栅堆叠的等效功函数大于所述第二栅堆叠的等效功函数。
  5. 根据权利要求1所述的半导体器件，其中，所述第一栅堆叠中的栅介质层和所述第二栅堆叠中的栅介质层包括不同的材料和/或具有不同的厚度。
  6. 根据权利要求1所述的半导体器件，其中，所述第一栅堆叠中的栅导体层和所述第二栅堆叠中的栅导体层包括不同的金属元素。
  7. 根据权利要求1所述的半导体器件，其中，所述第一栅堆叠和所述第二栅堆叠在所述第一方向上自对准。
  8. 根据权利要求7所述的半导体器件，其中，所述第一栅堆叠靠近所述沟道部的一端在竖直方向上的上边缘相对于所述第二栅堆叠靠近所述沟道部的一端在竖直方向上的上边缘的偏移与所述第一栅堆叠靠近所述沟道部的一端在竖直方向上的下边缘相对于所述第二栅堆叠靠近所述沟道部的一端在竖直方向上的下边缘的偏移实质上相同。
  9. 根据权利要求1所述的半导体器件，还包括：
    在竖直方向上彼此间隔开的第一半导体层和第二半导体层；以及
    从所述第一半导体层的侧壁延伸到所述第二半导体层的侧壁的第三半导体层，
    其中，所述沟道部形成在所述第三半导体层在竖直方向上处于所述第一半导体层与所述第二半导体层之间的部分中，
    其中，所述源/漏部分别形成在所述第一半导体层及其侧壁上的第三半导体层中以及所述第二半导体层及其侧壁上的第三半导体层中。
  10. 根据权利要求9所述的半导体器件，其中，所述第一半导体层和所述第二半导体层中至少之一在靠近所述第二栅堆叠的部分被低掺杂或基本上未有意掺杂。
  11. 根据权利要求1所述的半导体器件，还包括：
    覆盖所述沟道部在相对于衬底为横向的第二方向上的端部的保护层，所述第二方向与所述第一方向相交。
  12. 根据权利要求11所述的半导体器件，还包括：
    将所述第一栅堆叠与所述第二栅堆叠彼此电连接的导体层，其中，所述导体层围绕所述保护层。
  13. 根据权利要求12所述的半导体器件，其中，所述导体层仅设置在所述沟道部在所述第二方向上的相对两侧。
  14. 根据权利要求11所述的半导体器件，其中，
    所述第一栅堆叠包括第一栅介质层和第一栅导体层，所述第一栅介质层介于所述第一栅导体层与所述沟道部之间以及所述第一栅导体层与所述保护层之间，
    所述第二栅堆叠包括第二栅介质层和第二栅导体层，所述第二栅介质层介 于所述第二栅导体层与所述沟道部之间以及所述第二栅导体层与所述保护层之间。
  15. 根据权利要求1所述的半导体器件，其中，所述第一栅堆叠中的栅介质层仅设置在所述沟道部的第一侧，所述第二栅堆叠中的栅介质层仅设置在所述沟道部的第二侧。
  16. 根据权利要求1所述的半导体器件，其中，所述沟道部包括截面呈C形的弯曲纳米片或纳米线。
  17. 根据权利要求16所述的半导体器件，其中，所述弯曲纳米片或纳米线具有实质上均匀的厚度。
  18. 根据权利要求1所述的半导体器件，其中，所述沟道部在相对于衬底为横向的第二方向上的两端分别呈现向内侧凹进的C形，所述第二方向与所述第一方向相交。
  19. 根据权利要求1所述的半导体器件，其中，所述沟道部、所述源/漏部中至少之一包括单晶半导体材料。
  20. 根据16所述的半导体器件，其中，所述衬底上存在多个所述半导体器件，其中至少一对半导体器件的所述C形彼此背对。
  21. 根据权利要求20所述的半导体器件，其中，所述一对半导体器件各自的沟道部实质上共面。
  22. 一种制造半导体器件的方法，包括：
    在衬底上设置第一材料层、第二材料层和第三材料层的堆叠，所述堆叠具有在相对于衬底为横向的第一方向上彼此相对的第一侧和第二侧；
    在所述第一侧和第二侧，使所述第二材料层的侧壁相对于所述第一材料层和所述第三材料层的侧壁在所述第一方向上凹入，从而限定第一凹入部；
    在所述第一侧和第二侧，进一步刻蚀所述第一材料层、所述第二材料层和所述第三材料层，使所述第一凹入部在竖直方向上的尺寸增大；
    在所述第一凹入部中形成沟道层；
    在形成有所述沟道层的所述第一凹入部中形成第一栅堆叠；
    在所述堆叠中形成沿相对于衬底为横向的第二方向延伸的条形开口，所述第二方向与所述第一方向相交，从而将所述堆叠分为分别处于所述第一侧和第 二侧的两部分；
    通过所述开口，去除所述第二材料层，并在由于所述第二材料层的去除而释放的空间中形成第二栅堆叠，
    其中，所述第一栅堆叠在竖直方向上的尺寸大于所述第二栅堆叠在竖直方向上的尺寸。
  23. 根据权利要求22所述的方法，其中，
    在限定所述第一凹入部之前，该方法还包括：
    在所述堆叠在所述第二方向上彼此相对的第三侧和第四侧，使所述第二材料层的侧壁相对于所述第一材料层和所述第三材料层的侧壁在所述
    第二方向上凹入，从而限定第二凹入部；以及
    在所述第二凹入部中形成第一位置保持层，
    在形成沟道层之后，该方法还包括：
    在所述第一凹入部中形成第二位置保持层；以及
    在所述堆叠的侧壁上形成掺杂剂源层；以及
    将所述掺杂剂源层中的掺杂剂驱入所述第一材料层和所述第三材料层中，以形成源/漏部，
    其中，形成第一栅堆叠包括：
    去除所述第二位置保持层；以及
    在所述第一凹入部中由于所述第二位置保持层的去除而释放的空间中形成所述第一栅堆叠。
  24. 根据权利要求23所述的方法，还包括：
    对所述第一位置保持层进行选择性刻蚀，以释放所述第二凹入部中的部分空间，同时所述第一位置保持层仍然覆盖所述沟道层在所述第二方向上的端部；以及
    形成导体层，所述导体层填充所述第二凹入部中所释放的部分空间，将所述第一栅堆叠与所述第二栅堆叠彼此电连接。
  25. 根据权利要求23所述的方法，还包括：
    控制掺杂剂向所述第一材料层和所述第三材料层中的驱入程度，使得所述掺杂剂基本上没有到达所述第一材料层和所述第二材料层中靠近所述第二栅 堆叠的部分。
  26. 根据权利要求22所述的方法，其中，所述沟道层通过选择性外延生长形成。
  27. 根据权利要求22所述的方法，其中，所述第一凹入部在竖直方向上向下增大的尺寸实质上等于向上增大的尺寸。
  28. 一种电子设备，包括如权利要求1至21中任一项所述的半导体器件。
  29. 根据权利要求28所述的电子设备，包括智能电话、个人计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源。
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US11848357B2 (en) 2022-01-24 2023-12-19 International Business Machines Corporation Strained superlattice
CN117673167A (zh) * 2022-08-31 2024-03-08 华为技术有限公司 一种芯片及其制备方法、电子设备
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130075811A1 (en) * 2011-09-22 2013-03-28 Semiconductor Manufacturing International (Beijing) Corporation Double gate transistor and method of fabricating the same
CN104716171A (zh) * 2013-12-11 2015-06-17 中国科学院微电子研究所 半导体设置及其制造方法
CN111244161A (zh) * 2020-01-21 2020-06-05 中国科学院微电子研究所 C形沟道部半导体装置及包括其的电子设备
CN111384156A (zh) * 2020-01-21 2020-07-07 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备
CN112582464A (zh) * 2020-12-11 2021-03-30 中国科学院微电子研究所 应变竖直沟道半导体器件及其制造方法及包括其的电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130075811A1 (en) * 2011-09-22 2013-03-28 Semiconductor Manufacturing International (Beijing) Corporation Double gate transistor and method of fabricating the same
CN104716171A (zh) * 2013-12-11 2015-06-17 中国科学院微电子研究所 半导体设置及其制造方法
CN111244161A (zh) * 2020-01-21 2020-06-05 中国科学院微电子研究所 C形沟道部半导体装置及包括其的电子设备
CN111384156A (zh) * 2020-01-21 2020-07-07 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备
CN112582464A (zh) * 2020-12-11 2021-03-30 中国科学院微电子研究所 应变竖直沟道半导体器件及其制造方法及包括其的电子设备

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