WO2021147610A1 - C形沟道部半导体器件及其制造方法及包括其的电子设备 - Google Patents

C形沟道部半导体器件及其制造方法及包括其的电子设备 Download PDF

Info

Publication number
WO2021147610A1
WO2021147610A1 PCT/CN2020/139254 CN2020139254W WO2021147610A1 WO 2021147610 A1 WO2021147610 A1 WO 2021147610A1 CN 2020139254 W CN2020139254 W CN 2020139254W WO 2021147610 A1 WO2021147610 A1 WO 2021147610A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
channel
material layer
nanosheet
nanowire
Prior art date
Application number
PCT/CN2020/139254
Other languages
English (en)
French (fr)
Inventor
朱慧珑
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US17/759,226 priority Critical patent/US20230064415A1/en
Publication of WO2021147610A1 publication Critical patent/WO2021147610A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to a semiconductor device having a C-shaped nanosheet or nanowire channel portion, a method of manufacturing the same, and an electronic device including such a semiconductor device.
  • FinFET fin field effect transistors
  • MBCFET multi-bridge channel field effect transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • the purpose of the present disclosure is at least partly to provide a semiconductor device having a C-shaped nanosheet or nanowire channel portion, a method of manufacturing the same, and an electronic device including the semiconductor device.
  • a semiconductor device including: a channel portion on a substrate, the channel portion including curved nanosheets or nanowires with a C-shaped cross section; The source/drain parts at the upper and lower ends; and the gate stack surrounding the outer periphery of the channel part.
  • the channel part may include a plurality of curved nanosheets or nanowires that are sequentially stacked in a lateral direction with respect to the substrate and each have a C-shaped cross section.
  • a method of manufacturing a semiconductor device including: disposing a stack of a first material layer, a second material layer, and a third material layer on a substrate; and patterning the stack into a ridge shape Structure, the ridge structure includes a first side and a second side opposite to each other and a third side and a fourth side opposite to each other; on the third side and the fourth side, the sidewall of the second material layer is opposite to the first side
  • the sidewalls of the one material layer and the third material layer are recessed laterally to define the first recessed portion; the first position holding layer is formed in the first recessed portion; on the first side and the second side, the second material layer
  • the sidewall is recessed laterally with respect to the sidewalls of the first material layer and the third material layer, thereby defining the second recessed portion; at least the first channel layer is formed on the surface of the second material layer exposed by the second recessed portion; A second position holding layer is formed in the remaining space of the second recessed portion;
  • a single or multiple channel layers may be formed.
  • only a single channel layer, that is, the first channel layer may be formed on the surface of the second material layer exposed by the second recessed portion.
  • a plurality of channel layers may be formed on the surface of the second material layer exposed by the second concave portion, or may be formed on the surface of the second material layer exposed by the second concave portion
  • One or more channel layers and another channel layer is formed on the surface of the formed channel layer exposed by the third recessed portion.
  • an electronic device including the above-mentioned semiconductor device.
  • a semiconductor device with a novel structure is proposed, which can have the advantages of high performance and high density.
  • FIG. 1 to 22 schematically show some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • FIGS. 23(a) to 36 schematically show some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • Figures 5(a), 6(a), 18(a), 19, 20(a), 21(a), 22, 32(a), 33, 34(a), 35(a), 36 are top views ;
  • Figures 1 to 4, 5(b), 6(b), 7 to 13, 14(a), 14(b), 15, 16(a), 17, 18(b), 20(b), 21( b), 23(a), 23(b), 24, 25, 26, 27(a), 27(b), 28, 29, 30(a), 31, 32(b), 34(b), 35(b) is a cross-sectional view along the line AA';
  • Figure 6(c) is a cross-sectional view along the line BB';
  • Figures 5(c) and 6(d) are cross-sectional views along the CC' line
  • Figures 16(b), 18(c), 20(c), 30(b), 32(c), 34(c), 37, 38 are cross-sectional views taken along the line DD' in Figure 16(a) .
  • a layer/element when referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element if a layer/element is located "on” another layer/element in one orientation, the layer/element can be located "under” the other layer/element when the orientation is reversed.
  • a vertical type semiconductor device having an active region arranged vertically on a substrate (for example, in a direction substantially perpendicular to the surface of the substrate).
  • the channel portion may be a curved nanosheet or nanowire with a C-shaped cross-section (for example, a cross-section perpendicular to the surface of the substrate). Therefore, such a device may be called a C-Channel FET (CCFET).
  • CFET C-Channel FET
  • these curved nanosheets or nanowires may be sequentially stacked in a lateral direction relative to the substrate (for example, a direction substantially parallel to the surface of the substrate).
  • the nanosheets or nanowires can be formed by epitaxial growth, and therefore can be a single piece, and can have a substantially uniform thickness.
  • the plurality of nanosheets or nanowires may include first nanosheets or nanowires and second nanosheets or nanowires respectively located on both sides of the channel part in the lateral direction, and the first nanosheets or nanowires.
  • the first nanosheet or nanowire and the second nanosheet or nanowire may have improved interface quality with the gate stack, and the third nanosheet or nanowire may have high carrier mobility.
  • first nanosheet or nanowire and the second nanosheet or nanowire may have high carrier mobility
  • the third nanosheet or nanowire may optimize the carrier distribution.
  • the third nanosheet or nanowire may confine the carriers in the first nanosheet or nanowire and/or the second nanosheet or nanowire.
  • the lowest energy level of the conduction band of the third nanosheet or nanowire may be higher than the lowest energy level of the conduction band of the first nanosheet or nanowire and/or the second nanosheet or nanowire;
  • the highest energy level of the valence band of the third nanosheet or nanowire may be lower than the highest energy level of the valence band of the first nanosheet or nanowire and/or the second nanosheet or nanowire.
  • the semiconductor device may further include source/drain portions respectively provided at the upper and lower ends of the channel portion.
  • the size of the source/drain portion in the lateral direction relative to the substrate may be larger than the size of the channel portion in the corresponding direction to ensure that the upper and lower ends of the channel portion are connected to the source/drain portion.
  • the source/drain may have a certain doping. For example, for a p-type device, the source/drain may have p-type doping; for an n-type device, the source/drain may have n-type doping.
  • the channel part may have a certain doping to adjust the threshold voltage of the device.
  • the semiconductor device may be a junctionless device, in which the channel portion and the source/drain portion may have the same conductivity type doping.
  • the semiconductor device may be a tunneling type device, in which the source/drain portions at both ends of the channel portion may have doping types opposite to each other.
  • the source/drain portion may be provided in the corresponding semiconductor layer.
  • the source/drain may be a doped region in the corresponding semiconductor layer.
  • the source/drain portion may be a part or all of the corresponding semiconductor layer.
  • the source/drain may be formed by diffusion doping.
  • the doping concentration interface may be substantially along the vertical direction relative to the substrate.
  • the channel part may include a single crystal semiconductor material.
  • the source/drain portions or the semiconductor layer on which they are formed may also include single crystal semiconductor materials. For example, they can all be formed by epitaxial growth.
  • the semiconductor device may further include a gate stack surrounding the outer periphery of the channel portion. Therefore, the semiconductor device according to the embodiment of the present disclosure may be a wrap gate device. According to an embodiment of the present disclosure, the gate stack may be self-aligned to the channel part. For example, at least a portion of the gate stack close to the channel portion may be substantially coplanar with the channel portion, for example, the portion of the gate stack and the upper surface and/or the lower surface of the channel portion are substantially coplanar with each other.
  • Such a semiconductor device can be manufactured as follows, for example.
  • a stack of a first material layer, a second material layer, and a third material layer may be provided on the substrate.
  • the first material layer may define the position of the lower source/drain portion
  • the second material layer may define the position of the gate stack
  • the third material layer may define the position of the upper source/drain portion.
  • the first material layer may be provided through a substrate such as the upper part of the substrate, and the second material layer and the third material layer may be sequentially formed on the first material layer by, for example, epitaxial growth.
  • the first material layer, the second material layer, and the third material layer may be sequentially formed on the substrate by, for example, epitaxial growth.
  • the first material layer and the third material layer may be doped in situ while being epitaxially grown to form source/drain parts therein.
  • the stack can be patterned into a ridge structure.
  • the ridge structure may include first and second sides opposite to each other, and third and fourth sides opposite to each other.
  • the ridge structure may have a quadrangular shape such as a rectangle or a square in plan view.
  • the channel part may be formed on a pair of opposite sidewalls (for example, the first side and the second side) of the ridge structure.
  • a space for forming the gate stack may be defined on the third side and the fourth side of the ridge structure.
  • the side walls of the second material layer may be recessed laterally with respect to the side walls of the first material layer and the third material layer on the third side and the fourth side of the ridge structure, thereby defining the first recessed portion.
  • the first recessed portion may have a curved surface that is recessed toward the inner side of the ridge structure.
  • the first position holding layer may be formed in the first recessed portion.
  • the sidewalls of the second material layer may be recessed laterally relative to the sidewalls of the first material layer and the third material layer on the first side and the second side of the ridge structure, thereby defining a second recessed portion to Define the space for the gate stack.
  • the second recessed portion may have a curved surface that is recessed toward the inner side of the ridge structure.
  • a channel part may be formed on the surface of the second recessed part.
  • at least the first channel layer (which can then be used as a channel portion) can be formed by performing epitaxial growth on the exposed surface of the ridge structure.
  • One device may be formed based on the channel layer on the sidewalls of the first side and the second side of the ridge structure, respectively. Thus, based on a single ridge structure, two devices facing each other can be formed.
  • the second position holding layer may be formed in the second recessed portion in which the channel layer is formed on the surface.
  • the exposed surface of the ridge structure may be etched back by a certain amount, for example, roughly the thickness of the first channel layer to be formed. This helps to ensure that the subsequently formed gate stack has substantially equal gate lengths on opposite sides of the channel portion.
  • the source/drain may be formed in the first material layer and the third material layer.
  • the source/drain may be formed by doping the first material layer and the third material layer (especially when they are not doped when they are formed). This doping can be achieved by a solid-phase dopant source layer.
  • An opening can be formed in the ridge structure to separate the active regions of the two devices.
  • the opening may also extend substantially along the side wall of the first side or the second side of the ridge structure, so that the ridge structure is divided into two parts on the first side and the second side, respectively.
  • the second material layer can be removed through the opening to expose the first channel layer and thus define the third recessed portion. If the design number of channel layers is not formed in the above process of forming at least the first channel layer, at least the second channel layer may be formed on the surface of the first channel layer exposed by the third recessed portion to form a total of Design number of channel layers. After that, a third position holding layer may be formed in the remaining space of the third recessed portion. Alternatively, if a designed number of channel layers have been formed in the above-mentioned process of forming at least the first channel layer, the third position holding layer may be directly formed in the third recessed portion.
  • the first position holding layer, the second position holding layer, and the third position holding layer surround the channel part.
  • the first position holding layer, the second position holding layer, and the third position holding layer may be replaced with a gate stack by a replacement gate process, thereby forming a gate stack surrounding the channel portion.
  • the thickness and gate length of the nanosheets or nanowires used as the channel portion are mainly determined by epitaxial growth, rather than by etching or photolithography, so it is possible to have a good channel size/thickness And gate length control.
  • the present disclosure can be presented in various forms, some examples of which will be described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this kind of etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.
  • 1 to 22 schematically illustrate some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided (the upper part of which may constitute the above-mentioned first material layer).
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is taken as an example for description.
  • a silicon wafer is provided as the substrate 1001.
  • a well region may be formed. If a p-type device is to be formed, the well region may be an n-type well; if an n-type device is to be formed, the well region may be a p-type well.
  • the well region may be formed, for example, by injecting corresponding conductivity type dopants (p-type dopants such as B or In, or n-type dopants such as As or P) into the substrate 1001 and then performing thermal annealing.
  • p-type dopants such as B or In, or n-type dopants such as As or P
  • the second material layer 1003 and the third material layer 1005 can be formed by, for example, epitaxial growth.
  • the second material layer 1003 may be used to define the position of the gate stack, and the thickness is, for example, about 20 nm-50 nm.
  • the third material layer 1005 may be used to define the position of the upper source/drain portion, and the thickness is, for example, about 20 nm-200 nm.
  • the substrate 1001 and adjacent layers among the above-mentioned layers formed thereon may have etching selectivity with respect to each other.
  • the second material layer 1003 may include SiGe (for example, the atomic percentage of Ge is about 10%-30%)
  • the third material layer 1005 may include Si.
  • spacer graphic transfer technology is used in the following composition.
  • a mandrel can be formed.
  • a layer 1011 for a core pattern can be formed on the third material layer 1005 by, for example, deposition.
  • the layer 1011 used for the core mold pattern may include amorphous silicon or polysilicon, with a thickness of about 50 nm-150 nm.
  • the etching stop layer 1009 can be formed first by, for example, deposition.
  • the etch stop layer 1009 may include oxide (for example, silicon oxide), with a thickness of about 1 nm-10 nm.
  • a hard mask layer 1013 can be formed by, for example, deposition.
  • the hard mask layer 1013 may include nitride (for example, silicon nitride) with a thickness of about 30 nm-100 nm.
  • the layer 1011 for the core mold pattern can be patterned into a core mold pattern.
  • a photoresist 1007 may be formed on the hard mask layer 1013 and patterned into strips extending in the first direction (the direction perpendicular to the paper surface in FIG. 3) by photolithography.
  • the photoresist 1007 can be used as an etching mask, and the hard mask layer 1013 and the layer 1011 for the core mold pattern can be selectively etched by, for example, reactive ion etching (RIE) to transfer the photoresist pattern to The hard mask layer 1013 and the layer 1011 used for the core mold pattern.
  • RIE reactive ion etching
  • the etching may stop at the etching stop layer 1009. After that, the photoresist 1007 can be removed.
  • partition walls may be formed on the side walls on opposite sides of the core mold pattern 1011 in the second direction (the horizontal direction in the paper in FIG. 4) that intersects with the first direction (for example, vertical). 1017.
  • a layer of nitride with a thickness of about 10nm-100nm can be deposited in a substantially conformal manner, and then the deposited nitride layer can be anisotropically etched such as RIE in the vertical direction (it can be stopped at the etching stop Layer 1009) to remove its lateral extension part and leave its vertical extension part, thereby obtaining a partition wall 1017.
  • the partition wall 1017 can then be used to define the location of the active area of the device.
  • the core mold pattern formed as described above and the side walls 1017 formed on the side walls thereof extend in the first direction. It is possible to define their range in the first direction, and thus the range of the active area of the device in the first direction.
  • a photoresist 1015 can be formed on the structure shown in FIG. 4, and patterned by photolithography to occupy a certain range in the first direction, for example, along with A strip extending in a second direction perpendicular to the first direction.
  • the photoresist 1015 can be used as an etching mask, and the underlying layers can be selectively etched sequentially by, for example, RIE.
  • the etching may be performed into the substrate 1001, particularly the well region therein, so as to form a groove in the substrate 1001. Isolation, such as shallow trench isolation (STI), can then be formed in the formed groove.
  • Isolation such as shallow trench isolation (STI)
  • STI shallow trench isolation
  • the sidewalls of the second material layer 1003 in the first direction are currently exposed to the outside.
  • a space for the gate stack may be left at both ends of the second material layer in the first direction.
  • the second material layer 1003 may be selectively etched so that the sidewalls in the first direction are relatively concave.
  • atomic layer etching ALE
  • the amount of etching may be about 5nm-20nm.
  • the etching selectivity of the second material layer 1003 relative to the substrate 1001 and the third material layer 1005 may exhibit different shapes.
  • FIG. 6(d) shows that the sidewall of the second material layer 1003 after etching is a C-shaped concave inward.
  • the present disclosure is not limited to this.
  • the sidewall of the second material layer 1003 may be close to vertical after etching.
  • the etching can be isotropic, especially when a larger etching amount is required.
  • a dielectric material may be filled to define the space of the gate stack. This filling can be done by deposition and then etch back.
  • a dielectric material such as SiC sufficient to fill the recesses can be deposited on the substrate, and then the deposited dielectric material can be etched back such as RIE. In this way, the dielectric material outside the range defined by the hard mask layer 1013 and the partition wall 1017 can be removed, and the dielectric material is left in the recess to form the first position holding layer 1019.
  • a protective layer 1021 may also be formed on the substrate 1001.
  • an oxide layer may be formed on the substrate 1001 by deposition, and the deposited oxide layer may be planarized, such as chemical mechanical polishing (CMP) (CMP may stop at the hard mask layer 1013) and then further return Etched to form a protective layer 1021.
  • CMP chemical mechanical polishing
  • the protective layer 1021 may be in the groove of the substrate 1001, and the top surface of the protective layer 1021 is lower than the top surface of the substrate 1001.
  • the exposed part of the etch stop layer 1009 in this example, also oxide
  • the operation of forming the protective layer 1021 may be performed before the operation of forming the first position holding layer 1019 (including recessing and filling).
  • the protective layer 1021 can protect the surface of the substrate 1001. For example, in this example, the range of the active area in the first direction is first defined. Subsequently, the range of the active area in the second direction will be defined. The protective layer 1021 can avoid affecting the surface of the substrate currently exposed to the outside in the groove (see FIG. 5(c)) when defining the range in the second direction. In addition, when different types of well regions are formed in the substrate 1001, the protective layer 1021 can protect the pn junction between the different types of well regions from being etched (for example, etch back when forming the first position maintaining layer 1019) destroy.
  • the hard mask layer 1013 and the partition wall 1017 can be used to pattern the third material layer 1005, the second material layer 1003 and the upper part of the substrate 1001 (first material layer) into a ridge structure (in fact , The range of the ridge structure in the first direction has been defined by the above processing).
  • the hard mask layer 1013 and the partition wall 1017 can be used as an etching mask, and each layer is selectively etched sequentially by, for example, RIE, to transfer the pattern to the lower layer.
  • the upper portion of the substrate 1001, the second material layer 1003, and the third material layer 1005 may form a ridge structure.
  • the etching may not affect the portions of the substrate 1001 on both sides of the ridge structure in the first direction.
  • the etching can enter the well region of the substrate 1001.
  • the degree of etching into the substrate 1001 may be substantially the same as or similar to the degree of etching into the substrate 1001 described above in conjunction with FIGS. 5(a) to 5(c).
  • a groove is formed in the substrate 1001.
  • a protective layer can also be formed in these grooves (see 1023 in FIG. 8).
  • the protective layer 1023 and the previous protective layer 1021 surround the outer circumference of the ridge structure together. In this way, similar processing conditions can be provided around the ridge structure, that is, grooves are formed in the substrate 1001, and protective layers 1021 and 1023 are formed in the grooves.
  • a space for the gate stack may be left at both ends of the second material layer in the second direction.
  • the second material layer 1003 may be selectively etched so that the sidewalls in the second direction are relatively concave (the space for the gate stack may be defined).
  • the amount of etching may be about 10 nm-40 nm.
  • the sidewall of the second material layer 1003 may exhibit a C-shape that is recessed toward the inside.
  • the etching can be isotropic, especially when a larger etching amount is required.
  • the C-shaped side wall of the second material layer 1003 has a larger curvature at the upper and lower ends, and a smaller curvature at the waist or the middle.
  • the first channel layer may be formed on the sidewall of the ridge structure so as to subsequently define the channel portion.
  • the ridge structure specifically , The exposed surfaces of the first material layer, the second material layer, and the third material layer
  • ALE can be used to control the etching depth.
  • the etching depth may be substantially equal to the thickness of the first channel layer to be subsequently grown, for example, about 5 nm-15 nm.
  • the first channel layer 1025 may be formed on the sidewall of the ridge structure by, for example, selective epitaxial growth. Due to the selective epitaxial growth, the first channel layer 1025 may not be formed on the surface of the first position maintaining layer 1019.
  • the first channel layer 1025 may then define a channel portion, with a thickness of, for example, about 3 nm-15 nm. According to an embodiment of the present disclosure, the thickness of the first channel layer 1025 (which is then used as a channel portion) can be determined by an epitaxial growth process, so the thickness of the channel portion can be better controlled.
  • the first channel layer 1025 may be doped in situ during epitaxial growth to adjust the threshold voltage of the device.
  • the sidewalls of the portions of the first channel layer 1025 on the sidewalls of the first material layer and the third material layer are shown to be substantially flush with the sidewalls of the partition wall 1017. This can be achieved by controlling the amount of etch-back and the thickness of the epitaxial growth to be substantially the same.
  • the present disclosure is not limited to this.
  • part of the sidewalls of the first channel layer 1025 on the sidewalls of the first material layer and the third material layer may be recessed relative to the sidewalls of the partition wall 1017, or may even protrude.
  • performing the above-mentioned etch back can etch the upper end and the lower end of the recessed portion upward and downward, respectively, so that after the first channel layer 1025 is grown, the height t1 of the recessed portion and the thickness t2 of the second material layer 1003 can be substantially the same. .
  • the gate stacks subsequently formed on the left and right sides of the first channel layer 1025 may have substantially equal gate lengths.
  • the present disclosure is not limited to this.
  • the gate length on the outside of the first channel layer 1025 can also be changed by adjusting the amount of etch-back, thereby changing the ratio of the gate lengths on both sides to optimize the difference in morphology on the left and right sides of the C-shaped channel portion. Impact on device performance.
  • the material of the first channel layer 1025 can be appropriately selected according to the performance requirements of the design on the device.
  • the first channel layer 1025 may include various semiconductor materials, such as Si, Ge, SiGe, InP, GaAs, InGaAs, and so on.
  • the first channel layer 1025 may include the same material as the first material layer and the third material layer, such as Si.
  • the first channel layer 1025 on opposite sides of the ridge structure in the second direction may have substantially the same characteristics (for example, material, size, doping characteristics, etc.), and may be arranged symmetrically to each other On opposite sides of the second material layer.
  • the present disclosure is not limited to this.
  • the first channel layer 1025 on the opposite sides of the ridge structure may have different characteristics, such as at least one of thickness, material, and doping characteristics. This can be achieved by shielding another device region when the first channel layer is grown in one device region.
  • a void is formed on the outer side of the corresponding portion of the first channel layer 1025 and the second material layer 1003. In this gap, a gate stack can then be formed.
  • a second position maintaining layer 1027 may be formed in the gap.
  • the second position retaining layer 1027 may be formed by deposition and then etched back, and may include a dielectric material such as SiC.
  • the first position maintaining layer 1019 and the second position maintaining layer 1027 include the same material, so that they can be removed together with the same etching recipe later. But the present disclosure is not limited to this, for example, they may include different materials.
  • source/drain doping can be performed.
  • a solid-phase dopant source layer 1029 may be formed on the structure shown in FIG. 11 by, for example, deposition.
  • the solid phase dopant source layer 1029 may be formed in a substantially conformal manner.
  • the solid phase dopant source layer 1029 may be an oxide containing a dopant, and the thickness is about 1 nm to 5 nm.
  • the dopant contained in the solid-phase dopant source layer 1029 can be used to dope the source/drain portion (and optionally, the exposed surface of the substrate 1001), so it can have the same source/drain portion as the desired formation. Type of conductivity.
  • the solid-phase dopant source layer 1029 may contain a p-type dopant such as B or In; for an n-type device, the solid-phase dopant source layer 1029 may contain an n-type dopant such as P or As.
  • the concentration of the dopant of the solid phase dopant source layer 1029 may be about 0.1% to 5%.
  • the protective layer 1021, 1023 may be selectively etched by, for example, RIE, to expose the surface of the substrate 1001. In this way, the exposed surface of the substrate 1001 can also be doped to form respective contact regions of the source/drain portions S/D at the lower ends of the two devices.
  • the dopants in the solid-phase dopant source layer 1029 can be driven into the first channel layer and the first material layer and the third material layer by annealing treatment to form source/drain S/D (and optional Ground, it can be driven into the exposed surface of the substrate 1001 to form the respective contact regions of the source/drain portions (S/D) at the lower ends of the two devices, as shown in FIG. 13. After that, the solid phase dopant source layer 1029 may be removed.
  • the dopant is derived from the solid-phase dopant source layer.
  • the driving degree of 1029 into the first material layer and the third material layer may be approximately the same. Therefore, the (doping concentration) interface of the source/drain portion S/D (between the inner part of the first material layer and the third material layer) can be approximately parallel to the surfaces of the first material layer and the third material layer, and also That is, they can be in the vertical direction and can be aligned with each other.
  • the first material layer is provided through the upper portion of the substrate 1001.
  • the present disclosure is not limited to this.
  • the first material layer may also be an epitaxial layer on the substrate 1001.
  • the first material layer and the third material layer can be doped in situ during the external delay, instead of using a solid phase dopant source layer for doping.
  • an isolation layer 1031 may be formed, as shown in FIG. 14(a).
  • the method of forming the isolation layer may be similar to the method of forming the protective layers 1021 and 1023 as described above, and will not be repeated here.
  • the overlap between the gate and the source/drain can be further reduced.
  • the source/drain portion S/D can be further recessed by selective etching, so that the source/drain portion S/D The overlap with the first position holding layer 1019 and the second position holding layer 1027 (which subsequently defines the position of the gate stack) is reduced.
  • the source/drain portion S/D is further recessed, the portion of the first channel layer 1025 on the sidewalls of the first material layer and the third material layer is removed, and the first material The layer and the third material layer are further recessed.
  • a dielectric 1031' such as oxynitride or oxide can be filled. Filling can be achieved by deposition (and planarization) and then etch back. During the etch back, a certain thickness of the dielectric 1031' is left on the surface of the substrate 1001 to form an isolation portion.
  • partition wall 1017 can be used to complete the definition of the active area.
  • the hard mask layer 1013 may be removed by selective etching such as RIE or planarization treatment such as CMP to expose the core pattern 1011.
  • the height of the partition wall 1017 which is also nitride in this example, may decrease.
  • the core pattern 1011 can be removed by selective etching such as wet etching using TMAH solution or dry etching using RIE. In this way, a pair of partition walls 1017 extending opposite to each other are left on the ridge structure (the height is reduced, and the top morphology may also be changed).
  • the partition wall 1017 can be used as an etching mask, and the etch stop layer 1009, the third material layer 1005, the second material layer 1003, and the upper part of the substrate 1001 can be selectively etched by, for example, RIE.
  • the etching can be performed into the well region of the substrate 1001. In this way, in the space surrounded by the isolation layer 1031, the third material layer 1005, the second material layer 1003, and the upper portion of the substrate 1001 form a pair of stacks corresponding to the partition walls 1017 to define the active area.
  • the formation of the stack for defining the active region is not limited to the partition wall pattern transfer technology, and can also be performed by photolithography using photoresist or the like.
  • the second material layer 1003 used to define the gate stack position includes a semiconductor material.
  • the second material layer 1003 may be replaced with a dielectric material to form a third position maintaining layer.
  • the first channel layer 1025, the substrate 1001, and the third material layer 1005 can be selectively etched .
  • the second material layer 1003 SiGe in this example
  • a third position maintaining layer 1033 may be formed in the void left under the partition wall 1017 due to the removal of the second material layer 1003.
  • the third position maintaining layer 1033 can be formed by a method of deposition and then etch back.
  • the third position maintaining layer 1033 may include the same material as the first position maintaining layer 1019 and the second position maintaining layer 1027 so as to be subsequently removed by the same etching recipe in the replacement gate process.
  • the first position holding layer 1019, the second position holding layer 1027, and the third position holding layer 1033 surround a part of the first channel layer 1025.
  • This portion of the first channel layer 1025 may serve as a channel portion.
  • the channel part is a C-shaped curved nanosheet (when the nanosheet is narrow, for example, when the vertical dimension in the paper in FIG. 16(b) is small, it can become a nanowire).
  • the thickness of the channel portion (in the case of nanowires, the thickness or the diameter) It is basically determined by the selective growth process of the first channel layer 1025. This has a huge advantage over a technique that only uses an etching method or a photolithography method to determine the thickness, because the epitaxial growth process has much better process control than the etching or photolithography.
  • the height of the isolation layer 1031 can be increased.
  • the isolation layer 1035 can be formed by deposition (and planarization) and then etch back.
  • the isolation layer 1035 may include an oxide, and thus is shown as one body with the previous isolation layer 1031.
  • the top surface of the isolation layer 1035 may be close to, for example, not lower (preferably, slightly higher than) the top surface of the first material layer (ie, the top surface of the substrate 1001) or the bottom surface of the second material layer (ie, the first position).
  • the bottom surface of the holding layer 1019, the second position holding layer 1027, and the third position holding layer 1033), and not higher than the top surface of the second material layer (ie, the first position holding layer 1019, the second position holding layer 1027, and the second material layer) The top surface of the three-position holding layer 1033) or the bottom surface of the third material layer.
  • the overlap between the gate and the first material layer and the third material layer in which the active/drain portion is formed
  • the overlap between the gate and the first material layer and the third material layer can be further reduced.
  • the exposed surfaces of the first material layer and the third material layer may be further recessed by selective etching.
  • the overlap between the first material layer and the third material layer and the third position maintaining layer 1033 (which subsequently defines the position of the gate stack) is reduced.
  • the isolation layer 1035' can be formed similarly.
  • the dielectric material of the isolation layer 1035 ′ will also fill the void formed by the recess of the third material layer under the partition wall 1017.
  • FIG. 17 there is shown a structure obtained by performing the process of reducing overlap described with reference to FIG. 17 in addition to the process of reducing overlap described with reference to FIG. 14(b).
  • the outer periphery of the source/drain portion S/D is surrounded by the dielectric material.
  • the present disclosure is not limited to this.
  • the processing process for reducing overlap described with reference to FIG. 14(b) and the processing process for reducing overlap described with reference to FIG. 17 may be performed alternatively, or both may be performed.
  • FIGS. 16(a) and 16(b) the situation shown in FIGS. 16(a) and 16(b) is still taken as an example for description.
  • a replacement gate process can be performed to form a gate stack.
  • the first position holding layer 1019, the second position holding layer 1027, and the third position holding layer 1033 can be removed by selective etching, and formed on the isolation layer 1035 Grid stack.
  • the gate dielectric layer 1037 may be formed in a substantially conformal manner by deposition, and the gate conductor layer 1039 may be formed on the gate dielectric layer 1037.
  • the gate conductor layer 1039 may fill the space between the active regions.
  • the gate conductor layer 1039 can be planarized, such as CMP, and the CMP can be stopped at the partition wall 1017.
  • the gate conductor layer 1039 can be etched back so that its top surface is lower than the original top surface of the first position maintaining layer 1019, the second position maintaining layer 1027, and the third position maintaining layer 1033 (or the top surface of the second material layer). Surface or the bottom surface of the third material layer) to reduce the capacitance between the source/drain portion and the gate stack.
  • the end of the formed gate stack is embedded in the space where the first position holding layer 1019, the second position holding layer 1027, and the third position holding layer 1033 were previously located, surrounding the channel part.
  • the gate dielectric layer 1037 may include a high-k gate dielectric such as HfO 2 , and the thickness is, for example, about 1 nm-5 nm.
  • an interface layer may also be formed, for example, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of about 0.3 nm-1.5 nm.
  • the gate conductor layer 1039 may include a work function adjusting metal such as TiN, TaN, TiAlC, etc. and a gate conductive metal such as W.
  • the respective gate stacks of the two devices are connected to each other as a single body.
  • the gate conductor layer 1039 can be disconnected between the two devices by, for example, photolithography, and at the same time, the landing pad of the gate contact portion can be patterned.
  • the photoresist 1041 can be formed and patterned to cover the area where the landing pad of the gate contact is to be formed, while exposing other areas. Then, as shown in FIGS. 20(a) to 20(c), the photoresist 1041 (and the partition wall 1017) can be used as a mask, and the gate conductor layer 1039 such as RIE can be selectively etched. The RIE can stop at the gate dielectric layer 1037. . After that, the photoresist 1041 may be removed.
  • the gate conductor layer 1039 is basically left and self-aligned under the partition wall 1017, except that a part of the partition wall 1017 (upper side in FIG. 20(a)) protrudes to serve as a landing pad.
  • the gate conductor layer 1039 is separated between the two opposing devices respectively located under the opposing partition wall 1017, so as to combine with the gate dielectric layer 1037 to define a gate stack for the two devices respectively.
  • the landing pads of the two devices are located on the same side of the partition wall 1017.
  • the present disclosure is not limited to this.
  • the landing pads of the two devices may be located on different sides of the partition wall 1017.
  • the dielectric layer 1043 can be formed on the substrate by, for example, deposition and then planarization. Then, a contact hole may be formed, and a conductive material such as metal may be filled in the contact hole to form a contact portion 1045.
  • the contact portion 1045 may include a contact portion that penetrates the partition wall 1017 and the etch stop layer 1009 to connect to the upper source/drain portion, and penetrates the dielectric layer 1043 and the isolation layer 1035 to connect to the contact portion of the lower source/drain portion, And the contact part that penetrates the dielectric layer 1043 and is connected to the landing pad of the gate conductor layer.
  • the contact parts to the contact areas of the source/drain parts of the respective lower ends of the two devices can be located on opposite sides of the active area (left and right sides in the figure). ).
  • the contact portion to the contact area of the lower source/drain portion and the contact portion to the landing pad of the gate conductor layer of the corresponding device may be on opposite sides of the active area of the corresponding device, as shown in FIG. 22 Shown.
  • FIG. 23(a) to FIG. 36 schematically show some stages in a process of manufacturing a semiconductor device according to another embodiment of the present disclosure.
  • the differences from the above-mentioned embodiment will be mainly described.
  • the processing described above with reference to FIGS. 1 to 8 may be performed to form the second material layer 2003 and the third material layer 2005, and an etch stop layer 2009, sidewall spacers 2017, etc. for assisting patterning on the substrate 2001.
  • a recess may be formed in the second material layer 2003, and a protective layer 2023 may be formed on the substrate 2001.
  • the channel layer can be formed similarly.
  • a plurality of channel layers stacked one after another may be formed.
  • a preliminary channel layer 2025 may be formed on the sidewall of the ridge structure by, for example, selective epitaxial growth. Due to the selective epitaxial growth, the preliminary channel layer 2025 can be formed only on the semiconductor surface.
  • the thickness of the preliminary channel layer 2025 may be approximately equal to the sum (L1+L2) of the thickness of the first channel layer (for example, the first thickness L1) and the second channel layer (for example, the second thickness L2) formed subsequently, For example, it is about 3nm-15nm.
  • the main purpose of selecting the thickness of the preliminary channel layer 2025 in this way is to make the gate lengths on the left and right sides of the subsequent C-shaped channel portion substantially equal, which will be further described below.
  • the material of the preliminary channel layer 2025 can be appropriately selected according to the performance requirements of the design on the device.
  • the preliminary channel layer 2025 may include various semiconductor materials, such as Si, Ge, SiGe, InP, GaAs, InGaAs, and the like.
  • the preliminary channel layer 2025 may include the same material as the first material layer and the third material layer, such as Si.
  • the first channel layer 2025-1 and the second channel layer 2025-2 can be sequentially formed on the sidewalls of the ridge structure by, for example, selective epitaxial growth.
  • the third channel layer 2025-3 The thickness of the first channel layer 2025-1 may be a first thickness L1, for example, about 3nm-5nm; the thickness of the second channel layer 2025-2 may be a second thickness L2, for example, about 1nm-3nm; the third channel The thickness of the layer 2025-3 may be approximately the same as the thickness of the first channel layer 2025-1, which is the first thickness L1, for example, about 3 nm-5 nm.
  • the gate lengths (for example, in the direction perpendicular to the surface of the substrate) of the gate stacks formed on the left and right sides of the C-shaped channel part to be kept substantially equal, before the channel layer is formed The ridge structure (specifically, the exposed surfaces of the first material layer, the second material layer, and the third material layer) may be etched back so that the outer peripheral side wall thereof is laterally recessed relative to the outer peripheral side wall of the partition wall 2017. To control the etching amount, ALE can be used.
  • the etching amount may be approximately the sum of the thicknesses of the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3 to be formed (2L1+L2), for example, about 4 nm -20nm.
  • the formed first channel layer 2025-1, second channel layer 2025-2, and third channel layer 2025-3 may be (at least partially) blocked by the partition wall 2017 from above.
  • the sidewalls of the part of the outermost third channel layer 2025-3 on the sidewalls of the first material layer and the third material layer are shown as substantially similar to the sidewalls of the partition wall 2017. Flush. This can be achieved by controlling the amount of etch-back and the total thickness of epitaxial growth to be substantially the same.
  • the present disclosure is not limited to this.
  • the part of the sidewall of the outermost third channel layer 2025-3 on the sidewalls of the first material layer and the third material layer may be recessed relative to the sidewall of the partition wall 2017, or may even protrude.
  • the upper end and the lower end of the recessed portion can be etched upward and downward, respectively, so that the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025 are grown.
  • the height t1 of the recessed portion and the thickness t2 of the second material layer 2003 may be substantially the same.
  • the gate stacks subsequently formed on the left and right sides of the channel portion formed by the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3 may have substantially equal gate lengths. .
  • the present disclosure is not limited to this.
  • the gate length outside the channel portion can also be changed by adjusting the amount of etchback, thereby changing the ratio of the gate lengths on both sides to optimize the device performance due to the different topography on the left and right sides of the C-shaped channel portion. Impact.
  • each channel layer (which is subsequently used as a channel portion) can be determined by an epitaxial growth process, so the thickness of the channel portion can be better controlled.
  • the thickness of each channel layer formed by epitaxial growth may be substantially uniform.
  • Each channel layer can be doped in situ during epitaxial growth to adjust the threshold voltage of the device.
  • the materials of the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3 can be appropriately selected.
  • the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3 may each include various semiconductor materials, such as Si, Ge, SiGe, InP, GaAs, InGaAs, and the like.
  • At least some of the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3 may have different characteristics to optimize device performance.
  • the second channel layer 2025-2 may include (relative to the first channel layer 2025-1 and the third channel layer 2025-3) a material with high carrier mobility, such as SiGe (for example, Ge atomic percentage It is about 30%-100%, and becomes Ge when the Ge atomic percentage is 100%, so as to improve the current capability of the device.
  • SiGe for example, Ge atomic percentage It is about 30%-100%, and becomes Ge when the Ge atomic percentage is 100%, so as to improve the current capability of the device.
  • the quality of the interface between SiGe and the subsequently formed gate dielectric layer may be poor (for example, the interface state charge density is large, the surface roughness causes a large scattering of carriers, or the channel resistance is large, etc.).
  • the first channel layer 2025-1 and the third channel layer 2025-3 may include a material with good interface quality with the gate dielectric layer, such as Si.
  • the first channel layer 2025-1 and the third channel layer 2025-3 may include (relative to the second channel layer 2025-2) a material with high carrier mobility, and the second channel layer 2025 -2 may include materials capable of optimizing carrier distribution.
  • the second channel layer 2025-2 can confine carriers in the first channel layer 2025-1 and/or the third channel layer 2025-3, so as to be closer to the gate dielectric layer, which is beneficial to improve Short channel effect and reduce leakage current.
  • the lowest energy level of the conduction band of the second channel layer 2025-2 may be higher than the lowest energy level of the conduction band of the first channel layer 2025-1 and/or the third channel layer 2025-3.
  • the highest energy level of the valence band of the second channel layer 2025-2 may be lower than the highest energy level of the valence band of the first channel layer 2025-1 and/or the third channel layer 2025-3 class.
  • the channel layers on opposite sides of the ridge structure in the second direction may have substantially the same characteristics (for example, material, size, doping characteristics, etc.). ), and can be symmetrically arranged on opposite sides of the second material layer.
  • the present disclosure is not limited to this.
  • the channel layers on opposite sides of the ridge structure may have different characteristics, such as at least one of thickness, material, and doping characteristics.
  • FIG. 23(a) is mainly used as an example for description.
  • a second position maintaining layer 2027 may be formed.
  • the second position holding layer 2027 may include the same as the previously formed first position holding layer (see 2019 in FIG. 30(b), for details, please refer to the description of the first position holding layer 1019 in the above embodiment). Materials such as SiC, so that they can be removed together with the same etching recipe later. But the present disclosure is not limited to this, for example, they may include different materials.
  • source/drain doping can be performed.
  • a solid phase dopant source layer 2029 can be formed on the structure shown in FIG. 24 by, for example, deposition.
  • the solid phase dopant source layer 2029 may be formed in a substantially conformal manner.
  • the protective layer existing on the surface of the substrate 2001 may be selectively etched by, for example, RIE (for example, see FIGS. 23(a) and 23(b)). 2023) in order to expose the surface of the substrate 2001.
  • the exposed surface of the substrate 2001 can also be doped to form respective contact regions of the source/drain portions S/D at the lower ends of the two devices.
  • the dopants in the solid-phase dopant source layer 2029 can be driven into the preliminary channel layer 2025 and the first material layer and the third material layer by annealing treatment to form source/drain S/D (and optional Ground, it can be driven into the exposed surface of the substrate 2001 to form the respective contact regions of the source/drain portions (S/D) at the lower ends of the two devices, as shown in FIG. 26. After that, the solid phase dopant source layer 2029 may be removed.
  • the dopant is derived from the solid-phase dopant source layer.
  • the degree of drive 2029 into the first material layer and the third material layer may be approximately the same. Therefore, the (doping concentration) interface of the source/drain portion S/D (between the inner part of the first material layer and the third material layer) can be approximately parallel to the surfaces of the first material layer and the third material layer, and also That is, they can be in the vertical direction and can be aligned with each other.
  • the first material layer is provided through the upper part of the substrate 2001.
  • the present disclosure is not limited to this.
  • the first material layer may also be an epitaxial layer on the substrate 2001.
  • the first material layer and the third material layer can be doped in situ with an external delay, instead of using a solid-phase dopant source layer for doping.
  • an isolation layer 2031 may be formed, as shown in FIG. 27(a).
  • the overlap between the gate and the source/drain can be further reduced.
  • the source/drain portion S/D can be further recessed by selective etching, so that the source/drain portion S/D The overlap with the first position holding layer and the second position holding layer 2027 (which then defines the position of the gate stack) is reduced.
  • the source/drain portion S/D is further recessed, the part of the preliminary channel layer 2025 on the sidewalls of the first material layer and the third material layer is removed, and the first material layer can be made And the third material layer is further recessed.
  • a dielectric 2031 ′ such as oxynitride or oxide may be filled. Filling can be achieved by deposition (and planarization) and then etch back. During the etch back, a certain thickness of the dielectric 2031' is left on the surface of the substrate 2001 to form an isolation portion.
  • partition wall 2017 can be used to complete the definition of the active area.
  • a protective layer may be formed on the isolation layer 2031 to cover the preliminary isolation layer. 2025.
  • a dielectric material such as an oxide can be further formed on the isolation layer 2031 by, for example, deposition, and the deposited dielectric material can be planarized, such as CMP (which can be stopped at the hard mask layer).
  • CMP which can be stopped at the hard mask layer.
  • the formed dielectric material is shown as 2032 together with the previous isolation layer 2031 (both oxide in this example).
  • the partition wall 2017 can be used as an etching mask, through selective etching such as RIE (the etching can be carried out into the well region of the substrate 2001), in the space surrounded by the isolation layer (protective layer) 2032, the third material
  • RIE reactive ion etching
  • the upper part of the layer 2005, the second material layer 2003 and the substrate 2001 is patterned as a pair of stacks corresponding to the partition wall 2017 to define the active area. Due to the existence of the isolation layer (protective layer) 2032, the preliminary channel layer 2025 (in this example, includes Si like the third material layer 2005 and the substrate 2001) can be protected from etching.
  • an isolation layer 2032a (for example, oxide) can be formed by forming an isolation layer as described above, as shown in FIG. 29.
  • the isolation layer 2032a can be etched back so that its top surface is lower than the top surface of the second material layer 2003, thereby exposing (at least part of) the sidewalls of the second material layer 2003 for subsequent removal.
  • the top surface of the etched back isolation layer 2032a is close to (for example, slightly lower than) the bottom surface of the second material layer 2003 to fully expose the sidewalls of the second material layer 2003.
  • the formation of the isolation layer 2032a between the stacks can also be combined with the subsequent process of forming the isolation layer 2035.
  • another channel layer may be continuously grown based on the preliminary channel layer 2025.
  • the second material layer 2003 may be removed to expose the preliminary channel layer 2025.
  • the substrate 2001, and the third material layer 2005 are Si
  • the second material layer 2003 in the SiGe in this example.
  • the thickness of the preliminary channel layer 2025 in the form of nanosheets is mainly determined by the epitaxial growth process.
  • the preliminary channel layer 2025 is formed by (isotropically) selective etching of the second material layer 2003 and then epitaxial growth, and may have a C shape.
  • the method of the present disclosure has advantages in thickness control of the preliminary channel layer 2025 because the epitaxial growth process has better process control than etching or photolithography.
  • the exposed surfaces of the layer and the third material layer are etched back.
  • the preliminary channel layer 2025 after the etch back forms the first channel layer 2025-1.
  • ALE can be used.
  • the amount of etch back may be approximately the second thickness L2.
  • the thickness of the first channel layer 2025-1 may be approximately the first thickness L1.
  • the second channel layer 2025-2 and the third channel layer 2025-3 may be sequentially formed by, for example, selective epitaxial growth.
  • the thickness of the second channel layer 2025-2 may be substantially the second thickness L2, and the thickness of the third channel layer 2025-3 may be substantially the same as the thickness of the first channel layer 2025-1, which is substantially the first thickness L1.
  • the materials of the first channel layer 2025-1, the second channel layer 2025-2 and the third channel layer 2025-3 please refer to the above description in conjunction with FIG. 23(b).
  • the etching amount is selected to be the second thickness L2 in order to ensure that the two sides of the C-shaped channel portion formed subsequently can have substantially the same gate length.
  • the gates on both sides of the C-shaped channel portion can be adjusted by adjusting the amount of etch-back (or etch-back the ridge structure before the epitaxial growth process described in conjunction with FIG. 23(a), and control the amount of etch-back). long.
  • the use of an epitaxial growth process has advantages over etching or photolithography in determining the thickness.
  • the first material layer and the third material layer are also etched during the etch back process, which may cause discontinuity between the source/drain portion S/D and the channel portion. For this reason, annealing treatment may be performed to drive dopants into the newly grown active layer, so as to form source/drain S/D and extension region doping distributions.
  • a third position maintaining layer 2033 may be formed in the void left under the partition wall 2017 due to the removal of the second material layer 2003.
  • the third position holding layer 2033 may include the same material such as SiC as the first position holding layer 2019 and the second position holding layer 2027 so as to be removed by the same etching recipe in the replacement gate process.
  • the first position holding layer 2019, the second position holding layer 2027, and the third position holding layer 2033 surround the first channel layer 2025-1, the second Part of the channel layer 2025-2 and the third channel layer 2025-3.
  • the portions of the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3 may serve as a channel portion.
  • the channel part is a C-shaped curved nanosheet (when the nanosheet is narrow, for example, when the vertical dimension on the paper in FIG. 30(b) is small, it can become a nanowire).
  • the thickness of the channel portion (in the case of nanowires, the thickness or the diameter) is basically determined by the selective growth process of each channel layer. This has a huge advantage over a technique that only uses an etching method or a photolithography method to determine the thickness, because the epitaxial growth process has much better process control than the etching or photolithography.
  • the overlap between the gate and the first material layer and the third material layer in which the active/drain portion is formed
  • the exposed surfaces of the first material layer and the third material layer may be further recessed by selective etching.
  • the overlap between the first material layer and the third material layer and the third position maintaining layer 2033 (which subsequently defines the position of the gate stack) is reduced.
  • the isolation layer 2032' can be formed similarly.
  • FIG. 31 a structure obtained by performing the process of reducing the overlap described with reference to FIG. 31 in addition to the process of reducing the overlap described with reference to FIG. 27(b) is shown.
  • the outer periphery of the source/drain portion S/D is surrounded by the dielectric material.
  • the present disclosure is not limited to this.
  • the process of reducing overlap described with reference to FIG. 27(b) and the process of reducing overlap described with reference to FIG. 31 may be performed alternatively, or both may be performed.
  • FIGS. 30(a) and 30(b) the situation shown in FIGS. 30(a) and 30(b) is still taken as an example for description.
  • a replacement gate process can be performed to form a gate stack.
  • the height of the isolation layer 2032 can be reduced to (at least partially) expose the first position maintaining layer 2019 and the second position maintaining layer 2027 in order to They are removed.
  • a dielectric such as an oxide may be deposited on the structure shown in FIGS. 30(a) and 30(b), and the deposited dielectric may be planarized as CMP (can be stopped at the partition wall 2017), and etch back the planarized dielectric, such as RIE, to obtain an isolation layer 2035.
  • the top surface of the isolation layer 2035 may be close to, for example, not lower (preferably, slightly higher than) the top surface of the first material layer (that is, the top surface of the substrate 2001) or the bottom surface of the second material layer (that is, the first position).
  • the bottom surface of the holding layer 2019, the second position holding layer 2027, and the third position holding layer 2033), and not higher than the top surface of the second material layer (ie, the first position holding layer 2019, the second position holding layer 2027, and the second material layer) The top surface of the three-position holding layer 2033) or the bottom surface of the third material layer.
  • the first position holding layer 2019, the second position holding layer 2027, and the third position holding layer 2033 can be removed by selective etching, and a gate stack can be formed on the isolation layer 2035.
  • the gate dielectric layer 2037 may be formed in a substantially conformal manner by deposition, and the gate conductor layer 2039 may be formed on the gate dielectric layer 2037.
  • the gate conductor layer 2039 may fill the space between the active regions.
  • the gate conductor layer 2039 may be planarized, such as CMP, and the CMP may be stopped at the partition wall 2017.
  • the gate conductor layer 2039 may be etched back so that its top surface is lower than the original top surface of the first position maintaining layer 2019, the second position maintaining layer 2027, and the third position maintaining layer 2033 (or the top surface of the second material layer). Surface or the bottom surface of the third material layer) to reduce the capacitance between the source/drain portion and the gate stack.
  • the end of the formed gate stack is embedded in the space where the first position holding layer 2019, the second position holding layer 2027, and the third position holding layer 2033 were previously located, surrounding the channel part.
  • gate dielectric layer 2037 and the gate conductor layer 2039 please refer to the above description of the gate dielectric layer 1037 and the gate conductor layer 1039.
  • the shape of the gate conductor layer 2039 can be adjusted according to the device design.
  • a photoresist 2041 can be formed and patterned to cover the area where the landing pad of the gate contact is to be formed, while exposing other areas. Then, as shown in FIGS. 34(a) to 34(c), the photoresist 2041 (and the partition wall 2017) can be used as a mask, and the gate conductor layer 2039 such as RIE can be selectively etched. The RIE can stop at the gate dielectric layer 2037. . After that, the photoresist 2041 may be removed.
  • the gate conductor layer 2039 is basically left and self-aligned below the partition wall 2017, except for a part protruding on one side of the partition wall 2017 (upper side in FIG. 34(a)) to serve as a landing pad.
  • the gate conductor layer 2039 is separated between the two opposing devices respectively located under the opposing partition wall 2017, so as to combine with the gate dielectric layer 2037 to define a gate stack for the two devices respectively.
  • the landing pads of the two devices are located on the same side of the partition wall 2017.
  • the present disclosure is not limited to this.
  • the landing pads of the two devices may be located on different sides of the partition wall 2017.
  • the dielectric layer 2043 may be formed on the substrate by, for example, deposition and then planarization. Then, a contact hole may be formed, and a conductive material such as metal may be filled in the contact hole to form a contact portion 2045.
  • the contact portion 2045 may include a contact portion that penetrates the partition wall 2017 and an etch stop layer (see 1009 in the above embodiment) connected to the upper source/drain portion, and penetrates the dielectric layer 2043 and the isolation layer 2035 to connect to the lower source/drain.
  • the contact part of the contact area of the part, and the contact part of the landing pad which penetrates the dielectric layer 2043 and is connected to the gate conductor layer.
  • the contact parts to the contact areas of the source/drain parts of the respective lower ends of the two devices can be located on opposite sides of the active area (left and right sides in the figure). ).
  • the contact part to the contact area of the lower source/drain part and the contact part to the landing pad of the gate conductor layer of the corresponding device may be on opposite sides of the active area of the corresponding device, as shown in FIG. 36 Shown.
  • the first position holding layer 2019, the second position holding layer 2027 and the third position holding layer 2033 include the same material such as SiC, and thus are removed together in the replacement gate process.
  • the first position holding layer 2019 may include a different material from the second position holding layer 2027 and the third position holding layer 2033, such as oxynitride.
  • the first position holding layer 2019 may be removed first, thereby exposing the first channel layer 2025-1, the second channel layer 2025-2, and the third channel layer 2025-3. The end in the first direction.
  • the fourth channel layer 2025-4 can be formed on these exposed end portions by, for example, selective epitaxial growth, as shown in FIG. 37.
  • the fourth channel layer 2025-4 may connect the ends of the first channel layer 2025-1 and the third channel layer 2025-3 (and thus may also be referred to as a connecting portion).
  • the first channel layer 2025-1 and the third channel layer 2025-3 together with the fourth channel layer 2025-4 may surround the second channel layer 2025-2.
  • the fourth channel layer 2025-4 may include the same material as the first channel layer 2025-1 and the third channel layer 2025-3.
  • the fourth channel layer 2025-4 may have the same thickness, for example, L1, as the first channel layer 2025-1 and the third channel layer 2025-3.
  • the thickness of the fourth channel layer 2025-4 may be different from that of the first channel layer 2025-1 and the third channel layer 2025-3. thickness of.
  • a replacement gate process can be performed.
  • FIG. 38 shows the gate stack and the channel portion in this case.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, it is possible to form an integrated circuit (IC) based on such a semiconductor device, and thereby construct an electronic device. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device.
  • the electronic device may also include components such as a display screen matched with an integrated circuit and a wireless transceiver matched with an integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and so on.
  • a manufacturing method of a system on chip is also provided.
  • the method may include the method described above.
  • a variety of devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种C形沟道部半导体器件及其制造方法及包括这种半导体器件的电子设备。半导体器件可以包括：衬底（1001）上的沟道部，沟道部包括截面呈C形的弯曲纳米片或纳米线；相对于衬底（1001）分别处于沟道部的上下两端的源/漏部；以及围绕沟道部的外周的栅堆叠。

Description

C形沟道部半导体器件及其制造方法及包括其的电子设备
相关申请的引用
本申请要求于2020年1月21日递交的题为“C形沟道部半导体器件及其制造方法及包括其的电子设备”的中国专利申请202010072920.X、于2020年1月21日递交的题为“C形沟道部半导体器件及其制造方法及包括其的电子设备”的中国专利申请202010073094.0、以及于2020年5月22日递交的题为“C形沟道部半导体器件及其制造方法及包括其的电子设备”的中国专利申请202010445827.9的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有C形纳米片或纳米线沟道部的半导体器件及其制造方法及包括这种半导体器件的电子设备。
背景技术
随着半导体器件的不断小型化，提出了各种结构的器件例如鳍式场效应晶体管(FinFET)、多桥沟道场效应晶体管(MBCFET)等。但是，这些器件在增加集成密度和增强器件性能方面由于器件结构的限制而改进的空间仍然不能满足要求。
另外，由于光刻和刻蚀等工艺波动，竖直纳米片或纳米线器件如金属氧化物半导体场效应晶体管(MOSFET)难以控制纳米片或纳米线的厚度或直径。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有C形纳米片或纳米线沟道部的半导体器件及其制造方法及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底上的沟道部，沟道部包括截面呈C形的弯曲纳米片或纳米线；相对于衬底分别处于沟道部的上下两端的源/漏部；以及围绕沟道部的外周的栅堆叠。根据实施例，沟道部可以包括在相对于衬底的横向方向上依次叠置且各自的截面呈C形的多个 弯曲纳米片或纳米线。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底上设置第一材料层、第二材料层和第三材料层的堆叠；将所述堆叠构图为脊状结构，所述脊状结构包括彼此相对的第一侧和第二侧以及彼此相对的第三侧和第四侧；在第三侧和第四侧，使第二材料层的侧壁相对于第一材料层和第三材料层的侧壁横向凹入，从而限定第一凹入部；在第一凹入部中形成第一位置保持层；在第一侧和第二侧，使第二材料层的侧壁相对于第一材料层和第三材料层的侧壁横向凹入，从而限定第二凹入部；在第二材料层被第二凹入部露出的表面上至少形成第一沟道层；在第二凹入部的剩余空间中形成第二位置保持层；在第一材料层和第三材料层中形成源/漏部；在所述脊状结构中形成条形开口，从而将所述脊状结构分为分别处于第一侧和第二侧的两部分；通过开口，去除第二材料层以露出第一沟道层，从而限定第三凹入部；在第三凹入部中形成第三位置保持层；在衬底上形成隔离层，隔离层的顶面不低于第一材料层的顶面且不高于第二材料层的底面；去除第一位置保持层、第二位置保持层和第三位置保持层；以及在隔离层上围绕沟道层形成栅堆叠，所述栅堆叠具有嵌入到由于第一位置保持层、第二位置保持层和第三位置保持层的去除而留下的空间中的部分。根据实施例，可以形成单个或多个沟道层。例如，可以在第二材料层被第二凹入部露出的表面上仅形成单个沟道层即第一沟道层。在形成多个沟道层的情况下，可以在第二材料层被第二凹入部露出的表面上形成多个沟道层，或者可以在第二材料层被第二凹入部露出的表面上形成一个或多个沟道层且在所形成的沟道层被第三凹入部露出的表面上形成另外的沟道层。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体器件。
根据本公开的实施例，提出了一种新型结构的半导体器件，可以具有高性能和高密度的优点。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至22示意性示出了根据本公开实施例的制造半导体器件的流程中的 一些阶段；
图23(a)至图36示意性示出了根据本公开另一实施例的制造半导体器件的流程中的一些阶段；以及
图37和38示意性示出了根据本公开另一实施例的制造半导体器件的流程中的一些阶段，其中：
图5(a)、6(a)、18(a)、19、20(a)、21(a)、22、32(a)、33、34(a)、35(a)、36是俯视图；
图1至4、5(b)、6(b)、7至13、14(a)、14(b)、15、16(a)、17、18(b)、20(b)、21(b)、23(a)、23(b)、24、25、26、27(a)、27(b)、28、29、30(a)、31、32(b)、34(b)、35(b)是沿AA′线的截面图；
图6(c)是沿BB′线的截面图；
图5(c)、6(d)是沿CC′线的截面图；
图16(b)、18(c)、20(c)、30(b)、32(c)、34(c)、37、38是沿图16(a)中的DD′线截取的剖面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时， 该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种竖直型半导体器件，具有在衬底上竖直(例如，沿大致垂直于衬底表面的方向)设置的有源区。沟道部可以是截面(例如，垂直于衬底表面的截面)呈C形的弯曲纳米片或纳米线，因此这种器件可以称作C沟道场效应晶体管(C-Channel FET，即CCFET)。沟道部中可以有一个或多个弯曲纳米片或纳米线。在多个弯曲纳米片或纳米线的情况下，这些弯曲纳米片或纳米线可以在相对于衬底的横向方向(例如，大致平行于衬底表面的方向)上依次叠置。如下所述，纳米片或纳米线可以通过外延生长形成，因此可以是一体的单片，且可以具有实质上均匀的厚度。
在多个弯曲纳米片或纳米线的情况下，这些纳米片或纳米线中的至少一些可以具有不同的特性，以优化器件性能。例如，多个纳米片或纳米线可以包括分别处于沟道部在所述横向方向上的两侧的第一纳米片或纳米线和第二纳米片或纳米线，以及位于第一纳米片或纳米线与第二纳米片或纳米线之间的第三纳米片或纳米线。第一纳米片或纳米线和第二纳米片或纳米线可以与栅堆叠具有改进界面质量，而第三纳米片或纳米线可以具有高载流子迁移率。另外或者备选地，第一纳米片或纳米线和第二纳米片或纳米线可以具有高载流子迁移率，而第三纳米片或纳米线可以优化载流子分布。另外或者备选地，第三纳米片或纳米线可以将载流子限制在第一纳米片或纳米线和/或第二纳米片或纳米线中。例如，对于n型器件，第三纳米片或纳米线的导带的最低能级可以高于第一纳米片或纳米线和/或第二纳米片或纳米线的导带的最低能级；对于p型器件，第三纳米片或纳米线的价带的最高能级可以低于第一纳米片或纳米线和/或第二纳米片或纳米线的价带的最高能级。
该半导体器件还可以包括分别设置在沟道部上下两端的源/漏部。源/漏部在相对于衬底的横向方向上的尺寸可以大于沟道部在相应方向上的尺寸，以确保沟道部的上下两端与源/漏部连接。源/漏部可以具有一定的掺杂。例如，对于p型器件，源/漏部可以具有p型掺杂；对于n型器件，源/漏部可以具有n型掺杂。沟道部可以具有一定的掺杂，以调整器件的阈值电压。或者，该半导体器件可以是无结器件，其中沟道部与源/漏部可以具有相同导电类型的掺杂。或者，该半导体器件可以是隧穿型器件，其中沟道部两端的源/漏部可以具有 彼此相反的掺杂类型。
源/漏部可以设置在相应的半导体层中。例如，源/漏部可以是相应半导体层中的掺杂区。源/漏部可以是相应半导体层的一部分或者全部。在源/漏部是相应半导体层的一部分的情况下，源/漏部与相应半导体层中的其余部分之间可以存在掺杂浓度界面。如下所述，源/漏部可以通过扩散掺杂形成。这种情况下，掺杂浓度界面可以大致沿着相对于衬底的竖直方向。
沟道部可以包括单晶半导体材料。当然，源/漏部或者它们所形成于的半导体层也可以包括单晶半导体材料。例如，它们都可以通过外延生长来形成。
该半导体器件还可以包括围绕沟道部外周的栅堆叠。因此，根据本公开实施例的半导体器件可以是围栅器件。根据本公开的实施例，栅堆叠可以自对准于沟道部。例如，栅堆叠的至少靠近沟道部一侧的部分可以与沟道部实质上共面，例如栅堆叠的所述部分与沟道部的上表面和/或下表面彼此实质上共面。
这种半导体器件例如可以如下制造。
根据实施例，可以在衬底上设置第一材料层、第二材料层和第三材料层的堆叠。第一材料层可以限定下端源/漏部的位置，第二材料层可以限定栅堆叠的位置，第三材料层可以限定上端源/漏部的位置。可以通过衬底例如衬底的上部来提供第一材料层，并可以通过例如外延生长来在第一材料层上依次形成第二材料层和第三材料层。或者，可以在衬底上通过例如外延生长，依次形成第一材料层、第二材料层和第三材料层。第一材料层和第三材料层可以在外延生长同时原位掺杂，以在其中形成源/漏部。
可以将该堆叠构图为脊状结构。脊状结构可以包括彼此相对的第一侧和第二侧以及彼此相对的第三侧和第四侧。例如，脊状结构在平面图中可以呈四边形如矩形或方形。可以在脊状结构的一对相对侧壁(例如，第一侧和第二侧)上形成沟道部。
为了随后形成围绕沟道部的栅堆叠，可以在脊状结构的第三侧和第四侧限定用于形成栅堆叠的空间。例如，可以在脊状结构的第三侧和第四侧使第二材料层的侧壁相对于第一材料层和第三材料层的侧壁横向凹入，从而限定第一凹入部。第一凹入部可以具有向脊状结构的内侧凹入的弯曲表面。可以在第一凹入部中形成第一位置保持层。
同样地，可以在脊状结构的第一侧和第二侧使第二材料层的侧壁相对于第一材料层和第三材料层的侧壁横向凹入，从而限定第二凹入部，以限定用于栅堆叠的空间。第二凹入部可以具有向脊状结构的内侧凹入的弯曲表面。在第二凹入部的表面上可以形成沟道部。例如，可以通过在脊状结构的暴露表面上进行外延生长，来至少形成第一沟道层(随后可以用作沟道部)。可以基于脊状结构的第一侧和第二侧的侧壁上的沟道层，分别形成一个器件。于是，基于单个脊状结构，可以形成彼此相对的两个器件。可以在表面上形成有沟道层的第二凹入部中形成第二位置保持层。
在限定第二凹入部之后且在形成第一沟道层之前，还可以将脊状结构的外露表面回蚀一定的量，例如大致为将要形成的第一沟道层的厚度。这有助于确保随后形成的栅堆叠在沟道部的相对两侧具有基本相等的栅长。
可以在第一材料层和第三材料层中形成源/漏部。例如，可以通过掺杂第一材料层和第三材料层(特别是它们在形成时并未掺杂的情况下)来形成源/漏部。这种掺杂可以通过固相掺杂剂源层来实现。
可以在脊状结构中形成开口，以分离两个器件的有源区。开口也可以大致沿脊状结构的第一侧或第二侧的侧壁延伸，从而使脊状结构分为分别处于第一侧和第二侧的两部分。
可以通过该开口，去除第二材料层，以露出第一沟道层，并因此限定了第三凹入部。如果在上述至少形成第一沟道层的处理中未形成设计数量的沟道层，则可以在第一沟道层被第三凹入部露出的表面上至少形成第二沟道层，以总共形成设计数量的沟道层。之后，可以在第三凹入部的剩余空间中形成第三位置保持层。或者，在上述至少形成第一沟道层的处理中已形成设计数量的沟道层，则可以在第三凹入部中直接形成第三位置保持层。
当前，第一位置保持层、第二位置保持层和第三位置保持层围绕沟道部。可以通过替代栅工艺，将第一位置保持层、第二位置保持层和第三位置保持层替换为栅堆叠，从而形成围绕沟道部的栅堆叠。
根据本公开的实施例，用作沟道部的纳米片或纳米线的厚度以及栅长主要由外延生长确定，而不是通过刻蚀或光刻来确定，因此可以具有良好的沟道尺寸/厚度和栅长控制。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至22示意性示出了根据本公开实施例的制造半导体器件的流程中的一些阶段。
如图1所示，提供衬底1001(其上部可以构成上述的第一材料层)。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。
在衬底1001中，可以形成阱区。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。阱区例如可以通过向衬底1001中注入相应导电类型掺杂剂(p型掺杂剂如B或In，或n型掺杂剂如As或P)且随后进行热退火来形成。本领域存在多种方式来设置这种阱区，在此不再赘述。
在衬底1001上，可以通过例如外延生长，形成第二材料层1003和第三材料层1005。第二材料层1003可以用来限定栅堆叠的位置，厚度例如为约20nm-50nm。第三材料层1005可以用来限定上端源/漏部的位置，厚度例如为约20nm-200nm。
衬底1001以及之上形成的上述各层中相邻的层相对于彼此可以具有刻蚀选择性。例如，在衬底1001为硅晶片的情况下，第二材料层1003可以包括SiGe(例如，Ge原子百分比为约10％-30％)，第三材料层1005可以包括Si。
根据实施例，在以下构图中使用了隔墙(spacer)图形转移技术。为形成隔墙，可以形成芯模图案(mandrel)。例如，如图2所示，可以在第三材料层1005上，通过例如淀积，形成用于芯模图案的层1011。例如，用于芯模图案 的层1011可以包括非晶硅或多晶硅，厚度为约50nm-150nm。另外，为了更好的刻蚀控制，可以通过例如淀积，先形成刻蚀停止层1009。例如，刻蚀停止层1009可以包括氧化物(例如，氧化硅)，厚度为约1nm-10nm。
在用于芯模图案的层1011上，可以通过例如淀积，形成硬掩模层1013。例如，硬掩模层1013可以包括氮化物(例如，氮化硅)，厚度为约30nm-100nm。
可以将用于芯模图案的层1011构图为芯模图案。
例如，如图3所示，可以在硬掩模层1013上形成光刻胶1007，并通过光刻将其构图为沿第一方向(图3中垂直于纸面的方向)延伸的条状。可以光刻胶1007作为刻蚀掩模，通过例如反应离子刻蚀(RIE)依次对硬掩模层1013和用于芯模图案的层1011进行选择性刻蚀，将光刻胶的图案转移到硬掩模层1013和用于芯模图案的层1011中。刻蚀可以停止于刻蚀停止层1009。之后，可以去除光刻胶1007。
如图4所示，可以在芯模图案1011在与第一方向相交(例如，垂直)的第二方向(图4中纸面内的水平方向)上相对两侧的侧壁上，形成隔墙1017。例如，可以以大致共形的方式淀积一层厚度为约10nm-100nm的氮化物，然后沿竖直方向对淀积的氮化物层进行各向异性刻蚀如RIE(可以停止于刻蚀停止层1009)，以去除其横向延伸部分而留下其竖直延伸部分，从而得到隔墙1017。隔墙1017随后可以用来限定器件有源区的位置。
如上所述形成的芯模图案及其侧壁上形成的侧墙1017在第一方向上延伸。可以限定它们在第一方向上的范围，并因此限定器件有源区在第一方向上的范围。
如图5(a)至5(c)所示，可以在图4所示的结构上形成光刻胶1015，并通过光刻将其构图为在第一方向上占据一定范围，例如沿着与第一方向垂直的第二方向延伸的条状。可以光刻胶1015作为刻蚀掩模，通过例如RIE依次对下方的层进行选择性刻蚀。刻蚀可以进行到衬底1001特别是其中的阱区中，从而在衬底1001中形成凹槽。形成的凹槽中随后可以形成隔离，例如浅沟槽隔离(STI)。之后，可以去除光刻胶1015。
如图5(c)所示，第二材料层1003在第一方向上的侧壁当前暴露于外。
根据本公开的实施例，为了形成环绕沟道部的栅堆叠，可以在第二材料层 在第一方向上的两端留出用于栅堆叠的空间。
为此，如图6(a)至6(d)所示，可以对第二材料层1003进行选择性刻蚀，以使其在第一方向上的侧壁相对凹入。为更好地控制刻蚀的量，可以采用原子层刻蚀(ALE)。例如，刻蚀的量可以是约5nm-20nm。取决于刻蚀的特性，例如第二材料层1003相对于衬底1001和第三材料层1005的刻蚀选择性，刻蚀后第二材料层1003的侧壁可以呈现不同的形状。在图6(d)中示出了刻蚀后第二材料层1003的侧壁为向内侧凹入的C形。但是，本公开不限于此。例如，在刻蚀选择性好时，刻蚀后第二材料层1003的侧壁可以接近竖直。在此，刻蚀可以是各向同性的，特别是在需要较大刻蚀量时。在如此形成的凹入中，可以填充电介质材料，以限定栅堆叠的空间。这种填充可以通过淀积然后回蚀的方式来进行。例如，可以在衬底上淀积足以填满凹入的电介质材料如SiC，然后对淀积的电介质材料进行回蚀如RIE。这样，可以去除硬掩模层1013和隔墙1017所限定范围之外的电介质材料，且电介质材料留于上述凹入中而形成第一位置保持层1019。
根据本公开的实施例，还可以在衬底1001上形成保护层1021。例如，可以通过淀积，在衬底1001上形成氧化物层，并对淀积的氧化物层进行平坦化处理如化学机械抛光(CMP)(CMP可以停止于硬掩模层1013)后进一步回蚀，来形成保护层1021。在此，保护层1021可以处于衬底1001的凹槽中，其顶面低于衬底1001的顶面。另外，在回蚀的过程中，刻蚀停止层1009(在该示例中，也是氧化物)暴露于外的部分也可以被刻蚀。根据其他实施例，形成保护层1021的操作可以在形成第一位置保持层1019的操作(包括凹入和填充)之前执行。
保护层1021可保护衬底1001的表面。例如，在该示例中，先限定了有源区在第一方向上的范围。随后，将限定有源区在第二方向上的范围。保护层1021可以避免在限定第二方向上的范围时对衬底目前在凹槽中暴露于外的表面(参见图5(c))造成影响。另外，在衬底1001中形成不同类型的阱区的情况下，保护层1021可以保护不同类型阱区之间的pn结不被刻蚀(例如，形成第一位置保持层1019时的回蚀)破坏。
如图7所示，可以利用硬掩模层1013和隔墙1017，将第三材料层1005、 第二材料层1003和衬底1001的上部(第一材料层)构图为脊状结构(事实上，该脊状结构在第一方向上的范围已通过上述处理而限定)。例如，可以硬掩模层1013和隔墙1017作为刻蚀掩模，通过例如RIE依次对各层进行选择性刻蚀，将图案转移到下方的层中。于是，衬底1001的上部、第二材料层1003和第三材料层1005可以形成脊状结构。如上所述，由于保护层1021的存在，刻蚀可以不影响衬底1001在脊状结构在第一方向上两侧的部分。
在此，刻蚀可以进入衬底1001的阱区中。刻蚀进入衬底1001中的程度可以与以上结合图5(a)至5(c)描述的刻蚀接入衬底1001中的程度基本相同或者相似。同样地，在衬底1001中形成凹槽。并且也可以在这些凹槽中形成保护层(参见图8中的1023)。该保护层1023与之前的保护层1021一起围绕脊状结构的外周。这样，在脊状结构周围可以具有相似的处理条件，即，都是衬底1001中形成有凹槽，凹槽中形成有保护层1021、1023。
同样地，为了形成环绕沟道部的栅堆叠，可以在第二材料层在第二方向上的两端留出用于栅堆叠的空间。例如，如图8所示，可以对第二材料层1003进行选择性刻蚀，以使其在第二方向上的侧壁相对凹入(可以限定用于栅堆叠的空间)。为更好地控制刻蚀的量，可以采用ALE。例如，刻蚀的量可以为约10nm-40nm。如上所述，刻蚀后第二材料层1003的侧壁可以呈现向内侧凹入的C形。在此，刻蚀可以是各向同性的，特别是在需要较大刻蚀量时。通常，第二材料层1003的C形侧壁在上下两端处曲率较大，而在腰部或中部处曲率较小。
可以在脊状结构的侧壁上形成第一沟道层，以便随后限定沟道部。为使后续在C形沟道部左右两侧形成栅堆叠时它们的栅长(例如，沿垂直于衬底表面方向)可以保持基本相等，如图9所示，可以对脊状结构(具体地，第一材料层、第二材料层和第三材料层的外露表面)进行回蚀，使其外周侧壁相对于隔墙1017的外周侧壁横向凹入。为控制刻蚀深度，可以采用ALE。刻蚀深度可以基本等于随后要生长的第一沟道层的厚度，例如为约5nm-15nm。
然后，如图10所示，可以通过例如选择性外延生长，在脊状结构的侧壁上形成第一沟道层1025。由于选择性外延生长，第一位置保持层1019的表面上可以没有形成第一沟道层1025。第一沟道层1025随后可以限定沟道部，厚 度为例如约3nm-15nm。根据本公开的实施例，第一沟道层1025(随后用作沟道部)的厚度可以通过外延生长工艺决定，因此可以更好地控制沟道部的厚度。第一沟道层1025可以在外延生长时原位掺杂，以调节器件的阈值电压。
在图10中，将第一沟道层1025在第一材料层和第三材料层的侧壁上的部分的侧壁示出为与隔墙1017的侧壁基本齐平。这可以通过控制回蚀量和外延生长厚度基本相同来实现。但是，本公开不限于此。例如，第一沟道层1025在第一材料层和第三材料层的侧壁上的部分的侧壁可以相对于隔墙1017的侧壁凹入，或者甚至可能突出。
在此，进行上述回蚀可以将凹入部的上端和下端分别向上和向下刻蚀，使得生长第一沟道层1025之后，凹入部的高度t1与第二材料层1003的厚度t2可以基本相同。这样，随后在第一沟道层1025左右两侧形成的栅堆叠可以具有基本相等的栅长。但是，本公开不限于此。根据本公开的实施例，也可通过调节回蚀量来改变第一沟道层1025外侧的栅长，从而改变两侧栅长的比例，以优化由于C形沟道部左右两侧形貌不同对器件性能的影响。
可以根据设计对器件的性能要求，适当选择第一沟道层1025的材料。例如，第一沟道层1025可以包括各种半导体材料，例如Si、Ge、SiGe、InP、GaAs、InGaAs等。在该示例中，第一沟道层1025可以包括与第一材料层和第三材料层相同的材料如Si。
在图10的示例中，脊状结构在第二方向上相对两侧的第一沟道层1025可以具有实质上相同的特征(例如，材料、尺寸、掺杂特性等)，且彼此可以对称设置在第二材料层的相对两侧。但是，本公开不限于此。如下所述，通过单个脊状结构，可以形成彼此相对的两个器件。根据设计对这两个器件的性能要求，脊状结构相对两侧的第一沟道层1025可以具有不同的特征，例如在厚度、材料和掺杂特性等至少一个方面不同。这可以通过在一个器件区域中生长第一沟道层时遮蔽另一个器件区域来实现。
由于第二材料材料层1003凹入，因此在第一沟道层1025与第二材料层1003相对应的部分外侧，形成有空隙。在该空隙中，随后可以形成栅堆叠。为防止后继处理在该空隙中留下不必要的材料或者影响第一沟道层1025，如图11所示，可以在该空隙中形成第二位置保持层1027。同样地，第二位置保 持层1027可以通过淀积然后回蚀的方式形成，且可以包括电介质材料如SiC。在该示例中，第一位置保持层1019与第二位置保持层1027包括相同的材料，从而它们随后可以被相同的刻蚀配方一起去除。但是本公开不限于此，例如它们可以包括不同的材料。
之后，可以进行源/漏掺杂。
如图12所示，可以通过例如淀积，在图11所示的结构上形成固相掺杂剂源层1029。固相掺杂剂源层1029可以大致共形的方式形成。例如，固相掺杂剂源层1029可以是包含掺杂剂的氧化物，厚度为约1nm-5nm。固相掺杂剂源层1029中包含的掺杂剂可以用于掺杂源/漏部(以及可选地，衬底1001的露出表面)，因此可以具有与所需形成的源/漏部相同的导电类型。例如，对于p型器件，固相掺杂剂源层1029可以包含p型掺杂剂如B或In；对于n型器件，固相掺杂剂源层1029可以包含n型掺杂剂如P或As。固相掺杂剂源层1029的掺杂剂的浓度可以为约0.1％-5％。
在该示例中，在形成固相掺杂剂源层1029之前，可以通过例如RIE，选择性刻蚀保护层1021、1023，以露出衬底1001的表面。这样，衬底1001的露出表面也可被掺杂从而形成两个器件下端的源/漏部S/D各自的接触区。
可以通过退火处理，将固相掺杂剂源层1029中的掺杂剂驱入第一沟道层以及第一材料层和第三材料层中以形成源/漏部S/D(以及可选地，可以驱入衬底1001的露出表面中以形成两个器件下端的源/漏部S/D各自的接触区)，如图13所示。之后，可以去除固相掺杂剂源层1029。
由于第一材料层和第三材料层可以具有相同的材料，且固相掺杂剂源层1029可以大致共形的方式形成在它们的表面上，因此掺杂剂从固相掺杂剂源层1029向第一材料层和第三材料层中的驱入程度可以大致相同。因此，源/漏部S/D(与第一材料层、第三材料层的内侧部分之间)的(掺杂浓度)界面可以大致平行于第一材料层和第三材料层的表面，也即，可以在竖直方向上，且可以彼此对准。
在该示例中，第一材料层通过衬底1001的上部提供。但是，本公开不限于此。例如，第一材料层也可以是衬底1001上的外延层。在这种情况下，第一材料层和第三材料层可以在外延时原位掺杂，而不是利用固相掺杂剂源层进 行掺杂。
在脊状结构周围的凹槽中，可以形成隔离层1031，如图14(a)所示。形成隔离层的方法可以与如上所述形成保护层1021、1023的方法相似，在此不再赘述。
为降低栅与源/漏之间的电容，可以进一步降低栅与源/漏之间的交迭。例如，如图14(b)所示，在去除固相掺杂剂源层1029之后，可以通过选择性刻蚀，使源/漏部S/D进一步凹进，从而源/漏部S/D与第一位置保持层1019、第二位置保持层1027(随后限定栅堆叠的位置)之间的交迭减少。在该示例中，在使源/漏部S/D进一步凹进时，去除了第一沟道层1025在第一材料层和第三材料层的侧壁上的部分，并且可以使第一材料层和第三材料层进一步凹进。在由于源/漏部S/D的凹进而在硬掩模层1013和隔墙1017下方所形成的空隙中，可以填充电介质1031′如氮氧化物或氧化物。填充可以通过淀积(且平坦化)然后回蚀来实现。回蚀时留下一定厚度的电介质1031′在衬底1001的表面上从而形成隔离部。
在以下，为方便起见，仍以图14(a)所示的情形为例进行描述。
接下来，可以利用隔墙1017来完成有源区的限定。
如图15所示，可以通过选择性刻蚀如RIE或者平坦化处理如CMP，去除硬掩模层1013以露出芯模图案1011。在去除硬掩模层1013的过程中，在该示例中同为氮化物的隔墙1017的高度可能降低。然后，可以通过选择性刻蚀如采用TMAH溶液的湿法刻蚀或采用RIE的干法刻蚀，去除芯模图案1011。这样，在脊状结构上留下了彼此相对延伸的一对隔墙1017(高度降低，顶端形貌也可能有所改变)。
可以利用隔墙1017作为刻蚀掩模，通过例如RIE，依次选择性刻蚀刻蚀停止层1009、第三材料层1005、第二材料层1003以及衬底1001的上部。刻蚀可以进行到衬底1001的阱区中。这样，在隔离层1031围绕的空间内，第三材料层1005、第二材料层1003以及衬底1001的上部形成了与隔墙1017相对应的一对堆叠，用以限定有源区。
当然，形成用于限定有源区的堆叠不限于隔墙图形转移技术，也可以利用光刻胶等通过光刻来进行。
在此，出于外延生长的目的，用于限定栅堆叠位置的第二材料层1003包括半导体材料。为便于后继的替代栅工艺，可以将第二材料层1003替换为电介质材料，以形成第三位置保持层。
例如，如图16(a)和16(b)所示，可以相对于第一沟道层1025、衬底1001和第三材料层1005(在该示例中均为Si)，通过选择性刻蚀，去除第二材料层1003(在该示例中为SiGe)。然后，可以在隔墙1017下方由于第二材料层1003的去除而留下的空隙中形成第三位置保持层1033。同样地，第三位置保持层1033可以通过淀积然后回蚀的方法来形成。在该示例中，第三位置保持层1033可以与第一位置保持层1019、第二位置保持层1027包括相同的材料，以便随后在替代栅工艺中可以被相同的刻蚀配方一起去除。
如图16(b)所示，第一位置保持层1019、第二位置保持层1027与第三位置保持层1033(它们一起限定栅堆叠的位置)围绕第一沟道层1025的一部分。第一沟道层1025的该部分可以用作沟道部。可以看出，沟道部是呈C形的弯曲纳米片(当纳米片较窄时，例如，图16(b)中纸面内竖直方向的尺寸较小时，可以变成纳米线)。由于刻蚀第二材料层1003(SiGe)时相对于第一沟道层1025(Si)的高刻蚀选择性，因此沟道部的厚度(纳米线的情况下，为粗细，或者是直径)基本上由第一沟道层1025的选择性生长工艺来确定。这相对于仅使用刻蚀方法或光刻方法来确定厚度的技术具有巨大优势，因为相比于刻蚀或光刻，外延生长工艺具有好得多的工艺控制。
为了减少栅堆叠与源/漏部特别是下方的源/漏部之间的交迭，可以提升隔离层1031的高度。例如，可以通过淀积(且平坦化)然后回蚀的方式，形成隔离层1035。例如，隔离层1035可以包括氧化物，且因此与之前的隔离层1031示出为一体。隔离层1035的顶面可以接近例如不低于(优选地，略高于)第一材料层的顶面(即，衬底1001的顶面)或者第二材料层的底面(即，第一位置保持层1019、第二位置保持层1027和第三位置保持层1033的底面)，且不高于第二材料层的顶面(即，第一位置保持层1019、第二位置保持层1027和第三位置保持层1033的顶面)或者第三材料层的底面。
根据本公开的另一实施例，为降低电容，可以进一步降低栅与第一材料层和第三材料层(其中形成有源/漏部)之间的交迭。例如，如图17所示，在如 上所述形成第三位置保持层1033之后，可以通过选择性刻蚀，使第一材料层和第三材料层的暴露表面进一步凹进。从而第一材料层和第三材料层与第三位置保持层1033(随后限定栅堆叠的位置)之间的交迭减少。之后，可以类似地形成隔离层1035′。在形成隔离层1035′的过程中，隔离层1035′的电介质材料也会填充隔墙1017下方由于第三材料层的凹入而形成的空隙中。
在图17的示例中，示出了在参考图14(b)描述的缩减交迭的处理工艺之外再进行参考图17描述的缩减交迭的工艺而得到的结构。于是，源/漏部S/D的外周被电介质材料所围绕。但是，本公开不限于此。例如，参考图14(b)描述的缩减交迭的处理工艺与参考图17描述的缩减交迭的处理工艺可以择一进行，或者可以都进行。
在以下的描述中，仍然以图16(a)和16(b)所示的情形为例进行描述。
接下来，可以进行替代栅工艺，以形成栅堆叠。
如图18(a)至18(c)所示，可以通过选择性刻蚀，去除第一位置保持层1019、第二位置保持层1027和第三位置保持层1033，并在隔离层1035上形成栅堆叠。例如，可以通过淀积，以大致共形的方式形成栅介质层1037，并在栅介质层1037上形成栅导体层1039。栅导体层1039可以填充有源区之间的空间。可以对栅导体层1039进行平坦化处理如CMP，CMP可以停止于隔墙1017。然后，可以回蚀栅导体层1039，以使其顶面低于原先第一位置保持层1019、第二位置保持层1027和第三位置保持层1033的顶面(或者，第二材料层的顶面或第三材料层的底面)，以降低源/漏部与栅堆叠之间的电容。通过这种方式，所形成的栅堆叠的端部嵌入到先前第一位置保持层1019、第二位置保持层1027和第三位置保持层1033所在的空间中，围绕沟道部。
例如，栅介质层1037可以包括高k栅介质如HfO 2，厚度例如为约1nm-5nm。在形成高k栅介质之前，还可以形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物，厚度为约0.3nm-1.5nm。栅导体层1039可以包括功函数调节金属如TiN、TaN、TiAlC等和栅导电金属如W等。
当前，两个器件各自的栅堆叠彼此连接成一体。可以根据器件设计，通过例如光刻，将栅导体层1039在两个器件之间断开，同时也可以构图栅接触部的着落焊盘(1anding pad)。
如图19所示，可以形成光刻胶1041，并将其构图为遮蔽要形成栅接触部的着落焊盘的区域，而露出其他区域。然后，如图20(a)至20(c)所示，可以光刻胶1041(以及隔墙1017)作为掩模，选择性刻蚀如RIE栅导体层1039，RIE可以停止于栅介质层1037。之后，可以去除光刻胶1041。
于是，栅导体层1039基本留于且自对准于隔墙1017下方，除了在隔墙1017的一侧(图20(a)中的上侧)突出一部分以用作着落焊盘之外。栅导体层1039在分别处于相对隔墙1017下方的两个相对器件之间分离，从而与栅介质层1037相结合而限定分别用于两个器件的栅堆叠。
在该示例中，两个器件各自的着落焊盘位于隔墙1017的相同侧。但是，本公开不限于此。例如，两个器件各自的着落焊盘可以位于隔墙1017的不同侧。
至此，完成了器件基础结构的制作。随后，可以制作各种接触部、互连结构等。
例如，如图21(a)和21(b)所示，可以通过例如淀积然后平坦化的方式，在衬底上形成电介质层1043。然后，可以形成接触孔，并在接触孔中填充导电材料如金属，形成接触部1045。接触部1045可以包括穿透隔墙1017和刻蚀停止层1009连接到上端源/漏部的接触部，穿透电介质层1043和隔离层1035连接到下端源/漏部的接触区的接触部，以及穿透电介质层1043连接到栅导体层的着落焊盘的接触部。如图21(a)和21(b)所示，到两个器件各自的下端源/漏部的接触区的接触部可以分处于有源区的相对两侧(图中的左侧和右侧)。
根据本公开的其他实施例，到下端源/漏部的接触区的接触部可以与到相应器件的栅导体层的着落焊盘的接触部分处于相应器件有源区的相对两侧，如图22所示。
图23(a)至图36示意性示出了根据本公开另一实施例的制造半导体器件的流程中的一些阶段。以下，将主要描述与上述实施例之间的不同之处。
可以进行如以上参照图1至8描述的处理，在衬底2001上形成第二材料层2003和第三材料层2005以及用于帮助构图的刻蚀停止层2009、侧墙2017等。可以在第二材料层2003中形成凹入，并可以在衬底2001上形成保护层2023。关于其他未描述的组件和工艺，可以参见以上结合图1至8的描述。
可以类似地形成沟道层。在该实施例中，可以形成依次叠置的多个沟道层。
例如，如图23(a)所示，可以通过例如选择性外延生长，在脊状结构的侧壁上形成预备沟道层2025。由于选择性外延生长，预备沟道层2025可以仅形成在半导体表面上。预备沟道层2025的厚度可以大致等于随后形成的第一沟道层(例如，第一厚度L1)和第二沟道层(例如，第二厚度L2)的厚度之和(L1+L2)，例如为约3nm-15nm。预备沟道层2025的厚度如此选择的主要目的在于使后继C形沟道部左右两侧的栅长能够基本相等，以下将对此进一步说明。
可以根据设计对器件的性能要求，适当选择预备沟道层2025的材料。例如，预备沟道层2025可以包括各种半导体材料，例如Si、Ge、SiGe、InP、GaAs、InGaAs等。在该示例中，预备沟道层2025可以包括与第一材料层和第三材料层相同的材料如Si。
根据另一实施例，如图23(b)所示，可以通过例如选择性外延生长，在脊状结构的侧壁上依次形成第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3。第一沟道层2025-1的厚度可以为第一厚度L1，例如约3nm-5nm；第二沟道层2025-2的厚度可以为第二厚度L2，例如约1nm-3nm；第三沟道层2025-3的厚度可以与第一沟道层2025-1的厚度大致相同，为第一厚度L1，例如约3nm-5nm。
根据本公开的实施例，为使后续在C形沟道部左右两侧形成栅堆叠时它们的栅长(例如，沿垂直于衬底表面方向)可以保持基本相等，在形成沟道层之前，可以对脊状结构(具体地，第一材料层、第二材料层和第三材料层的外露表面)进行回蚀，使其外周侧壁相对于隔墙2017的外周侧壁横向凹入。为控制刻蚀量，可以采用ALE。例如，刻蚀量可以大致为要形成的第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3的厚度之和(2L1+L2)，例如约4nm-20nm。于是，所形成的第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3可以(至少部分地)被隔墙2017从上方遮挡。
在图23(b)中，将最外侧的第三沟道层2025-3在第一材料层和第三材料层的侧壁上的部分的侧壁示出为与隔墙2017的侧壁基本齐平。这可以通过控制回蚀量和外延生长总厚度基本相同来实现。但是，本公开不限于此。例如，最 外侧的第三沟道层2025-3在第一材料层和第三材料层的侧壁上的部分的侧壁可以相对于隔墙2017的侧壁凹入，或者甚至可能突出。
在此，进行上述回蚀可以将凹入部的上端和下端分别向上和向下刻蚀，使得生长第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3之后，凹入部的高度t1与第二材料层2003的厚度t2可以基本相同。这样，随后在第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3形成的沟道部的左右两侧形成的栅堆叠可以具有基本相等的栅长。但是，本公开不限于此。根据本公开的实施例，也可通过调节回蚀量来改变沟道部外侧的栅长，从而改变两侧栅长的比例，以优化由于C形沟道部左右两侧形貌不同对器件性能的影响。
尽管在图23(a)所示的示例中没有示出对脊状结构进行回蚀，但是同样可以如此处理。
根据本公开的实施例，各沟道层(随后用作沟道部)的厚度可以通过外延生长工艺决定，因此可以更好地控制沟道部的厚度。通过外延生长形成的各沟道层的厚度可以是实质上均匀的。各沟道层可以在外延生长时原位掺杂，以调节器件的阈值电压。
同样地，可以适当选择第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3的材料。例如，第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3均可以包括各种半导体材料，例如Si、Ge、SiGe、InP、GaAs、InGaAs等。
根据本公开的实施例，第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3中至少一些可以具有不同的特性，以优化器件性能。
例如，第二沟道层2025-2可以包括(相对于第一沟道层2025-1、第三沟道层2025-3)具有高载流子迁移率的材料如SiGe(例如，Ge原子百分比为约30％-100％，在Ge原子百分比为100％时成为Ge)，以提升器件电流能力。但是SiGe与随后形成的栅介质层的界面质量可能不好(例如，界面态电荷密度大，表面粗糙对载流子散射大或沟道电阻大，等等)。为此，第一沟道层2025-1和第三沟道层2025-3可以包括与栅介质层的界面质量好的材料如Si。
又如，第一沟道层2025-1和第三沟道层2025-3可以包括(相对于第二沟道层2025-2)具有高载流子迁移率的材料，第二沟道层2025-2可以包括能够 优化载流子分布的材料。
再如，第二沟道层2025-2可以将载流子限制在第一沟道层2025-1和/或第三沟道层2025-3中，从而与栅介质层更接近，有利于改善短沟道效应并降低漏电流。例如，对于n型器件，第二沟道层2025-2的导带的最低能级可以高于第一沟道层2025-1和/或第三沟道层2025-3的导带的最低能级；对于p型器件，第二沟道层2025-2的价带的最高能级可以低于第一沟道层2025-1和/或第三沟道层2025-3的价带的最高能级。
在图23(a)和23(b)所示的示例中，脊状结构在第二方向上相对两侧的沟道层可以具有实质上相同的特征(例如，材料、尺寸、掺杂特性等)，且彼此可以对称设置在第二材料层的相对两侧。但是，本公开不限于此。如上所述，根据设计，脊状结构相对两侧的沟道层可以具有不同的特征，例如在厚度、材料和掺杂特性等至少一个方面不同。
在以下，为方便起见，主要以图23(a)为例进行描述。
类似地，如图24所示，可以形成第二位置保持层2027。第二位置保持层2027可以与之前形成的第一位置保持层(参见图30(b)中的2019，关于其详情可以参见上述实施例中关于第一位置保持层1019的描述)可以包括相同的材料如SiC，从而它们随后可以被相同的刻蚀配方一起去除。但是本公开不限于此，例如它们可以包括不同的材料。
之后，可以进行源/漏掺杂。
如图25所示，可以通过例如淀积，在图24所示的结构上形成固相掺杂剂源层2029。固相掺杂剂源层2029可以大致共形的方式形成。关于固相掺杂剂源层2029，可以参见以上关于固相掺杂剂源层1029的描述。
在该示例中，在形成固相掺杂剂源层2029之前，可以通过例如RIE，选择性刻蚀衬底2001的表面上存在的保护层(例如，参见图23(a)和23(b)中的2023)，以露出衬底2001的表面。这样，衬底2001的露出表面也可被掺杂从而形成两个器件下端的源/漏部S/D各自的接触区。
可以通过退火处理，将固相掺杂剂源层2029中的掺杂剂驱入预备沟道层2025以及第一材料层和第三材料层中以形成源/漏部S/D(以及可选地，可以驱入衬底2001的露出表面中以形成两个器件下端的源/漏部S/D各自的接触 区)，如图26所示。之后，可以去除固相掺杂剂源层2029。
由于第一材料层和第三材料层可以具有相同的材料，且固相掺杂剂源层2029可以大致共形的方式形成在它们的表面上，因此掺杂剂从固相掺杂剂源层2029向第一材料层和第三材料层中的驱入程度可以大致相同。因此，源/漏部S/D(与第一材料层、第三材料层的内侧部分之间)的(掺杂浓度)界面可以大致平行于第一材料层和第三材料层的表面，也即，可以在竖直方向上，且可以彼此对准。
在该示例中，第一材料层通过衬底2001的上部提供。但是，本公开不限于此。例如，第一材料层也可以是衬底2001上的外延层。在这种情况下，第一材料层和第三材料层可以在外延时原位掺杂，而不是利用固相掺杂剂源层进行掺杂。
在脊状结构周围的凹槽中，可以形成隔离层2031，如图27(a)所示。
为降低栅与源/漏之间的电容，可以进一步降低栅与源/漏之间的交迭。例如，如图27(b)所示，在去除固相掺杂剂源层2029之后，可以通过选择性刻蚀，使源/漏部S/D进一步凹进，从而源/漏部S/D与第一位置保持层、第二位置保持层2027(随后限定栅堆叠的位置)之间的交迭减少。在该示例中，在使源/漏部S/D进一步凹进时，去除了预备沟道层2025在第一材料层和第三材料层的侧壁上的部分，并且可以使第一材料层和第三材料层进一步凹进。在由于源/漏部S/D的凹进而在硬掩模层和隔墙2017下方所形成的空隙中，可以填充电介质2031′如氮氧化物或氧化物。填充可以通过淀积(且平坦化)然后回蚀来实现。回蚀时留下一定厚度的电介质2031′在衬底2001的表面上从而形成隔离部。
在以下，为方便起见，仍以图27(a)所示的情形为例进行描述。
接下来，可以利用隔墙2017来完成有源区的限定。
在该示例中，由于预备沟道层2025的一部分突出在隔墙2017之外，为防止随后的处理对预备隔离层2025造成不利影响，可以先在隔离层2031上形成保护层以覆盖预备隔离层2025。如图28所示，可以在隔离层2031上通过例如淀积进一步形成电介质材料如氧化物，并可以对淀积的电介质材料进行平坦化处理如CMP(可以停止于硬掩模层)。在该示例中，将形成的电介质材料与 之前的隔离层2031(在该示例中均为氧化物)一起示出为2032。
之后，可以如以上结合图15所述，去除硬掩模层和芯模图案，从而在脊状结构上留下彼此相对延伸的一对隔墙2017(高度降低，顶端形貌也可能有所改变)。可以利用隔墙2017作为刻蚀掩模，通过选择性刻蚀如RIE(刻蚀可以进行到衬底2001的阱区中)，在隔离层(保护层)2032围绕的空间内，将第三材料层2005、第二材料层2003以及衬底2001的上部构图为与隔墙2017相对应的一对堆叠，用以限定有源区。由于隔离层(保护层)2032的存在，预备沟道层2025(在该示例中，与第三材料层2005、衬底2001一样包括Si)可以免受刻蚀的影响。
在用于分别限定相应有源区的这一对堆叠之间，可以通过如上所述形成隔离层的方式，形成隔离层2032a(例如，氧化物)，如图29所示。可以对该隔离层2032a进行回蚀，使其顶面低于第二材料层2003的顶面，从而露出第二材料层2003的(至少部分)侧壁以便随后将其去除。在该示例中，回蚀后的隔离层2032a的顶面靠近(例如，略低于)第二材料层2003的底面，以充分露出第二材料层2003的侧壁。当然，堆叠之间的隔离层2032a的形成也可以结合到随后形成隔离层2035的处理中。
在该示例中，为形成多纳米片或纳米线的堆叠结构，可以基于预备沟道层2025继续生长另外的沟道层。为此，可以去除第二材料层2003，以露出预备沟道层2025。
例如，如图29所示，可以相对于预备沟道层2025、衬底2001和第三材料层2005(在该示例中均为Si)，通过选择性刻蚀，去除第二材料层2003(在该示例中为SiGe)。
由于刻蚀SiGe时相对于Si的高刻蚀选择性，纳米片形式的预备沟道层2025的厚度主要由外延生长工艺决定。如上所述，预备沟道层2025通过对第二材料层2003进行(各向同性)选择性刻蚀，然后外延生长来形成，并可以具有C形。相比于仅使用刻蚀或光刻的方法，本公开的方法在预备沟道层2025的厚度控制方面具有优势，因为外延生长工艺具有比刻蚀或光刻好的工艺控制。
为使后续在C形沟道部左右两侧形成栅堆叠时它们的栅长可以保持基本相等，如图30(a)和30(b)所示，可以对预备沟道层2025、第一材料层和第三材 料层(在该示例中，Si)的外露表面进行回蚀。回蚀后的预备沟道层2025形成第一沟道层2025-1。为更好地控制刻蚀的量，可以采用ALE。例如，回蚀的量可以大致为第二厚度L2。于是，第一沟道层2025-1的厚度可以大致为第一厚度L1。之后，可以通过例如选择性外延生长，依次形成第二沟道层2025-2和第三沟道层2025-3。第二沟道层2025-2的厚度可以大致为第二厚度L2，第三沟道层2025-3的厚度可以与第一沟道层2025-1的厚度基本相同，大致为第一厚度L1。关于第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3的材料，可以参见以上结合图23(b)的说明。
在此，选择刻蚀量为第二厚度L2，目的在于确保随后形成的C形沟道部两侧可以具有基本相同的栅长。实际上，可以通过调整回蚀量(或者在结合图23(a)描述的外延生长工艺之前对脊状结构进行回蚀，并控制回蚀量)，来调整C形沟道部两侧的栅长。
同样地，如上所述，在确定厚度方面，使用外延生长工艺相比于刻蚀或光刻方法具有优势。
如上所述，在回蚀过程中第一材料层和第三材料层也被刻蚀，可能造成源/漏部S/D与沟道部之间的不连续。为此，可以进行退火处理，以将掺杂剂驱入新生长的有源层中，以便形成源/漏部S/D以及延伸区掺杂分布。
这里需要指出的是，如果采用图23(b)所示的结构，则可以省略刻蚀然后外延生长这些处理，只需将第二材料层2003去除即可。
然后，可以在隔墙2017下方由于第二材料层2003的去除而留下的空隙中形成第三位置保持层2033。第三位置保持层2033可以与第一位置保持层2019、第二位置保持层2027包括相同的材料如SiC，以便随后在替代栅工艺中可以被相同的刻蚀配方一起去除。
如图30(b)所示，第一位置保持层2019、第二位置保持层2027与第三位置保持层2033(它们一起限定栅堆叠的位置)围绕第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3的一部分。第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3的该部分可以用作沟道部。可以看出，沟道部是呈C形的弯曲纳米片(当纳米片较窄时，例如，图30(b)中纸面内竖直方向的尺寸较小时，可以变成纳米线)。如上所述，沟道部的厚度(纳米线的情况 下，为粗细，或者是直径)基本上由各沟道层的选择性生长工艺来确定。这相对于仅使用刻蚀方法或光刻方法来确定厚度的技术具有巨大优势，因为相比于刻蚀或光刻，外延生长工艺具有好得多的工艺控制。
根据本公开的另一实施例，为降低电容，可以进一步降低栅与第一材料层和第三材料层(其中形成有源/漏部)之间的交迭。例如，如图31所示，在如上所述形成第三位置保持层2033之后，可以通过选择性刻蚀，使第一材料层和第三材料层的暴露表面进一步凹进。从而第一材料层和第三材料层与第三位置保持层2033(随后限定栅堆叠的位置)之间的交迭减少。之后，可以类似地形成隔离层2032′。
在图31的示例中，示出了在参考图27(b)描述的缩减交迭的处理工艺之外再进行参考图31描述的缩减交迭的工艺而得到的结构。于是，源/漏部S/D的外周被电介质材料所围绕。但是，本公开不限于此。例如，参考图27(b)描述的缩减交迭的处理工艺与参考图31描述的缩减交迭的处理工艺可以择一进行，或者可以都进行。
在以下的描述中，仍然以图30(a)和30(b)所示的情形为例进行描述。
接下来，可以进行替代栅工艺，以形成栅堆叠。
由于当前隔离层2032覆盖了第一位置保持层2019和第二位置保持层2027，可以降低隔离层2032的高度，以(至少部分)露出第一位置保持层2019、第二位置保持层2027以便将它们去除。例如，如图32(a)至32(c)所示，可以在图30(a)和30(b)所示的结构上淀积电介质如氧化物，对淀积的电介质进行平坦化处理如CMP(可以停止于隔墙2017)，并对平坦化后的电介质进行回蚀如RIE，得到隔离层2035。隔离层2035的顶面可以接近例如不低于(优选地，略高于)第一材料层的顶面(即，衬底2001的顶面)或者第二材料层的底面(即，第一位置保持层2019、第二位置保持层2027和第三位置保持层2033的底面)，且不高于第二材料层的顶面(即，第一位置保持层2019、第二位置保持层2027和第三位置保持层2033的顶面)或者第三材料层的底面。
可以通过选择性刻蚀，去除第一位置保持层2019、第二位置保持层2027和第三位置保持层2033，并在隔离层2035上形成栅堆叠。例如，可以通过淀积，以大致共形的方式形成栅介质层2037，并在栅介质层2037上形成栅导体 层2039。栅导体层2039可以填充有源区之间的空间。可以对栅导体层2039进行平坦化处理如CMP，CMP可以停止于隔墙2017。然后，可以回蚀栅导体层2039，以使其顶面低于原先第一位置保持层2019、第二位置保持层2027和第三位置保持层2033的顶面(或者，第二材料层的顶面或第三材料层的底面)，以降低源/漏部与栅堆叠之间的电容。通过这种方式，所形成的栅堆叠的端部嵌入到先前第一位置保持层2019、第二位置保持层2027和第三位置保持层2033所在的空间中，围绕沟道部。
关于栅介质层2037和栅导体层2039的详情，可以参见以上关于栅介质层1037和栅导体层1039的描述。
类似地，可以根据器件设计，调整栅导体层2039的形状。
如图33所示，可以形成光刻胶2041，并将其构图为遮蔽要形成栅接触部的着落焊盘的区域，而露出其他区域。然后，如图34(a)至34(c)所示，可以光刻胶2041(以及隔墙2017)作为掩模，选择性刻蚀如RIE栅导体层2039，RIE可以停止于栅介质层2037。之后，可以去除光刻胶2041。
于是，栅导体层2039基本留于且自对准于隔墙2017下方，除了在隔墙2017的一侧(图34(a)中的上侧)突出一部分以用作着落焊盘之外。栅导体层2039在分别处于相对隔墙2017下方的两个相对器件之间分离，从而与栅介质层2037相结合而限定分别用于两个器件的栅堆叠。
在该示例中，两个器件各自的着落焊盘位于隔墙2017的相同侧。但是，本公开不限于此。例如，两个器件各自的着落焊盘可以位于隔墙2017的不同侧。
至此，完成了器件基础结构的制作。随后，可以制作各种接触部、互连结构等。
例如，如图35(a)和35(b)所示，可以通过例如淀积然后平坦化的方式，在衬底上形成电介质层2043。然后，可以形成接触孔，并在接触孔中填充导电材料如金属，形成接触部2045。接触部2045可以包括穿透隔墙2017和刻蚀停止层(参见上述实施例中的1009)连接到上端源/漏部的接触部，穿透电介质层2043和隔离层2035连接到下端源/漏部的接触区的接触部，以及穿透电介质层2043连接到栅导体层的着落焊盘的接触部。如图35(a)和35(b)所示， 到两个器件各自的下端源/漏部的接触区的接触部可以分处于有源区的相对两侧(图中的左侧和右侧)。
根据本公开的其他实施例，到下端源/漏部的接触区的接触部可以与到相应器件的栅导体层的着落焊盘的接触部分处于相应器件有源区的相对两侧，如图36所示。
在以上实施例中，第一位置保持层2019与第二位置保持层2027和第三位置保持层2033包括相同的材料如SiC，从而在替代栅工艺中被一起去除。根据本公开的另一实施例，第一位置保持层2019可以包括与第二位置保持层2027和第三位置保持层2033不同的材料如氮氧化物。这种情况下，在进行替代栅工艺之前，可以先去除第一位置保持层2019，从而露出第一沟道层2025-1、第二沟道层2025-2和第三沟道层2025-3在第一方向上的端部。可以通过例如选择性外延生长，在这些露出的端部上形成第四沟道层2025-4，如图37所示。第四沟道层2025-4可以连接第一沟道层2025-1和第三沟道层2025-3的端部(且因此也可以称为连接部分)。于是，第一沟道层2025-1和第三沟道层2025-3连同第四沟道层2025-4可以围绕第二沟道层2025-2。第四沟道层2025-4可以包括与第一沟道层2025-1和第三沟道层2025-3相同的材料。另外，第四沟道层2025-4可以具有与第一沟道层2025-1和第三沟道层2025-3相同的厚度例如L1。但是，由于纳米尺度的端部的表面特性可能不同于其他表面的特性，故而第四沟道层2025-4的厚度可以不同于第一沟道层2025-1和第三沟道层2025-3的厚度。之后可以进行替代栅工艺。图38示出了这种情况下的栅堆叠与沟道部。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，可以基于这样的半导体器件形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (50)

  1. 一种半导体器件，包括：
    衬底上的沟道部，所述沟道部包括截面呈C形的弯曲纳米片或纳米线；
    相对于所述衬底分别处于所述沟道部的上下两端的源/漏部；以及
    围绕所述沟道部的外周的栅堆叠。
  2. 根据权利要求1所述的半导体器件，其中，所述沟道部包括在相对于衬底的横向方向上依次叠置且各自的截面呈C形的多个所述弯曲纳米片或纳米线。
  3. 根据权利要求2所述的半导体器件，其中，所述多个弯曲纳米片或纳米线中的至少一些纳米片或纳米线具有不同的特性。
  4. 根据权利要求2或3所述的半导体器件，其中，所述多个弯曲纳米片或纳米线包括分别处于所述沟道部在所述横向方向上的两侧且与所述栅堆叠具有改进界面质量的第一纳米片或纳米线和第二纳米片或纳米线，以及位于所述第一纳米片或纳米线与所述第二纳米片或纳米线之间且具有高载流子迁移率的第三纳米片或纳米线。
  5. 根据权利要求2或3所述的半导体器件，其中，所述多个弯曲纳米片或纳米线包括分别处于所述沟道部在所述横向方向上的两侧且具有高载流子迁移率的第一纳米片或纳米线和第二纳米片或纳米线，以及位于所述第一纳米片或纳米线与所述第二纳米片或纳米线之间且能够优化载流子分布的第三纳米片或纳米线。
  6. 根据权利要求2或3所述的半导体器件，其中，所述多个弯曲纳米片或纳米线包括分别处于所述沟道部在所述横向方向上的两侧的第一纳米片或纳米线和第二纳米片或纳米线，以及位于所述第一纳米片或纳米线与所述第二纳米片或纳米线之间的第三纳米片或纳米线，
    其中，所述半导体器件是n型器件，所述第三纳米片或纳米线的导带的最低能级高于所述第一纳米片或纳米线和/或所述第二纳米片或纳米线的导带的最低能级；或者
    其中，所述半导体器件是p型器件，所述第三纳米片或纳米线的价带的最 高能级低于所述第一纳米片或纳米线和/或所述第二纳米片或纳米线的价带的最高能级。
  7. 根据权利要求4至6中任一项所述的半导体器件，其中，所述第一纳米片或纳米线与所述第二纳米片或纳米线包括Si，所述第三纳米片或纳米线包括SiGe或Ge。
  8. 根据权利要求4至6中任一项所述的半导体器件，其中，所述沟道部还包括将所述第一纳米片或纳米线与所述第二纳米片或纳米线的相应端部连接的连接部分，使得所述第一纳米片或纳米线与所述第二纳米片或纳米线以及所述连接部分围绕所述第三纳米片或纳米线，从而它们的外壁形成所述沟道部的所述外周。
  9. 根据权利要求8所述的半导体器件，其中，所述连接部分包括与所述第一纳米片或纳米线和/或所述第二纳米片或纳米线相同的材料。
  10. 根据权利要求4至6中任一项所述的半导体器件，其中，所述第一纳米片或纳米线与所述第二纳米片或纳米线具有基本相同的第一厚度，所述第三纳米片或纳米线具有第二厚度。
  11. 根据权利要求1或2所述的半导体器件，其中，所述栅堆叠的至少与所述沟道部相邻的部分与所述沟道部实质上共面。
  12. 根据权利要求1或2所述的半导体器件，其中，所述弯曲纳米片或纳米线具有实质上均匀的厚度。
  13. 根据权利要求1或2所述的半导体器件，其中，所述源/漏部在相对于所述衬底的横向方向上的尺寸大于所述沟道部在相应方向上的尺寸。
  14. 根据权利要求1或2所述的半导体器件，其中，所述沟道部在相对于所述衬底的横向方向上的两端分别呈现向内侧凹进的C形。
  15. 根据权利要求1或2所述的半导体器件，还包括：
    相对于所述衬底分别处于所述沟道部的上下两端的第一半导体层和第二半导体层，
    其中，所述源/漏部分别设置在所述第一半导体层和所述第二半导体层中。
  16. 根据权利要求15所述的半导体器件，其中，所述源/漏部是所述第一半导体层和所述第二半导体层各自在所述C形的开口一侧的部分中形成的掺 杂区。
  17. 根据权利要求16所述的半导体器件，其中，所述源/漏部与所述第一半导体层和所述第二半导体层中的其余部分之间具有相对于所述衬底沿着实质上竖直方向的掺杂浓度界面。
  18. 根据权利要求17所述的半导体器件，其中，上端的所述源/漏部与所述第一半导体层中其余部分之间竖直方向上的掺杂浓度界面与下端的所述源/漏部与所述第二半导体层中其余部分之间竖直方向上的掺杂浓度界面在竖直方向上实质上对准。
  19. 根据权利要求16所述的半导体器件，其中，所述栅堆叠的至少部分外周沿着所述沟道部上端的所述第一半导体层的相应外周延伸。
  20. 根据权利要求19所述的半导体器件，其中，所述栅堆叠中的栅导体层还包括沿着相对于所述衬底的横向方向延伸超出所述第一半导体层的外周以用作焊盘的部分。
  21. 根据权利要求15所述的半导体器件，还包括：
    相对于所述衬底分别处于所述沟道部的上下两端、分别绕所述第一半导体层和所述第二半导体层各自至少部分外周的电介质层，
    其中，所述电介质层与相应的第一半导体层或第二半导体层实质上共面。
  22. 根据权利要求21所述的半导体器件，其中，所述栅堆叠的至少部分外周沿着所述沟道部上端的所述电介质层和所述第一半导体层二者的相应外周延伸。
  23. 根据权利要求22所述的半导体器件，其中，所述栅堆叠中的栅导体层还包括沿着相对于所述衬底的横向方向延伸超出所述沟道部上端的所述电介质层和所述第一半导体层二者的外周以用作焊盘的部分。
  24. 根据权利要求15至23中任一项所述的半导体器件，其中，所述沟道部下端的所述第二半导体层的外周侧壁的至少上部与所述沟道部上端的所述第一半导体层的外周侧壁实质上对准。
  25. 根据权利要求1或2所述的半导体器件，其中，所述弯曲纳米片或纳米线和/或所述源/漏部包括单晶半导体材料。
  26. 根据前述权利要求中任一项所述的半导体器件，其中，所述衬底上存 在多个所述半导体器件，其中至少一对半导体器件的所述C形彼此背对。
  27. 根据权利要求26所述的半导体器件，其中，所述一对半导体器件各自的沟道部实质上共面。
  28. 根据权利要求27所述的半导体器件，其中，所述一对半导体器件各自的上端源/漏部实质上共面，各自的下端源/漏部实质上共面。
  29. 根据权利要求26所述的半导体器件，其中，所述一对半导体器件各自的C形相对于彼此对称。
  30. 根据权利要求1或2所述的半导体器件，其中，在所述C形的弯曲纳米片或纳米线的相对两侧，所述栅堆叠的栅长基本相等。
  31. 一种制造半导体器件的方法，包括：
    在衬底上设置第一材料层、第二材料层和第三材料层的堆叠；
    将所述堆叠构图为脊状结构，所述脊状结构包括彼此相对的第一侧和第二侧以及彼此相对的第三侧和第四侧；
    在第三侧和第四侧，使所述第二材料层的侧壁相对于所述第一材料层和所述第三材料层的侧壁横向凹入，从而限定第一凹入部；
    在所述第一凹入部中形成第一位置保持层；
    在第一侧和第二侧，使所述第二材料层的侧壁相对于所述第一材料层和所述第三材料层的侧壁横向凹入，从而限定第二凹入部；
    在所述第二材料层被所述第二凹入部露出的表面上至少形成第一沟道层；
    在所述第二凹入部的剩余空间中形成第二位置保持层；
    在所述第一材料层和所述第三材料层中形成源/漏部；
    在所述脊状结构中形成条形开口，从而将所述脊状结构分为分别处于所述第一侧和第二侧的两部分；
    通过所述开口，去除所述第二材料层以露出所述第一沟道层，从而限定第三凹入部；
    在所述第三凹入部中形成第三位置保持层；
    在所述衬底上形成隔离层，所述隔离层的顶面不低于所述第一材料层的顶面且不高于所述第三材料层的底面；
    去除所述第一位置保持层、所述第二位置保持层和所述第三位置保持层； 以及
    在隔离层上围绕所述沟道层形成栅堆叠，所述栅堆叠具有嵌入到由于所述第一位置保持层、所述第二位置保持层和所述第三位置保持层的去除而留下的空间中的部分。
  32. 根据权利要求31所述的方法，其中，在限定第三凹入部之后且在形成第三位置保持层之前，该方法还包括：
    在所述第一沟道层被所述第三凹入部露出的表面上至少形成第二沟道层。
  33. 根据权利要求31所述的方法，其中，在所述第二材料层被所述第二凹入部露出的表面上至少形成第一沟道层包括：
    通过外延生长，依次形成所述第一沟道层、第二沟道层和第三沟道层。
  34. 根据权利要求32所述的方法，其中，
    在所述第二材料层被所述第二凹入部露出的表面上至少形成第一沟道层包括：通过外延生长，形成所述第一沟道层，
    在所述第一沟道层被所述第三凹入部露出的表面上至少形成第二沟道层包括：通过外延生长，依次形成所述第二沟道层和第三沟道层。
  35. 根据权利要求34所述的方法，还包括：通过所述第三凹入部，回蚀所述第一沟道层、所述第一材料层和所述第三材料层。
  36. 根据权利要求35所述的方法，其中，所述第一沟道层形成为第一厚度与第二厚度之和，回蚀的量为所述第二厚度，所述第二沟道层形成为所述第二厚度，且所述第三沟道层形成为所述第一厚度。
  37. 根据权利要求33至36中任一项所述的方法，其中，以下至少之一成立：
    所述第一沟道层和所述第三沟道层包括与所述栅堆叠具有改进界面质量的材料，所述第二沟道层包括具有高载流子迁移率的材料；
    所述第一沟道层和所述第三沟道层包括具有高载流子迁移率的材料，所述第二沟道层包括能够优化载流子分布的材料；或者
    对于n型器件，所述第一沟道层和所述第三沟道层包括的材料的导带的最低能级高于所述第二沟道层包括的材料的导带的最低能级；或者对于p型器件，所述第一沟道层和所述第三沟道层包括的材料的价带的最高能级低于所述第 二沟道层包括的材料的价带的最高能级。
  38. 根据权利要求37所述的方法，其中，所述第一沟道层与所述第二沟道层包括Si，所述第三沟道层包括SiGe或Ge。
  39. 根据权利要求37所述的方法，其中，所述第一沟道层与所述第二沟道层具有基本相同的第一厚度，所述第三沟道层具有第二厚度。
  40. 根据权利要求37所述的方法，其中，
    去除所述第一位置保持层、所述第二位置保持层和所述第三位置保持层包括：首先去除第一位置保持层，
    所述方法还包括：在所述第一沟道层和所述第三沟道层由于所述第一位置保持层的去除而露出的端部上形成第四沟道层，以将所述第一沟道层和所述第三沟道层的暴露端部彼此连接。
  41. 根据权利要求31或32所述的方法，其中，所述第一材料层是所述衬底的上部，或者是所述衬底上的外延层。
  42. 根据权利要求31或32所述的方法，其中，所述第二材料层相对于所述第一材料层、所述第三材料层具有刻蚀选择性。
  43. 根据权利要求31或32所述的方法，其中，使所述第二材料层的侧壁凹入包括各向同性刻蚀。
  44. 根据权利要求31或32所述的方法，其中，形成沟道层包括选择性外延生长。
  45. 根据权利要求31或32所述的方法，其中，形成源/漏部包括：
    在所述脊状结构的侧壁上形成掺杂剂源层；以及
    将所述掺杂剂源层中的掺杂剂驱入所述第一材料层和所述第三材料层中。
  46. 根据权利要求31或32所述的方法，其中，在形成源/漏部之后且在形成开口之前，该方法还包括：
    回蚀所述第一材料层和所述第三材料层，使得所述第一材料层和所述第三材料层的侧壁横向凹进；以及
    在所述第一材料层和所述第三材料层由于横向凹进而留出的空间中形成电介质层。
  47. 根据权利要求31或32所述的方法，其中，在形成第三位置保持层之 后，该方法还包括：
    通过所述开口回蚀所述第一材料层和所述第三材料层，使得所述第一材料层和所述第三材料层在所述开口中露出的侧壁横向凹进；以及
    在所述第一材料层和所述第三材料层由于横向凹进而留出的空间中形成电介质层。
  48. 根据权利要求31所述的方法，其中，在限定第二凹入部之后，且在形成第一沟道层之前，该方法还包括：
    将所述脊状结构的外露表面回蚀与将要形成的第一沟道层的厚度基本上相同的厚度。
  49. 一种电子设备，包括如权利要求1至30中任一项所述的半导体器件。
  50. 根据权利要求49所述的电子设备，包括智能电话、计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源。
PCT/CN2020/139254 2020-01-21 2020-12-25 C形沟道部半导体器件及其制造方法及包括其的电子设备 WO2021147610A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/759,226 US20230064415A1 (en) 2020-01-21 2020-12-25 Semiconductor device with c-shaped channel portion, method of manufacturing the same, and electronic apparatus including the same

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN202010072920.X 2020-01-21
CN202010073094.0 2020-01-21
CN202010073094 2020-01-21
CN202010072920 2020-01-21
CN202010445827.9A CN111384156B (zh) 2020-01-21 2020-05-22 C形沟道部半导体器件及其制造方法及包括其的电子设备
CN202010445827.9 2020-05-22

Publications (1)

Publication Number Publication Date
WO2021147610A1 true WO2021147610A1 (zh) 2021-07-29

Family

ID=71219107

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/139254 WO2021147610A1 (zh) 2020-01-21 2020-12-25 C形沟道部半导体器件及其制造方法及包括其的电子设备

Country Status (3)

Country Link
US (1) US20230064415A1 (zh)
CN (1) CN111384156B (zh)
WO (1) WO2021147610A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111384156B (zh) * 2020-01-21 2021-08-03 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备
CN112582464A (zh) * 2020-12-11 2021-03-30 中国科学院微电子研究所 应变竖直沟道半导体器件及其制造方法及包括其的电子设备
CN113178484B (zh) * 2021-03-03 2024-05-03 中国科学院微电子研究所 一种薄电容耦合晶闸管及薄电容耦合晶闸管的制备方法
CN113745346B (zh) * 2021-08-27 2024-05-14 中国科学院微电子研究所 具有双栅结构的半导体器件及其制造方法及电子设备
CN114093949B (zh) * 2021-11-01 2024-04-26 中国科学院微电子研究所 抑制gidl的mosfet及其制造方法及包括mosfet的电子设备
CN117673167A (zh) * 2022-08-31 2024-03-08 华为技术有限公司 一种芯片及其制备方法、电子设备
CN116885004B (zh) * 2023-07-06 2024-05-14 长鑫存储技术有限公司 一种半导体结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089003A1 (en) * 1999-06-29 2002-07-11 Hyundai Electronics Industries Co., Ltd. Transistor in a semiconductor device and method of manufacturing the same
CN103811345A (zh) * 2012-11-09 2014-05-21 中国科学院微电子研究所 半导体器件及其制造方法
CN107887440A (zh) * 2016-09-30 2018-04-06 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
CN109326650A (zh) * 2018-10-10 2019-02-12 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
CN111384156A (zh) * 2020-01-21 2020-07-07 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102422240B1 (ko) * 2016-05-26 2022-07-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
WO2019035945A1 (en) * 2017-08-16 2019-02-21 Tokyo Electron Limited METHOD AND DEVICE FOR INCORPORATING SINGLE DIFFUSION BREAK IN NANOCANAL STRUCTURES OF FET DEVICES
US10651291B2 (en) * 2017-08-18 2020-05-12 Globalfoundries Inc. Inner spacer formation in a nanosheet field-effect transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089003A1 (en) * 1999-06-29 2002-07-11 Hyundai Electronics Industries Co., Ltd. Transistor in a semiconductor device and method of manufacturing the same
CN103811345A (zh) * 2012-11-09 2014-05-21 中国科学院微电子研究所 半导体器件及其制造方法
CN107887440A (zh) * 2016-09-30 2018-04-06 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
CN109326650A (zh) * 2018-10-10 2019-02-12 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
CN111384156A (zh) * 2020-01-21 2020-07-07 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备

Also Published As

Publication number Publication date
CN111384156B (zh) 2021-08-03
CN111384156A (zh) 2020-07-07
US20230064415A1 (en) 2023-03-02

Similar Documents

Publication Publication Date Title
WO2021147610A1 (zh) C形沟道部半导体器件及其制造方法及包括其的电子设备
WO2021104364A1 (zh) 半导体装置及其制造方法及包括该半导体装置的电子设备
WO2023024299A1 (zh) 具有双栅结构的半导体器件及其制造方法及电子设备
CN111048588B (zh) 半导体器件及其制造方法及包括该半导体器件的电子设备
US20230317838A1 (en) Nanowire/nanosheet device having self-aligned isolation portion and method of manufacturing the same, and electronic apparatus
US20220190169A1 (en) Strained vertical channel semiconductor device, method of manufacturing the same, and electronic apparatus including the same
US11482627B2 (en) C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same
US11532743B2 (en) Semiconductor device with U-shaped channel and manufacturing method thereof, and electronic apparatus including the same
US11677001B2 (en) Semiconductor device with c-shaped channel portion, method of manufacturing the same, and electronic apparatus including the same
US11532756B2 (en) C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same
US20240096709A1 (en) Semiconductor device with spacer and c-shaped channel portion, method of manufacturing semiconductor device with spacer and c-shaped channel portion, and electronic apparatus
US11616150B2 (en) Semiconductor device with C-shaped channel portion and electronic apparatus including the same
US11424323B2 (en) Semiconductor device with c-shaped active area and electronic apparatus including the same
WO2021213115A1 (zh) 具有u形结构的半导体器件及其制造方法及电子设备
CN215988757U (zh) C形沟道部存储器件
CN116666439B (zh) 具有连续栅长的竖直半导体器件及其制造方法及电子设备
CN114093949B (zh) 抑制gidl的mosfet及其制造方法及包括mosfet的电子设备
CN111063683B (zh) 具有u形沟道的半导体装置及包括其的电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20915670

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20915670

Country of ref document: EP

Kind code of ref document: A1