CN103811345A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN103811345A
CN103811345A CN201210448458.4A CN201210448458A CN103811345A CN 103811345 A CN103811345 A CN 103811345A CN 201210448458 A CN201210448458 A CN 201210448458A CN 103811345 A CN103811345 A CN 103811345A
Authority
CN
China
Prior art keywords
semiconductor layer
fin
substrate
layer
separator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210448458.4A
Other languages
English (en)
Other versions
CN103811345B (zh
Inventor
朱慧珑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201210448458.4A priority Critical patent/CN103811345B/zh
Priority to PCT/CN2012/085248 priority patent/WO2014071659A1/zh
Publication of CN103811345A publication Critical patent/CN103811345A/zh
Priority to US14/705,835 priority patent/US9564434B2/en
Application granted granted Critical
Publication of CN103811345B publication Critical patent/CN103811345B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请公开了一种半导体器件及其制造方法。一示例方法可以包括：在衬底上依次形成第一半导体层和第二半导体层；对第二半导体层、第一半导体层进行构图，以形成初始鳍；选择性刻蚀初始鳍中的第一半导体层，使其横向凹入；在所述横向凹入中填充电介质，以形成体侧墙；在衬底上形成隔离层，所述隔离层露出所述体侧墙的一部分，从而限定出位于隔离层上方的鳍；以及在隔离层上形成横跨鳍的栅堆叠。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着平面型半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了立体型半导体器件如FinFET(鳍式场效应晶体管)。一般而言，FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅极。因此，沟道区形成于鳍中，且其宽度主要由鳍的高度决定。然而，在集成电路制造工艺中，难以控制晶片上形成的鳍的高度相同，从而导致晶片上器件性能的不一致性。
另一方面，在鳍的底部，栅与鳍由于之间的电介质而形成寄生电容。这种寄生电容过大，会使得器件的响应时间过长。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成第一半导体层和第二半导体层；对第二半导体层、第一半导体层进行构图，以形成初始鳍；选择性刻蚀初始鳍中的第一半导体层，使其横向凹入；在所述横向凹入中填充电介质，以形成体侧墙；在衬底上形成隔离层，所述隔离层露出所述体侧墙的一部分，从而限定出位于隔离层上方的鳍；以及在隔离层上形成横跨鳍的栅堆叠。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；在衬底上依次形成的构图的第一半导体层和第二半导体层；在衬底上形成的隔离层，所述隔离层的顶面位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；以及在隔离层上形成的横跨鳍的栅堆叠，其中，第一半导体层相对于第二半导体层横向凹入，且该半导体器件还包括在所述横向凹入中形成的体侧墙。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-13是示出了根据本公开实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，可以在衬底上例如通过外延形成至少一个半导体层。这样，在例如通过刻蚀来构图鳍时，为形成相同高度的鳍，刻蚀进入衬底中的深度相对于常规技术可以减小(甚至可以为零，这种情况下，完全通过所述至少一个半导体层来形成鳍)，从而可以更加容易控制刻蚀深度的一致性。此外，外延层的厚度一致性可以相对容易地控制，结果，可以改善最终形成的鳍的厚度的一致性。
根本公开的优选实施例，所述至少一个半导体层包括两个或更多的半导体层。在这些半导体层中，相邻的半导体层可以相对于彼此具有刻蚀选择性，从而可以选择性刻蚀每一半导体层。在形成鳍之后，可以选择性刻蚀其中的某一层(或多层)，使其横向变窄(凹入)。可以在这种横向凹入中填充电介质，以形成体侧墙(body spacer)。另外，如此形成隔离层，使得隔离层露出体侧墙的一部分。从而体侧墙位于最终形成鳍的底部(初始形成鳍被隔离层所包围的部分不再充当用来形成沟道的真正鳍)。
这样，在最终形成鳍的底部，由于体侧墙，随后形成的栅与鳍之间的电介质层较厚，从而形成的寄生电容相对较小。
根据本公开的实施例，隔离层可以通过在衬底上淀积电介质材料然后回蚀来形成。电介质材料可以基本上覆盖所形成的初始鳍，且位于初始鳍顶部的电介质材料厚度充分小于位于衬底上的电介质材料厚度，例如初始鳍顶部的电介质材料厚度可以小于位于衬底上的电介质材料厚度的三分之一，优选为四分之一。例如，这可以通过高密度等离子体(HDP)淀积来实现。另外，在形成多个初始鳍的情况下，位于每一初始鳍的顶面之上的电介质材料的厚度可以小于与其相邻的鳍之间间距的二分之一。这样，在随后的回蚀中，可以减少刻蚀深度，从而能够增加刻蚀控制精度。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1000中，可以形成n型阱1000-1和p型阱1000-2，以供随后在其中分别形成n型器件和p型器件。例如，n型阱1000-1可以通过在衬底1000中注入n型杂质如P或As来形成，p型阱1000-2可以通过在衬底1000中注入p型杂质如B来形成。如果需要，在注入之后还可以进行退火。本领域技术人员能够想到多种方式来形成n型阱、p型阱，在此不再赘述。
这里需要指出的是，尽管在以下描述中说明了分别在n型阱和p型阱中形成互补器件的工艺，但是本公开不限于此。例如，本公开同样适用于非互补工艺。而且，以下涉及互补器件的一些处理，在某些实现方式中并非是必须的。
在衬底1000上，例如通过外延生长，形成第一半导体层1002。例如，第一半导体层1002可以包括SiGe(Ge原子百分比例如为约5-20％)，厚度为约10-50nm。在外延生长第一半导体层的过程中，可以对其进行原位掺杂，例如通过B而掺杂为p型。第一半导体层的掺杂浓度可以高于之下的p型阱的掺杂浓度，例如可为1E18-2E19cm-3。根据一示例，为降低B扩散，可以在p型第一半导体层1002中注入C。
然后，可以通过光刻胶(未示出)遮挡p型阱区上的第一半导体层，并向n型阱区上的第一半导体层注入杂质如As或P，以将该部分第一半导体层转换为n型，且其掺杂浓度可以高于之下的n型阱的掺杂浓度。注入浓度例如可以是2E18-4E19cm-3。之后可以去除光刻胶。于是，形成了n型第一半导体层1002-1和p型第一半导体层1002-2。
接下来，在第一半导体层1002(包括1002-1和1002-2)上，例如通过外延生长，形成第二半导体层1004。例如，第二半导体层1004可以包括Si，厚度为约20-100nm。
在第二半导体层1004上，可以形成保护层1006。保护层1006例如可以包括氧化物(例如，氧化硅)，厚度为约10-50nm。这种保护层1006可以在随后的处理中保护鳍的端部。
随后，可以对如此形成的第二半导体层1004、第一半导体层1002和衬底进行构图，以形成初始鳍。例如，这可以如下进行。具体地，在保护层1006上按设计形成构图的光刻胶1008。通常，光刻胶1008被构图为一系列平行的等间距线条。然后，如图2所示，以构图的光刻胶1008为掩模，依次选择性刻蚀例如反应离子刻蚀(RIE)保护层1006、第二半导体层1004、第一半导体层1002和衬底1000，从而形成初始鳍。
在互补工艺的情况下，还可以如图3所示，来在n型区域和p型区域之间形成隔离。具体地，可以在衬底上形成光刻胶1010，并对光刻胶1010进行构图，以露出n型区域和p型区域之间界面周围的一定区域。然后，通过选择性刻蚀例如RIE，去除该区域存在的保护层、第二半导体层、第一半导体层。也可以进一步选择性刻蚀如RIE衬底。从而在n型区域和p型区域之间形成隔离地带，该隔离地带随后可以被电介质所填充。然后，可以去除光刻胶1010。
可以看到，在图2的操作中，形成初始鳍的刻蚀步骤进入到衬底1000中；然后，通过图3中的操作，可以使得p型阱和n型阱之间的接触面积(即，形成的pn结的面积)较小。但是，本公开不限于此。例如，在非互补工艺，或者在单一类型(p型或n型)器件的局部区域，图2中对第一半导体层1002的刻蚀可以停止于衬底1000，并且随后不再对衬底1000进行刻蚀也是可行的；图3所示的操作可能也并非是必须的。通过刻蚀所形成的(初始鳍之间的)沟槽的形状不一定是图2中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥台形。另外，所形成的初始鳍的位置和数目不限于图2所示的示例。
在图2所示的示例中，在n型阱1000-1和p型阱1000-2之间的界面处，也形成了初始鳍。由于图3所示的隔离形成工艺，该初始鳍也被去除。于是，得到了图4所示的结构。
为了减小最终形成鳍底部的寄生电容，如图5所示，可以相对于保护层1006(例如，氧化硅)、衬底1000和第二半导体层1004(例如，Si)，选择性刻蚀第一半导体层1002(例如，SiGe)，使得第一半导体层1002横向凹入。因此，初始鳍中由第一半导体层构成的部分变窄。
然后，如图6所示，在横向凹入中填充电介质，以形成体侧墙1012。例如，这种填充例如可以通过淀积电介质，然后回蚀(例如，RIE)来实现。体侧墙1012可以包括氮化物(例如，氮化硅)或低K电介质如SiOF、SiCOH、SiO、SiCO、SiCON。在淀积的电介质包括氮化物的示例中，在淀积电介质之前，可选地可以淀积一层薄氧化物(未示出)作为垫层，以便缓解氮化物的应力。
在通过上述处理形成具有体侧墙的初始鳍之后，可以形成横跨鳍的栅堆叠，并形成最终的半导体器件。
为了隔离栅堆叠和衬底，在衬底上首先形成隔离层。这种隔离层例如可以通过在衬底上淀积电介质材料，且然后进行回蚀来形成。在回蚀过程中，控制回蚀深度，使得回蚀后的隔离层能够使体侧墙的一部分露出(相对于隔离层的顶面突出)。例如，隔离层可以包括高密度等离子体(HDP)氧化物(例如，氧化硅)。
在此，为了改善回蚀之后隔离层(顶面的)高度的一致性，并因此改善最终形成的鳍的高度的一致性，如图7所示，在淀积电介质材料1014的过程中，使得电介质材料1014基本上覆盖初始鳍(在多个初始鳍的情况下，基本上填充初始鳍之间的间隙)。根据本公开的实施例，可以如此淀积，使得初始鳍顶部的电介质材料厚度充分小于位于衬底上的电介质材料厚度，并且一般来说初始鳍顶部的电介质材料厚度都小于位于衬底上的电介质材料厚度的三分之一，优选为四分之一。例如，每一初始鳍顶部的电介质材料厚度一般不大于20nm，而位于衬底上的电介质材料厚度可达100nm左右。
根据本公开的一示例，电介质材料1014可以包括通过高密度等离子体(HDP)淀积形成的氧化物(例如，氧化硅)。由于HDP的特性，在淀积过程中可以使得初始鳍顶部的电介质材料(沿垂直于衬底方向的)厚度和初始鳍侧面的电介质材料(沿平行于衬底的方向，即横向的)厚度要小于初始鳍之间衬底上的电介质材料(沿垂直于衬底方向的)厚度。因为HDP的这种特性，在常规技术中通常并不采用HDP淀积来制作氧化隔离。
在此，例如可以通过控制淀积条件，使得电介质材料1014在基本上覆盖初始鳍时(或者，基本上填充初始鳍之间的空隙时)，位于每一初始鳍顶部上的厚度可以小于与其相邻的初始鳍之间间距的二分之一。如果初始鳍之间的间距并不相同，则可以使电介质材料1014位于每一初始鳍顶部的厚度小于与其相邻的初始鳍之间间距中较小间距的二分之一。
随后，如图8所示，对电介质材料1014进行回蚀。由于电介质材料1014的回蚀深度相对较小，从而对该刻蚀的控制相对容易，并因此可以更加精确地控制从鳍的顶面(在该示例中，第二半导体层1004的顶面)到隔离层1014的顶面的距离(至少部分地决定最终器件的鳍高度并因此决定最终器件的沟道宽度)，使得该距离在衬底上基本保持一致。这样，隔离层就限定了位于其上的鳍。在第一半导体层1002-1和1002-2是如上所述进行掺杂的示例中，其对应的阈值电压要高于第二半导体层1004对应的阈值电压。因此，通过控制栅极控制电压，可以使得第二半导体层导通而第一半导体层并不能导通。这样，最终用作器件的鳍可以仅包括第二半导体层1004，且第一半导体层可以充当穿通阻挡层，防止源漏之间的穿通。
在一个示例中，保护层1006和电介质材料1014包括相同的材料，如氧化物。因此，在对电介质材料1014回蚀的过程中，可能同时去除了保护层1006，如图8所示。
随后，可以在隔离层1014上形成横跨鳍的栅堆叠。例如，这可以如下进行。具体地，如图9所示(图9(b)示出了沿图9(a)中BB′线的截面图)，例如通过淀积，形成栅介质层1018。例如，栅介质层1018可以包括氧化物，厚度为约0.8-1.5nm。在图9所示的示例中，仅示出了“∏”形的栅介质层1016。但是，栅介质层1016也可以包括在隔离层1014的顶面上延伸的部分。然后，例如通过淀积，形成栅导体层1018。例如，栅导体层1018可以包括多晶硅。栅导体层1018可以填充鳍之间的间隙，并可以进行平坦化处理例如化学机械抛光(CMP)。之后，对栅导体层1018进行构图，以形成栅堆叠。在图8的示例中，栅导体层1018被构图为与鳍相交的条形。根据另一实施例，还可以构图后的栅导体层1018为掩模，进一步对栅介质层1016进行构图。
如图9(b)中的椭圆虚线圈所示，在鳍的底部(之下的鳍部分由于被隔离层所包围，从而在最终器件中并不充当用来形成沟道区的真正鳍)，栅导体1018与鳍(在该示例中，第一半导体层)之间存在体侧墙1012，从而产生的寄生电容相对较小。
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。
接下来，如图10(图10(b)示出了沿图10(a)中BB′线的截面图)所示，可以在栅导体层1018的侧壁上形成侧墙1020。例如，可以通过淀积形成厚度约为5-30nm的氮化物，然后对氮化物进行RIE，来形成侧墙1020。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。
在鳍之间的沟槽为从上到下逐渐变小的锥台形时(由于刻蚀的特性，通常为这样的情况)，侧墙1020基本上不会形成于鳍的侧壁上。
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区。这样，就得到了根据该实施例的半导体器件。如图10所示，该半导体器件可以包括：衬底；在衬底上依次形成的构图的第一半导体层和第二半导体层；在衬底上形成的隔离层，所述隔离层的顶面位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；以及在隔离层上形成的横跨鳍的栅堆叠。第一半导体层可以相对于第二半导体层横向凹入，且该半导体器件还可以包括在所述横向凹入中形成的体侧墙。
对于p型器件，第一半导体层中可以掺杂n型杂质；对于n型器件，第一半导体层中可以掺杂p型杂质。这种掺杂的第一半导体层可以充当穿通阻挡层。而且，这种掺杂的第一半导体层可以减少B扩散，从而可以在在沟道区和衬底本体之间形成清晰的结。
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。
根据本公开的另一实施例，在图9中形成的栅介质层1016和栅导体层1018为牺牲栅介质层和牺牲栅导体层。接下来，可以同样按以上结合图9、10描述的方法来进行处理。
接下来，如图11(图11(b)示出了沿图11(a)中BB′线的截面图)所示，例如通过淀积，形成电介质层1022。该电介质层1022例如可以包括氧化物。随后，对该电介质层1022进行平坦化处理例如CMP。该CMP可以停止于侧墙1020，从而露出牺牲栅导体1018。
随后，如图12(图12(b)示出了沿图12(a)中BB′线的截面图，图12(c)示出了沿图12(a)中CC′线的截面图)所示，例如通过TMAH溶液，选择性去除牺牲栅导体1018，从而在侧墙1020内侧形成了空隙1024。根据另一示例，还可以进一步去除牺牲栅介质层1016。
然后，如图13(图13(b)示出了沿图13(a)中BB′线的截面图，图13(c)示出了沿图13(a)中CC′线的截面图)所示，通过在空隙1024中形成栅介质层1026和栅导体层1028，形成最终的栅堆叠。栅介质层1026可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1028可以包括金属栅导体。优选地，在栅介质层1022和栅导体层1024之间还可以形成功函数调节层(未示出)。
这里需要指出的是，在图13中，将栅介质层1026示出为空隙1024底部的一薄层。但是，栅介质层1026还可以形成在空隙1024的侧壁上，从而包围栅导体层1028。
这样，就得到了根据该实施例的半导体器件。该半导体器件与图10所示的半导体器件在结构上基本相同，除了栅堆叠按不同方式形成之外。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (15)

1.一种制造半导体器件的方法，包括：
在衬底上依次形成第一半导体层和第二半导体层；
对第二半导体层、第一半导体层进行构图，以形成初始鳍；
选择性刻蚀初始鳍中的第一半导体层，使其横向凹入；
在所述横向凹入中填充电介质，以形成体侧墙；
在衬底上形成隔离层，所述隔离层露出所述体侧墙的一部分，从而限定出位于隔离层上方的鳍；以及
在隔离层上形成横跨鳍的栅堆叠。
2.根据权利要求1所述的方法，其中，在形成鳍的操作中，还进一步对衬底进行构图。
3.根据权利要求1所述的方法，其中，形成隔离层包括：
在衬底上淀积电介质材料，使得电介质材料实质上覆盖初始鳍，其中位于初始鳍顶部的电介质材料厚度充分小于位于衬底上的电介质材料厚度；以及
对电介质材料进行回蚀。
4.根据权利要求3所述的方法，其中，位于初始鳍顶部的电介质材料厚度小于位于衬底上的电介质材料厚度的三分之一。
5.根据权利要求3所述的方法，其中，其中，通过高密度等离子体(HDP)淀积形成电介质材料。
6.根据权利要求3所述的方法，其中，在衬底上形成多个初始鳍，且位于每一初始鳍顶部的电介质材料厚度小于与其相邻的初始鳍之间间距的二分之一。
7.根据权利要求1所述的方法，其中，对于p型器件，第一半导体层中掺杂n型杂质；对于n型器件，第一半导体层中掺杂p型杂质。
8.根据权利要求1所述的方法，在构图鳍之前，该方法还包括：
在第二半导体层上形成保护层。
9.根据权利要求3所述的方法，其中，
在构图鳍之前，该方法还包括：在第二半导体层上形成保护层，
其中，所述隔离层和所述保护层包括相同的电介质材料。
10.根据权利要求1所述的方法，其中，形成栅堆叠包括：
形成横跨鳍的牺牲栅堆叠；
在牺牲栅堆叠的侧壁上形成侧墙；
在衬底上形成电介质层，并平坦化，以露出牺牲栅堆叠；
选择性去除牺牲栅堆叠，从而侧墙限定空隙；以及
在所述空隙中形成栅堆叠。
11.一种半导体器件，包括：
衬底；
在衬底上依次形成的构图的第一半导体层和第二半导体层；
在衬底上形成的隔离层，所述隔离层的顶面位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；以及
在隔离层上形成的横跨鳍的栅堆叠，
其中，第一半导体层相对于第二半导体层横向凹入，且该半导体器件还包括在所述横向凹入中形成的体侧墙。
12.根据权利要求11所述的半导体器件，其中，衬底包括体Si，第一半导体层包括SiGe，第二半导体层包括Si。
13.根据权利要求11所述的半导体器件，其中，所述体侧墙包括氮化物或低K电介质，所述隔离层包括氧化物。
14.根据权利要求11所述的半导体器件，其中，栅堆叠包括高K栅介质层和金属栅导体层。
15.根据权利要求11所述的半导体器件，其中，对于p型器件，第一半导体层中掺杂n型杂质；对于n型器件，第一半导体层中掺杂p型杂质。
CN201210448458.4A 2012-11-09 2012-11-09 半导体器件及其制造方法 Active CN103811345B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201210448458.4A CN103811345B (zh) 2012-11-09 2012-11-09 半导体器件及其制造方法
PCT/CN2012/085248 WO2014071659A1 (zh) 2012-11-09 2012-11-26 半导体器件及其制造方法
US14/705,835 US9564434B2 (en) 2012-11-09 2015-05-06 Semiconductor device with body spacer at the bottom of the fin and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210448458.4A CN103811345B (zh) 2012-11-09 2012-11-09 半导体器件及其制造方法

Publications (2)

Publication Number Publication Date
CN103811345A true CN103811345A (zh) 2014-05-21
CN103811345B CN103811345B (zh) 2016-08-03

Family

ID=50683972

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210448458.4A Active CN103811345B (zh) 2012-11-09 2012-11-09 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US9564434B2 (zh)
CN (1) CN103811345B (zh)
WO (1) WO2014071659A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261645A (zh) * 2014-07-16 2016-01-20 联华电子股份有限公司 半导体装置及其制作方法
CN105390497A (zh) * 2015-11-05 2016-03-09 中国科学院微电子研究所 包括带电荷体侧墙的cmos器件及其制造方法
CN105405890A (zh) * 2015-11-05 2016-03-16 中国科学院微电子研究所 包括带电荷体侧墙的半导体器件及其制造方法
CN106206580A (zh) * 2014-10-17 2016-12-07 台湾积体电路制造股份有限公司 鳍式场效应晶体管（FinFET）器件及其形成方法
CN111192875A (zh) * 2018-11-14 2020-05-22 长鑫存储技术有限公司 一种半导体结构及其制作方法
WO2021147610A1 (zh) * 2020-01-21 2021-07-29 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103779210A (zh) * 2012-10-18 2014-05-07 中国科学院微电子研究所 FinFET鳍状结构的制造方法
CN103811344B (zh) * 2012-11-09 2016-08-10 中国科学院微电子研究所 半导体器件及其制造方法
US9269628B1 (en) * 2014-12-04 2016-02-23 Globalfoundries Inc. Methods of removing portions of at least one fin structure so as to form isolation regions when forming FinFET semiconductor devices
US9773786B2 (en) * 2015-04-30 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
US9805987B2 (en) * 2015-09-04 2017-10-31 International Business Machines Corporation Self-aligned punch through stopper liner for bulk FinFET
KR102460862B1 (ko) * 2016-08-04 2022-10-28 삼성전자주식회사 반도체 장치
KR102505065B1 (ko) 2018-04-26 2023-03-02 삼성전자주식회사 게이트 분리 영역을 포함하는 반도체 소자
US10529713B2 (en) 2018-06-08 2020-01-07 International Business Machines Corporation Fin field effect transistor devices with modified spacer and gate dielectric thicknesses
US10790395B2 (en) * 2018-06-12 2020-09-29 International Business Machines Corporation finFET with improved nitride to fin spacing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040217434A1 (en) * 2003-05-02 2004-11-04 Lee Sung-Young Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same
US20070102763A1 (en) * 2003-09-24 2007-05-10 Yee-Chia Yeo Multiple-gate transistors formed on bulk substrates
CN102104069A (zh) * 2009-12-16 2011-06-22 中国科学院微电子研究所 鳍式晶体管结构及其制作方法
CN102157554A (zh) * 2010-02-12 2011-08-17 中国科学院微电子研究所 鳍式晶体管结构及其制作方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8912602B2 (en) * 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9087725B2 (en) * 2009-12-03 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with different fin height and EPI height setting

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040217434A1 (en) * 2003-05-02 2004-11-04 Lee Sung-Young Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same
US20070102763A1 (en) * 2003-09-24 2007-05-10 Yee-Chia Yeo Multiple-gate transistors formed on bulk substrates
CN102104069A (zh) * 2009-12-16 2011-06-22 中国科学院微电子研究所 鳍式晶体管结构及其制作方法
CN102157554A (zh) * 2010-02-12 2011-08-17 中国科学院微电子研究所 鳍式晶体管结构及其制作方法

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261645A (zh) * 2014-07-16 2016-01-20 联华电子股份有限公司 半导体装置及其制作方法
US10686077B2 (en) 2014-10-17 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10964819B2 (en) 2014-10-17 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
CN106206580A (zh) * 2014-10-17 2016-12-07 台湾积体电路制造股份有限公司 鳍式场效应晶体管（FinFET）器件及其形成方法
US11721762B2 (en) 2014-10-17 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10164109B2 (en) 2014-10-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US11158744B2 (en) 2014-10-17 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10546956B2 (en) 2014-10-17 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10840378B2 (en) 2014-10-17 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
CN105390497A (zh) * 2015-11-05 2016-03-09 中国科学院微电子研究所 包括带电荷体侧墙的cmos器件及其制造方法
CN105405890A (zh) * 2015-11-05 2016-03-16 中国科学院微电子研究所 包括带电荷体侧墙的半导体器件及其制造方法
CN105390497B (zh) * 2015-11-05 2019-01-18 中国科学院微电子研究所 包括带电荷体侧墙的cmos器件及其制造方法
CN105405890B (zh) * 2015-11-05 2018-07-20 中国科学院微电子研究所 包括带电荷体侧墙的半导体器件及其制造方法
CN111192875A (zh) * 2018-11-14 2020-05-22 长鑫存储技术有限公司 一种半导体结构及其制作方法
WO2021147610A1 (zh) * 2020-01-21 2021-07-29 中国科学院微电子研究所 C形沟道部半导体器件及其制造方法及包括其的电子设备

Also Published As

Publication number Publication date
US20150270263A1 (en) 2015-09-24
US9564434B2 (en) 2017-02-07
CN103811345B (zh) 2016-08-03
WO2014071659A1 (zh) 2014-05-15

Similar Documents

Publication Publication Date Title
CN103811345A (zh) 半导体器件及其制造方法
CN103811341B (zh) 半导体器件及其制造方法
CN103811344A (zh) 半导体器件及其制造方法
US9508604B1 (en) Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers
CN111584486B (zh) 具有交错结构的半导体装置及其制造方法及电子设备
CN103928335B (zh) 半导体器件及其制造方法
CN103811346A (zh) 半导体器件及其制造方法
CN103811320B (zh) 半导体器件及其制造方法
US9966456B1 (en) Methods of forming gate electrodes on a vertical transistor device
CN103928333A (zh) 半导体器件及其制造方法
CN103928334B (zh) 半导体器件及其制造方法
US9129989B1 (en) Semiconductor device and method for manufacturing the same
CN111106176B (zh) 半导体器件及其制造方法及包括该半导体器件的电子设备
CN103811340A (zh) 半导体器件及其制造方法
CN103855009A (zh) 鳍结构制造方法
CN105390497A (zh) 包括带电荷体侧墙的cmos器件及其制造方法
KR20210125064A (ko) 반도체 디바이스, 그 제조 방법 및 상기 반도체 디바이스를 포함하는 전자 기기
CN103811339A (zh) 半导体器件及其制造方法
CN103000664B (zh) 半导体器件及其制造方法
CN103854981A (zh) 鳍结构制造方法
CN103985749A (zh) 半导体设置及其制造方法
CN105514109A (zh) Nand存储串及其制造方法、3d nand存储器
CN105405890B (zh) 包括带电荷体侧墙的半导体器件及其制造方法
CN105374878B (zh) 包括带电荷穿通阻止层以降低穿通的半导体器件及其制造方法
CN105489606A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant