CN103855009A - 鳍结构制造方法 - Google Patents

鳍结构制造方法 Download PDF

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CN103855009A
CN103855009A CN201210505760.9A CN201210505760A CN103855009A CN 103855009 A CN103855009 A CN 103855009A CN 201210505760 A CN201210505760 A CN 201210505760A CN 103855009 A CN103855009 A CN 103855009A
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layer
side wall
pattern
fin
substrate
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CN103855009B (zh
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朱慧珑
罗军
李春龙
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Institute of Microelectronics of CAS
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Priority to PCT/CN2012/086743 priority patent/WO2014082351A1/zh
Priority to US14/647,360 priority patent/US9419112B2/en
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Abstract

本申请公开了一种鳍结构制造方法。一示例方法可以包括：在衬底上形成构图的图案转移层；在图案转移层的侧壁上形成第一侧墙；在第一侧墙的侧壁上形成第二侧墙；选择性去除图案转移层和第一侧墙；以及以第二侧墙为掩模，对衬底进行构图，以形成初始鳍。

Description

鳍结构制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种鳍结构的制造方法。
背景技术
随着平面型半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了立体型半导体器件如鳍式场效应晶体管(FinFET)。一般而言，FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅堆叠。因此，可以在鳍的侧壁上形成导电沟道。
一般而言，鳍可以通过对衬底或者衬底上另外形成的半导体层进行构图而得到。但是，由于构图工艺如光刻、反应离子刻蚀(RIE)等的限制，得到的鳍通常具有较大的线边缘粗糙度(LER)。
发明内容
本公开的目的至少部分地在于提供一种鳍制造方法。
根据本公开的一个方面，提供了一种制造鳍结构的方法，包括：在衬底上形成构图的图案转移层；在图案转移层的侧壁上形成第一侧墙；在第一侧墙的侧壁上形成第二侧墙；选择性去除图案转移层和第一侧墙；以及以第二侧墙为掩模，对衬底进行构图，以形成初始鳍。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-19是示出了根据本公开实施例的制造鳍结构流程的示意图图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
通常，为了对衬底或者衬底上的材料层进行构图，可以在衬底或者材料层上形成掩模层(例如，光刻胶)，然后将该掩模层构图为所需的图案(例如，对于光刻胶，通过曝光、显影来构图)，并以构图后的掩模层为掩模，继续对衬底或材料层进行构图(例如，通过RIE)。在这种工艺中，存在多种导致LER的因素，例如，掩模层的构图(或者说，光刻)、RIE等。
代替上述常规工艺，根据本公开的示例，可以在衬底或材料层上形成构图的图案转移层。同样，该图案转移层由于构图处理而可能遭受LER的困扰。在该图案转移层的侧壁上，可以通过侧墙(spacer)形成工艺，来形成第一侧墙。这种通过侧墙形成工艺所形成的侧墙的侧壁一般而言具有的LER比直接利用掩模层通过构图(例如，RIE)获得的特征的侧壁(例如，图案转移层的侧壁)的LER要小。因此，如此得到的第一侧墙尽管在与图案转移层相接触一侧的侧壁具备与图案转移层的侧壁相应的LER，但是第一侧墙在与图案转移层相反的一侧具有LER较小的侧壁。
接着，可以在第一侧墙的外侧侧壁(即，具有较小LER的侧壁)上进一步形成第二侧墙。第二侧墙与第一侧墙相接触的一侧的侧壁所具有的LER与第一侧墙的外侧侧壁的LER相对应并因此较小，而第二侧墙与第一侧墙相反的一侧的侧壁如上所述由于是通过侧墙形成工艺形成而具有较小的LER。于是，第二侧墙两侧的侧壁均具有较小LER。
之后，可以选择性去除图案转移层和第一侧墙。这样，就在衬底或材料层上留下了侧壁LER较小的第二侧墙。以该第二侧墙为掩模，对衬底或材料层进行构图，可以获得LER较小的特征(例如，鳍)。
在此，为了选择性去除图案转移层和第一侧墙，可以选择第二侧墙的材料不同于图案转移层和第一侧墙的材料(图案转移层和第一侧墙的材料可以相同或不同)。图案转移层、第一侧墙和第二侧墙各自的材料可以选自非晶硅、多晶硅、氧化物和氮化物中之一。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1000上，例如可以通过淀积形成停止层1002。该停止层1002例如可以包括氧化物(例如，氧化硅)，厚度可以为约10-50nm。在停止层1002上，例如可以通过淀积形成图案转移层1004。该图案转移层1004例如可以包括非晶硅，厚度可以为约100-200nm。
可以根据设计，对图案转移层进行构图。具体地，如图1所示，可以在图案转移层1004上形成构图的掩模层1006(例如，经过曝光、显影的光刻胶)。然后，如图2所示，可以掩模层1006为掩模，例如通过RIE，对图案转移层1004进行构图。这种构图可以停止于停止层1002。在构图之后，可以去除掩模层1006。参见图2a，构图后的图案转移层1004的侧壁可以具有相对较大的LER。
然后，如图3所示，可以通过侧墙形成工艺，来在图案转移层1004的侧壁上形成第一侧墙1008。本领域技术人员知道多种侧墙形成工艺。根据一示例，第一侧墙1008可以如下形成。具体地，可以在衬底上(在该示例中，在停止层1002上)，例如通过淀积形成一侧墙材料层(例如，非晶硅)。该侧墙材料层的厚度可以为约10-60nm。然后，可以对该侧墙材料层进行RIE，使得其仅留于图案转移层1004的侧壁上，并因此形成第一侧墙1008。
参见图3a，第一侧墙1008与图案转移层1004相接触一侧的侧壁与图案转移层1004的侧壁相对应，并可以具有相对较大的LER。而第一侧墙1008与图案转移层1004相反一侧的侧壁可以具有较小的LER，这部分地是因为在侧墙形成工艺中可以不使用掩模。
接着，如图4所示，可以在第一侧墙1008的侧壁上进一步形成第二侧墙1010。本领域技术人员知道多种侧墙形成工艺。根据一示例，第二侧墙1010可以如下形成。具体地，可以在衬底上(在该示例中，在停止层1002上)，例如通过淀积形成另一侧墙材料层(例如，氮化物如氮化硅)。该另一侧墙材料层的厚度可以为约5-30nm。然后，可以相对于停止层1002(例如，氧化物)以及图案转移层1004和第一侧墙1008(例如，非晶硅)对该另一侧墙材料层进行RIE，使得其仅留于第一侧墙1008的侧壁上，并因此形成第二侧墙1010。
参见图4a，第二侧墙1010与第一侧墙1008相接触一侧的侧壁与第一侧墙1008的侧壁相对应，并因此可以具有较小的LER。第二侧墙1010与第一侧墙1008相反一侧的侧壁同样可以具有较小的LER，这部分地是因为在侧墙形成工艺中可以不使用掩模。
然后，如图5所示，可以相对于第二侧墙1010(例如，氮化物)和停止层1002(例如，氧化物)，选择性去除图案转移层1004和第一侧墙1008(例如，非晶硅)。例如，可以通过TMAH，来湿法腐蚀图案转移层1004和第一侧墙1008。于是，留下了第二侧墙1010，其两侧的侧壁的LER均较小，如图5a所示。
在上述示例中，图案转移层1004和第一侧墙1008包括非晶硅，第二侧墙1010包括氮化物。但是本公开不限于此。例如，图案转移层1004和第一侧墙1008可以包括氮化物，而第二侧墙1010可以包括非晶硅。只要能够相对于第二侧墙1010(以及衬底)选择性去除图案转移层1004和第一侧墙1008即可。
另外，图案转移层1004和第一侧墙1008也可以包括不同的材料。例如，图案转移层1004可以包括非晶硅，第一侧墙1008可以包括多晶硅(这种情况下，第一侧墙1010可以包括氮化物)。
另外，在图案转移层1004与衬底1000之间具有充分的刻蚀选择性的情况下，可以去除停止层1002。例如，在衬底1000包括Si的示例中，图案转移层1004(和第一侧墙1004)可以包括SiGe，第二侧墙1010可以包括氮化物。
随后，如图6所示，可以侧壁LER较小的第二侧墙1010为掩模，对衬底1000进行构图(例如，通过RIE)，以形成初始鳍1012。之后，可以去除第二侧墙1010。由于第二侧墙1010的侧壁的LER较小，由此形成的初始鳍1012的侧壁也具有相对较小的LER。
这里需要指出的是，在图6所示的示例中，通过第二侧墙1010形成了两个初始鳍1012。但是，本公开不限于此。例如，可以形成另外的第二侧墙，并由此形成另外的初始鳍1012。
另外，初始鳍不限于通过直接对衬底本身进行构图来形成。例如，可以在衬底上外延生长另外的半导体层，对该另外的半导体层进行构图来形成初始鳍。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性，则在对初始鳍进行构图时，可以使构图基本上停止于衬底，从而实现对初始鳍高度的较精确控制。
因此，在本公开中，表述“对衬底进行构图，以形成初始鳍”包括以任何适当的方式对衬底本身或者衬底上的材料层进行构图以形成鳍。在后一种情况下，可以认为材料层构成了衬底的一部分。
在通过上述处理形成初始鳍之后，可以在衬底上形成隔离层。
具体地，如图7所示，可以在衬底上例如通过淀积形成电介质层1014，以覆盖形成的初始鳍1012。例如，电介质层1014可以包括氧化物。在该示例中，由于电介质层1014与停止层1002包括相同的材料(氧化物)，因此在后继附图中不再单独示出停止层1002。
然后，可以相对于初始鳍1012(例如，Si)，回蚀电介质层1014，以露出初始鳍1012的一部分。初始鳍1012的露出部分随后可以用作最终器件的鳍。回蚀后的电介质层1014构成隔离层。
为了使得隔离层的顶面相对平坦，在回蚀电介质层1014之前可以对其进行平坦化处理，例如化学机械抛光(CMP)等。但是，CMP通常难以将表面平坦度控制在几个纳米以内。因此，根据本公开的一示例，为了改善隔离层的表面平坦度，如图8所示，可以通过溅射(sputtering)，对电介质层1014进行平坦化处理。例如，溅射可以使用等离子体如Ar或N等离子体等。在此，例如可以根据等离子体溅射对电介质层1014的切削速度，控制溅射的参数例如溅射功率或气压来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段以充分平滑电介质层1014的表面。尽管在图8中示出了微观上的起伏，但是事实上电介质层1014的顶面具有充分的平坦度，其起伏可以控制在例如几个纳米之内。
另一方面，在图8所示的示例中，等离子体溅射可以在到达初始鳍1012的顶面之前结束，以避免对初始鳍1012造成过多的损伤。根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的电介质层1014进行少许CMP。
接下来，如图9所示，对平坦化的电介质层1014进行回蚀(例如，RIE)，得到隔离层1014。由于回蚀之前电介质层1014的表面通过溅射而变得平滑，所以回蚀之后隔离层1014的表面在衬底上基本上保持一致。
为改善器件性能，根据本公开的一示例，还可以如图10中的箭头所示，通过注入来形成穿通阻挡部(参见图11所示的1016)。例如，对于n型器件而言，可以注入p型杂质，如B、BF2或In；对于p型器件，可以注入n型杂质，如As或P。离子注入可以垂直于衬底表面。控制离子注入的参数，使得穿通阻挡部大致形成于初始鳍位于隔离层1014表面之下的部分中，并且具有期望的掺杂浓度。应当注意，由于初始鳍的形状因子，一部分掺杂剂(离子或元素)可能从初始鳍的露出部分散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。可以进行退火，以激活注入的杂质。这种穿通阻挡部有助于减小源漏泄漏。
随后，可以在隔离层1014上形成横跨鳍的栅堆叠。例如，这可以如下进行。具体地，如图11所示，例如通过淀积，形成栅介质层1018。例如，栅介质层1018可以包括氧化物，厚度为约0.8-1.5nm。在图11所示的示例中，仅示出了“∏”形的栅介质层1018。但是，栅介质层1018也可以包括在隔离层1014的顶面上延伸的部分。
然后，例如通过淀积，形成栅导体层1020。例如，栅导体层1020可以包括多晶硅。栅导体层1020的厚度例如可以为约30-200nm，从而填充鳍之间的间隙。可以对栅导体层1020进行平坦化。同样，这种平坦化也可以通过溅射来进行，如图12所示。
之后，如图13(图13(b)示出了沿图13(a)中BB′线的截面图)所示，对栅导体层1020进行构图，以形成栅堆叠。在图13的示例中，栅导体层1020被构图为与鳍相交的条形。根据另一实施例，还可以构图后的栅导体层1020为掩模，进一步对栅介质层1018进行构图。
在图12和图13(b)中，示出了平坦化后的栅导体层1020表面存在的微观起伏。事实上，这种起伏是相当小的，例如，可以在几个纳米之内。在后继的附图中，为了方便起见，不再示出这种微观起伏。
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。
接下来，如图14(图14(b)示出了沿图14(a)中BB′线的截面图，图14(c)示出了沿图14(a)中CC′线的截面图)所示，可以在栅导体层1020的侧壁上形成侧墙1022。例如，可以通过淀积形成厚度约为5-20nm的氮化物，然后对氮化物进行RIE，来形成侧墙1022。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。在鳍之间的沟槽为从上到下逐渐变小的锥台形时(由于刻蚀的特性，通常为这样的情况)，侧墙1022基本上不会形成于鳍的侧壁上。
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区，得到FinFET。
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。另外，还可以应用应变源/漏技术。
根据本公开的另一实施例，在图11中形成的栅介质层1018和栅导体层1020为牺牲栅介质层和牺牲栅导体层。接下来，可以同样按以上结合图12-14描述的方法来进行处理。
然后，如图15所示(图15(b)示出了沿图15(a)中BB′线的截面图，图15(c)示出了沿图15(a)中CC′线的截面图)，首先选择性去除(例如，RIE)暴露在外的牺牲栅介质层1018。在牺牲栅介质层1018和隔离层1014均包括氧化物的情况下，由于牺牲栅介质层1018较薄，因此对牺牲栅介质层1018的RIE基本上不会影响隔离层1014。在以上形成牺牲栅堆叠的过程中，以牺牲栅导体为掩模进一步构图牺牲栅介质层的情况下，不再需要该操作。
然后，可以选择性去除(例如，RIE)由于牺牲栅介质层1018的去除而露出的初始鳍1012的部分。对初始鳍1012该部分的刻蚀可以进行至露出穿通阻挡部1016。由于牺牲栅堆叠(牺牲栅介质层、牺牲栅导体和侧墙)的存在，初始鳍1012可以留于牺牲栅堆叠下方。
接下来，如图16所示(图16(b)示出了沿图16(a)中BB′线的截面图，图16(c)示出了沿图16(a)中CC′线的截面图)，例如可以通过外延，在露出的初始鳍部分上形成半导体层1024。随后可以在该第三半导体层1024中形成源/漏区。根据本公开的一实施例，可以在生长半导体层1024的同时，对其进行原位掺杂。例如，对于n型器件，可以进行n型原位掺杂；而对于p型器件，可以进行p型原位掺杂。另外，为了进一步提升性能，半导体层1024可以包括不同于鳍1012的材料，以便能够向鳍1012(其中将形成器件的沟道)施加应力。例如，在鳍1012包括Si的情况下，对于n型器件，半导体层1024可以包括Si:C(C的原子百分比例如为约0.2-2％)，以施加拉应力；对于p型器件，半导体层1024可以包括SiGe(例如，Ge的原子百分比为约15-75％)，以施加压应力。
在牺牲栅导体层1020包括多晶硅的情况下，半导体层1024的生长可能也会发生在牺牲栅导体层1020的顶面上。这在附图中并未示出。
接下来，如图17(图17(b)示出了沿图17(a)中BB′线的截面图，图17(c)示出了沿图17(a)中CC′线的截面图)所示，例如通过淀积，形成另一电介质层1026。该电介质层1026例如可以包括氧化物。随后，对该电介质层1026进行平坦化处理例如CMP。该CMP可以停止于侧墙1022，从而露出牺牲栅导体1020。
随后，如图18(图18(b)示出了沿图18(a)中BB′线的截面图，图18(c)示出了沿图18(a)中CC′线的截面图)所示，例如通过TMAH溶液，选择性去除牺牲栅导体1020，从而在侧墙1022内侧形成了空隙1028。根据另一示例，还可以进一步去除牺牲栅介质层1018。
然后，如图19(图19(b)示出了沿图19(a)中BB′线的截面图，图19(c)示出了沿图19(a)中CC′线的截面图)所示，通过在空隙1028中形成栅介质层1030和栅导体层1032，形成最终的栅堆叠。栅介质层1030可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1032可以包括金属栅导体。优选地，在栅介质层1030和栅导体层1032之间还可以形成功函数调节层(未示出)。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (12)

1.一种制造鳍结构的方法，包括：
在衬底上形成构图的图案转移层；
在图案转移层的侧壁上形成第一侧墙；
在第一侧墙的侧壁上形成第二侧墙；
选择性去除图案转移层和第一侧墙；以及
以第二侧墙为掩模，对衬底进行构图，以形成初始鳍。
2.根据权利要求1所述的方法，其中，衬底包括Si，图案转移层包括非晶硅，并且该方法还包括：在衬底上形成停止层，其中图案转移层形成于停止层上。
3.根据权利要求2所述的方法，其中，第一侧墙包括非晶硅，第二侧墙包括氮化物，停止层包括氧化物。
4.根据权利要求1所述的方法，其中，图案转移层与第一侧墙的材料相同或不同，第二侧墙的材料不同于图案转移层和第一侧墙的材料。
5.根据权利要求1所述的方法，其中，图案转移层、第一侧墙以及第二侧墙各自的材料选自非晶硅、多晶硅、氧化物和氮化物中之一。
6.根据权利要求1所述的方法，其中，在形成初始鳍之后，该方法还包括：
在衬底上形成电介质层，以覆盖初始鳍；
通过溅射，对电介质层进行平坦化处理；
进一步对电介质层进行回蚀，以露出初始鳍的一部分，该露出部分用作鳍。
7.根据权利要求6所述的方法，其中，在进一步回蚀之后，该方法还包括：进行离子注入，以在初始鳍位于进一步回蚀后的电介质层的表面下方的部分中形成穿通阻挡层。
8.根据权利要求7所述的方法，其中，在离子注入之后，该方法还包括：
在电介质层上形成横跨鳍的牺牲栅堆叠；
以牺牲栅堆叠为掩模，选择性刻蚀初始鳍，直至穿通阻挡层露出；
在初始鳍的露出部分上形成半导体层，用以形成源/漏区；以及
形成栅堆叠替代牺牲栅堆叠。
9.根据权利要求8所述的方法，其中，形成牺牲栅堆叠包括：
形成牺牲栅介质层；
在牺牲栅介质层上形成牺牲栅导体层，以覆盖鳍；
通过溅射对牺牲栅导体层进行平坦化处理；以及
对栅导体层进行构图，以形成牺牲栅堆叠。
10.根据权利要求8所述的方法，其中，对于p型器件，半导体层带压应力；而对于n型器件，半导体层带拉应力。
11.根据权利要求10所述的方法，其中，衬底包括Si，初始鳍通过对衬底进行构图而形成，半导体层包括SiGe或Si:C。
12.根据权利要求8所述的方法，其中，在形成半导体层时，对半导体层进行原位掺杂。
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