CN103854981A - 鳍结构制造方法 - Google Patents

鳍结构制造方法 Download PDF

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CN103854981A
CN103854981A CN201210505449.4A CN201210505449A CN103854981A CN 103854981 A CN103854981 A CN 103854981A CN 201210505449 A CN201210505449 A CN 201210505449A CN 103854981 A CN103854981 A CN 103854981A
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fin
dielectric layer
initial fin
substrate
semiconductor layer
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朱慧珑
许淼
罗军
李春龙
王桂磊
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210505449.4A priority Critical patent/CN103854981A/zh
Priority to CN201810856787.XA priority patent/CN109216181A/zh
Priority to PCT/CN2012/086657 priority patent/WO2014082350A1/zh
Priority to US14/442,890 priority patent/US9691624B2/en
Publication of CN103854981A publication Critical patent/CN103854981A/zh
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Abstract

本发明公开了一种鳍结构制造方法。一示例方法可以包括：在衬底上形成初始鳍；在衬底上形成电介质层，以覆盖初始鳍；通过溅射，对电介质层平坦化处理；进一步电介质层进行回蚀，以露出初始鳍的一部分，该露出部分用作鳍。

Description

鳍结构制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种鳍结构的制造方法。
背景技术
在半导体工艺中，经常用到平坦化工艺，例如化学机械抛光(CMP)，以获得相对平坦的表面。然而，在通过CMP对材料层进行平坦化的情况下，如果需要研磨掉相对较厚的部分，则难以控制CMP后材料层的表面平坦度，例如控制到几个纳米之内。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造鳍结构的方法，包括：在衬底上形成初始鳍；在衬底上形成电介质层，以覆盖初始鳍；通过溅射，对电介质层平坦化处理；进一步电介质层进行回蚀，以露出初始鳍的一部分，该露出部分用作鳍。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-13是示出了根据本公开实施例的制造鳍结构流程的示意图；
图14、15是示出了根据本公开另一实施例的制造鳍结构流程的部分步骤的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的示例，可以通过溅射(sputtering)，例如Ar或N等离子体溅射，来对材料层进行平坦化处理。通过这种溅射平坦化处理，而非常规的CMP平坦化处理，可以实现更加平坦的材料层表面。这种材料层可以包括半导体制造工艺中使用的多种材料层，例如，包括但不限于绝缘体材料层、半导体材料层和导电材料层。
在一个示例中，本公开可以适用于鳍式场效应晶体管(FinFET)。
通常，FinFET可以如下来制造。例如，可以在衬底上形成初始鳍。然后，在衬底上淀积一层电介质层，以覆盖初始鳍。对于该电介质层，可以进行平坦化处理，例如化学机械抛光(CMP)。接着，可以对电介质层进行回蚀，以形成隔离层，并因此露出初始鳍的一部分。初始鳍的露出部分随后可以用作最终器件的鳍。然而，CMP处理通常难以将表面平坦度控制在几个纳米之内，从而使得回蚀处理的开始表面并非足够平坦，并因此导致最终形成的鳍高度在晶片上存在变化。
根据本公开的实施例，在淀积电介质层之后，可以利用等离子体溅射，来对电介质层进行平坦化处理。这样，可以不使用CMP或者相比于常规技术可以使用较少的CMP。因此，可以改善电介质层回蚀处理的开始表面的一致性。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
可以对衬底1000进行构图，以形成初始鳍。例如，这可以如下进行。具体地，在衬底1000上按设计形成构图的光刻胶1002。通常，光刻胶1002被构图为一系列平行的等间距线条。然后，如图2所示，以构图的光刻胶1002为掩模，刻蚀例如反应离子刻蚀(RIE)衬底1000，从而形成初始鳍1004。之后，可以去除光刻胶1002。
这里需要指出的是，通过刻蚀所形成的(初始鳍之间的)沟槽的形状不一定是图2中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥台形。另外，所形成的初始鳍的位置和数目不限于图2所示的示例。
另外，初始鳍不限于通过直接对衬底进行构图来形成。例如，可以在衬底上外延生长另外的半导体层，对该另外的半导体层进行构图来形成初始鳍。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性，则在对初始鳍进行构图时，可以使构图基本上停止于衬底，从而实现对初始鳍高度的较精确控制。
因此，在本公开中，表述“在衬底上形成初始鳍”包括以任何适当的方式在衬底上形成鳍。
在通过上述处理形成初始鳍之后，可以在衬底上形成隔离层。
具体地，如图3所示，可以在衬底上例如通过淀积形成电介质层1006，以覆盖形成的初始鳍1004。例如，电介质层1006可以包括氧化物(如氧化硅)。
然后，如图4所示，可以对电介质层1006进行溅射，来对电介质层1006进行平坦化处理。例如，溅射可以使用等离子体，如Ar或N等离子体。在此，例如可以根据等离子体溅射对电介质层1006的切削速度，控制溅射参数例如溅射功率和气压等，来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段以充分平滑电介质层1006的表面。另一方面，在图4所示的示例中，等离子体溅射可以在到达初始鳍1004的顶面之前结束，以避免对初始鳍1004造成过多的损伤。
尽管在图4中示出了微观上的起伏，但是事实上电介质层1004的顶面具有充分的平坦度，其起伏可以控制在例如几个纳米之内。
根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的电介质层1006进行少许CMP。
在电介质层1006的表面通过等离子体溅射而变得充分平滑之后，如图5所示，可以对电介质层1006进行回蚀(例如，RIE)，以露出初始鳍1004的一部分，该露出的部分随后可以用作最终器件的鳍。剩余的电介质层1006构成隔离层。由于回蚀之前电介质层1006的表面通过溅射而变得平滑，所以回蚀之后隔离层1006的表面在衬底上基本上保持一致。
为改善器件性能，根据本公开的一示例，还可以如图6中的箭头所示，通过注入来形成穿通阻挡部(参见图7所示的1008)。例如，对于n型器件而言，可以注入p型杂质，如B、BF2或In；对于p型器件，可以注入n型杂质，如As或P。离子注入可以垂直于衬底表面。控制离子注入的参数，使得穿通阻挡部形成于初始鳍位于隔离层1006表面之下的部分中，并且具有期望的掺杂浓度。应当注意，由于初始鳍的形状因子，一部分掺杂剂(离子或元素)可能从初始鳍的露出部分散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。可以进行退火，以激活注入的杂质。这种穿通阻挡部有助于减小源漏泄漏。
随后，可以在隔离层1006上形成横跨鳍的栅堆叠。例如，这可以如下进行。具体地，如图7(图7(b)示出了沿图7(a)中BB′线的截面图)所示，例如通过淀积，形成栅介质层1010。例如，栅介质层1010可以包括氧化物，厚度为约0.8-1.5nm。在图7所示的示例中，仅示出了“∏”形的栅介质层1010。但是，栅介质层1010也可以包括在隔离层1006的顶面上延伸的部分。
然后，例如通过淀积，形成栅导体层1012。例如，栅导体层1012可以包括多晶硅。栅导体层1012可以填充鳍之间的间隙，并可以进行平坦化处理例如CMP。之后，对栅导体层1012进行构图，以形成栅堆叠。在图7的示例中，栅导体层1012被构图为与鳍相交的条形。根据另一实施例，还可以构图后的栅导体层1012为掩模，进一步对栅介质层1010进行构图。
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。
接下来，如图8(图8(b)示出了沿图8(a)中BB′线的截面图，图8(c)示出了沿图8(a)中CC′线的截面图)所示，可以在栅导体层1012的侧壁上形成侧墙1014。例如，可以通过淀积形成厚度约为5-20nm的氮化物(如氮化硅)，然后对氮化物进行RIE，来形成侧墙1014。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。在鳍之间的沟槽为从上到下逐渐变小的锥台形时(由于刻蚀的特性，通常为这样的情况)，侧墙1014基本上不会形成于鳍的侧壁上。
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区，得到FinFET。
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。另外，还可以应用应变源/漏技术。
根据本公开的另一实施例，在图7中形成的栅介质层1010和栅导体层1012为牺牲栅介质层和牺牲栅导体层。接下来，可以同样按以上结合图8描述的方法来形成侧墙1014。
然后，如图9所示(图9(b)示出了沿图9(a)中BB′线的截面图，图9(c)示出了沿图9(a)中CC′线的截面图)，首先选择性去除(例如，RIE)暴露在外的牺牲栅介质层1010。在牺牲栅介质层1010和隔离层1006均包括氧化物的情况下，由于牺牲栅介质层1010较薄，因此对牺牲栅介质层1010的RIE基本上不会影响隔离层1006。在以上形成牺牲栅堆叠的过程中，以牺牲栅导体为掩模进一步构图牺牲栅介质层的情况下，不再需要该操作。
然后，可以选择性去除(例如，RIE)由于牺牲栅介质层1010的去除而露出的初始鳍1004的部分。对初始鳍1004该部分的刻蚀可以进行至露出穿通阻挡部1008。由于牺牲栅堆叠(牺牲栅介质层、牺牲栅导体和侧墙)的存在，初始鳍1004可以留于牺牲栅堆叠下方。
接下来，如图10所示(图10(b)示出了沿图10(a)中BB′线的截面图，图10(c)示出了沿图10(a)中CC′线的截面图)，例如可以通过外延，在露出的初始鳍部分上形成半导体层1016。随后可以在该第三半导体层1016中形成源/漏区。根据本公开的一实施例，可以在生长半导体层1016的同时，对其进行原位掺杂。例如，对于n型器件，可以进行n型原位掺杂；而对于p型器件，可以进行p型原位掺杂。另外，为了进一步提升性能，半导体层1016可以包括不同于鳍1004的材料，以便能够向鳍1004(其中将形成器件的沟道)施加应力。例如，在鳍1004包括Si的情况下，对于n型器件，半导体层1016可以包括Si:C(C的原子百分比例如为约0.2-2％)，以施加拉应力；对于p型器件，半导体层1016可以包括SiGe(例如，Ge的原子百分比为约15-75％)，以施加压应力。
在牺牲栅导体层1012包括多晶硅的情况下，半导体层1016的生长可能也会发生在牺牲栅导体层1012的顶面上。这在附图中并未示出。
接下来，如图11(图11(b)示出了沿图11(a)中BB′线的截面图)所示，例如通过淀积，形成另一电介质层1018。该电介质层1018例如可以包括氧化物。随后，对该电介质层1018进行平坦化处理例如CMP。该CMP可以停止于侧墙1014，从而露出牺牲栅导体1012。
随后，如图12(图12(b)示出了沿图12(a)中BB′线的截面图，图12(c)示出了沿图12(a)中CC′线的截面图)所示，例如通过TMAH溶液，选择性去除牺牲栅导体1012，从而在侧墙1014内侧形成了空隙1020。根据另一示例，还可以进一步去除牺牲栅介质层1010。
然后，如图13(图13(b)示出了沿图13(a)中BB′线的截面图，图13(c)示出了沿图13(a)中CC′线的截面图)所示，通过在空隙1020中形成栅介质层1022和栅导体层1024，形成最终的栅堆叠。栅介质层1022可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1024可以包括金属栅导体。优选地，在栅介质层1022和栅导体层1024之间还可以形成功函数调节层(未示出)。
根据本公开的另一示例，如图14所示，在衬底2000上形成初始鳍2004，并在衬底2000上形成电介质层2006覆盖初始鳍2004之后，可以通过溅射对电介质层2006进行平坦化处理。对此，例如可以参见以上结合图1-4进行的描述。在此，不同之处在于，进行溅射，直至去除了初始鳍2004顶端的一部分，如图15所示。可以控制溅射参数例如溅射功率和气压等直到溅射进行到初始鳍2004顶端。为了去除溅射对初始鳍2004造成的损伤，在溅射之后，可以对初始鳍2004的顶端进行退火或回蚀。
之后的处理可以按以上结合图5-13描述的方式进行。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (10)

1.一种制造鳍结构的方法，包括：
在衬底上形成初始鳍；
在衬底上形成电介质层，以覆盖初始鳍；
通过溅射，对电介质层平坦化处理；
进一步电介质层进行回蚀，以露出初始鳍的一部分，该露出部分用作鳍。
2.根据权利要求1所述的方法，其中，在溅射之后且在进一步回蚀之前，该方法还包括：进行化学机械抛光处理。
3.根据权利要求1所述的方法，其中，进行溅射，直到去除了初始鳍顶端的一部分。
4.根据权利要求3所述的方法，该方法还包括：对初始鳍的顶端进行退火或回蚀，以去除等离子损伤。
5.根据权利要求1所述的方法，其中，在进一步回蚀之后，该方法还包括：进行离子注入，以在初始鳍位于进一步回蚀后的电介质层的表面下方的部分中形成穿通阻挡部。
6.根据权利要求5所述的方法，其中，在形成穿通阻挡部时，对于p型器件，进行n型注入；而对于n型器件，进行p型注入。
7.根据权利要求5所述的方法，其中，在进形成穿通阻挡部之后，该方法还包括：
在电介质层上形成横跨鳍的牺牲栅堆叠；
以牺牲栅堆叠为掩模，选择性刻蚀初始鳍，直至穿通阻挡部露出；
在初始鳍的露出部分上形成半导体层，用以形成源/漏区；以及
形成栅堆叠替代牺牲栅堆叠。
8.根据权利要求7所述的方法，其中，对于p型器件，半导体层带压应力；而对于n型器件，半导体层带拉应力。
9.根据权利要求8所述的方法，其中，衬底包括Si，初始鳍通过对衬底进行构图而形成，半导体层包括SiGe或Si:C。
10.根据权利要求7所述的方法，其中，在形成半导体层时，对半导体层进行原位掺杂。
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Application publication date: 20140611