US8941161B2 - Semiconductor device including finFET and diode having reduced defects in depletion region - Google Patents
Semiconductor device including finFET and diode having reduced defects in depletion region Download PDFInfo
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- US8941161B2 US8941161B2 US13/888,680 US201313888680A US8941161B2 US 8941161 B2 US8941161 B2 US 8941161B2 US 201313888680 A US201313888680 A US 201313888680A US 8941161 B2 US8941161 B2 US 8941161B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 230000007547 defect Effects 0.000 title description 3
- 230000002829 reductive effect Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 description 18
- 239000004417 polycarbonate Substances 0.000 description 18
- 230000000873 masking effect Effects 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 229910052796 boron Inorganic materials 0.000 description 2
- -1 but not limited to Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/8611—Planar PN junction diodes
Definitions
- the present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device including a finFET and a diode having reduced defects in the depletion area.
- Conventional finFET semiconductors devices may include one or more diodes to perform various functions including voltage rectification, circuit protection, voltage biasing and thermal sensing. For example, when using an external thermal diode to measure temperature, the accuracy of the temperature measurement may be affected by the ideality factor which contributes to the sensitivity of the diode.
- FIG. 1A a cross-sectional view illustrating a conventional semiconductor device 10 in a first orientation is illustrated.
- the conventional semiconductor device 10 includes a first portion 12 having a fin area 14 and a second portion 16 having a planar area 18 .
- FIG. 1B is a cross-sectional view in a second orientation of the conventional semiconductor device 10 illustrated in FIG. 1A .
- a PC gate area 20 is illustrated being formed in the first portion 12 and the planar area 18 is formed on the second portion 16 .
- the PC gate area 20 may be etched to form a gate that extends across one or more fins 21 .
- planar area 18 i.e., forms eroded areas 22 .
- the planar area 18 comprises a diode, for example, the silicon area of the diode may be eroded thereby reducing the ideality factor.
- a semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion.
- the first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin.
- the first polycrystalline layer is patterned to define at least one semiconductor gate.
- the second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region.
- the doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.
- a method of fabricating a semiconductor device comprises depositing a masking layer on at least one semiconductor fin formed on a first substrate portion of the semiconductor device.
- the method further comprises forming a planar substrate on a second substrate portion located a distance away from the first substrate portion.
- the method further comprises forming an oxide layer on the masking layer and on the planar substrate.
- the method further comprises forming a resist layer on the oxide layer disposed on the planar substrate.
- the method further comprises etching the oxide layer disposed on the masking layer such that the first substrate portion excludes the oxide layer and the second substrate portion includes the oxide layer.
- FIGS. 1A-11 illustrate a series of operations to fabricate a semiconductor device in which:
- FIG. 1A is a cross-sectional view illustrating a conventional semiconductor device in a first orientation including a first portion having a fin area and a second portion having a planar area;
- FIG. 1B is a cross-sectional view illustrating the conventional semiconductor device in a second orientation including a gate area formed on the first portion and the planar area formed on the second portion;
- FIG. 2A illustrates the fin area and the planar area of a conventional semiconductor device in the first orientation following an etching process of the gate area
- FIG. 2B illustrates the gate area and the planar area following a conventional semiconductor device in the second orientation following the etching process shown in FIG. 2A ;
- FIG. 3 is a cross-sectional view of a semiconductor device in a first orientation showing a first substrate portion including a fin area having a masking layer deposited on a plurality of fins and showing second substrate portion including a planar substrate having a doped region according to an embodiment;
- FIG. 4 illustrates the semiconductor device of FIG. 3 in the first orientation after depositing an oxide layer on an upper surface of the masking layer and an upper surface of the doped region;
- FIG. 5 illustrates the semiconductor device of FIG. 4 , in the first orientation after depositing a resist layer on an upper surface of the oxide layer located at the second substrate portion;
- FIG. 6 illustrates the semiconductor device of FIG. 5 in the first orientation following an etching procedure that removes the oxide layer located at the first substrate portion to expose the masking layer;
- FIG. 7 illustrates the semiconductor device of FIG. 6 in the first orientation after removing the resist layer to expose the oxide layer formed at the second substrate portion;
- FIG. 8 illustrates the semiconductor device of FIG. 7 in the first orientation following an etching process that removes the masking layer at the first substrate portion to expose the fins;
- FIG. 9A illustrates the semiconductor device of FIG. 8 in the first orientation following a deposition process that deposits a polysilicon layer on the fins formed at the first substrate portion and on an upper portion of the oxide layer formed at the second substrate portion;
- FIG. 9B illustrates the semiconductor device of FIG. 9A in a second orientation showing the polysilicon layer formed at a gate area of the first substrate portion and the polysilicon layer formed on the oxide layer;
- FIG. 10A illustrates the semiconductor device of FIG. 9A in the first orientation after patterning the PC layer that forms a gate across the fins and that partially etches the PC layer located at the second substrate portion;
- FIG. 10B illustrates the semiconductor device of FIG. 10A in the second orientation showing the gate formed at the first substrate portion and the polycarbonate layer remaining the second substrate portion;
- FIG. 11 illustrates the second substrate portion of FIG. 10B undergoing an ion implantation process that forms respective N-doped regions and P-doped regions of the planar region to form a diode.
- FIG. 12 is a flow diagram illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the invention.
- the semiconductor device 100 includes a first substrate portion 102 and a second substrate portion 104 .
- the first and second substrate portions 102 , 104 are separated from one another by a predetermined distance.
- each of the first and second substrate portions 102 , 104 may at times realize the same fabrication processes.
- a fabrication process such as a reactive ion etching (RIE) process, applied to the first substrate portion 102 may also be applied to the second substrate portion 104 .
- RIE reactive ion etching
- the first substrate portion 102 includes a fin area having one or more semiconductor fins 106 and a masking layer 108 formed on and between the fins 106 .
- the semiconductor fins 106 may comprise an active semiconductor material including, but not limited to, silicon (Si).
- the masking layer 108 may be formed from, for example, silicon nitride (Si 3 N 4 ).
- the second substrate portion 104 includes a planar substrate 110 formed thereon.
- the planar substrate 110 may comprise an active semiconductor material including, but not limited to, Si.
- the planar substrate 110 includes an active semiconductor region 112 and a doped region 114 .
- the doped region 114 may be formed by implanting doped ions at the active semiconductor region 112 .
- the doped ions may include, for example, boron ions.
- the doped region 114 may occupy a volume of the active semiconductor region 112 of approximately 1e 18 per cubic centimeters (cm 3 ).
- an oxide layer 116 may be formed on an upper surface of the masking layer 108 located at the first substrate portion 102 , and on the doped region 114 located at the second substrate portion 104 to wrap around the planar substrate 110 .
- the oxide layer 116 may have a thickness ranging from approximately 15 nanometer (nm) to approximately 30 nm. Further, the oxide layer 116 may be continuously formed across the first and second substrate portions 102 , 104 . Accordingly, the oxide layer 116 may be continuous oxide layer 116 extending from the first substrate portion 102 to the second substrate portion 104 .
- a resist layer 118 is formed on an upper surface of the oxide layer 116 located at the second substrate portion 104 .
- the resist layer 118 may comprise various materials capable of inhibiting degradation of the underlying oxide layer 116 . Accordingly, the oxide layer 116 formed at the first substrate portion 102 may be removed without eroding the oxide layer 116 formed at the second substrate portion 104 . More specifically, an etching process may be applied to the oxide layer 116 formed on the masking layer 108 located at the second substrate portion 104 to expose the fins 106 as illustrated in FIG. 6 . The resist layer 118 , however, prevents etching of the oxide layer 116 formed at the second substrate portion 104 .
- the oxide layer 116 is removed from the first substrate portion 102 of the semiconductor device 100 while the oxide layer 116 is maintained at the second substrate portion 104 .
- the first substrate portion 102 excludes the oxide layer 116 , while the oxide layer 116 is maintained at the second substrate portion 104 .
- the resist layer 118 may be removed from the oxide layer 116 formed at the second substrate portion 104 , as illustrated in FIG. 7 . Accordingly, the upper surface of the masking layer 108 formed at the first substrate portion 102 and the upper surface of the oxide layer 116 formed at the second substrate portion 104 are exposed. An etching process may be applied to the first substrate portion 102 to remove the masking layer 108 and expose the fins 106 and areas between and/or adjacent to the fins 106 , as illustrated in FIG. 8 .
- a polycrystalline semiconductor layer i.e., a PC layer 120
- the PC layer 120 may be formed from a material including, but not limited to, polycrystalline silicon (i.e., polysilicon).
- the PC layer 120 formed on the fins 106 may be patterned to form a corresponding gate 122 .
- the PC layer 120 may be patterned such that a source region 124 and a drain region 126 of the fin 106 are exposed as illustrated in FIG. 10B .
- the PC layer 120 formed on the oxide layer 116 at the second substrate portion 104 is also etched such that portions of the oxide layer 116 are exposed.
- the oxide layer 116 protects the underlying planar substrate 110 .
- a diode 128 may be formed at the second substrate portion 104 according to at least one exemplary embodiment of the invention. More specifically, P-type ions (+) and N-type ions ( ⁇ ) may be implanted in the doped region 114 of the planar substrate 110 .
- the P-type ions may include, but are not limited to, boron (B).
- the N-type ions may include, but are not limited to, arsenic (As) or phosphorus (P).
- the P-type ions (+) form a positive region 130 and the N-type ions form a negative region 132 .
- the positive and negative regions 130 , 132 are separated from one another by a depletion region 134 .
- the active semiconductor region 112 and the doped region 114 are protected by the oxide layer 116 during patterning of the PC layer 120 , etching of the active semiconductor region 112 and/or the doped region 114 are prevented. Accordingly, defects in the depletion area 134 may be prevented and the ideality factor of the diode 128 is maintained. Further, at least one embodiment described above protects the depletion area 134 of a diode 128 formed near a finFET device, such that punch-through of the diode 128 is reduced.
- the oxide layer 116 and the remaining PC layer 120 may be maintained at the second substrate portion 104 without reducing the integrity of the diode 128 .
- the PC layer 120 formed on the oxide layer 116 of the second substrate portion 104 may promote alignment of the positive region 130 , the negative region 132 and the depletion region 134 .
- the PC layer 120 formed on the oxide layer 116 may define a first ion implantation area, i.e. a positive ion implantation area 136 , adjacent a first side of the PC layer 120 and a second ion implantation area, i.e., a negative ion implantation area 138 , adjacent a second side of the PC layer 120 opposite the first side.
- the P-type ions (+) may be deposited at the positive ion implantation area 136 to form the positive region 130 and the N-type ions ( ⁇ ) may be deposited at the negative ion implantation area 138 to form the negative region 132 .
- the PC layer 120 may block ions from traveling therethrough, thereby preventing ions from being implanted at the doped region 114 therebeneath to assist in forming the depletion region 134 . It is appreciated, however, that the oxide layer 116 and the remaining PC layer 120 may from the second substrate portion 104 be removed if desired.
- a flow diagram illustrates a method of fabricating a semiconductor device according to an exemplary embodiment of the invention.
- a masking layer is deposited on at least one semiconductor fin formed on a first substrate portion of the semiconductor device.
- a planar substrate is formed on a second substrate portion located a distance away from the first substrate portion.
- An oxide layer is formed on the masking layer and on the planar substrate at operation 1204 .
- a resist layer is formed on the oxide layer disposed of the planar substrate.
- the oxide layer disposed on the masking layer is etched such that the first substrate portion excludes the oxide layer and the second substrate portion includes the oxide layer, and the method ends.
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Abstract
Description
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US13/888,680 US8941161B2 (en) | 2013-05-07 | 2013-05-07 | Semiconductor device including finFET and diode having reduced defects in depletion region |
US13/909,673 US9059287B2 (en) | 2013-05-07 | 2013-06-04 | Semiconductor device including finfet and diode having reduced defects in depletion region |
CN201410187244.5A CN104143516B (en) | 2013-05-07 | 2014-05-06 | Semiconductor devices and its manufacture method |
US14/697,670 US9337317B2 (en) | 2013-05-07 | 2015-04-28 | Semiconductor device including finFET and diode having reduced defects in depletion region |
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US13/888,680 US8941161B2 (en) | 2013-05-07 | 2013-05-07 | Semiconductor device including finFET and diode having reduced defects in depletion region |
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US13/909,673 Expired - Fee Related US9059287B2 (en) | 2013-05-07 | 2013-06-04 | Semiconductor device including finfet and diode having reduced defects in depletion region |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US10319662B2 (en) | 2017-02-01 | 2019-06-11 | Indian Institute Of Science | Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks |
US10483258B2 (en) | 2017-02-25 | 2019-11-19 | Indian Institute Of Science | Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity |
Families Citing this family (5)
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CN109216181A (en) * | 2012-11-30 | 2019-01-15 | 中国科学院微电子研究所 | Fin structure manufacturing method |
US9048303B1 (en) * | 2014-01-30 | 2015-06-02 | Infineon Technologies Austria Ag | Group III-nitride-based enhancement mode transistor |
US9337279B2 (en) | 2014-03-03 | 2016-05-10 | Infineon Technologies Austria Ag | Group III-nitride-based enhancement mode transistor |
KR102320049B1 (en) | 2015-02-26 | 2021-11-01 | 삼성전자주식회사 | Semiconductor Devices Having a Tapered Active Region |
KR102449901B1 (en) * | 2015-06-23 | 2022-09-30 | 삼성전자주식회사 | Integrated circuit device and method of manufacturing the same |
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Also Published As
Publication number | Publication date |
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US20150243767A1 (en) | 2015-08-27 |
CN104143516B (en) | 2017-11-24 |
US20140335670A1 (en) | 2014-11-13 |
US20140332815A1 (en) | 2014-11-13 |
US9337317B2 (en) | 2016-05-10 |
CN104143516A (en) | 2014-11-12 |
US9059287B2 (en) | 2015-06-16 |
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