WO2014082350A1 - 鳍结构制造方法 - Google Patents

鳍结构制造方法 Download PDF

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Publication number
WO2014082350A1
WO2014082350A1 PCT/CN2012/086657 CN2012086657W WO2014082350A1 WO 2014082350 A1 WO2014082350 A1 WO 2014082350A1 CN 2012086657 W CN2012086657 W CN 2012086657W WO 2014082350 A1 WO2014082350 A1 WO 2014082350A1
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Prior art keywords
fin
dielectric layer
layer
initial
substrate
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PCT/CN2012/086657
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English (en)
French (fr)
Inventor
朱慧珑
许淼
罗军
李春龙
王桂磊
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中国科学院微电子研究所
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Priority to US14/442,890 priority Critical patent/US9691624B2/en
Publication of WO2014082350A1 publication Critical patent/WO2014082350A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present disclosure relates to the field of semiconductors and, more particularly, to a method of fabricating a fin structure. Background technique
  • CMP chemical mechanical polishing
  • a method of fabricating a fin structure comprising: forming an initial fin on a substrate; forming a dielectric layer on the substrate to cover the initial fin; planarizing the dielectric layer by sputtering The further dielectric layer is etched back to expose a portion of the initial fin that serves as a fin.
  • FIGS. 14 and 15 are schematic diagrams showing partial steps of a process of fabricating a fin structure in accordance with another embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • the material layer may be planarized by sputtering, such as Ar or N plasma sputtering.
  • sputtering planarization process instead of the conventional CMP planarization process, a flatter material layer surface can be achieved.
  • Such material layers may include multiple layers of materials used in semiconductor fabrication processes, including, for example, but not limited to, layers of insulator materials, layers of semiconductor materials, and layers of conductive materials.
  • the present disclosure may be applied to a fin field effect transistor (FinFET).
  • FinFET fin field effect transistor
  • FinFETs can be fabricated as follows. For example, an initial fin can be formed on the substrate. A layer of dielectric is then deposited over the substrate to cover the initial fins. For the dielectric layer, a planarization process such as chemical mechanical polishing (CMP) can be performed. The dielectric layer can then be etched back to form an isolation layer and thus expose a portion of the initial fin. The exposed portion of the initial fin can then be used as the fin of the final device.
  • CMP processing is generally difficult to control the surface flatness within a few nanometers, so that the starting surface of the etch back process is not sufficiently flat and thus causes the resulting fin height to vary across the wafer.
  • the dielectric layer after depositing the dielectric layer, the dielectric layer may be planarized by plasma sputtering.
  • CMP can be used or compared to conventional techniques. To use less CMP. Therefore, the uniformity of the starting surface of the dielectric layer etch back process can be improved.
  • the present disclosure can be presented in various forms, some of which are described below.
  • the substrate 1000 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a SiGe substrate, or the like.
  • a bulk Si substrate will be described as an example for convenience of explanation.
  • the substrate 1000 can be patterned to form an initial fin. For example, this can be done as follows. Specifically, a patterned photoresist 1002 is formed on the substrate 1000 as designed. Typically, photoresist 1002 is patterned into a series of parallel equally spaced lines. Then, as shown in FIG. 2, a reactive ion etch (RIE) substrate 1000 is etched using the patterned photoresist 1002 as a mask to form an initial fin 1004. Thereafter, the photoresist 1002 can be removed.
  • RIE reactive ion etch
  • the shape of the groove (between the initial fins) formed by the etching is not necessarily the regular rectangular shape shown in Fig. 2, and may be, for example, a frustum shape which gradually becomes smaller from the top to the bottom.
  • the position and number of initial fins formed are not limited to the example shown in Fig. 2.
  • the initial fin is not limited to being formed by directly patterning the substrate.
  • an additional semiconductor layer can be epitaxially grown on the substrate, and the additional semiconductor layer can be patterned to form an initial fin. If there is sufficient etch selectivity between the additional semiconductor layer and the substrate, the patterning can be substantially stopped at the substrate when the initial fin is patterned, thereby achieving more precise control of the initial fin height.
  • the expression "forming an initial fin on a substrate” includes forming a fin on the substrate in any suitable manner.
  • an isolation layer may be formed on the substrate.
  • dielectric layer 1006 may be formed over the substrate, such as by deposition, to cover the formed initial fins 1004.
  • dielectric layer 1006 can comprise an oxide such as silicon oxide.
  • the dielectric layer 1006 may be sputtered to planarize the dielectric layer 1006.
  • sputtering may use a plasma such as an Ar or N plasma.
  • the cutting speed of the dielectric layer 1006, the sputtering parameters such as the sputtering power, the gas pressure, and the like can be controlled according to plasma sputtering to determine the time during which the plasma sputtering is performed, so that the plasma sputtering can be performed for a certain period of time.
  • the segments are to sufficiently smooth the surface of the dielectric layer 1006.
  • FIG. 1 the example shown in FIG.
  • plasma sputtering may end before reaching the top surface of the initial fin 1004 to avoid excessive damage to the initial fin 1004.
  • FIG 4 shows microscopic fluctuations in Figure 4, in reality the top surface of the dielectric layer 1004 has sufficient flatness, and its undulations can be controlled, for example, within a few nanometers.
  • the dielectric layer 1006 may be etched back (eg, RIE) to expose a portion of the initial fin 1004, the exposed portion. It can then be used as a fin for the final device.
  • the remaining dielectric layer 1006 forms an isolation layer. Since the surface of the dielectric layer 1006 is smoothed by sputtering before etch back, the surface of the spacer layer 1006 remains substantially uniform on the substrate after etch back.
  • a punch-through barrier may also be formed by implantation as shown by an arrow in FIG. 6 (see 1008 shown in FIG. 7).
  • a p-type impurity such as 8, BF 2 or In may be implanted;
  • an n-type impurity such as As or P may be implanted.
  • Ion implantation can be perpendicular to the surface of the substrate. The parameters of the ion implantation are controlled such that the punch-through barrier is formed in a portion of the initial fin below the surface of the isolation layer 1006 and has a desired doping concentration.
  • a part of the dopant may be scattered from the exposed portion of the initial fin, thereby facilitating the formation of a steep doping profile in the depth direction.
  • Annealing can be performed to activate the implanted impurities. This feedthrough barrier helps to reduce source and drain leakage.
  • a gate stack across the fins can be formed on the isolation layer 1006.
  • this can be done as follows. Specifically, as shown in Fig. 7 (Fig. 7(b) shows a cross-sectional view taken along line BB' in Fig. 7(a)), a gate dielectric layer 1010 is formed, for example, by deposition.
  • the gate dielectric layer 1010 may include an oxide having a thickness of about 0.8 to 1.5 nm. In the example shown in Fig. 7, only the gate dielectric layer 1010 of the " ⁇ " shape is shown. However, the gate dielectric layer 1010 may also include a portion extending on the top surface of the isolation layer 1006.
  • the gate conductor layer 1012 is formed, for example, by deposition.
  • the gate conductor layer 1012 can comprise polysilicon.
  • the gate conductor layer 1012 may fill a gap between the fins and may be subjected to a planarization process such as CMP.
  • the gate conductor layer 1012 is patterned to form a gate stack.
  • the gate conductor layer 1012 is patterned into a strip shape that intersects the fins.
  • the patterned gate conductor layer 1012 can also be used as a mask to further pattern the gate dielectric layer 1010.
  • a halo implant and an extension implant may be performed using the gate conductor as a mask.
  • Fig. 8 shows a cross-sectional view taken along line BB' in Fig. 8(a)
  • Fig. 8(c) shows a cross-sectional view taken along line CC' in Fig. 8(a)
  • the spacers 1014 may be formed on the sidewalls of the gate conductor layer 1012.
  • the spacers 1014 can be formed by depositing a nitride (e.g., silicon nitride) having a thickness of about 5 to 20 nm and then performing RIE on the nitride.
  • a nitride e.g., silicon nitride
  • the side wall 1014 is substantially not formed on the side wall of the fin.
  • source/drain (S/D) implantation may be performed using the gate conductor and the sidewall as a mask. Subsequently, the implanted ions can be activated by annealing to form source/drain regions to obtain a FinFET.
  • the gate stack is directly formed.
  • the present disclosure is not limited to this.
  • an alternative gate process is equally applicable to the present disclosure.
  • strain source/drain technology can also be applied.
  • the gate dielectric layer 1010 and the gate conductor layer 1012 formed in FIG. 7 are a sacrificial gate dielectric layer and a sacrificial gate conductor layer.
  • the spacer 1014 can be formed in the same manner as described above in connection with Fig. 8.
  • FIG. 9 shows a cross-sectional view taken along line BB' in FIG. 9(a), and FIG. 9(c) shows a cross-section along CC' line in FIG. 9(a).
  • FIG. first selectively removing (eg, RIE) the exposed sacrificial gate dielectric layer 1010.
  • RIE e.g. etching
  • the sacrificial gate dielectric layer 1010 and the isolation layer 1006 each include an oxide
  • the RIE of the sacrificial gate dielectric layer 1010 does not substantially affect the isolation layer 1006.
  • the sacrificial gate dielectric layer is further patterned by using the sacrificial gate conductor as a mask, and the operation is no longer required.
  • Portions of the initial fins 1004 exposed by the removal of the sacrificial gate dielectric layer 1010 can then be selectively removed (e.g., RIE). This portion of the initial fin 1004 can be etched to expose the through barrier 1008.
  • the initial fins 1004 may remain below the sacrificial gate stack due to the presence of the sacrificial gate stack (sacrificial gate dielectric layer, sacrificial gate conductors, and sidewall spacers).
  • FIG. 10 shows a cross-sectional view taken along line BB' in FIG. 10(a), and FIG. 10(c) shows a line along CC' in FIG. 10(a).
  • Cross-sectional view for example, a semiconductor layer 1016 may be formed on the exposed initial fin portion by epitaxy. Source/drain regions may then be formed in the third semiconductor layer 1016.
  • the semiconductor layer 1016 may be doped in situ while being grown. For example, for n-type devices, n-type in-situ doping can be performed; for p-type devices Piece, p-type in-situ doping can be performed.
  • the semiconductor layer 1016 can include a different material than the fins 1004 to enable stress to be applied to the fins 1004 where the channels of the device will be formed.
  • the semiconductor layer 1016 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress; for the p-type device, the semiconductor layer 1016 may include SiGe (eg, an atomic percentage of Ge of about 15-75%) to apply a compressive stress to p.
  • the growth of the semiconductor layer 1016 may also occur on the top surface of the sacrificial gate conductor layer 1012. This is not shown in the drawings.
  • Fig. 11 (b) shows a cross-sectional view taken along line BB' in Fig. 11 (a)
  • another dielectric layer 1018 is formed, for example, by deposition.
  • the dielectric layer 1018 can comprise, for example, an oxide.
  • the dielectric layer 1018 is subjected to a planarization process such as CMP.
  • the CMP can stop at the sidewall 1014 to expose the sacrificial gate conductor 1012.
  • Fig. 12 shows a cross-sectional view taken along line BB' in Fig. 12 (a)
  • Fig. 12 (c) shows a cross-sectional view along line CC' in Fig. 12 (a)
  • the sacrificial gate conductor 1012 is selectively removed, for example, by a TMAH solution, thereby forming a void 1020 inside the sidewall spacer 1014.
  • the sacrificial gate dielectric layer 1010 can be further removed.
  • a final gate stack is formed by forming a gate dielectric layer 1022 and a gate conductor layer 1024 in the void 1020.
  • the gate dielectric layer 1022 can comprise a high K gate dielectric such as HfO 2 having a thickness of about 1-5 nm.
  • Gate conductor layer 1024 can include a metal gate conductor.
  • a function adjustment layer (not shown) can also be formed between the gate dielectric layer 1022 and the gate conductor layer 1024.
  • the dielectric layer 2006 may be flattened by sputtering.
  • Processing for this, for example, reference can be made to the description made above in connection with FIGS. 1-4.
  • the difference is that sputtering is performed until a portion of the top end of the initial fin 2004 is removed, as shown in FIG.
  • Sputtering parameters such as sputtering power and gas pressure can be controlled until sputtering proceeds to the top of the initial fin 2004.
  • the tip of the initial fin 2004 may be annealed or etched back after sputtering. Subsequent processing can be performed in the manner described above in connection with Figures 5-13.

Abstract

提供一种鳍结构的制造方法，包括：在衬底（1000）上形成初始鳍（1004）；在衬底（1000）上形成电介质层（1006），以覆盖初始鳍（1004）；通过溅射，对电介质层（1006）平坦化处理；进一歩电介质层（1006）进行回蚀，以露出初始鳍（1004）的一部分，该露出部分用作鳍。

Description

鳍结构制造方法 本申请要求了 2012年 11月 30日提交的、 申请号为 201210505449.4、 发 明名称为 "鰭结构制造方法" 的中国专利申请的优先权， 其全部内容通过引用 结合在本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种鰭结构的制造方法。 背景技术
在半导体工艺中， 经常用到平坦化工艺， 例如化学机械抛光（CMP ), 以 获得相对平坦的表面。 然而， 在通过 CMP对材料层进行平坦化的情况下， 如 果需要研磨掉相对较厚的部分， 则难以控制 CMP后材料层的表面平坦度， 例 如控制到几个纳米之内。 发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面， 提供了一种制造鰭结构的方法， 包括： 在衬底上 形成初始鰭； 在衬底上形成电介质层， 以覆盖初始鰭； 通过溅射， 对电介质层 平坦化处理； 进一步电介质层进行回蚀， 以露出初始鰭的一部分， 该露出部分 用作鰭。
附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和优点将更为清楚， 在附图中：
图 1-13是示出了根据本公开实施例的制造鰭结构流程的示意图； 图 14、 15是示出了根据本公开另一实施例的制造鰭结构流程的部分步骤 的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是 示例性的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知 结构和技术的描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些 细节。 图中所示出的各种区域、 层的形状以及它们之间的相对大小、位置关系 仅是示例性的， 实际中可能由于制造公差或技术限制而有所偏差， 并且本领域 技术人员根据实际所需可以另外设计具有不同形状、 大小、 相对位置的区域 / 层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该 层 /元件可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外，如果在一种朝向中一层 /元件位于另一层 /元件"上"，那么当调转朝向时， 该层 /元件可以位于该另一层 /元件 "下"。
根据本公开的示例， 可以通过溅射（ sputtering ), 例如 Ar或 N等离子体 溅射， 来对材料层进行平坦化处理。 通过这种溅射平坦化处理， 而非常规的 CMP平坦化处理， 可以实现更加平坦的材料层表面。 这种材料层可以包括半 导体制造工艺中使用的多种材料层， 例如， 包括但不限于绝缘体材料层、 半导 体材料层和导电材料层。
在一个示例中， 本公开可以适用于鰭式场效应晶体管 （ FinFET )。
通常， FinFET可以如下来制造。 例如， 可以在衬底上形成初始鰭。 然后， 在衬底上淀积一层电介质层， 以覆盖初始鰭。 对于该电介质层， 可以进行平坦 化处理， 例如化学机械抛光（CMP )。 接着， 可以对电介质层进行回蚀， 以形 成隔离层， 并因此露出初始鰭的一部分。初始鰭的露出部分随后可以用作最终 器件的鰭。 然而， CMP处理通常难以将表面平坦度控制在几个纳米之内， 从 而使得回蚀处理的开始表面并非足够平坦，并因此导致最终形成的鰭高度在晶 片上存在变化。
根据本公开的实施例， 在淀积电介质层之后， 可以利用等离子体溅射， 来 对电介质层进行平坦化处理。 这样， 可以不使用 CMP或者相比于常规技术可 以使用较少的 CMP。 因此， 可以改善电介质层回蚀处理的开始表面的一致性。 本公开可以各种形式呈现， 以下将描述其中一些示例。
如图 1所示， 提供衬底 1000。 该衬底 1000可以是各种形式的衬底， 例如 但不限于体半导体材料衬底如体 Si衬底、 绝缘体上半导体（ SOI )衬底、 SiGe 衬底等。 在以下的描述中， 为方便说明， 以体 Si衬底为例进行描述。
可以对衬底 1000进行构图， 以形成初始鰭。 例如， 这可以如下进行。 具 体地， 在衬底 1000上按设计形成构图的光刻胶 1002。 通常， 光刻胶 1002被 构图为一系列平行的等间距线条。 然后， 如图 2所示， 以构图的光刻胶 1002 为掩模， 刻蚀例如反应离子刻蚀 （RIE )衬底 1000, 从而形成初始鰭 1004。 之后， 可以去除光刻胶 1002。
这里需要指出的是， 通过刻蚀所形成的（初始鰭之间的）沟槽的形状不一 定是图 2中所示的规则矩形形状， 可以是例如从上到下逐渐变小的锥台形。 另 外， 所形成的初始鰭的位置和数目不限于图 2所示的示例。
另外， 初始鰭不限于通过直接对衬底进行构图来形成。 例如， 可以在衬底 上外延生长另外的半导体层，对该另外的半导体层进行构图来形成初始鰭。如 果该另外的半导体层与衬底之间具有足够的刻蚀选择性，则在对初始鰭进行构 图时， 可以使构图基本上停止于衬底， 从而实现对初始鰭高度的较精确控制。
因此， 在本公开中， 表述 "在衬底上形成初始鰭" 包括以任何适当的方式 在衬底上形成鰭。
在通过上述处理形成初始鰭之后， 可以在衬底上形成隔离层。
具体地， 如图 3所示， 可以在衬底上例如通过淀积形成电介质层 1006, 以覆盖形成的初始鰭 1004。例如，电介质层 1006可以包括氧化物（如氧化硅）。
然后， 如图 4所示， 可以对电介质层 1006进行溅射， 来对电介质层 1006 进行平坦化处理。 例如， 溅射可以使用等离子体， 如 Ar或 N等离子体。 在此， 例如可以根据等离子体溅射对电介质层 1006的切削速度， 控制溅射参数例如 溅射功率和气压等， 来确定进行等离子体溅射的时间，使得等离子体溅射能够 执行一定的时间段以充分平滑电介质层 1006的表面。 另一方面， 在图 4所示 的示例中， 等离子体溅射可以在到达初始鰭 1004的顶面之前结束， 以避免对 初始鰭 1004造成过多的损伤。 尽管在图 4中示出了微观上的起伏， 但是事实上电介质层 1004的顶面具 有充分的平坦度， 其起伏可以控制在例如几个纳米之内。
根据本公开的另一实施例，还可以根据需要，对通过溅射平坦化后的电介 质层 1006进行少许 CMP。
在电介质层 1006的表面通过等离子体溅射而变得充分平滑之后， 如图 5 所示， 可以对电介质层 1006进行回蚀 （例如， RIE ), 以露出初始鰭 1004的 一部分， 该露出的部分随后可以用作最终器件的鰭。 剩余的电介质层 1006构 成隔离层。 由于回蚀之前电介质层 1006的表面通过溅射而变得平滑， 所以回 蚀之后隔离层 1006的表面在衬底上基本上保持一致。
为改善器件性能， 根据本公开的一示例， 还可以如图 6中的箭头所示， 通 过注入来形成穿通阻挡部（参见图 7所示的 1008 )。例如，对于 n型器件而言， 可以注入 p型杂质， 如：8、 BF2或 In; 对于 p型器件， 可以注入 n型杂质， 如 As或 P。 离子注入可以垂直于衬底表面。 控制离子注入的参数， 使得穿通阻 挡部形成于初始鰭位于隔离层 1006表面之下的部分中， 并且具有期望的掺杂 浓度。 应当注意， 由于初始鰭的形状因子， 一部分掺杂剂 （离子或元素）可能 从初始鰭的露出部分散射出去， 从而有利于在深度方向上形成陡峭的掺杂分 布。可以进行退火，以激活注入的杂质。这种穿通阻挡部有助于减小源漏泄漏。
随后， 可以在隔离层 1006上形成横跨鰭的栅堆叠。 例如， 这可以如下进 行。 具体地， 如图 7 (图 7 ( b )示出了沿图 7 ( a ) 中 BB'线的截面图）所示， 例如通过淀积， 形成栅介质层 1010。 例如， 栅介质层 1010可以包括氧化物， 厚度为约 0.8-1.5nm。在图 7所示的示例中，仅示出了 "Π"形的栅介质层 1010。 但是， 栅介质层 1010也可以包括在隔离层 1006的顶面上延伸的部分。
然后， 例如通过淀积， 形成栅导体层 1012。 例如， 栅导体层 1012可以包 括多晶硅。 栅导体层 1012可以填充鰭之间的间隙， 并可以进行平坦化处理例 如 CMP。之后，对栅导体层 1012进行构图， 以形成栅堆叠。在图 7的示例中， 栅导体层 1012被构图为与鰭相交的条形。 根据另一实施例， 还可以构图后的 栅导体层 1012为掩模， 进一步对栅介质层 1010进行构图。
在形成构图的栅导体之后， 例如可以栅导体为掩模， 进行晕圈 （halo )注 入和延伸区 ( extension ) 注入。 接下来， 如图 8 (图 8 (b)示出了沿图 8(a)中 BB'线的截面图， 图 8(c) 示出了沿图 8 (a) 中 CC'线的截面图） 所示， 可以在栅导体层 1012的侧壁上 形成侧墙 1014。 例如， 可以通过淀积形成厚度约为 5-20nm的氮化物（如氮化 硅）， 然后对氮化物进行 RIE, 来形成侧墙 1014。 本领域技术人员知道多种方 式来形成这种侧墙，在此不再赘述。在鰭之间的沟槽为从上到下逐渐变小的锥 台形时（由于刻蚀的特性， 通常为这样的情况）， 侧墙 1014基本上不会形成于 鰭的侧壁上。
在形成侧墙之后， 可以栅导体及侧墙为掩模， 进行源 /漏（ S/D )注入。 随 后， 可以通过退火， 激活注入的离子， 以形成源 /漏区， 得到 FinFET。
在上述实施例中， 在形成鰭之后， 直接形成了栅堆叠。 本公开不限于此。 例如， 替代栅工艺同样适用于本公开。 另外， 还可以应用应变源 /漏技术。
根据本公开的另一实施例， 在图 7 中形成的栅介质层 1010 和栅导体层 1012为牺牲栅介质层和牺牲栅导体层。 接下来， 可以同样按以上结合图 8描 述的方法来形成侧墙 1014。
然后， 如图 9所示（图 9 (b)示出了沿图 9 (a) 中 BB'线的截面图， 图 9 (c)示出了沿图 9 (a) 中 CC'线的截面图 ), 首先选择性去除（例如， RIE) 暴露在外的牺牲栅介质层 1010。 在牺牲栅介质层 1010和隔离层 1006均包括 氧化物的情况下， 由于牺牲栅介质层 1010较薄， 因此对牺牲栅介质层 1010 的 RIE基本上不会影响隔离层 1006。 在以上形成牺牲栅堆叠的过程中， 以牺 牲栅导体为掩模进一步构图牺牲栅介质层的情况下， 不再需要该操作。
然后， 可以选择性去除（例如， RIE) 由于牺牲栅介质层 1010 的去除而 露出的初始鰭 1004的部分。对初始鰭 1004该部分的刻蚀可以进行至露出穿通 阻挡部 1008。 由于牺牲栅堆叠（牺牲栅介质层、 牺牲栅导体和侧墙）的存在， 初始鰭 1004可以留于牺牲栅堆叠下方。
接下来， 如图 10所示（图 10 (b)示出了沿图 10 (a)中 BB'线的截面图， 图 10 (c)示出了沿图 10 (a) 中 CC'线的截面图）， 例如可以通过外延， 在露 出的初始鰭部分上形成半导体层 1016。 随后可以在该第三半导体层 1016中形 成源 /漏区。 根据本公开的一实施例， 可以在生长半导体层 1016的同时， 对其 进行原位掺杂。 例如， 对于 n型器件， 可以进行 n型原位掺杂； 而对于 p型器 件， 可以进行 p型原位掺杂。 另外， 为了进一步提升性能， 半导体层 1016可 以包括不同于鰭 1004的材料， 以便能够向鰭 1004 (其中将形成器件的沟道） 施加应力。 例如， 在鰭 1004包括 Si的情况下， 对于 n型器件， 半导体层 1016 可以包括 Si:C ( C的原子百分比例如为约 0.2-2% ), 以施加拉应力； 对于 p型 器件， 半导体层 1016可以包括 SiGe (例如， Ge的原子百分比为约 15-75% ), 以施力 p压应力。
在牺牲栅导体层 1012包括多晶硅的情况下，半导体层 1016的生长可能也 会发生在牺牲栅导体层 1012的顶面上。 这在附图中并未示出。
接下来， 如图 11 (图 11 ( b )示出了沿图 11 ( a ) 中 BB'线的截面图） 所 示， 例如通过淀积， 形成另一电介质层 1018。 该电介质层 1018例如可以包括 氧化物。 随后， 对该电介质层 1018进行平坦化处理例如 CMP。 该 CMP可以 停止于侧墙 1014, 从而露出牺牲栅导体 1012。
随后， 如图 12 (图 12 ( b )示出了沿图 12 ( a ) 中 BB'线的截面图， 图 12 ( c )示出了沿图 12 ( a ) 中 CC'线的截面图）所示， 例如通过 TMAH溶液， 选择性去除牺牲栅导体 1012,从而在侧墙 1014内侧形成了空隙 1020。根据另 一示例， 还可以进一步去除牺牲栅介质层 1010。
然后， 如图 13 (图 13 ( b )示出了沿图 13 ( a ) 中 BB'线的截面图， 图 13 ( c )示出了沿图 13 ( a ) 中 CC'线的截面图）所示， 通过在空隙 1020中形成 栅介质层 1022和栅导体层 1024, 形成最终的栅堆叠。 栅介质层 1022可以包 括高 K栅介质例如 Hf02, 厚度为约 l-5nm。 栅导体层 1024可以包括金属栅导 体。优选地， 在栅介质层 1022和栅导体层 1024之间还可以形成功函数调节层 (未示出）。
根据本公开的另一示例， 如图 14所示， 在衬底 2000上形成初始鰭 2004, 并在衬底 2000上形成电介质层 2006覆盖初始鰭 2004之后， 可以通过溅射对 电介质层 2006进行平坦化处理。 对此， 例如可以参见以上结合图 1-4进行的 描述。 在此， 不同之处在于， 进行溅射， 直至去除了初始鰭 2004顶端的一部 分， 如图 15所示。 可以控制溅射参数例如溅射功率和气压等直到溅射进行到 初始鰭 2004顶端。 为了去除溅射对初始鰭 2004造成的损伤， 在溅射之后， 可 以对初始鰭 2004的顶端进行退火或回蚀。 之后的处理可以按以上结合图 5-13描述的方式进行。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说 明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来形成所需形状 的层、 区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是， 这些实施例仅仅是为了说明的 目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价 物限定。 不脱离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本公开的范围之内。

Claims

权 利 要 求 书
1. 一种制造鰭结构的方法， 包括：
在衬底上形成初始鰭；
在衬底上形成电介质层， 以覆盖初始鰭；
通过溅射， 对电介质层平坦化处理；
进一步电介质层进行回蚀， 以露出初始鰭的一部分， 该露出部分用作鰭。
2. 根据权利要求 1所述的方法， 其中， 在溅射之后且在进一步回蚀之 前， 该方法还包括： 进行化学机械抛光处理。
3. 根据权利要求 1所述的方法， 其中， 进行溅射， 直到去除了初始鰭 顶端的一部分。
4. 根据权利要求 3所述的方法， 该方法还包括： 对初始鰭的顶端进行 退火或回蚀， 以去除等离子损伤。
5. 根据权利要求 1所述的方法， 其中， 在进一步回蚀之后， 该方法还 包括： 进行离子注入， 以在初始鰭位于进一步回蚀后的电介质层的表面下方的 部分中形成穿通阻挡部。
6. 根据权利要求 5所述的方法， 其中， 在形成穿通阻挡部时， 对于 p 型器件， 进行 n型注入； 而对于 n型器件， 进行 p型注入。
7. 根据权利要求 5所述的方法， 其中， 在进形成穿通阻挡部之后， 该 方法还包括：
在电介质层上形成横跨鰭的牺牲栅堆叠；
以牺牲栅堆叠为掩模， 选择性刻蚀初始鰭， 直至穿通阻挡部露出； 在初始鰭的露出部分上形成半导体层， 用以形成源 /漏区； 以及
形成栅堆叠替代牺牲栅堆叠。
8. 根据权利要求 7所述的方法， 其中， 对于 p型器件， 半导体层带压 应力； 而对于 n型器件， 半导体层带拉应力。
9. 根据权利要求 8所述的方法， 其中， 衬底包括 Si, 初始鰭通过对衬 底进行构图而形成， 半导体层包括 SiGe或 Si:C。
10. 根据权利要求 7所述的方法， 其中， 在形成半导体层时， 对半导体 层进行原位掺杂。
PCT/CN2012/086657 2012-11-30 2012-12-14 鳍结构制造方法 WO2014082350A1 (zh)

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