WO2014012263A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014012263A1
WO2014012263A1 PCT/CN2012/079081 CN2012079081W WO2014012263A1 WO 2014012263 A1 WO2014012263 A1 WO 2014012263A1 CN 2012079081 W CN2012079081 W CN 2012079081W WO 2014012263 A1 WO2014012263 A1 WO 2014012263A1
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Prior art keywords
layer
masking layer
forming
substrate
semiconductor
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PCT/CN2012/079081
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English (en)
French (fr)
Inventor
朱慧珑
梁擎擎
钟汇才
吴昊
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中国科学院微电子研究所
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Priority to US13/981,808 priority Critical patent/US9147745B2/en
Publication of WO2014012263A1 publication Critical patent/WO2014012263A1/zh

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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same. Background technique
  • a gate stack comprising a high-k gate dielectric and a metal gate conductor.
  • semiconductor devices including such gate stacks are typically fabricated using a replacement gate process.
  • the replacement gate process involves forming a high K gate dielectric and a metal gate conductor in the aperture defined between the gate spacers.
  • due to the shrinking device size it has become increasingly difficult to form high-k gate dielectrics and metal conductors in such small pores.
  • ET-SOI substrates are expensive. Summary of the invention
  • a method of fabricating a semiconductor device comprising: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first masking layer on the semiconductor layer; using the first masking layer as a mask, Forming an opening into the substrate; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulator material therein; forming one of a source region and a drain region in the opening; forming a second masking layer on the substrate Forming another one of the source region and the drain region with the second masking layer as a mask; removing a portion of the second masking layer; and forming a gate dielectric layer, and forming a sidewall spacer on a sidewall of the remaining portion of the second masking layer
  • the form forms a gate conductor.
  • a semiconductor device comprising: a substrate; a buried insulator layer on the substrate; a semiconductor layer on the buried insulator layer; and a source region formed on the substrate, a drain region and a gate stack formed on the semiconductor layer, wherein the gate stack includes: a gate dielectric; and a gate conductor, the gate conductor DRAWINGS
  • FIGS. 1-12 are schematic diagrams showing a flow of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a masking layer may be utilized to form source and drain regions in an active region on a substrate.
  • the first masking layer may be utilized to mask the active region, exposing a portion of the active region, which may be processed to form one of the source and drain regions.
  • the second masking layer can be used to mask the active region to expose Another portion of the active region can be processed to form another of the source and drain regions.
  • the first and second masking layers may be formed in various ways as long as they are capable of masking the active regions and exposing corresponding portions of the active regions, thereby serving as a mask in the source/drain formation process. Additionally, the second masking layer can include a portion of the first masking layer.
  • the second masking layer can be patterned to remove a portion of the second masking layer to further expose a further portion of the active region.
  • a gate stack can be formed over the exposed portion.
  • the gate stack can be formed by a sidewall process.
  • the second masking layer preferably includes portions of different materials, at least some of which may have etch selectivity with respect to each other such that portions thereof may be selectively removed.
  • a sacrificial layer can be utilized to define the buried insulator layer.
  • a sacrificial layer and a semiconductor layer may be sequentially formed on the substrate.
  • An opening is then formed to expose the sacrificial layer and selectively remove at least a portion of the sacrificial layer.
  • the buried insulator layer is formed by filling an insulator material in a cavity formed by removing the sacrificial layer.
  • buried insulators can be combined with alternative sidewall processes. For example, an opening may be formed using the first masking layer as a mask, and a buried insulator layer may be formed through the opening. Then, a source region or a drain region is formed by forming (e.g., by epitaxially growing) a semiconductor material in the opening.
  • the substrate 100 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a SiGe substrate, or the like.
  • a body Si substrate will be described as an example for convenience of explanation.
  • the sacrificial layer 102 and the semiconductor layer 104 may be sequentially formed, for example, by epitaxial growth.
  • the sacrificial layer 102 may, for example, comprise SiGe (Ge atomic percentage is, for example, about 10% to 30%) and has a thickness of about 10-50 nm.
  • the semiconductor layer 104 may comprise the same or a different material than the substrate 100; in this example, Si is included and has a thickness of about 5-30 nm.
  • shallow trench isolation (STI) 106 may be formed to isolate the active regions of the individual devices.
  • STI 106 can include, for example, an oxide (e.g., silicon oxide). It is to be noted here that in the examples described below, only the case of forming a single device has been described for convenience of explanation. However, the present disclosure is not limited to this, but can be applied to the case of forming two or more devices.
  • a thin oxide layer (not shown) is formed on the surface of the semiconductor layer 104, for example by deposition.
  • the oxide layer for example, has a thickness of 5 to 1 nm, which can then be used to form an interfacial layer (IL).
  • a first masking layer 108 having a thickness of about 100-200 nm is formed on the semiconductor layer 104, for example, by deposition.
  • the first masking layer 108 can include a nitride (eg, silicon nitride) and can be patterned to cover a portion of the active region by, for example, reactive ion etching (RIE) (this portion generally corresponds to a subsequently formed source region Or the drain region and the channel region).
  • RIE reactive ion etching
  • a source/drain formation process may be performed to form one of the source and drain regions in the exposed active region portion.
  • the opening 110 extending into the substrate 100 may be formed by selective etching using the first masking layer 108 as a mask.
  • This selective etching can be performed, for example, by anisotropic etching of the semiconductor layer 104 (for example, Si) and the sacrificial layer 102 (for example, SiGe) by TMAH, KOH, EDP, ⁇ 2 ⁇ 4 ⁇ ⁇ 2 0 solution. .
  • the buried insulator layer may be formed by replacing the sacrificial layer 102 (in whole or in part) with an insulator material to further improve device performance.
  • the sacrificial layer 102 eg, SiGe
  • the semiconductor layer 104 eg, Si
  • the sacrificial layer 102 is removed to form a void (this void and opening are shown together in FIG. 3 as 110').
  • the void extends beyond the gate region to be formed to the source or drain region on the other side.
  • the voids may be filled, for example, by regrowth (for example, by oxidation in an oxygen atmosphere) or deposition (for example, chemical vapor deposition (CVD)) to form oxides and etch back. Insulator material 112 (oxide in this example).
  • one of the source and drain regions 114 is formed in the opening 100, for example, by epitaxial growth.
  • one of the source and drain regions 114 may include a semiconductor material having a different composition from the semiconductor layer 104, thereby generating stress in a channel region to be formed in the semiconductor layer 104, for example, due to a difference in lattice constant therebetween. .
  • source/drain regions 114 can be stressed; for n-type devices, source/drain regions 114 can be tensile stressed.
  • the source/drain regions 114 may include SiGe (for example, a Ge atomic percentage is about 15-75%) for a p-type device; and for an n-type device, the source/drain regions 114 Si:C may be included (eg, a C atomic percentage is about 0.2-2%). While epitaxially growing the source/drain regions 114, in-situ doping may be performed to dope them into corresponding conductor types.
  • a person skilled in the art can conceive various ways to form such a stressed source/drain region, which will not be described herein.
  • the present disclosure is not limited to forming stress-bearing source/drain regions.
  • a semiconductor material e.g., Si
  • the semiconductor layer 104 may be formed by epitaxial growth in the opening 110 and the source/drain regions may be formed by respective doping.
  • a second sub-masking layer 116 is formed on the substrate 100.
  • the second sub-masking layer 116 may include, for example, an oxide such as silicon oxide.
  • a planarization process such as chemical mechanical polishing (CMP) can then be performed, The first masking layer 108 is exposed for subsequent processing.
  • CMP chemical mechanical polishing
  • the first masking layer 108 e.g., silicon nitride
  • the second sub-masking layer 116 e.g., silicon oxide
  • This selective etching can be performed, for example, by wet etching (e.g., hot phosphoric acid) or by wet/RIE combined etching.
  • the well implantation (shown by an arrow in FIG. 7) may be performed with the second sub-masking layer 116 as a mask to be buried in the substrate 100 under the insulator layer 112.
  • An asymmetric well 118 is formed.
  • the dashed box 118 in Fig. 7 is only shown as a regular rectangular shape for convenience of illustration. In fact, the shape of the well 118 is determined by the implantation process and may not have a clear boundary.
  • Such an asymmetric well 118 can effectively effect the punch-through effect of the device and can reduce band-to-band leakage, and it should be noted here that the formation of the well 118 is final. It is not necessary for semiconductor devices.
  • a spacer 120 may be formed on the sidewall of the second sub-masking layer 116.
  • the spacer 120 is formed to have a width of about 8-30 nm to cover a portion of the active region (this portion substantially corresponds to the subsequently formed gate region).
  • Sidewall 120 can include, for example, a nitride (e.g., silicon nitride).
  • a nitride e.g., silicon nitride
  • the second sub-masking layer 116 and the sidewall spacers 120 expose a portion of the active region.
  • the source/drain formation process may be performed using the second masking layer as a mask to form the other of the source region and the drain region in the exposed active region portion.
  • a stressed source/drain region may be formed to improve device performance.
  • the semiconductor layer 104 (due to extending beyond the gate region), the insulating material 112 that may exist, and the remaining sacrificial layer 102 may exist.
  • the portion and substrate 100 are selectively etched to form openings 122 that extend into substrate 100.
  • the semiconductor layer 104 (eg, Si) may be anisotropically etched by a TMAH solution; then, an insulating material 112 (eg, an oxide) that may be present may be etched by RIE; The TMAH solution is performed to anisotropically etch the sacrificial layer 102 and the substrate 100 that may be present. Then, as shown in FIG. 10, another 124 of the source and drain regions is formed in the opening 122, for example, by epitaxial growth.
  • TMAH solution eg, an oxide
  • the source/drain regions 124 may include a semiconductor material having a different composition from the semiconductor layer 104, thereby generating stress in a channel region to be formed in the semiconductor layer 104, for example, due to a difference in lattice constant therebetween.
  • the source/drain regions 124 may be under compressive stress; and for an n-type device, the source/drain regions 124 may be under tensile stress.
  • the source/drain regions 124 may include SiGe (for example, a Ge atomic percentage is about 15-75%) for a p-type device; and for an n-type device, the source/drain regions 124 Si:C may be included (eg, a C atomic percentage is about 0.2-2%). While epitaxially growing the source/drain regions 114, In-situ doping can be performed to dope them to the corresponding conductor type.
  • a person skilled in the art can conceive various ways to form such a stressed source/drain region, which will not be described herein.
  • the present disclosure is not limited to forming stress-bearing source/drain regions.
  • a semiconductor material e.g., Si
  • the semiconductor layer 104 may be formed by epitaxial growth in the opening 122 and the source/drain regions may be formed by respective doping.
  • a portion of the second masking layer can be removed by selective etching.
  • sidewall spacers 120 e.g., silicon nitride
  • hot phosphoric acid can be selectively removed by hot phosphoric acid.
  • the gate dielectric layer 126 can be formed, for example, by deposition.
  • the gate dielectric layer 126 can comprise a high-k gate dielectric material such as HfO 2 and can have a thickness of about 2-4 nm.
  • the gate conductor 130 may be formed in the form of a sidewall. In forming the gate conductor, for example, by controlling parameters in the sidewall forming process such as deposition thickness, RIE parameters, etc., the gate conductor 130 in the form of a sidewall spacer formed is formed to have a width of about 10-35 nm, so that it is formed substantially below. Between the source and drain areas.
  • the gate conductor 130 may include a metal gate conductor material such as Ti, Co, Ni, Al, W, alloys thereof, and the like.
  • the function adjustment layer 128 can also be formed between the gate dielectric layer 126 and the gate conductor 130.
  • the work function adjusting layer 128 may include, for example, TaC, window, TaTbN, TaErN TaYbN TaSiN, HfSiN MoSiN, RuTa, NiTa, MoN, TiSiN TiCN TaAlC, TiAlN TaN, PtSi, Ni 3 Si Pt, Ru, Ir, Mo, HfRu, RuO x and combinations thereof may have a thickness of about 2-10 nm.
  • the gate dielectric layer 126 and the work function adjusting layer 128 shown in FIG. 11 are selectively etched using the gate conductor 130 as a mask.
  • the interlayer dielectric layer 132 may be formed by deposition and subjected to a planarization treatment such as CMP.
  • the interlayer dielectric layer 132 may include an oxide (e.g., silicon oxide), a nitride, or a combination thereof.
  • a contact portion 136 corresponding to the source and drain regions can be formed.
  • the contact portion 136 may include, for example, a metal such as W, Cu, or the like.
  • a metal silicide layer 134 may also be formed in the source and drain regions such that the contact portion 136 is in contact with the source and drain regions through the metal silicide layer 134.
  • the metal silicide layer 134 may include, for example, NiPtSi. There are various means for forming the metal silicide layer 134 and the contact portion 136, which will not be described herein.
  • the semiconductor device is formed on a structure of a substrate + buried insulator layer + semiconductor layer (similar to an SOI substrate), including source and drain regions (114, 124) and a gate stack (126, 128). , 130).
  • the buried insulator layer 112 may include an insulator material sandwiched between cavities between the source and drain regions, such cavities being defined, for example, by a sacrificial layer.
  • Gate stack In particular, the gate conductor 130 therein is formed in the form of a side wall on the sidewall of the masking layer (or dielectric layer) 116 on the side of the gate stack (the left side in FIG. 12).
  • the semiconductor device may further include a gate spacer structure surrounding the gate stack.
  • the semiconductor device may further include an asymmetric well 118 formed in the substrate, the asymmetric well being away from a source region of the one side of the gate stack (left side in FIG. 12) or The drain area extends.
  • the asymmetric well is located in the source region, thereby effectively preventing device penetration and reducing leakage current between the strips.
  • the form and formation manner of the first masking layer and the second masking layer of the present disclosure are not limited to the above examples.
  • the first masking layer does not expose the active area portion on the left side in the drawing as shown in Fig. 2, but may expose the active area portion on the right side in the drawing.
  • the first masking layer may not be completely removed, but a part of the first masking layer may be left on the sidewall of the second sub-masking layer, similar to the side wall shown in FIG. (Under this example, the asymmetric well shown in Fig. 7 cannot be formed).
  • the sidewall spacer may not be completely removed, but a portion of the sidewall spacer may be left on the sidewall of the second sub-masking layer, which may serve as a gate stack formed subsequently. Grid side wall.

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Abstract

提供一种半导体器件及其制造方法。该方法包括：在衬底（100）上依次形成牺牲层（102）和半导体层（104）；在半导体层（104）上形成第一掩蔽层（108）；以第一掩蔽层（108）为掩模，形成进入衬底（100）的开口（110）；经由所述开口（110），选择性去除至少一部分牺牲层（102），并在其中填充绝缘体材料（112）；在所述开口（110）中形成源区和漏区之一（114）；在衬底（100）上形成第二掩蔽层（116，120）；以第二掩蔽层（116，120）为掩模，形成源区和漏区中另一个（124）；去除第二掩蔽层（116，120）的一部分；以及形成栅介质层（126），并在第二掩蔽层（116，120）的剩余部分的侧壁上以侧墙的形式形成栅导体（130）。

Description

半导体器件及其制造方法
本申请要求了 2012年 7月 17日提交的、 申请号为 201210247385.2、 发明名称为
"半导体器件及其制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在 本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种半导体器件及其制造方法。 背景技术
随着半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为此， 提出了使用包括 高 K栅介质和金属栅导体的栅堆叠。 为避免栅堆叠的性能退化， 包括这种栅堆叠的半 导体器件通常利用替代栅工艺来制造。 替代栅工艺涉及在栅侧墙之间限定的孔隙中形 成高 K栅介质和金属栅导体。 然而， 由于器件尺寸的缩小， 要在如此小的孔隙中形成 高 K栅介质和金属导体越来越困难。
另一方面， 在极薄绝缘体上半导体 （ET-SOI)衬底上形成的半导体器件具有良好 的短沟道效应控制和相对小的随机掺杂剂波动。 但是， ET-SOI衬底是昂贵的。 发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面， 提供了一种制造半导体器件的方法， 包括： 在衬底上依 次形成牺牲层和半导体层； 在半导体层上形成第一掩蔽层； 以第一掩蔽层为掩模， 形 成进入衬底的开口； 经由所述开口， 选择性去除至少一部分牺牲层， 并在其中填充绝 缘体材料； 在所述开口中形成源区和漏区之一； 在衬底上形成第二掩蔽层； 以第二掩 蔽层为掩模， 形成源区和漏区中另一个； 去除第二掩蔽层的一部分； 以及形成栅介质 层， 并在第二掩蔽层的剩余部分的侧壁上以侧墙的形式形成栅导体。
根据本公开的另一方面， 提供了一种半导体器件， 包括： 衬底； 位于衬底上的埋 入绝缘体层； 位于埋入绝缘体层上的半导体层； 以及在衬底上形成的源区、 漏区和在 半导体层上形成的栅堆叠， 其中， 所述栅堆叠包括： 栅介质； 和栅导体， 所述栅导体 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和 优点将更为清楚， 在附图中：
图 1-12是示出了根据本公开实施例的制造半导体器件流程的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是示例性 的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知结构和技术的 描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。 这些图并非是按比例绘制 的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些细节。 图中所 示出的各种区域、 层的形状以及它们之间的相对大小、 位置关系仅是示例性的， 实际 中可能由于制造公差或技术限制而有所偏差， 并且本领域技术人员根据实际所需可以 另外设计具有不同形状、 大小、 相对位置的区域 /层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该层 /元件 可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外， 如果在 一种朝向中一层 /元件位于另一层 /元件"上"， 那么当调转朝向时， 该层 /元件可以位于 该另一层 /元件 "下"。
在常规工艺中， 在利用 "伪"栅堆叠以及该伪栅堆叠两侧的侧墙在衬底中制造出 源区和漏区之后， 保留两侧的侧墙而在侧墙之间限定出孔隙， 通过填充孔隙来形成真 正的栅堆叠。 与此不同， 在本公开中， 提出了一种 "替代侧墙"工艺。 在形成源区和 漏区之后， 保留在源区和漏区之一一侧存在的材料层， 并在该保留的材料层的侧壁上 以侧墙的形式形成栅堆叠 （特别是， 栅导体）。 从而可以在较大的空间 （具体地， 大 致为栅区 +源区和漏区中另一个的区域） 上来形成栅堆叠， 相比于仅在侧墙之间的小 孔隙中形成栅堆叠的常规工艺， 可以使得工艺更加容易进行。
根据本发明的实施例， 可以利用掩蔽层来在衬底上的有源区中形成源区和漏区。 具体地， 例如可以利用第一掩蔽层来掩蔽有源区， 露出有源区的一部分， 可以对该部 分进行处理以形成源区和漏区之一。 另外， 可以利用第二掩蔽层来掩蔽有源区， 露出 有源区的另一部分， 可以对该另一部分进行处理以形成源区和漏区中另一个。
第一和第二掩蔽层可以按各种方式来形成， 只要它们能够掩蔽有源区并露出有源 区的相应部分， 从而在源 /漏形成工艺中充当掩模。 另外， 第二掩蔽层可以包括第一掩 蔽层的一部分。
在如上所述形成源区和漏区之后， 可以对第二掩蔽层进行构图， 以去除第二掩蔽 层的一部分， 从而进一步露出有源区的又一部分。 可以在露出的该又一部分上来形成 栅堆叠。 例如， 栅堆叠可以通过侧墙工艺来形成。 为了便于第二掩蔽层的构图， 第二 掩蔽层优选地包括由不同材料构成的若干部分， 这些部分中的至少一些相对于彼此可 以具有刻蚀选择性， 从而可以选择性去除其中的一些部分。
另外， 在本公开中， 可以利用牺牲层来限定埋入绝缘体层。 例如， 在衬底上可以 依次形成牺牲层和半导体层。 然后， 形成开口以露出牺牲层， 并选择性去除牺牲层的 至少一部分。 通过在由于去除牺牲层而形成的空腔中填充绝缘体材料， 来形成埋入绝 缘体层。
这种埋入绝缘体的形成可以与替代侧墙工艺相结合。 例如， 可以以第一掩蔽层为 掩模， 来形成开口， 并经由所述开口形成埋入绝缘体层。 然后， 通过在该开口中形成 (例如， 通过外延生长） 半导体材料， 来形成源区或漏区。
本公开可以各种形式呈现， 以下将描述其中一些示例。
如图 1所示， 提供衬底 100。 该衬底 100可以是各种形式的衬底， 例如但不限于体 半导体材料衬底如体 Si衬底、 SiGe衬底等。 在以下的描述中， 为方便说明， 以体 Si衬 底为例进行描述。
在衬底 100上， 例如可以通过外延生长， 依次形成牺牲层 102和半导体层 104。 牺 牲层 102例如可以包括 SiGe (Ge原子百分比例如为约 10%-30%)， 厚度为约 10-50nm。 半导体层 104可以包括与衬底 100相同或不同的材料； 在本示例中包括 Si， 厚度为约 5-30nm。
在衬底 100上， 可以形成有浅沟槽隔离 （STI) 106， 用以隔离单独器件的有源区。 STI 106例如可以包括氧化物 （例如， 氧化硅）。 这里需要指出的是， 在以下描述的示 例中， 为方便说明， 仅描述了形成单个器件的情况。 但是本公开不局限于此， 而是可 以应用于形成两个或更多器件的情况。
可选地， 在半导体层 104的表面上例如通过沉积形成一薄氧化物层 （未示出）。 该 氧化物层例如具有 5-lOnm的厚度， 可以在随后用来形成界面层 （IL)。 接着， 如图 2所示， 在半导体层 104上例如通过沉积形成厚度约为 100-200nm的第 一掩蔽层 108。 例如， 第一掩蔽层 108可以包括氮化物 （例如， 氮化硅）， 且可以通过 例如反应离子刻蚀 （RIE) 被构图为覆盖有源区的一部分 （该部分大致对应于随后形 成的源区或漏区以及沟道区部分）。 此时， 可以进行源 /漏形成工艺， 来在该露出的有 源区部分中形成源区和漏区之一。
具体地， 可以以第一掩蔽层 108为掩模， 通过选择性刻蚀， 来形成延伸进入衬底 100的开口 110。 这种选择性刻蚀例如可以通过 TMAH、 KOH、 EDP、 Ν2Η4·Η20溶液对 半导体层 104 (例如， Si) 和牺牲层 102 (例如， SiGe) 进行各向异性刻蚀来完成。
由于开口 110的形成， 露出了牺牲层 102。 根据本公开的一实施例， 可以通过以绝 缘体材料将牺牲层 102 (全部或部分地） 替代， 来形成埋入绝缘体层， 以便进一步改 善器件性能。 具体地， 如图 3所示， 可以经由开口 100， 通过湿法刻蚀， 相对于衬底 100 和半导体层 104 (例如， Si)选择性刻蚀牺牲层 102 (例如， SiGe)， 来至少部分地去除 牺牲层 102， 从而形成空隙 （该空隙与开口在图 3中一起示出为 110')。 优选地， 该空隙 延伸超过要形成的栅区到达另一侧的源区或漏区。 然后， 如图 4所示， 例如可以通过 再生长 （例如， 通过在氧气气氛中氧化） 或沉积 （例如， 化学气相淀积 （CVD)) 来 形成氧化物并进行回蚀， 来在空隙中填充绝缘体材料 112 (在该示例中为氧化物）。
然后， 如图 5所示， 在开口 100中例如通过外延生长形成源区和漏区之一 114。 例 如， 源区和漏区之一 114可以包括与半导体层 104不同成分的半导体材料， 从而例如由 于两者之间的晶格常数不同而在将要在半导体层 104中形成的沟道区中产生应力。 对 于 p型器件， 源 /漏区 114可以带压应力； 而对于 n型器件， 源 /漏区 114可以带拉应力。 例如， 在半导体层 104包括 Si的情况下， 对于 p型器件， 源 /漏区 114可以包括 SiGe (例 如， Ge原子百分比为约 15-75%); 而对于 n型器件， 源 /漏区 114可以包括 Si:C (例如， C原子百分比为约 0.2-2%)。 在外延生长源 /漏区 114的同时， 可以进行原位掺杂， 以将 其掺杂为相应的导体类型。
本领域技术人员可以想到多种方式来形成这种带应力的源 /漏区， 在此不再赘述。 当然， 本公开不限于形成带应力的源 /漏区。 例如， 可以在开口 110中通过外延生 长形成与半导体层 104相同的半导体材料 （例如， Si) 并通过相应的掺杂来形成源 /漏 区。
接下来， 如图 6所示， 在衬底 100上形成第二子掩蔽层 116。 第二子掩蔽层 116例如 可以包括氧化物 （如氧化硅）。 然后可以进行平坦化处理例如化学机械抛光 （CMP)， 以露出第一掩蔽层 108， 以便随后进行处理。
随后， 如图 7所示， 可以通过相对于第二子掩蔽层 116 (例如， 氧化硅）， 选择性 刻蚀第一掩蔽层 108 (例如， 氮化硅）， 以去除第一掩蔽层 108。 这种选择性刻蚀例如 可以通过湿法刻蚀 （例如， 热磷酸） 或者通过湿法 /RIE组合刻蚀来进行。
此时， 根据本公开的一实施例， 可以以第二子掩蔽层 116为掩模， 进行阱注入（如 图 7中的箭头所示）， 以在埋入绝缘体层 112下方的衬底 100中形成非对称阱 118。 这里 需要指出的是， 图 7中的虚线框 118仅仅是为了图示方便而示出为规则的矩形形状。 实 际上， 阱 118的形状由注入工艺决定， 并且可能没有明确的边界。 这种非对称阱 118可 以有效地方式器件的穿通（punch-through)效应， 并可以减小带间泄漏 （band-to-band leakage),,这里需要指出的是，阱 118的形成对于最终的半导体器件而言并非是必要的。
然后， 如图 8所示， 在第二子掩蔽层 116的侧壁上可以形成侧墙 120。 例如， 侧墙 120被形成为具有约 8-30nm的宽度， 以覆盖有源区的一部分 （该部分大致对应于随后 形成的栅区）。 侧墙 120例如可以包括氮化物 （例如， 氮化硅）。 存在多种手段来形成 侧墙， 在此不对侧墙的形成进行详细描述。
这样， 第二子掩蔽层 116和侧墙 120 (构成 "第二掩蔽层"） 露出了有源区的一部 分。此时， 可以第二掩蔽层为掩模进行源 /漏形成工艺， 来在该露出的有源区部分中形 成源区和漏区中另一个。
根据本公开的一实施例， 可以形成带应力的源 /漏区， 以改善器件性能。 具体地， 如图 9所示， 以第二掩蔽层（116+120)为掩模， 对半导体层 104、 （由于延伸超过栅区） 可能存在的绝缘体材料 112、 可能存在的牺牲层 102的剩余部分以及衬底 100进行选择 性刻蚀， 来形成延伸进入衬底 100的开口 122。 例如， 可以通过 TMAH溶液， 对半导体 层 104 (例如， Si) 进行各向异性刻蚀； 然后， 可以通过 RIE， 对可能存在的绝缘体材 料 112 (例如， 氧化物）进行刻蚀； 随后， 可以利用 TMAH溶液进行， 对可能存在的牺 牲层 102和衬底 100各向异性刻蚀。 然后， 如图 10所示， 在开口 122中例如通过外延生 长形成源区和漏区中另一个 124。 例如， 源 /漏区 124可以包括与半导体层 104不同成分 的半导体材料， 从而例如由于两者之间的晶格常数不同而在将要在半导体层 104中形 成的沟道区中产生应力。 对于 p型器件， 源 /漏区 124可以带压应力； 而对于 n型器件， 源 /漏区 124可以带拉应力。 例如， 在半导体层 104包括 Si的情况下， 对于 p型器件， 源 / 漏区 124可以包括 SiGe (例如， Ge原子百分比为约 15-75%); 而对于 n型器件， 源 /漏区 124可以包括 Si:C (例如， C原子百分比为约 0.2-2%)。 在外延生长源 /漏区 114的同时， 可以进行原位掺杂， 以将其掺杂为相应的导体类型。
本领域技术人员可以想到多种方式来形成这种带应力的源 /漏区， 在此不再赘述。 当然， 本公开不限于形成带应力的源 /漏区。 例如， 可以在开口 122中通过外延生 长形成与半导体层 104相同的半导体材料 （例如， Si) 并通过相应的掺杂来形成源 /漏 区。
随后， 可以通过选择性刻蚀， 去除第二掩蔽层的一部分。 例如， 侧墙 120 (例如， 氮化硅） 可以通过热磷酸来选择性去除。 这样， 就在第二子掩蔽层 116的一侧留下了 较大的空间 （大致对应于栅区 +所述源区和漏区中另一个的区域）， 从而可以容易地进 行栅堆叠的形成。
然后， 如图 11所示， 形成栅堆叠。 具体地， 例如可以通过沉积形成栅介质层 126。 例如， 栅介质层 126可以包括高 K栅介质材料如 Hf02， 厚度可以为约 2-4nm。 在栅介质 层 130上， 可以以侧墙的形式形成栅导体 130。 在形成栅导体时， 例如可以通过控制侧 墙形成工艺中的参数如沉积厚度、 RIE参数等， 使得所形成的侧墙形式的栅导体 130宽 度为约 10-35nm， 从而基本上位于下方已经形成的源区和漏区之间。 例如， 栅导体 130 可以包括金属栅导体材料如 Ti 、 Co、 Ni、 Al、 W及其合金等。 优选地， 在栅介质层 126和栅导体 130之间还可以形成功函数调节层 128。 功函数调节层 128例如可以包括 TaC、 窗、 TaTbN、 TaErN TaYbN TaSiN、 HfSiN MoSiN、 RuTa、 NiTa、 MoN、 TiSiN TiCN TaAlC、 TiAlN TaN、 PtSi、 Ni3Si Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx及 其组合， 厚度可以约为 2-10nm。 图 11中示出的栅介质层 126和功函数调节层 128是以栅 导体 130为掩模进行选择性刻蚀后的形式。
此后， 如图 12所示， 可以通过沉积形成层间电介质层 132， 并进行平坦化处理如 CMP。 层间电介质层 132可以包括氧化物 （例如， 氧化硅）、 氮化物或其组合。 然后， 可以形成与源区和漏区相对应的接触部 136。接触部 136例如可以包括金属如 W、 Cu等。 根据一实施例， 为了增强接触， 还可以在源区和漏区中形成金属硅化物层 134， 从而 接触部 136通过金属硅化物层 134与源区和漏区接触。 金属硅化物层 134例如可以包括 NiPtSi。 存在多种手段来形成金属硅化物层 134和接触部 136， 在此不再赘述。
这样， 就得到了根据本公开实施例的示例半导体器件。 如图 12所示， 该半导体器 件形成在衬底 +埋入绝缘体层 +半导体层的结构 （类似于 SOI衬底） 上， 包括源区和漏 区 （114、 124) 以及栅堆叠 （126， 128， 130)。 埋入绝缘体层 112可以包括夹于源区 和漏区之间的空腔中的绝缘体材料， 这种空腔例如是通过牺牲层来限定的。 栅堆叠， 尤其是其中的栅导体 130， 以侧墙的形式形成于栅堆叠一侧 （图 12中的左侧） 的掩蔽 层 （或者说， 电介质层） 116的侧壁上。 源区和漏区 114、 124可以带应力。 在本发明 的一个实施例中， 该半导体器件还可以包括环绕栅堆叠的栅侧墙结构。 在本公开的一 个实施例中， 该半导体器件还可以包括在衬底中形成的非对称阱 118， 所述非对称阱 远离栅堆叠所述一侧（图 12中的左侧）的源区或漏区延伸。在本发明的一个实施例中， 该非对称阱位于源区， 从而能够有效避免器件穿透以及减少带 -带之间的漏电流。
这里需要指出的是， 本公开的第一掩蔽层和第二掩蔽层的形式和形成方式不限于 以上示例。 例如， 第一掩蔽层并非如图 2所示那样露出图中左侧的有源区部分， 而是 可以露出图中右侧的有源区部分。 另外， 在图 6所示的结构中， 可以并非完全去除第 一掩蔽层， 而是可以在第二子掩蔽层的侧壁上留下一部分第一掩蔽层， 类似于图 8所 示的侧墙（这种示例下， 不能形成图 7所示的非对称阱）。 另外， 在图 10所示的结构中， 可以并非完全去除侧墙， 而是可以在第二子掩蔽层的侧壁上留下侧墙的一部分， 这一 部分侧墙例如可以充当随后形成的栅堆叠的栅侧墙。
在以上的描述中， 对于各层的构图、 刻蚀等技术细节并没有做出详细的说明。 但 是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以上描述的方法并不完全 相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例 中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。 但是， 这些实施例仅仅是为了说明的目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价物限定。 不脱 离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这些替代和修改都应落 在本公开的范围之内。

Claims

权 利 要 求
1 . 一种制造半导体器件的方法， 包括：
在衬底上依次形成牺牲层和半导体层；
在半导体层上形成第一掩蔽层；
以第一掩蔽层为掩模， 形成进入衬底的开口；
经由所述开口， 选择性去除至少一部分牺牲层， 并在其中填充绝缘体材料； 在所述开口中形成源区和漏区之一；
在衬底上形成第二掩蔽层；
以第二掩蔽层为掩模， 形成源区和漏区中另一个；
去除第二掩蔽层的一部分； 以及
形成栅介质层， 并在第二掩蔽层的剩余部分的侧壁上以侧墙的形式形成栅导体。
2. 根据权利要求 1所述的方法， 其中， 形成第二掩蔽层的操作包括： 在衬底上形成第二子掩蔽层， 并平坦化以露出第一掩蔽层；
去除第一掩蔽层； 以及
在第二子掩蔽层的侧壁上形成侧墙，
其中， 所述第二子掩蔽层和侧墙构成所述第二掩蔽层。
3. 根据权利要求 2所述的方法， 在去除第一掩蔽层之后， 以及在第二子掩蔽 层的侧壁上形成侧墙之前， 还包括：
以第二子掩蔽层为掩模， 进行阱注入。
4. 根据权利要求 2所述的方法， 其中， 去除第二掩蔽层的一部分包括： 去除所述侧墙的至少一部分。
5. 根据权利要求 1所述的方法， 其中， 在所述开口中形成源区和漏区之一包 括：
在所述开口中外延生长能够在半导体层中施加应力的半导体材料。
6. 根据权利要求 5所述的方法， 其中， 形成源区和漏区中另一个包括： 以第二掩蔽层为掩模， 形成进入衬底的另一开口； 以及
在所述另一开口中外延生长能够在半导体层中施加应力的所述半导体材料。
7. 根据权利要求 2所述的方法， 其中，
第一掩蔽层包括氮化物； 第二子掩蔽层包括氧化物； 以及
侧墙包括氮化物。
8. 一种半导体器件， 包括：
衬底；
位于衬底上的埋入绝缘体层；
位于埋入绝缘体层上的半导体层； 以及
在衬底上形成的源区、 漏区和在半导体层上形成的栅堆叠，
其中， 所述栅堆叠包括：
栅介质； 和
栅导体，所述栅导体以侧墙形式形成于位于栅堆叠一侧的电介质层或者栅侧 墙的侧壁上。
9. 根据权利要求 8所述的半导体器件， 其中， 埋入绝缘体层包括夹于源区和 漏区之间的空腔中的绝缘体材料。
10. 根据权利要求 8所述的半导体器件， 其中， 源区和漏区分别包括： 延伸至 衬底、 能够在半导体层中施加应力的半导体材料填充部。
11. 根据权利要求 8所述的半导体器件， 还包括：
在衬底中形成的非对称阱， 所述非对称阱远离栅堆叠所述一侧的源区或漏区延 伸。
12. 根据权利要求 9所述的半导体器件， 其中， 衬底和半导体层包括 Si， 牺牲 层包括 SiGe。
13. 根据权利要求 10所述的半导体器件， 其中， 半导体材料填充部包括 SiGe 或 Si:C。
14. 根据权利要求 9所述的半导体器件， 其中， 绝缘体材料包括氧化物。
15. 根据权利要求 8所述的半导体器件， 还包括： 设置在栅介质层和栅导体之 间的功函数调节层。
PCT/CN2012/079081 2012-07-17 2012-07-24 半导体器件及其制造方法 WO2014012263A1 (zh)

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