CN103681279B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN103681279B
CN103681279B CN201210356635.6A CN201210356635A CN103681279B CN 103681279 B CN103681279 B CN 103681279B CN 201210356635 A CN201210356635 A CN 201210356635A CN 103681279 B CN103681279 B CN 103681279B
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side wall
substrate
masking layer
drain region
source region
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CN103681279A (zh
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朱慧珑
梁擎擎
钟汇才
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210356635.6A priority Critical patent/CN103681279B/zh
Priority to US14/389,095 priority patent/US10128351B2/en
Priority to PCT/CN2012/082570 priority patent/WO2014043947A1/zh
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Abstract

本申请公开了一种半导体器件及其制造方法。一示例方法可以包括：在衬底上形成第一掩蔽层；以第一掩蔽层为掩模，形成源区和漏区之一；在衬底上形成第二掩蔽层，并去除第一掩蔽层；在第二掩蔽层的侧壁上形成掩蔽侧墙；以第二掩蔽层和掩蔽侧墙为掩模，形成源区和漏区中另一个；去除掩蔽侧墙的至少一部分；以及形成栅介质层，并在第二掩蔽层或者在掩蔽侧墙的剩余部分的侧壁上以侧墙的形式形成栅导体。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了使用包括高K栅介质和金属栅导体的栅堆叠。为避免栅堆叠的性能退化，包括这种栅堆叠的半导体器件通常利用替代栅工艺来制造。替代栅工艺涉及在栅侧墙之间限定的孔隙中形成高K栅介质和金属栅导体。然而，由于器件尺寸的缩小，要在如此小的孔隙中形成高K栅介质和金属导体越来越困难。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上形成第一掩蔽层；以第一掩蔽层为掩模，形成源区和漏区之一；在衬底上形成第二掩蔽层，并去除第一掩蔽层；在第二掩蔽层的侧壁上形成掩蔽侧墙；以第二掩蔽层和掩蔽侧墙为掩模，形成源区和漏区中另一个；去除掩蔽侧墙的至少一部分；以及形成栅介质层，并在第二掩蔽层或者在掩蔽侧墙的剩余部分的侧壁上以侧墙的形式形成栅导体。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；以及在衬底上形成的源区和漏区以及栅堆叠，其中，所述源区和漏区分别包括嵌入衬底中的外延生长层，所述栅堆叠包括：栅介质；和栅导体，所述栅导体以侧墙形式形成于位于栅堆叠一侧的电介质层或者栅侧墙的侧壁上。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-8是示出了根据本公开实施例的制造半导体器件流程的示意图；以及
图9-16是示出了根据本公开另一实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
在常规工艺中，在利用“伪”栅堆叠以及该伪栅堆叠两侧的侧墙在衬底中制造出源区和漏区之后，保留两侧的侧墙而在侧墙之间限定出孔隙，通过填充孔隙来形成真正的栅堆叠。与此不同，在本公开中，提出了一种“替代侧墙”工艺。在形成源区和漏区之后，保留源区和漏区之一一侧存在的材料层，并在该保留的材料层的侧壁上以侧墙的形式形成栅堆叠(特别是，栅导体)。从而可以在较大的空间(具体地，大致为栅区+源区和漏区中另一个的区域)上来形成栅堆叠，相比于仅在侧墙之间的小孔隙中形成栅堆叠的常规工艺，可以使得工艺更加容易进行。
本公开可以各种形式呈现，以下将描述其中一些示例。
首先，参照图1-8，描述根据本公开一实施例的制造半导体器件的流程。
如图1所示，提供衬底100。该衬底100可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在衬底100上，可以形成有浅沟槽隔离(STI)102，用以隔离单独器件的有源区。STI 102例如可以包括氧化物(例如，氧化硅)。这里需要指出的是，在以下描述的示例中，为方便说明，仅描述了形成单个器件的情况。但是本公开不局限于此，而是可以应用于形成两个或更多器件的情况。
可选地，在衬底100的表面上例如通过沉积形成一薄氧化物层(例如，氧化硅)104。该氧化物层104例如具有5-10nm的厚度，可以在随后用来形成界面层(IL)。在衬底100上(在形成氧化物层104的情况下，在氧化物层104的表面上)例如通过沉积形成厚度约为100-200nm的第一掩蔽层106。例如，第一掩蔽层1006可以包括氮化物(例如，氮化硅)，且可以通过例如反应离子刻蚀(RIE)被构图为露出有源区的一部分(该部分大致对应于随后形成的源区或漏区)。
在形成氧化物层104的情况下，可以相对于第一掩蔽层106(例如，氮化物)和衬底100(例如，体Si)，选择性刻蚀氧化物层104，以形成例如厚度约为0.5-1nm的IL 108。这里，为了图示方便，并没有示出IL 108的厚度与氧化物层104的厚度之间的差异。
由于第一掩蔽层106露出了有源区的一部分，可以以第一掩蔽层106为掩模进行源/漏形成工艺，来在该露出的有源区部分中形成源区和漏区之一。例如，这可以如下进行。
具体地，如图1(其中的竖直箭头)所示，可以进行延伸区(extension)注入，以形成延伸区116。例如，对于p型器件，可以通过注入p型杂质如In、BF2或B；对于n型器件，可以通过注入n型杂质如As或P，来形成延伸区。这里需要指出的是，图1中的虚线框116仅仅是为了图示方便而示出为规则的矩形形状。实际上，延伸区116的形状由注入工艺决定，并且可能没有明确的边界。另外，为了优化性能，可以在延伸区注入之前，进行晕圈(halo)注入。例如，对于p型器件，可以通过注入n型杂质如As或P；对于n型器件，可以通过注入p型杂质如In、BF2或B，来形成晕圈(未示出)。
然后，如图1中的倾斜箭头所示，可以进行倾角(angular)源/漏注入，形成源/漏注入区118。对于p型器件，可以通过注入p型杂质如In、BF2或B；对于n型器件，可以通过注入n型杂质如As或P，来形成源/漏注入区。这里需要指出的是，图1中的虚线框118仅仅是为了图示方便而示出为规则的矩形形状。实际上，源/漏注入区118的形状由注入工艺决定，并且可能没有明确的边界。
接下来，如图2所示，在衬底100上形成第二掩蔽层120，以至少覆盖上述形成的源区和漏区之一。第二掩蔽层120例如可以包括氧化物(如氧化硅)。然后可以进行平坦化处理例如化学机械抛光(CMP)，以露出第一掩蔽层106，以便随后进行处理。
随后，如图3所示，可以通过相对于第二掩蔽层120、氧化物层104(例如，氧化硅)，选择性刻蚀第一掩蔽层106(例如，氮化硅)，以去除第一掩蔽层106。这种选择性刻蚀例如可以通过热磷酸来进行。
根据本公开的一个实施例，为更好地控制短沟道效应以及抑制带间泄露，如图3所示，可以通过以第二掩蔽层120为掩模进行离子注入(图中箭头所示)，形成超陡后退阱(Super-steep-retrograded well，SSRW)110。例如，对于p型器件，可以通过注入n型杂质如As或P或Sb；对于n型器件，可以通过注入p型杂质如In、BF2或B，来形成SSRW。这里需要指出的是，图3中的虚线框110仅仅是为了图示方便而示出为规则的矩形形状。实际上，SSRW 110的形状由注入工艺决定，并且可能没有明确的边界。超陡后退阱有利于沟道离子的耗尽，有效改善短沟道效应。
然后，如图4所示，在第二掩蔽层120的侧壁上形成掩蔽侧墙112。例如，该掩蔽侧墙112被形成为具有约8-30nm的宽度，以覆盖有源区的一部分(该部分大致对应于随后形成的栅区)。掩蔽侧墙112例如可以包括电介质如氮化物(例如，氮化硅)，或者多晶硅。在以下以氮化硅掩蔽侧墙为例进行描述，但是本公开不限于此。
这样，如图4所示，第二掩蔽层120和掩蔽侧墙112露出了有源区的一部分。此时，可以该第二掩蔽层120和掩蔽侧墙112为掩模进行源/漏形成工艺，来在该露出的有源区部分中形成源区和漏区中另一个。例如，这可以如下进行。
具体地，如图5所示，可以进行延伸区(extension)注入，以形成延伸区124。另外，为了优化性能，可以在延伸区注入之前，进行晕圈(halo)注入，来形成晕圈(未示出)。然后，可以进行倾角源/漏注入，形成源/漏注入区126。关于这些注入，可以参见以上结合图1的描述。
接下来，如图6所示，可以进行退火处理例如尖峰退火、激光退火、快速退火等，以激活注入的杂质，形成最终的源/漏区128。
然后，可以通过选择性刻蚀，去除掩蔽侧墙112。例如，掩蔽侧墙112(例如，氮化硅)可以通过热磷酸来选择性去除。这样，就在第二掩蔽层120的一侧留下了较大的空间(大致对应于栅区+源区和漏区中另一个的区域)，从而可以容易地进行栅堆叠的形成。
然后，如图7所示，形成栅堆叠。具体地，例如可以通过沉积形成栅介质层130。例如，栅介质层130可以包括高K栅介质材料如HfO2，厚度可以为约2-4nm。可选地，在形成栅介质130之前，可以重构IL。例如，如以上参考图1所述，可以通过对氧化物层104进行选择性刻蚀，来形成IL(未示出)。在栅介质层130上，可以以侧墙的形式形成栅导体134。在形成栅导体时，例如可以通过控制侧墙形成工艺中的参数如沉积厚度、RIE参数等，使得所形成的侧墙形式的栅导体134基本上位于下方已经形成的源区和漏区之间。例如，栅导体134可以包括金属栅导体材料如Ti、Co、Ni、Al、W及其合金等。优选地，在栅介质层130和栅导体134之间还可以形成功函数调节层132。功函数调节层132例如可以包括TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTa、NiTa、MoN、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSi、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx及其组合，厚度可以约为2-10nm。
此后，如图8所示，可以通过沉积形成电介质层136，并进行平坦化处理如CMP。电介质层136可以包括氧化物(例如，氧化硅)、氮化物或其组合。此外，可以形成与源区和漏区相对应的接触部140。接触部140例如可以包括金属如W、Cu等。根据一实施例，为了增强接触，还可以在源区和漏区中形成金属硅化物层138，从而接触部140通过金属硅化物层138与源区和漏区接触。金属硅化物层138例如可以包括NiPtSi。存在多种手段来形成金属硅化物层138和接触部140，在此不再赘述。
这样，就得到了根据本公开的示例半导体器件。如图8所示，该半导体器件可以包括在衬底上形成的源区和漏区(128)以及栅堆叠(130，132，134)。栅堆叠，尤其是其中的栅导体134，以侧墙的形式形成于第二掩蔽层120的侧壁上。该半导体器件可以包括非对称的SSRW 110，该SSRW 110大致在栅堆叠下方的半导体衬底中延伸，具体地，远离源区和漏区中的一个(图8中左侧的源/漏区)向着源区和漏区中的另一个(图8中右侧的源/漏区)一侧延伸。
这里需要指出的是，在上述实施例中，掩蔽侧墙112被完全去除。可选地，可以保留掩蔽侧墙112位于第二掩蔽层120侧壁上的一部分。该部分随后可以充当栅堆叠的栅侧墙。
接下来，参照图9-16，描述根据本公开另一实施例的制造半导体器件的流程。图9-16与图1-8中相似的附图标记表示相似的部件。在以下描述中，主要说明该实施例与上述实施例之间的不同。
如图9所述，提供衬底200，该衬底200上可以形成有STI 202。在衬底200的表面上，可选地可以形成薄氧化物层(未示出)。关于衬底200和氧化物层的详情，可以参见以上结合图1对于衬底100和氧化物层104的描述。
在衬底200上例如通过沉积形成厚度约为100-200nm的第一掩蔽层206。例如，第一掩蔽层206可以包括氮化物(例如，氮化硅)，且可以通过例如RIE被构图为露出有源区的一部分(该部分大致对应于随后形成的源区或漏区)。此时，可以第一掩蔽层206为掩模进行源/漏形成工艺，来在该露出的有源区部分中形成源区和漏区之一。例如，这可以如下进行。
具体地，可以以第一掩蔽层206为掩模，通过选择性刻蚀，来形成延伸进入衬底200的开口216。这种选择性刻蚀例如可以通过TMAH溶液对衬底200(例如，Si)进行各向异性刻蚀来完成。
然后，如图10所示，在开口216中例如通过外延生长形成源区和漏区之一218。例如，源区和漏区之一218可以包括与衬底200不同成分的半导体材料，从而例如由于两者之间的晶格常数不同而在将要在衬底200中形成的沟道区中产生应力。对于p型器件，源/漏区218可以带压应力；而对于n型器件，源/漏区218可以带拉应力。例如，在衬底200包括Si的情况下，对于p型器件，源/漏区218可以包括SiGe(例如，Ge原子百分比为约15-75％)；而对于n型器件，源/漏区218可以包括Si:C(例如，C原子百分比为约0.2-2％)。在外延生长源/漏区218的同时，可以进行原位掺杂，以将其掺杂为相应的导电类型。
接下来，如图11所示，在衬底200上形成第二掩蔽层220。第二掩蔽层220例如可以包括氧化物(如氧化硅)。然后可以进行平坦化处理例如化学机械抛光(CMP)，以露出第一掩蔽层206，以便随后进行处理。
随后，如图12所示，可以通过相对于第二掩蔽层220(例如，氧化硅)，选择性刻蚀第一掩蔽层206(例如，氮化硅)，以去除第一掩蔽层206。这种选择性刻蚀例如可以通过湿法刻蚀(例如，热磷酸)或者通过湿法/RIE组合刻蚀来进行。
根据本公开的一个实施例，为更好地控制短沟道效应以及抑制带间泄露，如图12所示，可以通过以第二掩蔽层220为掩模进行离子注入(图中箭头所示)，形成超陡后退阱(SSRW)210。关于SSRW 210的详细描述，可以参见以上结合图3的说明。此后，可以进行退火处理例如尖峰退火、激光退火、快速退火等，以激活注入的杂质。
然后，如图13所示，在第二掩蔽层220的侧壁上可以形成掩蔽侧墙212。例如，掩蔽侧墙212被形成为具有约8-30nm的宽度，以覆盖有源区的一部分(该部分大致对应于随后形成的栅区)。掩蔽侧墙212例如可以包括电介质如氮化物(例如，氮化硅)。存在多种手段来形成掩蔽侧墙，在此不对掩蔽侧墙的形成进行详细描述。
这样，第二掩蔽层220和掩蔽侧墙212露出了有源区的一部分。此时，可以第二掩蔽层220和掩蔽侧墙212为掩模进行源/漏形成工艺，来在该露出的有源区部分中形成源区和漏区中另一个。例如，这可以如下进行。
具体地，以第二掩蔽层220和掩蔽侧墙212为掩模，对衬底200进行选择性刻蚀，来形成延伸进入衬底200的开口226。例如，可以通过TMAH溶液，对衬底200(例如，Si)进行各向异性刻蚀。
然后，如图15所示，在开口226例如通过外延生长形成源区和漏区中另一个228。例如，源/漏区228可以包括与衬底200不同成分的半导体材料，从而例如由于两者之间的晶格常数不同而在将要在衬底200中形成的沟道区中产生应力。对于p型器件，源/漏区228可以带压应力；而对于n型器件，源/漏区228可以带拉应力。例如，在衬底200包括Si的情况下，对于p型器件，源/漏区228可以包括SiGe(例如，Ge原子百分比为约15-75％)；而对于n型器件，源/漏区228可以包括Si:C(例如，C原子百分比为约0.2-2％)。在外延生长源/漏区228的同时，可以进行原位掺杂，以将其掺杂为相应的导体类型。
随后，可以通过选择性刻蚀，去除掩蔽侧墙212的至少一部分。例如，掩蔽侧墙212(例如，氮化硅)可以通过热磷酸来选择性去除。这样，就在第二掩蔽层220的一侧留下了较大的空间(大致对应于栅区+所述源区和漏区中另一个的区域)，从而可以容易地进行栅堆叠的形成。
然后，如图16所示，形成栅堆叠。具体地，例如可以通过沉积形成栅介质层230。在栅介质层230上，可以以侧墙的形式形成栅导体234。在形成栅导体时，例如可以通过控制侧墙形成工艺中的参数如沉积厚度、RIE参数等，使得所形成的侧墙形式的栅导体234宽度为约10-35nm，从而基本上位于下方已经形成的源区和漏区之间。优选地，在栅介质层230和栅导体234之间还可以形成功函数调节层232。图16中示出的栅介质层230和功函数调节层232是以栅导体234为掩模进行选择性刻蚀后的形式。关于栅介质层230、功函数调节层232、栅导体层234的详细描述，可以参照以上结合附图7的说明。
之后可以沉积电介质并进行平坦化，形成接触部等外围部件，在此不再赘述。
尽管在对图9-16所示的实施例进行描述时并未提及IL，但是可以如上述实施例一样进行形成IL的工艺。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (8)

1.一种制造半导体器件的方法，包括：
在衬底上形成第一掩蔽层；
以第一掩蔽层为掩模，形成源区和漏区之一；
在衬底上形成第二掩蔽层，并去除第一掩蔽层；
以第二掩蔽层为掩模，在衬底中形成超陡后退阱；
在第二掩蔽层的侧壁上形成掩蔽侧墙；
以第二掩蔽层和掩蔽侧墙为掩模，形成源区和漏区中另一个；
去除掩蔽侧墙的至少一部分；以及
形成栅介质层，并在第二掩蔽层或者在掩蔽侧墙的剩余部分的侧壁上以侧墙的形式形成栅导体。
2.根据权利要求1所述的方法，其中，掩蔽侧墙包括电介质或多晶硅。
3.根据权利要求2所述的方法，其中，
第一掩蔽层包括氮化物，
第二掩蔽层包括氧化物，
掩蔽侧墙包括氮化物。
4.根据权利要求1所述的方法，其中，形成源区或漏区包括：
执行延伸区注入；和
执行倾角源/漏注入。
5.根据权利要求4所述的方法，其中，形成源区或漏区还包括：
执行晕圈注入。
6.根据权利要求1所述的方法，其中，形成源区或漏区包括：
对衬底进行各向异性刻蚀，以在衬底中形成开口；
在开口中通过外延生长形成源区或漏区。
7.根据权利要求1所述的方法，在形成栅介质之前，还包括：
在衬底上形成界面层。
8.一种半导体器件，包括：
衬底；
在衬底上形成的源区和漏区以及栅堆叠；以及
在衬底中形成的非对称超陡后退阱，
其中，
所述源区和漏区分别包括嵌入衬底中的外延生长层，
所述栅堆叠包括：
栅介质；和
栅导体，所述栅导体以侧墙形式形成于位于栅堆叠一侧的电介质层的侧壁上，其中栅介质呈L形，在栅导体位于所述一侧的侧壁上以及在栅导体的底壁上延伸，
其中，该超陡后退阱远离源区和漏区中的一个向着源区和漏区中的另一个一侧延伸。
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