WO2014082357A1 - 平坦化处理方法 - Google Patents

平坦化处理方法 Download PDF

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Publication number
WO2014082357A1
WO2014082357A1 PCT/CN2012/087020 CN2012087020W WO2014082357A1 WO 2014082357 A1 WO2014082357 A1 WO 2014082357A1 CN 2012087020 W CN2012087020 W CN 2012087020W WO 2014082357 A1 WO2014082357 A1 WO 2014082357A1
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WIPO (PCT)
Prior art keywords
layer
sputtering
masking
sacrificial gate
material layer
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PCT/CN2012/087020
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English (en)
French (fr)
Inventor
朱慧珑
罗军
李春龙
邓坚
赵超
Original Assignee
中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US14/647,393 priority Critical patent/US9406549B2/en
Publication of WO2014082357A1 publication Critical patent/WO2014082357A1/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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Definitions

  • CMP chemical mechanical polishing
  • the material layer covering the feature particularly the non-uniform hook distribution feature
  • the material layer may have uneven distribution of irregularities due to the presence of the feature, and thus may cause the planarization to be performed inconsistently.
  • Figure 4a illustrates an alternative operation of the operation illustrated in Figure 4 in accordance with another embodiment of the present disclosure
  • Figure 5a illustrates an alternate operation of the operation illustrated in Figure 5 in accordance with another embodiment of the present disclosure
  • Figure 11a illustrates An alternate operation of the operation illustrated in FIG. 11 of another embodiment of the present disclosure
  • FIG. 12a illustrates an alternative operation of the operation illustrated in FIG. 12 in accordance with another embodiment of the present disclosure.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • load corresponding means that the pattern existing on the material layer to which sputtering is applied and the density of the pattern (or the morphology of the material layer) and the like will affect the thickness and/or morphology of the material layer after sputtering. . Therefore, in order to obtain a relatively flat surface, it is preferable to consider the load effect at the time of sputtering.
  • the part that has a recess needs to be subjected to "less" sputtering in order to be flat with other parts. That is, for sputtering, the load corresponding to this recess The conditions are smaller.
  • the material layer may have protrusions and/or depressions of non-homogeneous distribution due to the features, thus causing a change in load conditions on the substrate.
  • load condition in a region with a higher distribution density is higher than the load condition in a region with a lower distribution density; and for the IHJ trap, the load condition in a region with a higher distribution density is lower than the distribution density.
  • load condition in the lower zone may be detrimental to sputtering uniformity.
  • the first masking layer can be removed, and sputtering is performed on the entire material layer (the uniformity of the load conditions is improved due to the first sputtering) (hereinafter referred to as "second sputtering").
  • second sputtering the second sputtering can be performed substantially uniformly on the substrate to help achieve a flat surface.
  • the above features may include various features that can be formed on a substrate, such as, but not limited to, protruding features on the substrate such as gates, fins, etc., and/or recessed features on the substrate, such as removal in a replacement gate process a gate trench formed by sacrificing the gate, or the like.
  • the substrate 1000 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a SiGe substrate, or the like.
  • a bulk Si substrate will be described as an example for convenience of explanation.
  • the substrate 1000 can be patterned to form fins. For example, this can be done as follows. Specifically, a patterned photoresist (not shown) is formed on the substrate 1000, and then patterned, such as a reactive ion etching (RIE) substrate 1000, to form a fin. 1002. After that, the photoresist can be removed. In the example shown in Fig. 1, the fins 1002 have a higher distribution density in the region 100-1 and a lower distribution density in the region 100-2, depending on design requirements.
  • RIE reactive ion etching
  • the shape of the groove (between the fins) formed by etching is not necessarily the regular rectangular shape shown in Fig. 1, and may be, for example, a frustum shape which gradually becomes smaller from the top to the bottom.
  • the position and number of fins formed are not limited to the example shown in FIG.
  • the fin is not limited to being formed by directly patterning the substrate.
  • an additional semiconductor layer can be epitaxially grown on the substrate, and the additional semiconductor layer patterned to form fins. If there is sufficient etch selectivity between the additional semiconductor layer and the substrate, the patterning can be substantially stopped at the substrate when the fin is patterned, thereby achieving more precise control of the fin height.
  • an isolation layer may be formed on the substrate.
  • a dielectric layer 1004 may be formed on a substrate, for example by deposition, to cover the formed fins 1002.
  • dielectric layer 1004 can include an oxide (e.g., silicon oxide). Due to the presence of the fins 1002, there are protrusions B on the dielectric layer 1004. Accordingly, the distribution density of the projections B in the region 100-1 is high, and the distribution density in the region 100-2 is low. To this end, the dielectric layer 1004 needs to be planarized. According to a preferred embodiment of the present disclosure, the planarization process is performed by two sputterings.
  • a patterned masking layer 1006 is formed on the dielectric layer 1004 to shield the region 100-2 having a lower density of the bumps B.
  • the masking layer 1006 can include a photoresist, which can The composition is patterned by exposure, development, and the like through a mask.
  • a mask for exposing the masking layer 1006 can be designed in accordance with a mask used to form the fins 1002 (determining the position and shape of the fins, etc., and thus partially determining the distribution density of the fins 1002).
  • a portion of the exposed dielectric layer 1004 can be sputtered ("first sputter").
  • sputtering may use a plasma such as an Ar or N plasma.
  • the cutting speed of the dielectric layer 1004, the sputtering parameters such as the sputtering power, the gas pressure, and the like can be controlled according to plasma sputtering to determine the time during which the plasma sputtering is performed, so that the plasma sputtering can be performed for a certain period of time.
  • the segment is used to reduce the load condition in region 100-1 to be close to or substantially equal to the load condition in region 100-2.
  • the time of the first sputtering can be determined based on the difference in feature density in the regions 100-1, 100-2 and the sputtering parameters.
  • the masking layer 1006 can be removed.
  • the structure shown in Fig. 4 is obtained.
  • the bump B has been lowered by a certain height, so that the load condition in the region is lowered, and thus can be close to or even substantially equal to the load condition in the region 100-2, which is advantageous.
  • Subsequent second sputtering is performed in a hook.
  • Fig. 6 shows the results after planarization by the second sputtering.
  • the microscopic undulations are shown in Fig. 6, in fact, the top surface of the dielectric layer 1004 has sufficient flatness, and its undulation can be controlled, for example, within a few nanometers.
  • plasma sputtering may end before reaching the top surface of fin 1002 to avoid excessive damage to fin 1002.
  • a punch-through barrier may also be formed by implantation as shown by an arrow in FIG. 7 (see 1008 shown in FIG. 8).
  • a p-type impurity such as 8, BF 2 or In may be implanted;
  • an n-type impurity such as As or P may be implanted.
  • Ion implantation can be perpendicular to the surface of the substrate. The parameters of the ion implantation are controlled such that the punch-through barrier is formed in a portion of the fin below the surface of the isolation layer 1004 and has a desired doping concentration.
  • a part of the dopant may be scattered from the exposed portion of the fin, thereby facilitating the formation of a steep doping profile in the depth direction. Annealing can be performed to activate the implanted impurities. This feedthrough barrier helps to reduce source and drain leakage.
  • a gate stack across the fins can be formed on the isolation layer 1004.
  • a gate dielectric layer 1010 is formed, for example, by deposition.
  • the gate dielectric layer 1010 may include an oxide having a thickness of about 0.8 to 1.5 nm.
  • the gate dielectric layer 1010 may also include a portion extending on the top surface of the isolation layer 1004.
  • the gate conductor layer 1012 is formed, for example, by deposition.
  • the gate conductor layer 1012 may comprise polysilicon having a thickness of about 30-200 nm.
  • the gate conductor layer 1012 can fill the gap between the fins. Due to the presence of the fins, bumps are also present on the gate conductor layer 1012. Accordingly, the distribution density of the protrusions in the region 100-1 is higher, and the distribution density in the region 100-2 is lower.
  • the gate conductor layer 1012 can also be planarized using the techniques in accordance with the present disclosure. Specifically, as shown in FIG. 10, a patterned masking layer 1014 is formed on the gate conductor layer 1012 to shield the region 100-2 having a lower bump density.
  • the masking layer 1014 can be formed, for example, similarly to the masking layer 1006 described above (see the description above in connection with FIG. 2).
  • a portion of the exposed gate conductor layer 1012 may be sputtered ("first sputtering").
  • sputtering may use a plasma such as an Ar or N plasma.
  • the cutting speed of the gate conductor layer 1012, the sputtering parameters such as the sputtering power, the gas pressure, and the like can be controlled according to plasma sputtering to determine the time during which the plasma sputtering is performed, so that the plasma sputtering can perform a certain degree.
  • the time period is to reduce the load condition in region 100-1 to be close to or substantially equal to the load condition in region 100-2.
  • the time of the first sputtering can be determined based on the difference in feature density in the regions 100-1, 100-2 and the sputtering parameters.
  • the masking layer 1014 can be removed.
  • the projection has been lowered by a certain height, so that the load condition in the region is lowered, and thus can be close to or even substantially equal to the load condition in the region 100-2, which is advantageous for subsequent
  • the second sputtering is performed in a hook manner.
  • the entire gate conductor layer 1012 may be sputtered ("second sputtering") to planarize the gate conductor layer 1012.
  • sputtering can use a plasma such as an Ar or N plasma.
  • the cutting speed of the gate conductor layer 1012 can be controlled by plasma sputtering, and sputtering parameters such as sputtering power and gas pressure can be controlled to determine the time during which plasma sputtering is performed, so that plasma sputtering can perform a certain degree.
  • the surface of the gate conductor layer 1012 is sufficiently smoothed for a period of time. Since the uniformity of the load conditions on the first sputtered substrate is improved as described above, the sputtering can be performed substantially uniformly, and thus a flatter surface can be realized.
  • Fig. 13 shows the results after planarization by the second sputtering. Although microscopic fluctuations are shown in Fig. 13, in fact, the top surface of the gate conductor layer 1012 has sufficient flatness, and its undulation can be controlled within, for example, several nanometers. According to another embodiment of the present disclosure, it is also possible to perform a little CMP on the gate conductor layer 1012 which is planarized by sputtering as needed.
  • the gate conductor layer 1012 is patterned to form a gate stack.
  • the gate conductor layer 1012 is patterned into a strip shape that intersects the fins.
  • the gate dielectric layer 1012 can be patterned by further patterning the gate conductor layer 1012 as a mask.
  • a halo implant and an extension implant may be performed using the gate conductor as a mask.
  • a spacer 1014 may be formed on the sidewall of the gate conductor layer 1012.
  • the spacer 1014 can be formed by depositing a nitride (e.g., silicon nitride) having a thickness of about 5 to 20 nm and then performing RIE on the nitride.
  • a nitride e.g., silicon nitride
  • RIE reactive ion etching
  • source/drain (S/D) implantation may be performed using the gate conductor and the sidewall as a mask. Subsequently, the implanted ions can be activated by annealing to form source/drain regions to obtain a FinFET.
  • the gate stack is directly formed.
  • the present disclosure is not limited to this.
  • an alternative gate process is equally applicable to the present disclosure.
  • strain source/drain technology can also be applied.
  • the gate dielectric layer 1010 and the gate conductor layer 1012 formed in FIG. 9 are a sacrificial gate dielectric layer and a sacrificial gate conductor layer. Next, it can be handled in the same manner as described above in connection with Figures 9-15.
  • the exposed sacrificial gate dielectric layer 1010 is first selectively removed (e.g., RIE).
  • RIE etching-reactive ion etching
  • the sacrificial gate dielectric layer 1010 and the isolation layer 1004 each include an oxide
  • the RIE of the sacrificial gate dielectric layer 1010 does not substantially affect the isolation layer 1004.
  • the sacrificial gate dielectric layer is further patterned with the sacrificial gate conductor as a mask, which is no longer required.
  • Portions of the fins 1002 that are exposed due to the removal of the sacrificial gate dielectric layer 1010 can then be selectively removed (e.g., RIE). The etching of the portion of the fin 1002 can proceed until the through barrier 1008 is exposed. Due to the presence of the sacrificial gate stack (sacrificial gate dielectric layer, sacrificial gate conductor and sidewall spacers), the fins 1002 can remain below the sacrificial gate stack.
  • the semiconductor layer 1016 may include Si:C (the atomic percentage of C is, for example, about 0.2 to 2%) to apply tensile stress; for the p-type device, the semiconductor layer 1016 may include SiGe (eg, an atomic percentage of Ge of about 15-75%) to apply compressive stress.
  • another dielectric layer 1018 is formed, for example, by deposition.
  • the dielectric layer 1018 can comprise, for example, an oxide.
  • the dielectric layer 1018 is subjected to a planarization process such as CMP.
  • the CMP can be stopped at the sidewall 1014 to expose the sacrificial gate conductor 1012.
  • the sacrificial gate conductor 1012 is selectively removed, for example, by a TMAH solution, thereby forming a void inside the sidewall spacer 1014.
  • the sacrificial gate can be further removed Dielectric layer 1010.
  • a final gate stack is formed by forming a gate dielectric layer 1020 and a gate conductor layer 1022 in the voids.
  • the gate dielectric layer 1020 may comprise a high-k gate dielectric such as HfO 2 having a thickness of about 1-5 nm.
  • the gate conductor layer 1022 can include a metal gate conductor.
  • a success function adjustment layer (not shown) may also be formed between the gate dielectric layer 1020 and the gate conductor layer 1022.
  • the first sputtering does not achieve true flatness of the surface, and its main purpose is to reduce the sputtering load condition in the region where the bump density is high (or, in the region where the load condition is high). According to another embodiment of the present disclosure, the first sputtering can also be used to achieve surface planarization.
  • Fig. 4a shows the result after planarization by the first sputtering.
  • the top surface of dielectric layer 1004 in region 100-1) has sufficient flatness, and its relief can be controlled, for example, within a few nanometers.
  • plasma sputtering may end before reaching the top surface of fin 1002 to avoid excessive damage to fin 1002.
  • the masking layer 1024 can include a photoresist that can be patterned by exposure, development, etc., through a mask.
  • a mask for exposing the masking layer 1024 can be designed based on the mask used to form the fins 1002 (determining the position and shape of the fins, etc., and thus partially determining the distribution density of the fins 1002).
  • the masking layer 1024 does not overlap in position with the previous masking layer 1006, for example, there may be a gap G between them.
  • a portion of the exposed dielectric layer 1004 can be sputtered ("second sputtering").
  • sputtering may use a plasma such as an Ar or N plasma.
  • the cutting speed of the dielectric layer 1004, the sputtering parameters such as the sputtering power, the gas pressure, and the like can be controlled according to plasma sputtering to determine the time during which the plasma sputtering is performed, so that the plasma sputtering can be performed for a certain period of time. Segments to sufficiently smooth the surface of dielectric layer 1004 (in region 100-2).
  • the first sputter and the second post-spray dielectric layer 1004 may be made according to sputtering load conditions in the regions 100-1, 100-2 and process parameters used in the first sputtering, the second sputtering.
  • the surfaces in regions 100-1, 100-2 are substantially flat. For example, the difference in surface height is within 3-5 nm.
  • the masking layer 1024 can be removed.
  • the structure shown in Fig. 6 can also be obtained by the above-described first sputtering and second sputtering processing.
  • the order of the first sputtering and the second sputtering may be changed.
  • a portion of the exposed gate conductor layer 1012 can be sputtered ("second sputtering").
  • sputtering may use a plasma such as an Ar or N plasma.
  • the cutting speed of the gate conductor layer 1012, the sputtering parameters such as the sputtering power, the gas pressure, and the like can be controlled according to plasma sputtering to determine the time during which the plasma sputtering is performed, so that the plasma sputtering can perform a certain degree. The time period is to sufficiently smooth the surface of the gate conductor layer 1012 (in the region 100-2).
  • the structure shown in Fig. 13 can also be obtained by the above-described first sputtering and second sputtering processing.
  • the order of the first sputtering and the second sputtering may be changed.

Abstract

一种平坦化处理方法，其中一示例方法包括：对材料层（1004）进行第一溅射，在进行第一溅射时，以第一掩蔽层（1006）遮蔽材料层中溅射的负载条件相对较低的区域（100-2）；去除第一掩蔽层；以及对材料层进行第二溅射，以使材料层平坦。

Description

平坦化处理方法 本申请要求了 2012年 11月 30日提交的、 申请号为 201210505860.1、 发 明名称为 "平坦化处理方法" 的中国专利申请的优先权， 其全部内容通过引用 结合在本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种平坦化处理方法。 背景技术
在半导体工艺中， 经常用到平坦化工艺， 例如化学机械抛光（CMP ), 以 获得相对平坦的表面。 然而， 在通过 CMP对材料层进行平坦化的情况下， 如 果需要研磨掉相对较厚的部分， 则难以控制 CMP后材料层的表面平坦度， 例 如控制到几个纳米之内。
另一方面， 如果要对覆盖特征、特别是非均勾分布特征的材料层进行平坦 化， 那么材料层由于特征的存在而可能出现非均匀分布的凹凸起伏， 因此可能 导致平坦化不能一致地执行。 发明内容
本公开的目的至少部分地在于提供一种平坦化处理方法。
根据本公开的一个方面，提供了一种对衬底上形成的材料层进行平坦化的 方法， 包括： 对材料层进行第一溅射， 在进行第一溅射时， 以第一掩蔽层遮蔽 材料层中溅射的负载条件相对较低的区域； 去除第一掩蔽层； 以及对材料层进 行第二溅射， 以使材料层平坦。
根据本公开的另一方面，提供了一种对衬底上形成的材料层进行平坦化的 方法， 包括： 对材料层进行第一溅射， 在进行第一溅射时， 以第一掩蔽层遮蔽 材料层中溅射的负载条件相对较高的区域， 其中进行第一溅射， 以使材料层中 未被第一掩蔽层遮蔽的部分平坦； 去除第一掩蔽层； 在材料层的所述部分上形 成第二掩蔽层， 其中第二掩蔽层的位置与第一掩蔽层的位置不交迭； 以及对材 料层进行第二溅射， 以使材料层平坦。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和优点将更为清楚， 在附图中：
图 1-19示出了制造半导体器件的示例流程， 其中利用了根据本公开实施 例的平坦化处理方法；
图 4a示出了根据本公开另一实施例的图 4所示操作的替代操作； 图 5a示出了根据本公开另一实施例的图 5所示操作的替代操作； 图 11a示出了根据本公开另一实施例的图 11所示操作的替代操作； 以及 图 12a示出了根据本公开另一实施例的图 12所示操作的替代操作。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是 示例性的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知 结构和技术的描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些 细节。 图中所示出的各种区域、 层的形状以及它们之间的相对大小、位置关系 仅是示例性的， 实际中可能由于制造公差或技术限制而有所偏差， 并且本领域 技术人员根据实际所需可以另外设计具有不同形状、 大小、 相对位置的区域 / 层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该 层 /元件可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外，如果在一种朝向中一层 /元件位于另一层 /元件"上"，那么当调转朝向时， 该层 /元件可以位于该另一层 /元件 "下"。
根据本公开的示例， 可以通过溅射（ sputtering ), 例如 Ar或 N等离子体 溅射， 来对材料层进行平坦化处理。 通过这种溅射平坦化处理， 而非常规的 CMP平坦化处理， 可以实现更加平坦的材料层表面。 这种材料层可以包括半 导体制造工艺中使用的多种材料层， 例如， 包括但不限于绝缘体材料层、 半导 体材料层和导电材料层。
另外， 在进行溅射时， 可能存在负载效应（ loading effect )。 所谓 "负载相 应"， 是指溅射所针对的材料层上存在的图案以及图案的密度（或者说， 材料 层的形貌）等将会影响溅射后材料层的厚度和 /或形貌等。 因此， 为了获得较 为平坦的表面， 优选地在溅射时考虑负载效应。
例如， 如果材料层由于之下存在（凸出的）特征而存在凸起， 那么相对于 其他没有凸起的部分而言， 存在凸起的部分需要经受 "更多" 的溅射， 才能与 其他部分保持平坦。 在此， 所谓 "更多，， 的溅射， 例如是指在相同的溅射参数 (如， 溅射功率和 /或气压） 情况下， 需要进行更长时间的溅射； 或者， 在相 同溅射时间的情况下， 溅射强度的更大（如， 溅射功率和 /或气压更大）； 等等。 也就是说，对于溅射而言，这种凸起对应的负载条件（ loading condition )更大。 对于其他没有凹陷的部分而言， 存在凹陷的部分需要经受 "更少" 的溅射， 才 能与其他部分保持平坦。 也就是说， 对于溅射而言， 这种凹陷对应的负载条件 更小。
另夕卜，如果存在多个非均勾分布的特征， 那么材料层可能由于特征而具有 非均勾分布的凸起和 /或凹陷， 因此导致负载条件在衬底上发生变化。 例如， 对于凸起而言，其分布密度较高区域的负载条件要高于分布密度较低区域的负 载条件； 而对于 IHJ陷而言， 其分布密度较高区域的负载条件要低于分布密度较 低区域的负载条件。 非均匀分布的负载条件可能不利于溅射均匀地进行。
根据本公开的示例，在通过溅射对材料层进行平坦化的处理中， 可以结合 光刻， 以便能够实现选择性平坦化。 例如， 在进行溅射之前， 可以通过掩蔽层 来遮蔽材料层中溅射的负载条件相对较低的区域， 然后对露出的材料层部分 (负载条件相对较高 )进行溅射 (以下称作 "第一溅射" )。 通过第一溅射， 可 以降低露出的材料层部分的负载条件，并使之接近或大致等于被遮蔽的材料层 部分的负载条件。 之后， 可以去除第一掩蔽层， 并对整个材料层（由于第一溅 射， 其负载条件的均勾性得以改进）进行溅射（以下称作 "第二溅射"）。 这样， 第二溅射可以在衬底上大致均勾地进行， 从而有助于获得平坦的表面。 上述特征可以包括能够在衬底上形成的各种特征， 例如， 包括但不限于衬 底上的凸出特征如栅、 鰭等， 和 /或衬底上的凹入特征如替代栅工艺中去除牺 牲栅而形成的栅槽等。
本公开可以各种形式呈现， 以下将描述其应用于鰭式场效应晶体管
( FinFET ) 的一些示例。
如图 1所示， 提供衬底 1000。 该衬底 1000可以是各种形式的衬底， 例如 但不限于体半导体材料衬底如体 Si衬底、 绝缘体上半导体（ SOI )衬底、 SiGe 衬底等。 在以下的描述中， 为方便说明， 以体 Si衬底为例进行描述。
可以对衬底 1000进行构图， 以形成鰭。 例如， 这可以如下进行。 具体地， 在衬底 1000上按设计形成构图的光刻胶（未示出 ), 然后以构图的光刻胶为掩 模， 刻蚀例如反应离子刻蚀 （RIE )衬底 1000, 从而形成鰭 1002。 之后， 可 以去除光刻胶。 在图 1所示的示例中， 根据设计需要， 鰭 1002在区域 100-1 中的分布密度较高， 而在区域 100-2中的分布密度较低。
这里需要指出的是， 通过刻蚀所形成的（鰭之间的）沟槽的形状不一定是 图 1中所示的规则矩形形状， 可以是例如从上到下逐渐变小的锥台形。 另外， 所形成的鰭的位置和数目不限于图 1所示的示例。
另外， 鰭不限于通过直接对衬底进行构图来形成。 例如， 可以在衬底上外 延生长另外的半导体层，对该另外的半导体层进行构图来形成鰭。如果该另外 的半导体层与衬底之间具有足够的刻蚀选择性， 则在对鰭进行构图时， 可以使 构图基本上停止于衬底， 从而实现对鰭高度的较精确控制。
在通过上述处理形成鰭之后， 可以在衬底上形成隔离层。
具体地， 如图 1所示， 可以在衬底上例如通过淀积形成电介质层 1004, 以覆盖形成的鰭 1002。 例如， 电介质层 1004可以包括氧化物（如， 氧化硅）。 由于鰭 1002的存在， 电介质层 1004上存在凸起 B。 相应地， 凸起 B在区域 100-1 中的分布密度较高， 而在区域 100-2中的分布密度较低。 为此， 需要对 电介质层 1004进行平坦化。 根据本公开的优选实施例， 通过两次溅射来进行 平坦化处理。
具体地， 如图 2所示， 在电介层 1004上形成构图的掩蔽层 1006, 以遮蔽 凸起 B密度较低的区域 100-2。 例如， 掩蔽层 1006可以包括光刻胶， 其可以 通过掩模进行曝光、 显影等操作来构图。 例如， 可以根据用来形成鰭 1002的 掩模（确定鰭的位置和形状等， 并因此部分地确定鰭 1002的分布密度）， 来设 计用来对掩蔽层 1006进行曝光的掩模。
然后， 如图 3所示， 可以对露出的电介质层 1004部分进行溅射（ "第一溅 射"）。 例如， 溅射可以使用等离子体， 如 Ar或 N等离子体。 在此， 例如可以 根据等离子体溅射对电介质层 1004的切削速度， 控制溅射参数例如溅射功率 和气压等， 来确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定 的时间段， 以降低区域 100-1中的负载条件， 使之接近或大致等于区域 100-2 中的负载条件。 例如， 可以根据区域 100-1、 100-2 中的特征密度差异以及溅 射参数， 来确定第一溅射的时间。 之后， 可以去除掩蔽层 1006。
这样， 就得到了图 4所示的结构。 如图 4所示， 在区域 100-1 , 凸起 B已 经降低了一定的高度，从而该区域中的负载条件降低， 并因此可以接近乃至大 致等于区域 100-2中的负载条件， 这有利于随后的第二溅射均勾地进行。
接下来，如图 5所示，可以对整个电介质层 1004进行溅射（ "第二溅射" ), 来对电介质层 1004 进行平坦化处理。 同样， 溅射可以使用等离子体， 如 Ar 或 N等离子体。 在此， 例如可以根据等离子体溅射对电介质层 1004的切削速 度， 控制溅射参数例如溅射功率和气压等， 来确定进行等离子体溅射的时间， 使得等离子体溅射能够执行一定的时间段， 充分平滑电介质层 1004的表面。 由于如上所述，通过第一溅射衬底上负载条件的均勾性得以改善， 因此溅射可 以大致均勾地执行， 并因此可以实现更加平坦的表面。
图 6示出了通过第二溅射进行平坦化之后的结果。尽管在图 6中示出了微 观上的起伏， 但是事实上电介质层 1004的顶面具有充分的平坦度， 其起伏可 以控制在例如几个纳米之内。在图 6所示的示例中， 等离子体溅射可以在到达 鰭 1002的顶面之前结束， 以避免对鰭 1002造成过多的损伤。根据本公开的另 一实施例， 还可以根据需要， 对通过溅射平坦化后的电介质层 1004进行少许 CMP。
在电介质层 1004的表面通过等离子体溅射而变得充分平滑之后， 如图 7 所示， 可以对电介质层 1004进行回蚀 （例如， RIE ), 以露出鰭 1002的一部 分， 该露出的部分随后可以用作最终器件的真正鰭。 剩余的电介质层 1004构 成隔离层。 由于回蚀之前电介质层 1004的表面通过溅射而变得平滑， 所以回 蚀之后隔离层 1004的表面在衬底上基本上保持一致。
为改善器件性能， 根据本公开的一示例， 还可以如图 7中的箭头所示， 通 过注入来形成穿通阻挡部（参见图 8所示的 1008 )。例如，对于 n型器件而言， 可以注入 p型杂质， 如：8、 BF2或 In; 对于 p型器件， 可以注入 n型杂质， 如 As或 P。 离子注入可以垂直于衬底表面。 控制离子注入的参数， 使得穿通阻 挡部形成于鰭位于隔离层 1004表面之下的部分中，并且具有期望的掺杂浓度。 应当注意， 由于鰭的形状因子， 一部分掺杂剂 （离子或元素）可能从鰭的露出 部分散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。可以进行退火， 以激活注入的杂质。 这种穿通阻挡部有助于减小源漏泄漏。
随后， 可以在隔离层 1004上形成横跨鰭的栅堆叠。 例如， 这可以如下进 行。 具体地， 如图 9所示， 例如通过淀积， 形成栅介质层 1010。 例如， 栅介 质层 1010可以包括氧化物， 厚度为约 0.8-1.5nm。 在图 7所示的示例中， 仅示 出了 " Π "形的栅介质层 1010。但是，栅介质层 1010也可以包括在隔离层 1004 的顶面上延伸的部分。 然后， 例如通过淀积， 形成栅导体层 1012。 例如， 栅 导体层 1012可以包括多晶硅， 厚度为约 30-200nm。 栅导体层 1012可以填充 鰭之间的间隙。 由于鰭的存在， 栅导体层 1012上也存在凸起。 相应地， 凸起 在区域 100-1中的分布密度较高， 而在区域 100-2中的分布密度较低。
在此， 同样可以利用根据本公开的技术来对栅导体层 1012进行平坦化。 具体地， 如图 10所示， 在栅导体层 1012上形成构图的掩蔽层 1014 , 以遮蔽 凸起密度较低的区域 100-2。 该掩蔽层 1014例如可以与上述掩蔽层 1006类似 地形成（参见以上结合图 2的说明）。 然后， 可以对露出的栅导体层 1012部分 进行溅射（"第一溅射"）。 例如， 溅射可以使用等离子体， 如 Ar或 N等离子 体。 在此， 例如可以根据等离子体溅射对栅导体层 1012的切削速度， 控制溅 射参数例如溅射功率和气压等， 来确定进行等离子体溅射的时间，使得等离子 体溅射能够执行一定的时间段， 以降低区域 100-1中的负载条件， 使之接近或 大致等于区域 100-2中的负载条件。 例如， 可以根据区域 100-1、 100-2中的特 征密度差异以及溅射参数， 来确定第一溅射的时间。 之后， 可以去除掩蔽层 1014。 这样， 就得到了图 11所示的结构。 如图 11所示， 在区域 100-1 , 凸起已 经降低了一定的高度，从而该区域中的负载条件降低， 并因此可以接近乃至大 致等于区域 100-2中的负载条件， 这有利于随后的第二溅射均勾地进行。
接下来，如图 12所示，可以对整个栅导体层 1012进行溅射（ "第二溅射" ), 来对栅导体层 1012 进行平坦化处理。 同样， 溅射可以使用等离子体， 如 Ar 或 N等离子体。 在此， 例如可以根据等离子体溅射对栅导体层 1012的切削速 度， 控制溅射参数例如溅射功率和气压等， 来确定进行等离子体溅射的时间， 使得等离子体溅射能够执行一定的时间段， 充分平滑栅导体层 1012的表面。 由于如上所述，通过第一溅射衬底上负载条件的均勾性得以改善， 因此溅射可 以大致均勾地执行， 并因此可以实现更加平坦的表面。
图 13示出了通过第二溅射进行平坦化之后的结果。尽管在图 13中示出了 微观上的起伏， 但是事实上栅导体层 1012的顶面具有充分的平坦度， 其起伏 可以控制在例如几个纳米之内。 根据本公开的另一实施例， 还可以根据需要， 对通过溅射平坦化后的栅导体层 1012进行少许 CMP。
之后，如图 14 (图 14是顶视图， 以上图 1-13是沿 AA'线的截面图）所示， 对栅导体层 1012进行构图， 以形成栅堆叠。在图 14的示例中，栅导体层 1012 被构图为与鰭相交的条形。 根据另一实施例， 还可以构图后的栅导体层 1012 为掩模， 进一步对栅介质层 1010进行构图。
在形成构图的栅导体之后， 例如可以栅导体为掩模， 进行晕圈 （halo )注 入和延伸区 ( extension ) 注入。
接下来， 如图 15 (图 15 ( b )示出了沿图 15 ( a ) 中 BB'线的截面图） 所 示， 可以在栅导体层 1012的侧壁上形成侧墙 1014。 例如， 可以通过淀积形成 厚度约为 5-20nm的氮化物（如， 氮化硅）， 然后对氮化物进行 RIE, 来形成侧 墙 1014。 本领域技术人员知道多种方式来形成这种侧墙， 在此不再赘述。 在 鰭之间的沟槽为从上到下逐渐变小的锥台形时（由于刻蚀的特性， 通常为这样 的情况）， 侧墙 1014基本上不会形成于鰭的侧壁上。
在形成侧墙之后， 可以栅导体及侧墙为掩模， 进行源 /漏（ S/D )注入。 随 后， 可以通过退火， 激活注入的离子， 以形成源 /漏区， 得到 FinFET。
在上述实施例中， 在形成鰭之后， 直接形成了栅堆叠。 本公开不限于此。 例如， 替代栅工艺同样适用于本公开。 另外， 还可以应用应变源 /漏技术。 根据本公开的另一实施例， 在图 9 中形成的栅介质层 1010 和栅导体层 1012为牺牲栅介质层和牺牲栅导体层。 接下来， 可以同样按以上结合图 9-15 描述的方法来处理。
然后， 如图 16 所示， 首先选择性去除（例如， RIE )暴露在外的牺牲栅 介质层 1010。 在牺牲栅介质层 1010和隔离层 1004均包括氧化物的情况下， 由于牺牲栅介质层 1010较薄， 因此对牺牲栅介质层 1010的 RIE基本上不会 影响隔离层 1004。 在以上形成牺牲栅堆叠的过程中， 以牺牲栅导体为掩模进 一步构图牺牲栅介质层的情况下， 不再需要该操作。
然后， 可以选择性去除（例如， RIE ) 由于牺牲栅介质层 1010 的去除而 露出的鰭 1002的部分。 对鰭 1002该部分的刻蚀可以进行至露出穿通阻挡部 1008。 由于牺牲栅堆叠（牺牲栅介质层、 牺牲栅导体和侧墙）的存在， 鰭 1002 可以留于牺牲栅堆叠下方。
接下来， 如图 17所示， 例如可以通过外延， 在露出的鰭部分上形成半导 体层 1016。 随后可以在该半导体层 1016中形成源 /漏区。根据本公开的一实施 例， 可以在生长半导体层 1016的同时， 对其进行原位掺杂。 例如， 对于 n型 器件， 可以进行 n型原位掺杂； 而对于 p型器件， 可以进行 p型原位掺杂。 另 外， 为了进一步提升性能， 半导体层 1016可以包括不同于鰭 1002的材料， 以 便能够向鰭 1002 (其中将形成器件的沟道）施加应力。 例如， 在鰭 1002包括 Si的情况下， 对于 n型器件， 半导体层 1016可以包括 Si:C ( C的原子百分比 例如为约 0.2-2% ), 以施加拉应力； 对于 p型器件， 半导体层 1016可以包括 SiGe (例如， Ge的原子百分比为约 15-75% ) , 以施加压应力。
在牺牲栅导体层 1012包括多晶硅的情况下，半导体层 1016的生长可能也 会发生在牺牲栅导体层 1012的顶面上。 这在附图中并未示出。
接下来， 如图 18所示， 例如通过淀积， 形成另一电介质层 1018。 该电介 质层 1018例如可以包括氧化物。 随后，对该电介质层 1018进行平坦化处理例 如 CMP。 该 CMP可以停止于侧墙 1014, 从而露出牺牲栅导体 1012。
随后，如图 19所示，例如通过 TMAH溶液，选择性去除牺牲栅导体 1012, 从而在侧墙 1014内侧形成了空隙。 根据另一示例， 还可以进一步去除牺牲栅 介质层 1010。 然后， 通过在空隙中形成栅介质层 1020和栅导体层 1022 , 形成 最终的栅堆叠。 栅介质层 1020 可以包括高 K栅介质例如 Hf02, 厚度为约 l-5nm。 栅导体层 1022可以包括金属栅导体。 优选地， 在栅介质层 1020和栅 导体层 1022之间还可以形成功函数调节层（未示出）。
在以上实施例中， 第一溅射并没有实现表面的真正平坦， 其主要目的在于 减小凸起密度较高区域（或者说， 负载条件较高区域）中的溅射负载条件。 根 据本公开的另一实施例， 第一溅射也可以用于实现表面平坦化。
例如， 在以上图 3所示的第一溅射操作中， 并非仅仅使得区域 100-1上的 负载条件降低， 而是使得等离子体溅射能够执行一定的时间段， 充分平滑电介 质层 1004 (在区域 100-1中） 的表面。 图 4a示出了通过第一溅射进行平坦化 之后的结果。 尽管在图 4a中示出了微观上的起伏， 但是事实上电介质层 1004 (在区域 100-1中）的顶面具有充分的平坦度， 其起伏可以控制在例如几个纳 米之内。在图 4a所示的示例中， 等离子体溅射可以在到达鰭 1002的顶面之前 结束， 以避免对鰭 1002造成过多的损伤。
然后， 代替图 5所示的操作， 如图 5a所示， 可以在电介层 1004上形成构 图的另一掩蔽层 1024, 以遮蔽凸起密度较高的区域 100-1 (该区域已经经过平 坦化处理， 如图 4a所示）。 例如， 掩蔽层 1024可以包括光刻胶， 其可以通过 掩模进行曝光、 显影等操作来构图。 例如， 可以根据用来形成鰭 1002的掩模 (确定鰭的位置和形状等， 并因此部分地确定鰭 1002的分布密度）， 来设计用 来对掩蔽层 1024进行曝光的掩模。优选地，掩蔽层 1024与之前的掩蔽层 1006 不存在位置上的交迭， 例如它们之间可以存在间隙 G。
然后， 可以对露出的电介质层 1004部分进行溅射（ "第二溅射"）。 例如， 溅射可以使用等离子体， 如 Ar或 N等离子体。 在此， 例如可以根据等离子体 溅射对电介质层 1004的切削速度， 控制溅射参数例如溅射功率和气压等， 来 确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段， 以 充分平滑电介质层 1004(在区域 100-2中）的表面。在此，可以根据区域 100-1、 100-2中的溅射负载条件以及第一溅射、 第二溅射中使用的工艺参数， 来使得 第一溅射和第二溅射后电介质层 1004在区域 100-1、100-2中的表面大致持平。 例如， 表面高度的差异在 3-5nm之内。 之后， 可以去除掩蔽层 1024。 经过上述第一溅射、 第二溅射的处理， 同样可以得到如图 6所示的结构。 另外， 在该实施例中， 第一溅射、 第二溅射的顺序可以改变。
同样地， 在以上图 10所示的第一溅射操作中， 并非仅仅使得区域 100-1 上的负载条件降低， 而是使得等离子体溅射能够执行一定的时间段， 充分平滑 栅导体层 1012 (在区域 100-1中）的表面。 图 11a示出了通过第一溅射进行平 坦化之后的结果。尽管在图 11a中示出了微观上的起伏， 但是事实上栅导体层 1012 (在区域 100-1中）的顶面具有充分的平坦度， 其起伏可以控制在例如几 个纳米之内。
然后， 代替图 12所示的操作， 如图 12a所示， 可以在栅导体层 1012上形 成构图的另一掩蔽层 1026, 以遮蔽凸起密度较高的区域 100-1 (该区域已经经 过平坦化处理， 如图 11a所示）。 例如， 掩蔽层 1026可以包括光刻胶， 其可以 通过掩模进行曝光、 显影等操作来构图。 例如， 可以根据用来形成鰭 1002的 掩模（确定鰭的位置和形状等， 并因此部分地确定鰭 1002的分布密度）， 来设 计用来对掩蔽层 1026进行曝光的掩模。优选地，掩蔽层 1026与之前的掩蔽层 1014不存在位置上的交迭， 例如它们之间可以存在间隙 G。
然后， 可以对露出的栅导体层 1012部分进行溅射（ "第二溅射"）。 例如， 溅射可以使用等离子体， 如 Ar或 N等离子体。 在此， 例如可以根据等离子体 溅射对栅导体层 1012的切削速度， 控制溅射参数例如溅射功率和气压等， 来 确定进行等离子体溅射的时间，使得等离子体溅射能够执行一定的时间段， 以 充分平滑栅导体层 1012(在区域 100-2中）的表面。在此，可以根据区域 100-1、 100-2中的溅射负载条件以及第一溅射、 第二溅射中使用的工艺参数， 来使得 第一溅射和第二溅射后栅导体层 1012在区域 100-1、100-2中的表面大致持平。 例如， 表面高度的差异在 3-5nm之内。 之后， 可以去除掩蔽层 1026。
经过上述第一溅射、第二溅射的处理， 同样可以得到如图 13所示的结构。 另外， 在该实施例中， 第一溅射、 第二溅射的顺序可以改变。
这里需要指出的是， 尽管在上述实施例中描述了本公开的技术应用于 FinFET 的制造， 但是本公开不限于此。 本公开的技术可以适用于各种需要进 行平坦化处理的应用中。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说 明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来形成所需形状 的层、 区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是， 这些实施例仅仅是为了说明的 目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价 物限定。 不脱离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本公开的范围之内。

Claims

权 利 要 求 书
1. 一种对衬底上形成的材料层进行平坦化的方法， 包括：
对材料层进行第一溅射， 在进行第一溅射时， 以第一掩蔽层遮蔽材料层中 溅射的负载条件相对较低的区域；
去除第一掩蔽层； 以及
对材料层进行第二溅射， 以使材料层平坦。
2. 根据权利要求 1所述的方法， 其中， 所述衬底上形成有非均匀分布 的多个特征， 所述材料层形成于衬底上覆盖所述多个特征， 所述特征分布密度 较低的区域对应于所述溅射的负载条件相对较低的区域。
3. 根据权利要求 1所述的方法， 其中，
进行第一溅射， 以使材料层未被第一掩蔽层覆盖的部分平坦；
在去除第一掩蔽层之后， 且在进行第二溅射之前， 该方法还包括： 在材料层的所述部分上形成第二掩蔽层，其中第二掩蔽层的位置与第一掩 蔽层的位置不交迭。
4. 根据权利要求 1所述的方法， 其中， 利用 Ar或 N等离子体进行溅 射。
5. 根据权利要求 2所述的方法， 其中， 所述特征包括鰭， 所述材料层 包括电介质。
6. 根据权利要求 5所述的方法， 其中， 在第二溅射之后， 该方法还包 括：
进一步回蚀材料层， 以露出鰭。
7. 根据权利要求 6所述的方法， 其中， 在进一步回蚀之后， 该方法还 包括： 进行离子注入， 以在鰭位于进一步回蚀后的材料层的表面下方的部分中 形成穿通阻挡层。
8. 根据权利要求 7所述的方法， 其中， 在离子注入之后， 该方法还包 括：
在材料层上形成横跨鰭的牺牲栅堆叠；
以牺牲栅堆叠为掩模， 选择性刻蚀鰭， 直至露出穿通阻挡层； 在鰭的露出部分上形成半导体层， 用以形成源 /漏区； 以及
形成栅堆叠替代牺牲栅堆叠。
9. 根据权利要求 2所述的方法， 其中， 所述特征包括鰭， 所述材料层 包括栅导体层， 所述栅导体层介由栅介质层覆盖鰭。
10. 根据权利要求 8所述的方法， 其中，
形成牺牲栅堆叠包括：
在材料层上形成牺牲栅介质层；
在牺牲栅介质层上形成牺牲栅导体层；
对牺牲栅导体层进行平坦化， 并构图； 以及
在构图后的牺牲栅导体的侧壁上形成侧墙，
其中， 对牺牲栅导体层进行平坦化包括：
在所述特征分布密度较低的区域， 形成另外的第一掩蔽层， 并对露出的牺 牲栅导体层部分进行另外的第一溅射；
去除另外的第一掩蔽层； 以及
对牺牲栅导体层进行另外的第二溅射， 以使牺牲栅导体层平坦。
11. 根据权利要求 10所述的方法， 其中，
进行另外的第一溅射， 以使牺牲栅导体层的露出部分平坦；
在去除另外的第一掩蔽层之后， 且在进行另外的第二溅射之前， 该方法还 包括：
在牺牲栅导体层的露出部分上形成另外的第二掩蔽层，另外的第二掩蔽层 的位置与另外的第一掩蔽层的位置不交迭。
12. 一种对衬底上形成的材料层进行平坦化的方法， 包括：
对材料层进行第一溅射， 在进行第一溅射时， 以第一掩蔽层遮蔽材料层中 溅射的负载条件相对较高的区域， 其中进行第一溅射， 以使材料层中未被第一 掩蔽层遮蔽的部分平坦；
去除第一掩蔽层；
在材料层的所述部分上形成第二掩蔽层，其中第二掩蔽层的位置与第一掩 蔽层的位置不交迭； 以及
对材料层进行第二溅射， 以使材料层平坦。
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